non-volatile memory

Abstract

The application discloses a nonvolatile memory, a memory cell comprising a memory transistor and a select transistor formed in first and second well regions of a second conductivity type, respectively. A first gate structure of the select transistor comprises a first gate oxide layer, a first high-k layer, a first work function metal layer, and a first gate conductive material layer stacked in sequence. A second gate structure of the memory transistor comprises an ONO layer, a second high-k layer, a second work function metal layer, and a second gate conductive material layer stacked in sequence. A first threshold voltage of the select transistor is greater than a second threshold voltage of the memory transistor. The first threshold voltage is increased by reducing a difference between a first work function of the first work function metal layer and a first energy level of the first well region near a Fermi energy level, so that a doping concentration of the first well region is set independently of a required value of the first threshold voltage and is thus reduced. The application reduces the doping concentration of the first well region in the select transistor formation region and improves the uniformity of device performance.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor integrated circuit, and in particular to a non-volatile memory. BACKGROUND

[0002] For a SONOS non-volatile memory, a select transistor needs a higher threshold voltage and a storage transistor needs a lower threshold voltage.

[0003] The current technology is to use different in-well ion implantation conditions for the select transistor and the storage transistor to achieve a higher threshold voltage for the select gate and a lower threshold voltage for the storage gate, but the more ion implantation for the select transistor will enhance the random doping fluctuation effect, affecting the uniformity of the select transistor device performance, and with the miniaturization of the memory, the ion implantation of the select transistor and the storage transistor will mutually diffuse, affecting the uniformity of the device performance more and more.

[0004] As shown in FIG. 1, it is a structural schematic diagram of a storage unit of a prior art non-volatile memory; the prior art non-volatile memory includes a memory device in a storage area, and the storage unit of the memory device includes a storage transistor and a select transistor. Figure 1

[0005] The first well region 102 is formed in the formation area of the select transistor, and the second well region 103 is formed in the formation area of the storage transistor; both the first well region 102 and the second well region 103 are formed in the semiconductor substrate 101 and both have a second conductivity type doping.

[0006] The select transistor has a first gate structure, and the first gate structure includes a first gate oxide layer 104, a high dielectric constant layer 106, a work function metal layer 107, and a gate conductive material layer 108 which are sequentially superimposed on the surface of the first well region 102.

[0007] The storage transistor has a second gate structure, and the second gate structure includes an ONO layer 105, a high dielectric constant layer 106, a work function metal layer 107, and a gate conductive material layer 108 which are sequentially superimposed on the surface of the second well region 103. The ONO layer 105 is superimposed by an oxide layer 1051, a nitride layer 1052, and an oxide layer 1053, and the nitride layer 1052 is used for storing charges.

[0008] The select transistor has a first threshold voltage.

[0009] The storage transistor has a second threshold voltage when the ONO layer 105 does not store charges, and the first threshold voltage is greater than the second threshold voltage.

[0010] ​Generally, the select transistor and the storage transistor are both N-type devices, and the first well region 102 and the second well region 103 are both P-type wells. In the prior art, the first gate structure and the second gate structure have the same high dielectric constant layer 106, work function metal layer 107 and gate conductive material layer 108. The select transistor has a higher first threshold voltage, and the doping concentration of the first well region 102 needs to be increased. Therefore, the first well region 102 needs to be separately fabricated, which increases the process cost.

[0011] Since the storage region is composed of a large number of storage cells, when the doping concentration of the first well region 102 is too high, the doping concentration deviation of the first well region 102 in different regions increases, the uniformity becomes poor, and finally the performance uniformity of the select transistor becomes poor.

[0012] In addition, although the size of the device is continuously reduced, the spacing between the select transistor and the storage transistor is also reduced. When the doping concentration of the first well region 102 is high, the concentration difference between the first well region 102 and the second well region 103 is large, which causes the mutual diffusion of doping impurities, and finally affects the performance uniformity of the storage transistor and the select transistor. SUMMARY

[0013] The technical problem to be solved by the present application is to provide a non-volatile memory, which can reduce the doping concentration of the first well region in the formation region of the select transistor under the condition that the threshold voltage of the select transistor is greater than the threshold voltage of the storage transistor when the storage transistor has no stored charge, thereby improving the performance uniformity of the select transistor and reducing the mutual diffusion of well region doping of the select transistor and the storage transistor, and thereby improving the performance uniformity of the select transistor and the storage transistor.

[0014] To solve the above technical problem, the non-volatile memory provided by the present application includes a storage device located in a storage region, and the storage cell of the storage device includes a storage transistor and a select transistor.

[0015] The formation region of the select transistor has a first well region, and the formation region of the storage transistor has a second well region; the first well region and the second well region are both formed in a semiconductor substrate and both have a second conductive type doping.

[0016] The select transistor has a first gate structure, and the first gate structure includes a first gate oxide layer, a first high dielectric constant layer, a first work function metal layer and a first gate conductive material layer which are sequentially stacked on the surface of the first well region.

[0017] The storage transistor has a second gate structure, and the second gate structure includes an ONO layer, a second high dielectric constant layer, a second work function metal layer and a second gate conductive material layer which are sequentially stacked on the surface of the second well region.

[0018] The select transistor has a first threshold voltage.

[0019] The storage transistor has a second threshold voltage when the ONO layer does not store charge, the first threshold voltage being greater than the second threshold voltage.

[0020] In the first well region, the energy band structure of the semiconductor substrate has a conduction band bottom and a valence band top, a first energy level close to the Fermi energy level of the first well region is a first energy level, the first energy level being one of the conduction band bottom and the valence band top, and a second energy level being the other of the conduction band bottom and the valence band top.

[0021] The first work function metal layer has a first work function, and the second work function metal layer has a second work function.

[0022] The first work function and the second work function are both close to the second energy level, and a first energy level difference between the first work function and the first energy level is smaller than a second energy level difference between the second work function and the first energy level; by reducing the first energy level difference to increase the first threshold voltage, the doping concentration of the first well region is set independently of a required value of the first threshold voltage, and the doping concentration of the first well region is reduced to meet a uniformity requirement of performance of the select transistor and interdiffusion between the first well region and the second well region is reduced to meet a uniformity requirement of performance of the storage transistor.

[0023] A further improvement is that the nonvolatile memory further includes a logic device in the peripheral circuit region.

[0024] The logic device includes an NMOS and a PMOS.

[0025] The NMOS is formed in a third well region of P type, the third well region being set according to a requirement of a third threshold voltage possessed by the NMOS.

[0026] The PMOS is formed in a fourth well region of N type, the fourth well region being set according to a requirement of a fourth threshold voltage possessed by the PMOS.

[0027] A further improvement is that the second conductivity type is P type; the first energy level is a valence band top, and the second energy level is a conduction band bottom.

[0028] A further improvement is that the second conductivity type is N type; the first energy level is a conduction band bottom, and the second energy level is a valence band top.

[0029] A further improvement is that the doping concentration of the first well region is the same as the doping concentration of the third well region.

[0030] The first well region and the third well region are formed simultaneously by the same ion implantation plus annealing process.

[0031] Further improvement is that the doping concentration of the first well region is the same as the doping concentration of the fourth well region.

[0032] The first well region and the fourth well region are formed simultaneously by the same ion implantation plus annealing process.

[0033] Further improvement is that the semiconductor substrate comprises a silicon substrate.

[0034] Further improvement is that the first high dielectric constant layer and the second high dielectric constant layer are of the same material and formed simultaneously by the same process.

[0035] Further improvement is that the material of the first high dielectric constant layer and the second high dielectric constant layer comprises hafnium oxide.

[0036] Further improvement is that the material of the first work function metal layer and the second work function metal layer are different and the first work function and the second work function are set by the difference of the materials.

[0037] Further improvement is that the material of the first work function metal layer and the second work function metal layer are the same and the first work function and the second work function are set by the difference of the thickness.

[0038] Further improvement is that the first gate conductive material layer and the second gate conductive material layer are both polycrystalline silicon gates or both metal gates.

[0039] Further improvement is that the select transistor further comprises first source and drain regions composed of heavily doped regions of the first conductivity type formed in the surface region of the first well region self-aligned to the first gate structure on both sides.

[0040] Further improvement is that the storage transistor further comprises second source and drain regions composed of heavily doped regions of the first conductivity type formed in the surface region of the second well region self-aligned to the second gate structure on both sides.

[0041] Further improvement is that the first drain region and the second source region share the same heavily doped region of the first conductivity type.

[0042] The present application can reduce the doping concentration of the first well region, and thus can adopt a less doped first well region. Since the lower the doping concentration is, the smaller the fluctuation of the doping concentration of the doped region is, the less doped structure can reduce the fluctuation of the doping concentration of the first well region and thus improve the uniformity of the doping concentration of the first well region, and finally improve the uniformity of the performance of the select transistor.

[0043] Meanwhile, the less doped concentration can also reduce the mutual diffusion of the doped impurities between the first well region and the second well region of the storage transistor, and thus can reduce the adverse effect of the mutual diffusion of the impurities on the uniformity of the performance of the select transistor and the storage transistor, especially can prevent the adverse effect of the high-concentration doped first well region on the second well region, and thus can improve the uniformity of the performance of the storage transistor, so that the present application can improve the uniformity of the performance of the whole memory device.

[0044] In addition, the process structure of the first well region of the select transistor of the present application can adopt the process structure of the well region of the same type of logic device in the peripheral circuit region, and thus does not need to define the first well region of the select transistor separately and perform separate implantation and annealing processes, and thus can reduce the process cost. BRIEF DESCRIPTION OF DRAWINGS

[0045] The present application will be further described in detail below in combination with the drawings and specific embodiments:

[0046] Figure 1 is a structure diagram of a storage unit of a prior nonvolatile memory;

[0047] Figure 2 is a structure diagram of a storage unit of a nonvolatile memory according to an embodiment of the present application. DETAILED DESCRIPTION

[0048] As shown in Figure 2 is a structure diagram of a storage unit of a nonvolatile memory according to an embodiment of the present application; the nonvolatile memory according to the embodiment of the present application comprises a memory device located in a storage region, and the storage unit of the memory device comprises a storage transistor and a select transistor.

[0049] The first well region 202 is formed in the formation region of the select transistor, and the second well region 203 is formed in the formation region of the storage transistor; both the first well region 202 and the second well region 203 are formed in the semiconductor substrate 201 and both have a second-conductivity-type doping.

[0050] The selection tube has a first gate structure, which includes a first gate oxide layer 204, a first high dielectric constant layer 2061, a first work function metal layer 2071 and a first gate conductive material layer 2081 successively stacked on the surface of the first well region 202.

[0051] The storage tube has a second gate structure, which includes an ONO layer 205, a second high dielectric constant layer 2062, a second work function metal layer 2072 and a second gate conductive material layer 2082 successively stacked on the surface of the second well region 203. The ONO layer 205 is stacked by an oxide layer 2051, a nitride layer 2052 and an oxide layer 2053, and the nitride layer 2052 is used for storing charges.

[0052] The selection tube has a first threshold voltage.

[0053] The storage tube has a second threshold voltage when the ONO layer 205 does not store charges, and the first threshold voltage is greater than the second threshold voltage.

[0054] In the first well region 202, the energy band structure of the semiconductor substrate 201 has a conduction band bottom and a valence band top, the Fermi level of the first well region 202 is close to a first energy level, the first energy level is one of the conduction band bottom and the valence band top, and a second energy level is the other of the conduction band bottom and the valence band top.

[0055] The first work function metal layer 2071 has a first work function, and the second work function metal layer 2072 has a second work function.

[0056] The first work function and the second work function are close to the second energy level, and the first energy level difference between the first work function and the first energy level is less than the second energy level difference between the second work function and the first energy level; by reducing the first energy level difference to increase the first threshold voltage, the doping concentration of the first well region 202 is set independently of the required value of the first threshold voltage, the doping concentration of the first well region 202 is reduced to meet the uniformity requirement of the performance of the selection tube, and the mutual diffusion of the first well region 202 and the second well region 203 is reduced to meet the uniformity requirement of the performance of the storage tube.

[0057] In the embodiment of the present application, the nonvolatile memory further includes a logic device (not shown) in the peripheral circuit region.

[0058] The logic device includes NMOS and PMOS.

[0059] The NMOS is formed in a third well region of P type, and the third well region is set according to the requirement of a third threshold voltage of the NMOS.

[0060] The PMOS is formed in a fourth well region of N type, which is set according to the requirement of a fourth threshold voltage that the PMOS has.

[0061] In the embodiment of the present application, the second conductivity type is P type, the select transistor and the storage transistor are both N type devices; the first energy level is the valence band top, and the second energy level is the conduction band bottom. That is, the first well region 202 and the second well region 203 are both P type well regions, the first work function and the second work function are both close to the conduction band bottom, but the first work function is closer to the valence band top than the second work function. Compared with the case that the first work function and the second work function are equal in the prior art structure, the embodiment of the present application reduces the distance between the first work function and the valence band top, and finally reduces the flat band voltage of the select transistor, thereby increasing the threshold voltage of the select transistor.

[0062] In the embodiment of the present application, the doping concentration of the first well region 202 is the same as the doping concentration of the third well region.

[0063] The first well region 202 and the third well region are simultaneously formed by using the same ion implantation and annealing process.

[0064] In other embodiments, the select transistor and the storage transistor can also be P type devices, and the second conductivity type is N type; the first energy level is the conduction band bottom, and the second energy level is the valence band top. The doping concentration of the first well region 202 is the same as the doping concentration of the fourth well region. The first well region 202 and the fourth well region are simultaneously formed by using the same ion implantation and annealing process.

[0065] In the embodiment of the present application, the semiconductor substrate 201 includes a silicon substrate.

[0066] The first high dielectric constant layer 2061 and the second high dielectric constant layer 2062 are simultaneously formed by using the same process and the same material.

[0067] The material of the first high dielectric constant layer 2061 and the second high dielectric constant layer 2062 includes hafnium oxide.

[0068] The materials of the first work function metal layer 2071 and the second work function metal layer 2072 are different, and the first work function and the second work function with differences are set by the difference in the materials. In other embodiments, the materials of the first work function metal layer 2071 and the second work function metal layer 2072 can also be the same, and the thicknesses are different, and the first work function and the second work function with differences are set by the difference in the thicknesses.

[0069] In the embodiment of the present application, the first gate conductive material layer 2081 and the second gate conductive material layer 2082 are both polycrystalline silicon gates or both metal gates.

[0070] In the embodiment of the present application, the select transistor further comprises first source and drain regions composed of heavily doped regions of the first conductivity type self-aligned formed in the surface region of the first well 202 on both sides of the first gate structure.

[0071] The storage transistor further comprises second source and drain regions composed of heavily doped regions of the first conductivity type self-aligned formed in the surface region of the second well 203 on both sides of the second gate structure.

[0072] The first drain region and the second source region share the same heavily doped region of the first conductivity type.

[0073] In the embodiment of the present application, the threshold voltage of the select transistor, i.e. the first threshold voltage, and the threshold voltage of the storage transistor, i.e. the second threshold voltage, are different, and the doping concentration of the well of the select transistor, i.e. the first well 202, is increased to increase the first threshold voltage, but the first work function of the first work function metal layer 2071 of the select transistor is set independently of the second work function of the second work function metal layer 2072 of the storage transistor to increase the first threshold voltage, so that the doping concentration of the first well 202 can be reduced, and a less heavily doped first well 202 can be used, because the lower the doping concentration, the smaller the fluctuation of the doping concentration of the doped region, so that the use of a less heavily doped structure can reduce the fluctuation of the doping concentration of the first well 202 and thus improve the uniformity of the doping concentration of the first well 202, and finally the uniformity of the performance of the select transistor can be improved.

[0074] At the same time, the less heavily doped concentration can also reduce the mutual diffusion of doped impurities between the first well 202 and the second well 203 of the storage transistor, and thus can reduce the adverse effects of impurity mutual diffusion on the uniformity of the performance of the select transistor and the storage transistor, especially can prevent the adverse effects of the heavily doped first well 202 on the second well 203, and thus can improve the uniformity of the performance of the storage transistor. Therefore, the embodiment of the present application can improve the uniformity of the performance of the entire memory device.

[0075] In addition, the process structure of the first well 202 of the select transistor of the embodiment of the present application can use the process structure of the well of the same type of logic device in the peripheral circuit region, so that the first well 202 of the select transistor does not need to be defined and injected and annealed separately, and thus the process cost can be reduced.

[0076] The application is described in detail above with specific examples, but these do not constitute a limitation on the application. Those skilled in the art can make many modifications and improvements without departing from the principles of the application, and these should be considered as within the scope of the application.

Claims

1. A nonvolatile memory, comprising: The nonvolatile memory includes a memory device in a memory region, a storage unit of the memory device including a storage transistor and a selection transistor; A first well region is formed in a formation region of the selection transistor, and a second well region is formed in a formation region of the storage transistor; both the first well region and the second well region are formed in a semiconductor substrate and both have a second conductivity type doping; The selection transistor has a first gate structure including a first gate oxide layer, a first high dielectric constant layer, a first work function metal layer and a first gate conductive material layer, which are sequentially stacked on a surface of the first well region; The storage transistor has a second gate structure including an ONO layer, a second high dielectric constant layer, a second work function metal layer and a second gate conductive material layer, which are sequentially stacked on a surface of the second well region; The selection transistor has a first threshold voltage; The storage transistor has a second threshold voltage when the ONO layer does not store electric charges, and the first threshold voltage is greater than the second threshold voltage; In the first well region, the semiconductor substrate has a conduction band bottom and a valence band top in a band structure, a first energy level close to a Fermi energy level of the first well region is one of the conduction band bottom and the valence band top, and a second energy level is the other one of the conduction band bottom and the valence band top; The first work function metal layer has a first work function, and the second work function metal layer has a second work function; Both the first work function and the second work function are close to the second energy level, and a first energy level difference between the first work function and the first energy level is less than a second energy level difference between the second work function and the first energy level; by reducing the first energy level difference to increase the first threshold voltage, a doping concentration of the first well region is set independently of a required value of the first threshold voltage, the doping concentration of the first well region is reduced to meet a uniformity requirement of performance of the selection transistor, and mutual diffusion of the first well region and the second well region is reduced to meet a uniformity requirement of performance of the storage transistor.

2. The nonvolatile memory of claim 1, wherein: The nonvolatile memory further includes a logic device in a peripheral circuit region; The logic device includes an NMOS and a PMOS; The NMOS is formed in a third well region of a P type, and the third well region is set according to a requirement of a third threshold voltage of the NMOS; The PMOS is formed in a fourth well region of an N type, and the fourth well region is set according to a requirement of a fourth threshold voltage of the PMOS.

3. The nonvolatile memory of claim 2, wherein: The second conductivity type is a P type; the first energy level is a valence band top, and the second energy level is a conduction band bottom.

4. The nonvolatile memory of claim 2, wherein: The second conductivity type is an N type; the first energy level is a conduction band bottom, and the second energy level is a valence band top.

5. The nonvolatile memory of claim 3, wherein: The doping concentration of the first well region is the same as a doping concentration of the third well region; The first well region and the third well region are simultaneously formed by using a same ion implantation plus annealing process.

6. The nonvolatile memory of claim 4, wherein: The doping concentration of the first well region is the same as a doping concentration of the fourth well region; The first well region and the fourth well region are simultaneously formed by using a same ion implantation plus annealing process.

7. The nonvolatile memory of claim 1, wherein: The semiconductor substrate includes a silicon substrate.

8. The nonvolatile memory of claim 1, wherein: The first high dielectric constant layer and the second high dielectric constant layer are formed simultaneously by using the same material and the same process.

9. The nonvolatile memory of claim 8, wherein: The first high dielectric constant layer and the second high dielectric constant layer comprise hafnium oxide.

10. The nonvolatile memory of claim 1 or 2, wherein: The first work function metal layer and the second work function metal layer are formed by using different materials, and the first work function and the second work function are set by the difference between the materials.

11. The nonvolatile memory of claim 1 or 2, wherein: The first work function metal layer and the second work function metal layer are formed by using the same material and different thicknesses, and the first work function and the second work function are set by the difference between the thicknesses.

12. The nonvolatile memory of claim 1 or 2, wherein: The first gate conductive material layer and the second gate conductive material layer are both formed by using a polysilicon gate or both formed by using a metal gate.

13. The nonvolatile memory of claim 1, wherein: The selection tube further comprises a first source region and a first drain region formed by a first conductive type heavily doped region in the surface region of the first well region on both sides of the first gate structure in a self-aligned manner.

14. The nonvolatile memory of claim 13, wherein: The storage tube further comprises a second source region and a second drain region formed by a first conductive type heavily doped region in the surface region of the second well region on both sides of the second gate structure in a self-aligned manner.

15. The nonvolatile memory of claim 14, wherein: The first drain region and the second source region share the same first conductive type heavily doped region.

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