A semiconductor device and a method of fabricating the same

Abstract

The application relates to a semiconductor device and a preparation method thereof, wherein a nanosheet stack part of the semiconductor device comprises: a nanosheet stack part arranged on a substrate; wherein the nanosheet stack part comprises: a plurality of nanosheet-formed stacks, the nanosheets being formed of a semiconductor material; the nanosheet-formed stacks constitute a plurality of conductive channels; a surrounding gate surrounding the nanosheet stack part; and a source-drain region (SD) being a lightly-doped and steep source-drain extension region (SDE) at the junction with the nanosheet stack part. The application forms the SDE doping through an inclined ion injection after inner sidewall etching and before source-drain selective epitaxy, and then forms the SDE region which is steep, uniformly distributed and with a precisely controllable lateral junction depth after source-drain annealing, so that the effective channel length is effectively controlled and a complex in-situ doping epitaxy process is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, and in particular, to a semiconductor device and a method for manufacturing the same. BACKGROUND

[0002] With the continuous miniaturization of transistor feature size, the traditional MOSFET device has undergone a transition from a planar structure to a three-dimensional structure, improving device performance while reducing the impact of short channel effects. The mainstream three-dimensional structure transistor is FinFET. However, FinFET faces great challenges below 5nm technology node, and in the latest International Roadmap for Devices and Systems (IRDS), nanosheet gate-all-around transistor (Nanosheet-GAAFET) is a key device that can effectively replace FinFET after 3nm node, and can significantly suppress short channel effects and improve device current driving performance.

[0003] Currently, the research progress of GAA stacked nanosheet FET has attracted widespread attention from academia and industry. The constantly updated preparation process and key technology, as well as the optimized device structure are the hot research direction of new CMOS devices.

[0004] GAA stacked nanosheet FET is a new type of device with a gate-all-around structure and horizontal nanosheet (NS) as a conductive channel, which is developed on the basis of FinFET and Nanowire-FET. In terms of gate control, the gate-all-around structure has better gate control ability than the FinFET device structure, which can effectively suppress the short channel effect of the device; in terms of current driving, Nanosheet-GAAFET has effective gate adjustable and vertical and horizontal direction stacking design, which can significantly enhance the current driving performance of the device.

[0005] However, in the current CMOS integrated process of conventional stacked nanosheet GAA-FET, it is difficult to form a lightly doped and steep source-drain extension region (S / D Extension, SDE or Lightly Doped Drain, LDD), which affects the effective channel length and easily leads to short channel effect, which needs to be realized by source-drain epitaxial in-situ doping or post-injection heavy doping and then annealing diffusion, but it is difficult to control the lateral junction depth of SDE doping and affect the epitaxial quality, which is easy to bring epitaxial defects. SUMMARY

[0006] In order to solve the above technical problems, the application provides a novel semiconductor device and a preparation method thereof, wherein after inner wall etching and before source-drain selective epitaxy, SDE doping is formed by angle ion implantation, then after source-drain annealing, the SDE region with steep, uniform distribution and accurate controllable lateral junction depth is formed, thereby effectively controlling the effective channel length and avoiding complex in-situ doping epitaxy process.

[0007] The application adopts the following technical scheme:

[0008] A semiconductor device comprises:

[0009] A substrate;

[0010] A nanosheet stack portion is arranged on the substrate; wherein the nanosheet stack portion comprises: a plurality of nanosheet-formed stacks, the nanosheet is formed of a semiconductor material; the nanosheet-formed stack constitutes a plurality of conductive channels;

[0011] A wraparound gate is wrapped around the nanosheet stack portion;

[0012] A source-drain region is a lightly doped and steep source-drain extension region at the junction with the nanosheet stack portion.

[0013] Meanwhile, the application also discloses a preparation method of a semiconductor device, and the preparation method is characterized by comprising the following steps:

[0014] A preparation method of a semiconductor device comprises the following steps:

[0015] A substrate is provided;

[0016] An ultralattice stack formed of first semiconductor / second semiconductor alternated layers is epitaxially grown on the substrate;

[0017] The ultralattice stack is etched to form a plurality of fins;

[0018] A dummy gate is formed on the fin, and the fin is etched;

[0019] The ultralattice stack of the first semiconductor and the second semiconductor on the fin is selectively etched to form a nanosheet stack portion, nanosheets formed of the first semiconductor in part of the ultralattice stack are etched out from the outside to the inside, an inner wall is deposited in the etched space, and angle ion implantation is performed on the inner wall to form an SDE doping region, and annealing is performed;

[0020] A source-drain region is formed by selective epitaxy growth process;

[0021] A medium is deposited and planarized to expose the dummy gate;

[0022] Channel release of the nanosheet is realized, wherein the nanosheet-formed stack constitutes a plurality of conductive channels.

[0023] A wrap-around gate is formed around the nanostack portion. BRIEF DESCRIPTION OF DRAWINGS

[0024] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a better understanding of the preferred embodiments, and are not intended to be a limitation on the application. In the drawings, like reference numerals refer to same components throughout the several views.

[0025] Figure 1 A schematic diagram of growing a superlattice stack on a substrate.

[0026] Figure 2 A schematic diagram of forming a first sidewall on the superlattice stack.

[0027] Figure 3 A schematic diagram of etching the superlattice stack to form a fin.

[0028] Figure 4 A schematic diagram of removing the first sidewall and forming a shallow trench isolation region in a vertical fin line direction.

[0029] Figure 5 A schematic diagram of forming a dummy gate on the fin in a vertical fin line direction.

[0030] Figure 6 A schematic diagram of defining X-X and Y-Y directions in the device.

[0031] Figure 7 A schematic diagram of a cross-section along the X-X line, forming a second sidewall on both sides of the dummy gate and performing a source / drain etch.

[0032] Figure 8 A schematic diagram of a cross-section along the X-X line, etching away portions of the first semiconductor layer from the outside in, further depositing a second sidewall, etching away the outer second sidewall.

[0033] Figure 9 A schematic diagram of a cross-section along the X-X line, performing an angled ion implant to form an SDE doped region, depositing a source / drain region and doping.

[0034] Figure 10 A schematic diagram of a cross-section along the X-X line, depositing an ILD0 layer of dielectric, removing the dummy gate, releasing the nanochannel.

[0035] Figure 11 A schematic diagram of a cross-section along the X-X line, forming a metal gate, a high-K dielectric layer, depositing an ILD-1 dielectric layer, contact hole lithography and etching. DETAILED DESCRIPTION

[0036] Embodiments of the present application will be described below with reference to the accompanying drawings. It should be understood, however, that the description that follows is merely exemplary and is not intended to limit the scope of the application. Furthermore, in the following description, well-known structures and techniques have not been described in detail in order to avoid obscuring the application.

[0037] In the drawings, various structural diagrams according to embodiments of the present application are shown. These diagrams are not drawn to scale, in which certain details are shown exaggerated for clarity and others omitted. The shapes and relative sizes of the various regions, layers, and elements illustrated in the drawings are exemplary only and can vary depending on the manufacturing techniques used to produce the structures and the intended technical effects to be achieved. The same reference numerals are used in different drawings to represent similar structures and / or elements.

[0038] In the context of the present application, when a layer / element is said to be located "on" another layer / element, it can be directly on the other layer / element or there can be intervening layers / elements between them. Also, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed.

[0039] In the present embodiment, a method for manufacturing a semiconductor device is provided. In conjunction with Figures 1-11 For the preparation process of the FET device of the present application, the preparation process of the FET device includes:

[0040] As Figure 1 The substrate 101 is provided, which can be a bulk silicon substrate.

[0041] The substrate 101 is a portion of a semiconductor wafer suitable for forming one or more IC devices. When a bulk silicon substrate is used, a high-doped well region is formed in the bulk silicon substrate by implanting impurities, diffusion, and annealing to achieve the desired well depth. For a P-type FET, the high-doped well region is an N-well, and the implanted impurities are n-type impurity ions, such as phosphorus (P) ions. For an N-type FET, the high-doped well region is a p-well, and the implanted impurities are p-type impurity ions, such as boron (B) ions. During the superlattice epitaxial process, the thicknesses of SiGe and Si are respectively controlled, and the Ge content is controlled to form a multi-component SiGe conductive channel.

[0042] The silicon dioxide (SiO2) on the surface of the bulk silicon substrate is removed, and a plurality of periods of a superlattice structure of the first semiconductor 201' / the second semiconductor 202' is epitaxially grown on the bulk silicon substrate; the thickness of each layer of semiconductor in the superlattice structure is below 30 nanometers, and the final production thickness will directly determine the height of the nanosheet channel and the electrostatic performance.

[0043] For P-type FETs, the superlattice of the first semiconductor 201' / second semiconductor 202' is a Si / SiGe stack, and for N-type FETs, the superlattice of the first semiconductor 201' / second semiconductor 202' is a SiGe / Si stack.

[0044] like Figure 2 The first sidewall 301 array is formed at the nanoscale using a self-aligned sidewall transfer (SIT) process. The first sidewall 301 is made of silicon nitride (SiN). X The specific formation process is as follows: a sacrificial layer 302 is deposited on the superlattice stack. The sacrificial layer can be polycrystalline silicon (p-si) or amorphous silicon (a-si). Part of the sacrificial layer is etched away, and silicon nitride (SiN) is deposited. x The sacrificial layer is then etched away using anisotropic etching, leaving only the multiple periodic silicon nitride (SiN) layers on the superlattice stack. x First sidewall (spacers) 301, the silicon nitride (SiN) x The first sidewall 301 acts as a hard mask in photolithography.

[0045] The epitaxially grown superlattice stack is etched into multiple periodically distributed fins. The first sidewall 301 is used as a mask for etching to form fins with a superlattice stack structure. The upper part of the fin is a conductive channel region formed by the superlattice stack, and the lower part is a substrate, forming a structure as shown below. Figure 3 The fin shown is an example. This fin includes not only a superlattice stacked structure but also a single-crystal silicon structure extending into the substrate. The etching process is either dry etching or wet etching, and in one embodiment, reactive ion etching (RIE) may be used. The fin will be used to form horizontal nanosheets of one or more n-type and / or p-type field-effect transistors. Although Figure 3 A fin is shown; it should be understood that any suitable number and shape of fins can be used. The fin height is approximately 10nm-400nm, and the width is approximately 1-100nm.

[0046] like Figure 4As shown, a shallow trench isolation (STI) region 103 is formed between two adjacent fins. First, a dielectric insulating material is deposited, then planarized, for example using a CMP process, followed by selective etching back of the dielectric insulating material to expose the three-dimensional fin structure, thereby forming the shallow trench isolation region 103 adjacent to the fins. The upper surface of the shallow trench isolation region 103 is generally flush with the interface between the superlattice stacked structure in the fin and the substrate single-crystal silicon, but may be higher or lower than this interface level. The shallow trench isolation region 103 can be formed from a suitable dielectric material, such as silicon dioxide (SiO2) or silicon nitride (SiN). x The shallow trench isolation region 103 serves to separate transistors on adjacent fins. The shallow trench isolation region 103 exposes the first semiconductor layer 201' at the bottom of the superlattice stack.

[0047] like Figure 5 As shown, a dummy gate stack is formed on the exposed fin in a direction perpendicular to the fin line (i.e., the YY direction). The dummy gate stack is a multi-layer structure, including a gate insulating dielectric (not shown), a dummy gate layer 106, and a hard mask layer 108. The dummy gate stack structure can be formed using processes such as thermal oxidation, chemical vapor deposition, or sputtering. The dummy gate stack structure spans the superlattice stack above the fin, with multiple dummy gates periodically distributed along the fin line direction. The material used for the dummy gate layer 106 can be polycrystalline silicon (p-si) or amorphous silicon (a-si). The material used for the hard mask layer 108 can be oxides, carbides, organic materials, etc.

[0048] like Figure 6 Define direction in the middle. Figure 6 Two dashed lines, XX and YY, are set in the diagram. Line XX is the center line of the fin along the fin line direction, and line YY is the center line of the fin perpendicular to the fin line direction. The following figures are cross-sectional schematic diagrams based on the two lines XX and YY.

[0049] Figure 7 As shown, silicon nitride (SiN) is disposed on both sides of the dummy gate stack along the fin direction (i.e., the XX direction). x The second sidewall 107 has the same thickness on both sides. Then, using the dummy gate layer 106 / hard mask 108 and the second sidewall 107 as a mask, the source and drain fins are etched by an etching process.

[0050] Then as Figure 8 As shown, pull-back etching is performed, partially etching away the first semiconductor layer 201' from the source / drain region towards the center. Then, silicon nitride (SiN) is deposited around the fin. xThe third sidewall 107' is etched until it is flush with the second semiconductor layer 202' in the vertical direction. The portion of the first semiconductor layer 201' missing due to the aforementioned pull-back etching is covered by the silicon nitride (SiN) of the third sidewall 107'. x Fill in the gaps.

[0051] like Figure 9 As shown, after etching, ions are implanted into the fins at an angle, causing ions to be implanted at the outer edge of the second semiconductor layer 202', forming a source / drain region extension ion implantation layer (i.e., SDE implantation), and forming the SDE sidewall doped region 109, thus providing a diffusion buffer layer for high-concentration source / drain region doping. SDE implantation is a high-current, low-energy ion implantation process with a very high dose. The tilt implantation angle ranges from 5° to 45°, and the energy ranges from 0.1 keV to 100 keV.

[0052] After SDE implantation, source / drain regions 110' are epitaxially grown. Source / drain regions 110' can be formed using suitable methods such as metal-organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, selective epitaxial growth (SEG), similar methods, or combinations thereof.

[0053] like Figure 10 As shown, for a P-type FET, the source / drain region material is boron (B)-doped SiGe (SiGe:B), and for an N-type FET, the source / drain region material is phosphorus (P)-doped silicon (Si) (Si:P), ultimately forming the source / drain region 110. After annealing the source / drain region 110, a steep, uniformly distributed, and precisely controllable lateral junction depth SDE region is formed at the interface between the source / drain region 110 and the fins. This effectively controls the effective channel length, avoids complex in-situ doping epitaxial processes, and performs an annealing process with an annealing temperature range of 500℃ to 1000℃.

[0054] Then, an isolation layer 111 is deposited on the dummy gate and source / drain regions 110 to prevent short circuits between the dummy gate layer 106 and the source / drain regions 110 in subsequent steps. The isolation layer 111 is then chemically and mechanically polished to planarize it. The hard mask layer 108 is then removed to expose the dummy gate layer 106.

[0055] Then, the dummy gate layer 106 formed by the aforementioned polysilicon (p-si) or amorphous silicon (a-si) is etched or etched away by selective etching or etching processes, that is, the dummy gate layer 106 is removed.

[0056] Subsequently, the sacrificial layer in the superlattice stack is selectively etched to release the nanosheet channels. The exposed conductive channel regions of the fins are processed by removing the first semiconductor layer 201' of each layer; the first semiconductor layer 201' serves as the sacrificial layer, releasing the nanosheets 202 formed from the second semiconductor. The nanosheets 202 have a width ranging from 1-100 nm, a thickness ranging from 1-30 nm, and a spacing of 3-30 nm between each nanosheet 202.

[0057] In one embodiment, for both P-type and N-type FETs, the sacrificial layer is a GeSi layer. The GeSi layer is selectively removed, leaving the Si layer, to form a Si horizontal stacked nanostructure device. The selective removal process can use an etchant that selectively etches SiGe at a faster rate relative to Si. In one embodiment, a conventional wet process isotropically etches the sacrificial layer to release the nanochannel, thereby forming a nanosheet conductive channel.

[0058] In another embodiment, channel release is performed separately for P-type and N-type FETs.

[0059] For P-type FETs, the sacrificial layer is a Si layer. The Si layer is selectively removed, leaving a SiGe layer, forming a SiGe horizontal stacked nanostructure device. In the selective removal process, an etchant that selectively etches Si at a faster rate than SiGe can be used. In one embodiment, a conventional wet process isotropically etches the sacrificial layer to release the nanochannel, thereby forming a nanosheet conductive channel.

[0060] For N-type FETs, the sacrificial layer is a SiGe layer. The SiGe layer is selectively removed, leaving the Si layer, forming a Si horizontal stacked nanostructured device. In the selective removal process, an etchant that selectively etches SiGe at a faster rate relative to Si can be used. In one embodiment, a conventional wet process isotropically etches the sacrificial layer to release the nanochannel, thereby forming a nanosheet conductive channel. A second semiconductor nanosheet 202 is stacked to form the nanostructured portion.

[0061] Next, as Figure 11 As shown, an interfacial oxide layer (IL) is deposited or grown, followed by the deposition of a high-k dielectric layer, such that the high-k dielectric layer surrounds the surface of the nanostack. The high-k dielectric layer may have a dielectric constant higher than about 6.0, and the high-k dielectric layer material may be HfO2 or HfSiO2. x HfON, HfSiON, HfAlO x Al2O3, ZrO2, ZrSiO x One or a combination of Ta2O5 or La2O3.

[0062] Next, a metal gate is deposited outside the high-k dielectric layer formed by the dummy gate 106, forming a multilayer high-k / metal gate structure. The metal gate includes a capping layer, a barrier layer, a work function layer, and a filler layer. Different effective work function film structures can be formed by selecting photolithography and etching to control the device threshold. Generally, processes such as chemical vapor deposition and physical vapor deposition are used to form the metal gate. The metal gate material is TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, or RuTa. x NiTa x MoN x , TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi x , Ni3Si, Pt, Ru, Ir, Mo, Ti, Al, Cr, Au, Cu, Ag, HfRu or RuO x One or more combinations. For example... Figure 11 As shown, the metal gate fills the space left after the removal of the dummy gate layer 106. Subsequently, the multilayer high-k / metal gate structure is chemically and mechanically polished to planarize it, and excess multilayer high-k / metal gate material exposed on the surface of the dielectric layer outside the dummy gate space is removed to form a high-k dielectric layer 115 and a metal gate 113, which fill the space of the original first semiconductor layer 201' to form a ring gate structure 113-1.

[0063] Next, ILD-1 dielectric deposition is performed on the top to form dielectric CMP layer 112. Contact hole photolithography and etching are performed on dielectric CMP layer 112 to deposit hole silicide 114 and bring out contact electrodes.

[0064] The subsequent process involves multi-layer back-end interconnection and passivation protection.

[0065] The above is the process flow for fabricating a complete semiconductor device, forming a structure as follows: Figure 11 The FET device shown.

[0066] In one embodiment, the FET can use silicon-on-insulator (SOI) as the substrate, and a superlattice stack can be epitaxially grown directly on the insulating layer SiO2. The remaining process flow is the same as the aforementioned FET process flow using bulk silicon as the substrate, and will not be repeated here. Replacing the substrate 101 with an SOI substrate can effectively suppress the substrate leakage current of the device.

[0067] This provides a FET device structure, such as... Figure 11The FET device includes a stack portion formed by a plurality of nanosheets 202 formed of a second semiconductor on a substrate 101.

[0068] For a P-type FET, the implanted element is B, In, Al or Ga for a SiGe horizontal nanosheet stack device; for an N-type FET, the implanted element is P, As or Sb for a Si horizontal nanosheet stack device.

[0069] A wrap-around gate surrounds the nanosheet stack portion; the wrap-around gate includes, from the inside out, an interface oxide layer (not labeled), a high-K dielectric layer 115 and a metal gate 113. The high-K dielectric layer surrounds the surface of the nanosheet stack portion; the high-K dielectric layer can have a dielectric constant higher than about 6.0, and the high-k dielectric layer material can be one or a combination of HfO2, HfSiO x , HfON, HfSiON, HfAlO x , Al2O3, ZrO2, ZrSiO x , Ta2O5 or La2O3.

[0070] The metal gate 113 is located within the high-K dielectric layer 115; the metal gate 113 can be a multi-layer structure, and the metal gate material can be one or a combination of TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa x , NiTa x , MoN x , TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi x , Ni3Si, Pt, Ru, Ir, Mo, Ti, Al, Cr, Au, Cu, Ag, HfRu or RuO x .

[0071] The technical solutions in the embodiments of the present application have at least the following technical effects or advantages:

[0072] The present application forms an SDE doped region by an inclined ion implantation after etching the inner side wall and before epitaxial growth of the source and drain, and then forms an SDE region with a steep, uniform distribution and a precisely controllable lateral junction depth after annealing the source and drain, thereby effectively controlling the effective channel length and avoiding a complex in-situ doping epitaxial process.

[0073] In the above description, the technical details of the patterning, etching, etc. of each layer are not described in detail. However, it should be understood by those skilled in the art that the layers, regions, etc. of desired shapes can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above to form the same structure. In addition, although each embodiment is described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0074] The embodiments of the present application are described above. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present application. The scope of the present application is defined by the appended claims and their equivalents. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present application, and all such substitutions and modifications should fall within the scope of the present application.

Claims

1. A method for fabricating a semiconductor device, characterized in that: Includes the following steps: Provide substrate; A superlattice stack consisting of alternating layers of a first semiconductor and a second semiconductor is epitaxially grown on the substrate; The superlattice stack is etched to form multiple fins; A false grid is formed on the fin, and the fin is etched. Selective etching is performed on the superlattice stack of the first semiconductor and the second semiconductor on the fin to form a nanosheet stack. Part of the nanosheet formed by the first semiconductor in the superlattice stack is etched away from the outside to the inside. Then, a third sidewall of silicon nitride is deposited on the outer periphery of the fin and etched until it is flush with the second semiconductor layer in the vertical direction. After etching, the fins are implanted with tilted ions to inject ions into the outer edge of the second semiconductor layer, forming an extended ion implantation layer for the source / drain region. The tilted implantation angle ranges from 5° to 45°, and the energy ranges from 0.1 keV to 100 keV. The source and drain regions are formed by epitaxial growth and then annealed at a temperature range of 500℃ to 1000℃. Dielectric deposition and planarization expose the dummy gate; To achieve channel release of nanosheets, wherein the stack of nanosheets forms multiple conductive channels; A surrounding gate is formed, encircling the nano-stack.

2. The method according to claim 1, characterized in that: The step of forming multiple fins specifically involves: setting a first sidewall on the superlattice stack; and etching the superlattice stack using the first sidewall as a mask to form the multiple fins.

3. The method according to claim 2, characterized in that: It also includes forming a shallow trench isolation area, specifically: generating a shallow trench isolation area between adjacent fins, such that the plurality of conductive channels are located above the shallow trench isolation area.

4. The method according to claim 3, characterized in that: The formation of the source / drain region specifically involves: etching away the fin structure between adjacent dummy gates to form a source / drain growth space; growing the source / drain region epitaxially outside the growth space; and depositing an isolation layer on the source / drain region.

5. The method according to claim 4, characterized in that: The specific steps for forming the all-around gate are as follows: after forming the source and drain regions, selective etching is used to remove the dummy gate, and after realizing the release of the nanosheet channel, the gate is deposited at the original dummy gate position.

6. The method according to claim 1, characterized in that: The first semiconductor is Si, and the second semiconductor is SiGe.

7. The method according to claim 1, characterized in that: The first semiconductor is SiGe, and the second semiconductor is Si.

8. The method according to claim 5, characterized in that: The surrounding gate comprises, from the outside to the inside, an interface oxide layer, a high-k dielectric layer, and a metal gate.

9. The method according to claim 1, characterized in that: For N-type semiconductor devices, the ion implantation element is P, As, or Sb; for P-type semiconductor devices, the implantation element is B, In, Al, or Ga.

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