A fast turn-on delay compensation circuit

Abstract

The present invention discloses a fast turn-on delay compensation circuit, which is applied to the receiving-end circuit of a series-series resonant wireless energy transfer system. The turn-on delay compensation circuit obtains the output signals of the first comparator, the second comparator, the third comparator, and the fourth comparator in the active rectifier circuit, and through the first logic circuit and the second logic circuit, generates the first compensation signal, the second compensation signal, the third compensation signal, and the fourth compensation signal based on digital logic control to compensate for the turn-on delay of the active rectifier circuit, thereby realizing fast turn-on of the turn-on delay compensation within one working cycle of the active rectifier circuit; and because the turn-on delay compensation only depends on digital logic control, the stability and anti-PVT variation characteristics of the turn-on delay compensation are improved, and further the accuracy of the turn-on delay compensation is improved. The present invention can be widely applied to the field of integrated circuits.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a fast turn-on delay compensation circuit. Background Art

[0002] Compared with magnetic induction wireless energy transmission, magnetic resonance wireless energy transmission has the advantages of long-distance power supply and one-to-many power supply. The relative position freedom between its transmitter and receiver is higher, and it will surely be widely used in the future wireless power supply market. Commonly used magnetic resonance wireless energy transmission systems include series-parallel resonance wireless energy transmission systems and series-series resonance wireless energy transmission systems, among which the series-series resonance wireless energy transmission system has more excellent stability.

[0003] For the receiver circuit of a series-series resonance wireless energy transmission system, a rectifier circuit for converting alternating current to direct current and a voltage stabilizing circuit are generally provided to achieve regulated power supply. In order to improve the rectification efficiency of the rectifier, an active rectifier bridge is generally used to replace the traditional passive rectifier bridge based on diodes. However, at higher operating frequencies, such as at frequencies of 6.78 MHz or 13.56 MHz, the turn-on delay and turn-off delay of the active diodes in the active rectifier bridge will become non-negligible, that is, the active diodes cannot be turned on or off in time, thereby affecting the rectification efficiency of the active rectifier bridge. Existing active diode delay compensation methods are all realized by introducing the offset voltage of a dynamic comparator. Currently, an automatic adjustment is generally carried out by using a sampling negative feedback mechanism to achieve a good delay compensation effect. In order to further improve the overall energy conversion efficiency of the receiver, the existing latest structure is to integrate the rectifier circuit and the voltage regulator circuit on a single stage, that is, to use the principle of a switched-mode voltage regulator to achieve single-stage rectification and voltage regulation. In the single-stage rectification and voltage regulation structure, the active diodes sometimes work and sometimes do not work, and the delay compensation for the active diodes also sometimes works and sometimes does not work. If a traditional sampling negative feedback-based delay compensation scheme is used in the single-stage rectification and voltage regulation structure, a sufficiently large loop bandwidth is required to achieve the fast turn-on of the delay compensation, but at the same time, the delay compensation accuracy will decrease accordingly. Summary of the Invention

[0004] To solve the above technical problems, an embodiment of the present invention provides a fast turn-on delay compensation circuit.

[0005] The technical solution adopted by the embodiment of the present invention is as follows:

[0006] A fast turn-on delay compensation circuit is applied to the receiver circuit of a series-series resonance wireless energy transmission system, and includes:

[0007] An active rectifier circuit includes a first comparator, a second comparator, a third comparator, and a fourth comparator. The first comparator is configured to output a first output signal, the second comparator is configured to output a second output signal, the third comparator is configured to output a third output signal, and the fourth comparator is configured to output a fourth output signal;

[0008] An on-delay compensation circuit is configured to obtain the first output signal, the second output signal, the third output signal, and the fourth output signal. The on-delay compensation circuit includes a first logic circuit and a second logic circuit. The first logic circuit is configured to generate a first compensation signal and a second compensation signal based on digital logic control according to the first output signal and the second output signal. The second logic circuit is configured to generate a third compensation signal and a fourth compensation signal based on digital logic control according to the third output signal and the fourth output signal; or, the first logic circuit is configured to generate the first compensation signal and the third compensation signal based on digital logic control according to the first output signal and the third output signal, and the second logic circuit is configured to generate the second compensation signal and the fourth compensation signal based on digital logic control according to the second output signal and the fourth output signal. The first compensation signal, the second compensation signal, the third compensation signal, and the fourth compensation signal are used to compensate for the on-delay of the active rectifier circuit.

[0009] As an alternative embodiment, the active rectifier circuit further includes a first buffer, a second buffer, a third buffer, a fourth buffer, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a ground terminal, an output terminal, and an AC input source. The AC input source is an equivalent input source that inputs the active rectifier circuit from the receiving-end circuit of a series-series resonant wireless power transfer system;

[0010] The output terminal of the first comparator is connected to the first input terminal of the turn-on delay compensation circuit. The first output terminal of the turn-on delay compensation circuit is connected to the input terminal of the first buffer. The output terminal of the first buffer is connected to the gate of the first PMOS transistor. The source of the first PMOS transistor is connected to the non-inverting input terminal of the first comparator. The non-inverting input terminal of the first comparator is connected to the output terminal. The output terminal is connected to the source of the second PMOS transistor. The source of the second PMOS transistor is connected to the non-inverting input terminal of the second comparator. The output terminal of the second comparator is connected to the second input terminal of the turn-on delay compensation circuit. The second output terminal of the turn-on delay compensation circuit is connected to the input terminal of the second buffer. The output terminal of the second buffer is connected to the gate of the second PMOS transistor. The drain of the second PMOS transistor is connected to the inverting input terminal of the second comparator. The inverting input terminal of the second comparator is connected to the second terminal of the AC input source. The second terminal of the AC input source is connected to the drain of the second NMOS transistor. The drain of the second NMOS transistor is connected to the inverting input terminal of the fourth comparator. The output terminal of the fourth comparator is connected to the fourth input terminal of the turn-on delay compensation circuit. The fourth output terminal of the turn-on delay compensation circuit is connected to the input terminal of the fourth buffer. The output terminal of the fourth buffer is connected to the gate of the second NMOS transistor. The source of the second NMOS transistor is connected to the non-inverting input terminal of the fourth comparator. The non-inverting input terminal of the fourth comparator is connected to the ground terminal. The ground terminal is connected to the source of the first NMOS transistor. The source of the first NMOS transistor is connected to the non-inverting input terminal of the third comparator. The output terminal of the third comparator is connected to the third input terminal of the turn-on delay compensation circuit. The third output terminal of the turn-on delay compensation circuit is connected to the input terminal of the third buffer. The output terminal of the third buffer is connected to the gate of the first NMOS transistor. The drain of the first NMOS transistor is connected to the inverting input terminal of the third comparator. The inverting input terminal of the third comparator is connected to the first terminal of the AC input source. The first terminal of the AC input source is connected to the drain of the first PMOS transistor. The drain of the first PMOS transistor is connected to the inverting input terminal of the first comparator.

[0011] As an optional implementation manner, the first logic circuit includes a first turn-on delay information acquisition module, a first turn-on delay information classification module, and a first turn-on delay compensation module;

[0012] The first turn-on delay information acquisition module obtains a first turn-on delay based on the first output signal and the second output signal. The first turn-on delay information classification module generates turn-on delay information for the second PMOS transistor based on the first turn-on delay and the rising edge signal of the first output signal. The first turn-on delay information classification module generates turn-on delay information for the first PMOS transistor based on the first turn-on delay and the rising edge signal of the second output signal. The first turn-on delay compensation module generates the first compensation signal based on the turn-on delay information of the first PMOS transistor and the first output signal. The first turn-on delay compensation module generates the second compensation signal based on the turn-on delay information of the second PMOS transistor and the second output signal.

[0013] As an optional implementation, the first turn-on delay information acquisition module includes a first NOT gate, a second NOT gate, and a first AND gate;

[0014] The input terminal of the first NOT gate is connected to the first input terminal of the turn-on delay compensation circuit. The output terminal of the first NOT gate is connected to the first input terminal of the first AND gate. The input terminal of the second NOT gate is connected to the second input terminal of the turn-on delay compensation circuit. The output terminal of the second NOT gate is connected to the second input terminal of the first AND gate. The output terminal of the first AND gate outputs the first turn-on delay;

[0015] The first turn-on delay information classification module includes a first rising edge signal acquisition module, a second rising edge signal acquisition module, a second AND gate, and a third AND gate;

[0016] The input terminal of the first rising edge signal acquisition module is connected to the first input terminal of the turn-on delay compensation circuit. The output terminal of the first rising edge signal acquisition module is connected to the first input terminal of the second AND gate. The first rising edge signal acquisition module outputs the rising edge signal of the first output signal. The second input terminal of the second AND gate is connected to the output terminal of the first AND gate. The output terminal of the second AND gate outputs the turn-on delay information of the second PMOS transistor. The input terminal of the second rising edge signal acquisition module is connected to the second input terminal of the turn-on delay compensation circuit. The output terminal of the second rising edge signal acquisition module is connected to the first input terminal of the third AND gate. The second rising edge signal acquisition module outputs the rising edge signal of the second output signal. The second input terminal of the third AND gate is connected to the output terminal of the first AND gate. The output terminal of the third AND gate outputs the turn-on delay information of the first PMOS transistor;

[0017] The first turn-on delay compensation module includes a third NOT gate, a fourth NOT gate, a fourth AND gate, and a fifth AND gate;

[0018] The input terminal of the third NOT gate is connected to the output terminal of the third AND gate. The output terminal of the third NOT gate is connected to the first input terminal of the fourth AND gate. The second input terminal of the fourth AND gate is connected to the first input terminal of the turn-on delay compensation circuit. The output terminal of the fourth AND gate is connected to the first output terminal of the turn-on delay compensation circuit. The output terminal of the fourth AND gate outputs the first compensation signal. The input terminal of the fourth NOT gate is connected to the output terminal of the second AND gate. The output terminal of the fourth NOT gate is connected to the first input terminal of the fifth AND gate. The second input terminal of the fifth AND gate is connected to the second input terminal of the turn-on delay compensation circuit. The output terminal of the fifth AND gate is connected to the second output terminal of the turn-on delay compensation circuit. The output terminal of the fifth AND gate outputs the second compensation signal.

[0019] As an optional implementation manner, the first logic circuit includes a second turn-on delay information acquisition module, a second turn-on delay information classification module, and a second turn-on delay compensation module.

[0020] The second turn-on delay information acquisition module obtains a second turn-on delay according to the first output signal and the third output signal. The second turn-on delay information classification module generates the turn-on delay information of the first PMOS transistor according to the second turn-on delay and the falling edge signal of the third output signal. The second turn-on delay information classification module generates the turn-on delay information of the first NMOS transistor according to the second turn-on delay and the rising edge signal of the first output signal. The second turn-on delay compensation module generates the first compensation signal according to the turn-on delay information of the first PMOS transistor and the first output signal. The second turn-on delay compensation module generates the second compensation signal according to the turn-on delay information of the first NMOS transistor and the third output signal.

[0021] As an optional implementation manner, the second turn-on delay information acquisition module includes a fifth NOT gate and a first NOR gate.

[0022] The input terminal of the fifth NOT gate is connected to the first input terminal of the turn-on delay compensation circuit. The output terminal of the fifth NOT gate is connected to the first input terminal of the first NOR gate. The second input terminal of the first NOR gate is connected to the third input terminal of the turn-on delay compensation circuit. The output terminal of the first NOR gate outputs the second turn-on delay.

[0023] The second turn-on delay information classification module includes a first rising edge signal acquisition module, a first falling edge signal acquisition module, a first NAND gate, and a sixth AND gate.

[0024] The input end of the first rising edge signal acquisition module is connected to the first input end of the turn-on delay compensation circuit. The output end of the first rising edge signal acquisition module is connected to the first input end of the sixth AND gate. The first rising edge signal acquisition module outputs the rising edge signal of the first output signal. The second input end of the sixth AND gate is connected to the output end of the first NOR gate. The output end of the sixth AND gate outputs the turn-on delay information of the first NMOS transistor. The input end of the first falling edge signal acquisition module is connected to the third input end of the turn-on delay compensation circuit. The output end of the first falling edge signal acquisition module is connected to the first input end of the first NAND gate. The first falling edge signal acquisition module outputs the falling edge signal of the third output signal. The second input end of the first NAND gate is connected to the output end of the first NOR gate. The output end of the first NAND gate outputs the turn-on delay information of the first PMOS transistor.

[0025] The second turn-on delay compensation module includes a first OR gate and a seventh AND gate.

[0026] The first input end of the seventh AND gate is connected to the output end of the first NAND gate. The second input end of the seventh AND gate is connected to the first input end of the turn-on delay compensation circuit. The output end of the seventh AND gate is connected to the first output end of the turn-on delay compensation circuit. The output end of the seventh AND gate outputs the first compensation signal. The first input end of the first OR gate is connected to the output end of the sixth AND gate. The second input end of the first OR gate is connected to the third input end of the turn-on delay compensation circuit. The output end of the first OR gate is connected to the third output end of the turn-on delay compensation circuit. The output end of the first OR gate outputs the third compensation signal.

[0027] As an optional implementation manner, the second logic circuit includes a third turn-on delay information acquisition module, a third turn-on delay information classification module, and a third turn-on delay compensation module.

[0028] The third turn-on delay information acquisition module obtains a third turn-on delay according to the third output signal and the fourth output signal. The third turn-on delay information classification module generates the turn-on delay information of the second NMOS transistor according to the third turn-on delay and the falling edge signal of the third output signal. The third turn-on delay information classification module generates the turn-on delay information of the first NMOS transistor according to the third turn-on delay and the falling edge signal of the fourth output signal. The third turn-on delay compensation module generates the third compensation signal according to the turn-on delay information of the first NMOS transistor and the third output signal. The third turn-on delay compensation module generates the fourth compensation signal according to the turn-on delay information of the second NMOS transistor and the fourth output signal.

[0029] As an alternative implementation, the third turn-on delay information acquisition module includes an eighth AND gate;

[0030] The first input terminal of the eighth AND gate is connected to the third input terminal of the turn-on delay compensation circuit, the second input terminal of the eighth AND gate is connected to the fourth input terminal of the turn-on delay compensation circuit, and the output terminal of the eighth AND gate outputs the third turn-on delay;

[0031] The third turn-on delay information classification module includes a first falling-edge signal acquisition module, a second falling-edge signal acquisition module, a ninth AND gate, and a tenth AND gate;

[0032] The input terminal of the first falling-edge signal acquisition module is connected to the third input terminal of the turn-on delay compensation circuit, the output terminal of the first falling-edge signal acquisition module is connected to the first input terminal of the ninth AND gate, the first falling-edge signal acquisition module outputs the falling-edge signal of the third output signal, the second input terminal of the ninth AND gate is connected to the output terminal of the eighth AND gate, and the output terminal of the ninth AND gate outputs the turn-on delay information of the second NMOS transistor; the input terminal of the second falling-edge signal acquisition module is connected to the fourth input terminal of the turn-on delay compensation circuit, the output terminal of the second falling-edge signal acquisition module is connected to the first input terminal of the tenth AND gate, the second falling-edge signal acquisition module outputs the falling-edge signal of the fourth output signal, the second input terminal of the tenth AND gate is connected to the output terminal of the eighth AND gate, and the output terminal of the tenth AND gate outputs the turn-on delay information of the first NMOS transistor;

[0033] The third turn-on delay compensation module includes a second OR gate and a third OR gate;

[0034] The first input terminal of the second OR gate is connected to the output terminal of the tenth AND gate, the second input terminal of the second OR gate is connected to the third input terminal of the turn-on delay compensation circuit, the output terminal of the second OR gate is connected to the third output terminal of the turn-on delay compensation circuit, and the output terminal of the second OR gate outputs the third compensation signal; the first input terminal of the third OR gate is connected to the output terminal of the ninth AND gate, the second input terminal of the third OR gate is connected to the fourth input terminal of the turn-on delay compensation circuit, the output terminal of the third OR gate is connected to the fourth output terminal of the turn-on delay compensation circuit, and the output terminal of the third OR gate outputs the fourth compensation signal.

[0035] As an alternative implementation, the second logic circuit includes a fourth turn-on delay information acquisition module, a fourth turn-on delay information classification module, and a fourth turn-on delay compensation module;

[0036] The fourth turn-on delay information acquisition module obtains a fourth turn-on delay according to the second output signal and the fourth output signal. The fourth turn-on delay information classification module generates turn-on delay information of the second PMOS transistor according to the fourth turn-on delay and the falling edge signal of the fourth output signal. The fourth turn-on delay information classification module generates turn-on delay information of the second NMOS transistor according to the fourth turn-on delay and the rising edge signal of the second output signal. The fourth turn-on delay compensation module generates the second compensation signal according to the turn-on delay information of the second PMOS transistor and the second output signal. The fourth turn-on delay compensation module generates the fourth compensation signal according to the turn-on delay information of the second NMOS transistor and the fourth output signal.

[0037] As an optional implementation manner, the fourth turn-on delay information acquisition module includes a sixth NOT gate and a second NOR gate;

[0038] The input end of the sixth NOT gate is connected to the second input end of the turn-on delay compensation circuit. The output end of the sixth NOT gate is connected to the first input end of the second NOR gate. The second input end of the second NOR gate is connected to the fourth input end of the turn-on delay compensation circuit. The output end of the second NOR gate outputs the fourth turn-on delay;

[0039] The fourth turn-on delay information classification module includes a second rising edge signal acquisition module, a second falling edge signal acquisition module, a second NAND gate, and an eleventh AND gate;

[0040] The input end of the second rising edge signal acquisition module is connected to the second input end of the turn-on delay compensation circuit. The output end of the second rising edge signal acquisition module is connected to the first input end of the eleventh AND gate. The second rising edge signal acquisition module outputs the rising edge signal of the second output signal. The second input end of the eleventh AND gate is connected to the output end of the second NOR gate. The output end of the eleventh AND gate outputs the turn-on delay information of the second NMOS transistor. The input end of the second falling edge signal acquisition module is connected to the fourth input end of the turn-on delay compensation circuit. The output end of the second falling edge signal acquisition module is connected to the first input end of the second NAND gate. The second falling edge signal acquisition module outputs the falling edge signal of the fourth output signal. The second input end of the second NAND gate is connected to the output end of the second NOR gate. The output end of the second NAND gate outputs the turn-on delay information of the second PMOS transistor;

[0041] The fourth turn-on delay compensation module includes a fourth OR gate and a twelfth AND gate;

[0042] The first input terminal of the twelfth AND gate is connected to the output terminal of the second NAND gate, the second input terminal of the twelfth AND gate is connected to the second input terminal of the turn-on delay compensation circuit, the output terminal of the twelfth AND gate is connected to the second output terminal of the turn-on delay compensation circuit, and the second compensation signal is output from the output terminal of the twelfth AND gate; the first input terminal of the fourth OR gate is connected to the output terminal of the eleventh AND gate, the second input terminal of the fourth OR gate is connected to the fourth input terminal of the turn-on delay compensation circuit, the output terminal of the fourth OR gate is connected to the fourth output terminal of the turn-on delay compensation circuit, and the fourth compensation signal is output from the output terminal of the fourth OR gate.

[0043] The fast turn-on delay compensation circuit according to the embodiment of the present invention is applied to the receiving-end circuit of a series-series resonant wireless energy transmission system. The turn-on delay compensation circuit obtains the output signals of the first comparator, the second comparator, the third comparator, and the fourth comparator in the active rectifier circuit, and through the first logic circuit and the second logic circuit, generates the first compensation signal, the second compensation signal, the third compensation signal, and the fourth compensation signal based on digital logic control to compensate for the turn-on delay of the active rectifier circuit, thereby realizing fast turn-on of the turn-on delay compensation within one working cycle of the active rectifier circuit; and because the turn-on delay compensation only depends on digital logic control, the stability and anti-PVT change characteristics of the turn-on delay compensation are improved, and further the accuracy of the turn-on delay compensation is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 is a circuit connection schematic diagram of the fast turn-on delay compensation circuit according to the embodiment of the present invention;

[0045] Figure 2 is a structural schematic diagram of the first logic circuit of the fast turn-on delay compensation circuit according to the embodiment of the present invention;

[0046] Figure 3 is a structural schematic diagram of the second logic circuit of the fast turn-on delay compensation circuit according to the embodiment of the present invention;

[0047] Figure 4 is a working principle diagram of the third turn-on delay information acquisition module of the fast turn-on delay compensation circuit according to the embodiment of the present invention;

[0048] Figure 5 is a working principle diagram of the third turn-on delay information classification module of the fast turn-on delay compensation circuit according to the embodiment of the present invention;

[0049] Figure 6 is a working principle diagram of the third turn-on delay compensation module of the fast turn-on delay compensation circuit according to the embodiment of the present invention;

[0050] Figure 7This is the transient response simulation diagram of the fast turn-on delay compensation circuit according to an embodiment of the present invention;

[0051] Figure 8 This is the post-simulation diagram of the turn-on delay compensation effect of the fast turn-on delay compensation circuit according to an embodiment of the present invention.

[0052] Reference numerals: CMP1, the first comparator; CMP2, the second comparator; CMP3, the third comparator; CMP4, the fourth comparator; B1, the first buffer; B2, the second buffer; B3, the third buffer; B4, the fourth buffer; I AC , AC input source; PV DD , output terminal; PV SS , ground terminal; PM L , the first PMOS transistor; PM R , the second PMOS transistor; NM L , the first NMOS transistor; NM R , the second NMOS transistor. Detailed implementation manners

[0053] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0054] The terms "first", "second", "third", and "fourth" in the specification and claims of the present application and the accompanying drawings thereof are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products, or devices.

[0055] Referring to "embodiment" herein means that a specific feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The phrase appears at various positions in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0056] For the receiving-end circuit of a series-series resonant wireless energy transfer system, a rectifier circuit for converting AC to DC and a voltage stabilizing circuit are generally provided to achieve regulated power supply. To improve the rectification efficiency of the rectifier, an active rectifier bridge is generally used to replace the traditional diode-based passive rectifier bridge. However, at higher operating frequencies, such as at frequencies of 6.78 MHz or 13.56 MHz, the turn-on delay and turn-off delay of the active diodes in the active rectifier bridge will become non-negligible, that is, the active diodes cannot turn on or off in time, thereby affecting the rectification efficiency of the active rectifier bridge. Existing active diode delay compensation methods are all achieved through the introduction of the offset voltage of a dynamic comparator. Currently, an automatic adjustment is generally performed using a sampling negative feedback mechanism to achieve a good delay compensation effect. To further improve the overall energy conversion efficiency of the receiving end, the existing latest structure is to integrate the rectifier circuit and the voltage regulator circuit on a single stage, that is, to use the principle of a switched-mode voltage regulator to achieve single-stage rectification and voltage regulation. In the single-stage rectification and voltage regulation structure, the active diodes sometimes work and sometimes do not work, and the delay compensation for the active diodes also sometimes works and sometimes does not work. If the traditional sampling negative feedback-based delay compensation scheme is used in the single-stage rectification and voltage regulation structure, a sufficiently large loop bandwidth is required to achieve the rapid turn-on of the delay compensation, but at the same time, the delay compensation accuracy will decrease accordingly. For this reason, the embodiments of the present invention propose a fast turn-on delay compensation circuit. The output signals of the first comparator, the second comparator, the third comparator, and the fourth comparator in the active rectifier circuit are obtained through the turn-on delay compensation circuit, and the first compensation signal, the second compensation signal, the third compensation signal, and the fourth compensation signal are generated based on digital logic control through the first logic circuit and the second logic circuit to compensate for the turn-on delay of the active rectifier circuit, thereby enabling the fast turn-on of the turn-on delay compensation within one operating cycle of the active rectifier circuit; and since the turn-on delay compensation only depends on digital logic control, the stability and anti-PVT variation characteristics of the turn-on delay compensation are improved, and thus the accuracy of the turn-on delay compensation is improved.

[0057] As Figure 1 shown, the embodiments of the present invention propose a fast turn-on delay compensation circuit, which is applied to the receiving-end circuit of a series-series resonant wireless energy transfer system and includes:

[0058] An active rectifier circuit, including a first comparator CMP1, a second comparator CMP2, a third comparator CMP3, and a fourth comparator CMP4. The first comparator CMP1 is used to output a first output signal, the second comparator CMP2 is used to output a second output signal, the third comparator CMP3 is used to output a third output signal, and the fourth comparator CMP4 is used to output a fourth output signal;

[0059] An enabling delay compensation circuit is used to obtain the first output signal, the second output signal, the third output signal, and the fourth output signal. The enabling delay compensation circuit includes a first logic circuit and a second logic circuit. The first logic circuit is configured to generate a first compensation signal and a second compensation signal based on digital logic control according to the first output signal and the second output signal. The second logic circuit is configured to generate a third compensation signal and a fourth compensation signal based on digital logic control according to the third output signal and the fourth output signal. Alternatively, the first logic circuit is configured to generate the first compensation signal and the third compensation signal based on digital logic control according to the first output signal and the third output signal. The second logic circuit is configured to generate the second compensation signal and the fourth compensation signal based on digital logic control according to the second output signal and the fourth output signal. The first compensation signal, the second compensation signal, the third compensation signal, and the fourth compensation signal are used to compensate for the enabling delay of the active rectifier circuit.

[0060] In an embodiment of the present invention, the active rectifier circuit further includes a first buffer B1, a second buffer B2, a third buffer B3, a fourth buffer B4, a first PMOS transistor PM L , a second PMOS transistor PM R , a first NMOS transistor NM L , a second NMOS transistor NM R , a ground terminal PV SS , an output terminal PV DD , and an AC input source I AC . The AC input source I AC is an equivalent input source of the receiving end circuit of the series - series resonant wireless energy transfer system input to the active rectifier circuit.

[0061] The output terminal of the first comparator CMP1 is connected to the first input terminal of the enabling delay compensation circuit. The first output terminal of the enabling delay compensation circuit is connected to the input terminal of the first buffer B1. The output terminal of the first buffer B1 is connected to the gate of the first PMOS transistor PM L . The source of the first PMOS transistor PM L is connected to the non - inverting input terminal of the first comparator CMP1. The non - inverting input terminal of the first comparator CMP1 is connected to the output terminal PV DD . The output terminal PV DD is connected to the source of the second PMOS transistor PM R . The source of the second PMOS transistor PM RThe source of is connected to the non-inverting input terminal of the second comparator CMP2. The output terminal of the second comparator CMP2 is connected to the second input terminal of the turn-on delay compensation circuit. The second output terminal of the turn-on delay compensation circuit is connected to the input terminal of the second buffer B2. The output terminal of the second buffer B2 is connected to the gate of the second PMOS transistor PM R The drain of the second PMOS transistor PM R is connected to the inverting input terminal of the second comparator CMP2. The inverting input terminal of the second comparator CMP2 is connected to the second terminal of the AC input source I AC The second terminal of the AC input source I AC is connected to the drain of the second NMOS transistor NM R The drain of the second NMOS transistor NM R is connected to the inverting input terminal of the fourth comparator CMP4. The output terminal of the fourth comparator CMP4 is connected to the fourth input terminal of the turn-on delay compensation circuit. The fourth output terminal of the turn-on delay compensation circuit is connected to the input terminal of the fourth buffer B4. The output terminal of the fourth buffer B4 is connected to the gate of the second NMOS transistor NM R The source of the second NMOS transistor NM R is connected to the non-inverting input terminal of the fourth comparator. The non-inverting input terminal of the fourth comparator CMP4 is connected to the ground terminal PV SS The ground terminal PV SS is connected to the source of the first NMOS transistor NM L The source of the first NMOS transistor NM L is connected to the non-inverting input terminal of the third comparator CMP3. The output terminal of the third comparator CMP3 is connected to the third input terminal of the turn-on delay compensation circuit. The third output terminal of the turn-on delay compensation circuit is connected to the input terminal of the third buffer B3. The output terminal of the third buffer B3 is connected to the gate of the first NMOS transistor NM L The drain of the first NMOS transistor NM L is connected to the inverting input terminal of the third comparator CMP3. The inverting input terminal of the third comparator CMP3 is connected to the first terminal of the AC input source I AC The first terminal of the AC input source I AC is connected to the drain of the first PMOS transistor PM L The drain of the first PMOS transistor PM L is connected to the inverting input terminal of the first comparator CMP1.

[0062] Among them, the AC input source I ACThe first end outputs an alternating current, and the alternating current input source is I AC The second end outputs an alternating current that is out of phase with the alternating current output from the first end. It can be understood that under the action of the alternating current output by the alternating current input source I AC In the ideal case (no turn-on delay), there are the following strong correlation relationships: When the active diode of the first PMOS transistor PM L is turned on, the active diode of the second PMOS transistor PM R is turned off. When the active diode of the first PMOS transistor PM L is turned off, the active diode of the second PMOS transistor PM R is turned on; When the active diode of the first NMOS transistor NM L is turned on, the active diode of the second NMOS transistor NM R is turned off. When the active diode of the first NMOS transistor NM L is turned off, the active diode of the second NMOS transistor NM R is turned on; When the active diode of the first PMOS transistor PM L is turned on, the active diode of the first NMOS transistor NM L is turned off. When the active diode of the first PMOS transistor PM L is turned off, the active diode of the first NMOS transistor NM L is turned on; When the active diode of the second PMOS transistor PM R is turned on, the active diode of the second NMOS transistor NM R is turned off. When the active diode of the second PMOS transistor PM R is turned off, the active diode of the second NMOS transistor NM R is turned on. In an embodiment of the present invention, according to the above strong correlation relationships, by using a turn-on delay compensation circuit, turn-on delay compensation of the active rectifier startup circuit is realized based on digital logic control.

[0063] A fast turn-on delay compensation circuit according to an embodiment of the present invention obtains the output signals of the first comparator CMP1, the second comparator CMP2, the third comparator CMP3, and the fourth comparator CMP4 in the active rectifier circuit through the turn-on delay compensation circuit, and generates a first compensation signal, a second compensation signal, a third compensation signal, and a fourth compensation signal based on digital logic control through the first logic circuit and the second logic circuit to compensate for the turn-on delay of the active rectifier circuit, thereby realizing fast turn-on of turn-on delay compensation within one working cycle of the active rectifier circuit; and since the turn-on delay compensation only depends on digital logic control, the stability and anti-PVT change characteristics of the turn-on delay compensation are improved, and further the accuracy of the turn-on delay compensation is improved.

[0064] Refer to Figure 2 As Figure 2As shown in (a), as an alternative embodiment, the first logic circuit includes a first turn-on delay information acquisition module, a first turn-on delay information classification module, and a first turn-on delay compensation module;

[0065] The first turn-on delay information acquisition module obtains a first turn-on delay according to the first output signal and the second output signal. The first turn-on delay information classification module generates turn-on delay information of the second PMOS transistor PM R according to the first turn-on delay and the rising edge signal of the first output signal. The first turn-on delay information classification module generates turn-on delay information of the first PMOS transistor PM L according to the first turn-on delay and the rising edge signal of the second output signal. The first turn-on delay compensation module generates the first compensation signal according to the turn-on delay information of the first PMOS transistor PM L and the first output signal. The first turn-on delay compensation module generates the second compensation signal according to the turn-on delay information of the second PMOS transistor PM R and the second output signal.

[0066] Among them, as an alternative embodiment, the first turn-on delay information acquisition module includes a first NOT gate, a second NOT gate, and a first AND gate;

[0067] The input end of the first NOT gate is connected to the first input end of the turn-on delay compensation circuit. The output end of the first NOT gate is connected to the first input end of the first AND gate. The input end of the second NOT gate is connected to the second input end of the turn-on delay compensation circuit. The output end of the second NOT gate is connected to the second input end of the first AND gate. The output end of the first AND gate outputs the first turn-on delay;

[0068] The first turn-on delay information classification module includes a first rising edge signal acquisition module, a second rising edge signal acquisition module, a second AND gate, and a third AND gate;

[0069] The input end of the first rising edge signal acquisition module is connected to the first input end of the turn-on delay compensation circuit. The output end of the first rising edge signal acquisition module is connected to the first input end of the second AND gate. The first rising edge signal acquisition module outputs the rising edge signal of the first output signal. The second input end of the second AND gate is connected to the output end of the first AND gate. The output end of the second AND gate outputs the turn-on delay information of the second PMOS transistor PM RThe turn-on delay information; the input end of the second rising edge signal acquisition module is connected to the second input end of the turn-on delay compensation circuit, the output end of the second rising edge signal acquisition module is connected to the first input end of the third AND gate, the second rising edge signal acquisition module outputs the rising edge signal of the second output signal, the second input end of the third AND gate is connected to the output end of the first AND gate, and the output end of the third AND gate outputs the first PMOS transistor PM L The turn-on delay information;

[0070] The first turn-on delay compensation module includes a third NOT gate, a fourth NOT gate, a fourth AND gate, and a fifth AND gate;

[0071] The input end of the third NOT gate is connected to the output end of the third AND gate, the output end of the third NOT gate is connected to the first input end of the fourth AND gate, the second input end of the fourth AND gate is connected to the first input end of the turn-on delay compensation circuit, the output end of the fourth AND gate is connected to the first output end of the turn-on delay compensation circuit, and the output end of the fourth AND gate outputs the first compensation signal; the input end of the fourth NOT gate is connected to the output end of the second AND gate, the output end of the fourth NOT gate is connected to the first input end of the fifth AND gate, the second input end of the fifth AND gate is connected to the second input end of the turn-on delay compensation circuit, the output end of the fifth AND gate is connected to the second output end of the turn-on delay compensation circuit, and the output end of the fifth AND gate outputs the second compensation signal.

[0072] Continue to refer to Figure 2 , as Figure 2 (b) shown, as an alternative embodiment, the first logic circuit includes a second turn-on delay information acquisition module, a second turn-on delay information classification module, and a second turn-on delay compensation module;

[0073] The second turn-on delay information acquisition module obtains a second turn-on delay according to the first output signal and the third output signal, and the second turn-on delay information classification module generates the turn-on delay information of the first PMOS transistor PM L according to the second turn-on delay and the falling edge signal of the third output signal, and the second turn-on delay information classification module generates the turn-on delay information of the first NMOS transistor NM L according to the second turn-on delay and the rising edge signal of the first output signal, and the second turn-on delay compensation module generates the first compensation signal according to the turn-on delay information of the first PMOS transistor PM L and the first output signal, and the second turn-on delay compensation module generates the second compensation signal according to the turn-on delay information of the first NMOS transistor NM L and the third output signal.

[0074] Wherein, as an optional implementation manner, the second turn-on delay information acquisition module includes a fifth NOT gate and a first NOR gate;

[0075] The input end of the fifth NOT gate is connected to the first input end of the turn-on delay compensation circuit, the output end of the fifth NOT gate is connected to the first input end of the first NOR gate, the second input end of the first NOR gate is connected to the third input end of the turn-on delay compensation circuit, and the output end of the first NOR gate outputs the second turn-on delay;

[0076] The second turn-on delay information classification module includes a first rising edge signal acquisition module, a first falling edge signal acquisition module, a first NAND gate and a sixth AND gate;

[0077] The input end of the first rising edge signal acquisition module is connected to the first input end of the turn-on delay compensation circuit, the output end of the first rising edge signal acquisition module is connected to the first input end of the sixth AND gate, the first rising edge signal acquisition module outputs the rising edge signal of the first output signal, the second input end of the sixth AND gate is connected to the output end of the first NOR gate, and the output end of the sixth AND gate outputs the turn-on delay information of the first NMOS transistor NM L The input end of the first falling edge signal acquisition module is connected to the third input end of the turn-on delay compensation circuit, the output end of the first falling edge signal acquisition module is connected to the first input end of the first NAND gate, the first falling edge signal acquisition module outputs the falling edge signal of the third output signal, the second input end of the first NAND gate is connected to the output end of the first NOR gate, and the output end of the first NAND gate outputs the turn-on delay information of the first PMOS transistor PM L ;

[0078] The second turn-on delay compensation module includes a first OR gate and a seventh AND gate;

[0079] The first input end of the seventh AND gate is connected to the output end of the first NAND gate, the second input end of the seventh AND gate is connected to the first input end of the turn-on delay compensation circuit, the output end of the seventh AND gate is connected to the first output end of the turn-on delay compensation circuit, and the output end of the seventh AND gate outputs the first compensation signal; the first input end of the first OR gate is connected to the output end of the sixth AND gate, the second input end of the first OR gate is connected to the third input end of the turn-on delay compensation circuit, the output end of the first OR gate is connected to the third output end of the turn-on delay compensation circuit, and the output end of the first OR gate outputs the third compensation signal.

[0080] Refer to Figure 3 As Figure 3As shown in (a), as an alternative embodiment, the second logic circuit includes a third turn-on delay information acquisition module, a third turn-on delay information classification module, and a third turn-on delay compensation module;

[0081] The third turn-on delay information acquisition module obtains a third turn-on delay based on the third output signal and the fourth output signal. The third turn-on delay information classification module generates turn-on delay information of the second NMOS transistor NM R based on the third turn-on delay and the falling edge signal of the third output signal, and the third turn-on delay information classification module generates turn-on delay information of the first NMOS transistor NM L based on the third turn-on delay and the falling edge signal of the fourth output signal. The third turn-on delay compensation module generates the third compensation signal based on the turn-on delay information of the first NMOS transistor NM L and the third output signal, and the third turn-on delay compensation module generates the fourth compensation signal based on the turn-on delay information of the second NMOS transistor NM R and the fourth output signal.

[0082] As an alternative embodiment, referring to Figure 4 , the third turn-on delay information acquisition module includes an eighth AND gate;

[0083] The first input terminal of the eighth AND gate is connected to the third input terminal of the turn-on delay compensation circuit, the second input terminal of the eighth AND gate is connected to the fourth input terminal of the turn-on delay compensation circuit, and the output terminal of the eighth AND gate outputs the third turn-on delay;

[0084] According to the above strong correlation relationship, when there is a turn-on delay in the active diode of the first NMOS transistor NM L and the active diode of the second NMOS transistor NM R , there is a situation of simultaneous turn-on and simultaneous turn-off between the active diode of the first NMOS transistor NM L and the active diode of the second NMOS transistor NM R . It can be understood that the part of the signal that is high (1) after the third output signal and the fourth output signal pass through the eighth AND gate is the turn-on delay of the active diode of the first NMOS transistor NM L and the active diode of the second NMOS transistor NM R , that is, the third turn-on delay.

[0085] It can be understood that due to the above strong correlation relationship, the active diode of the first NMOS transistor NM L and the active diode of the second NMOS transistor NM RThe turn-on delays of the active diodes occur alternately. Therefore, the first NMOS transistor NM is separated from the active diodes of the second NMOS transistor NM by the third turn-on delay information classification module. L and the active diodes of the second NMOS transistor NM R in terms of their turn-on delays.

[0086] Referring to Figure 5 , the third turn-on delay information classification module includes a first falling-edge signal acquisition module, a second falling-edge signal acquisition module, a ninth AND gate, and a tenth AND gate;

[0087] The input end of the first falling-edge signal acquisition module is connected to the third input end of the turn-on delay compensation circuit. The output end of the first falling-edge signal acquisition module is connected to the first input end of the ninth AND gate. The first falling-edge signal acquisition module outputs the falling-edge signal of the third output signal. The second input end of the ninth AND gate is connected to the output end of the eighth AND gate. The output end of the ninth AND gate outputs the turn-on delay information of the second NMOS transistor NM R ; the input end of the second falling-edge signal acquisition module is connected to the fourth input end of the turn-on delay compensation circuit. The output end of the second falling-edge signal acquisition module is connected to the first input end of the tenth AND gate. The second falling-edge signal acquisition module outputs the falling-edge signal of the fourth output signal. The second input end of the tenth AND gate is connected to the output end of the eighth AND gate. The output end of the tenth AND gate outputs the turn-on delay information of the first NMOS transistor NM L .

[0088] Referring to Figure 6 , the third turn-on delay compensation module includes a second OR gate and a third OR gate;

[0089] The first input end of the second OR gate is connected to the output end of the tenth AND gate. The second input end of the second OR gate is connected to the third input end of the turn-on delay compensation circuit. The output end of the second OR gate is connected to the third output end of the turn-on delay compensation circuit. The output end of the second OR gate outputs the third compensation signal. The first input end of the third OR gate is connected to the output end of the ninth AND gate. The second input end of the third OR gate is connected to the fourth input end of the turn-on delay compensation circuit. The output end of the third OR gate is connected to the fourth output end of the turn-on delay compensation circuit. The output end of the third OR gate outputs the fourth compensation signal.

[0090] Continuing to refer to Figure 3 , as Figure 3 (b) shows, as an alternative implementation, the second logic circuit includes a fourth turn-on delay information acquisition module, a fourth turn-on delay information classification module, and a fourth turn-on delay compensation module;

[0091] The fourth turn-on delay information acquisition module obtains a fourth turn-on delay based on the second output signal and the fourth output signal. The fourth turn-on delay information classification module generates turn-on delay information of the second PMOS transistor PM based on the fourth turn-on delay and the falling edge signal of the fourth output signal. R The fourth turn-on delay information classification module generates turn-on delay information of the second NMOS transistor NM based on the fourth turn-on delay and the rising edge signal of the second output signal. R The fourth turn-on delay compensation module generates the second compensation signal based on the turn-on delay information of the second PMOS transistor PM R and the second output signal. The fourth turn-on delay compensation module generates the fourth compensation signal based on the turn-on delay information of the second NMOS transistor NM R and the fourth output signal.

[0092] As an optional implementation manner, the fourth turn-on delay information acquisition module includes a sixth NOT gate and a second NOR gate;

[0093] The input end of the sixth NOT gate is connected to the second input end of the turn-on delay compensation circuit. The output end of the sixth NOT gate is connected to the first input end of the second NOR gate. The second input end of the second NOR gate is connected to the fourth input end of the turn-on delay compensation circuit. The output end of the second NOR gate outputs the fourth turn-on delay;

[0094] The fourth turn-on delay information classification module includes a second rising edge signal acquisition module, a second falling edge signal acquisition module, a second NAND gate, and an eleventh AND gate;

[0095] The input end of the second rising edge signal acquisition module is connected to the second input end of the turn-on delay compensation circuit. The output end of the second rising edge signal acquisition module is connected to the first input end of the eleventh AND gate. The second rising edge signal acquisition module outputs the rising edge signal of the second output signal. The second input end of the eleventh AND gate is connected to the output end of the second NOR gate. The output end of the eleventh AND gate outputs the turn-on delay information of the second NMOS transistor NM R The input end of the second falling edge signal acquisition module is connected to the fourth input end of the turn-on delay compensation circuit. The output end of the second falling edge signal acquisition module is connected to the first input end of the second NAND gate. The second falling edge signal acquisition module outputs the falling edge signal of the fourth output signal. The second input end of the second NAND gate is connected to the output end of the second NOR gate. The output end of the second NAND gate outputs the turn-on delay information of the second PMOS transistor PM R ;

[0096] The second turn-on delay compensation module includes a fourth OR gate and a twelfth AND gate;

[0097] The first input terminal of the twelfth AND gate is connected to the output terminal of the second NAND gate, the second input terminal of the twelfth AND gate is connected to the second input terminal of the turn-on delay compensation circuit, the output terminal of the twelfth AND gate is connected to the second output terminal of the turn-on delay compensation circuit, and the second compensation signal is output from the output terminal of the twelfth AND gate; the first input terminal of the fourth OR gate is connected to the output terminal of the eleventh AND gate, the second input terminal of the fourth OR gate is connected to the fourth input terminal of the turn-on delay compensation circuit, the output terminal of the fourth OR gate is connected to the fourth output terminal of the turn-on delay compensation circuit, and the fourth compensation signal is output from the output terminal of the fourth OR gate.

[0098] Figure 7 It is a transient response simulation diagram of the fast turn-on delay compensation circuit of the embodiment of the present invention applied to the 0X / 1X switched single-stage rectifier voltage regulator structure. According to Figure 7 It can be seen that the fast turn-on delay compensation circuit of the embodiment of the present invention has a fast transient response during the change from 0X to 1X and can complete good compensation for the turn-on delay within one cycle.

[0099] Figure 8 It is a post-simulation diagram of the turn-on delay compensation effect of the fast turn-on delay compensation circuit of the embodiment of the present invention. According to Figure 8 It can be seen that the conduction time of the body diode of the active diode drops from the original 9.876 ns to 1.381 ns, and the body diode time decreases significantly. It can be understood that the compensated delay is mainly the delay of the layout wiring and the digital logic circuit. Therefore, the fast turn-on delay compensation circuit of the embodiment of the present invention also has good anti-PVT characteristics.

[0100] The above is a specific description of the preferred embodiment of the present invention, but the present invention is not limited to the above embodiment. Those skilled in the art can make various equivalent deformations or substitutions without departing from the spirit of the present invention, and these equivalent deformations or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A fast - turn - on delay compensation circuit, which is applied to the receiving - end circuit of a series - series resonant wireless energy transfer system, and is characterized in that, Comprising: An active rectifier circuit, including a first comparator, a second comparator, a third comparator, and a fourth comparator, where the first comparator is used to output a first output signal, the second comparator is used to output a second output signal, the third comparator is used to output a third output signal, and the fourth comparator is used to output a fourth output signal; An on-delay compensation circuit, configured to obtain the first output signal, the second output signal, the third output signal, and the fourth output signal. The on-delay compensation circuit includes a first logic circuit and a second logic circuit. The first logic circuit is configured to generate a first compensation signal and a second compensation signal based on digital logic control according to the first output signal and the second output signal. The second logic circuit is configured to generate a third compensation signal and a fourth compensation signal based on digital logic control according to the third output signal and the fourth output signal; alternatively, the first logic circuit is configured to generate the first compensation signal and the third compensation signal based on digital logic control according to the first output signal and the third output signal, and the second logic circuit is configured to generate the second compensation signal and the fourth compensation signal based on digital logic control according to the second output signal and the fourth output signal. The first compensation signal, the second compensation signal, the third compensation signal, and the fourth compensation signal are used to compensate for the on-delay of the active rectifier circuit; The active rectifier circuit further includes a first buffer, a second buffer, a third buffer, a fourth buffer, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a ground terminal, an output terminal, and an AC input source. The AC input source is an equivalent input source that inputs the active rectifier circuit from the receiving-end circuit of a series-series resonant wireless energy transfer system; The output terminal of the first comparator is connected to the first input terminal of the turn-on delay compensation circuit. The first output terminal of the turn-on delay compensation circuit is connected to the input terminal of the first buffer. The output terminal of the first buffer is connected to the gate of the first PMOS transistor. The source of the first PMOS transistor is connected to the non-inverting input terminal of the first comparator. The non-inverting input terminal of the first comparator is connected to the output terminal. The output terminal is connected to the source of the second PMOS transistor. The source of the second PMOS transistor is connected to the non-inverting input terminal of the second comparator. The output terminal of the second comparator is connected to the second input terminal of the turn-on delay compensation circuit. The second output terminal of the turn-on delay compensation circuit is connected to the input terminal of the second buffer. The output terminal of the second buffer is connected to the gate of the second PMOS transistor. The drain of the second PMOS transistor is connected to the inverting input terminal of the second comparator. The inverting input terminal of the second comparator is connected to the second terminal of the AC input source. The second terminal of the AC input source is connected to the drain of the second NMOS transistor. The drain of the second NMOS transistor is connected to the inverting input terminal of the fourth comparator. The output terminal of the fourth comparator is connected to the fourth input terminal of the turn-on delay compensation circuit. The fourth output terminal of the turn-on delay compensation circuit is connected to the input terminal of the fourth buffer. The output terminal of the fourth buffer is connected to the gate of the second NMOS transistor. The source of the second NMOS transistor is connected to the non-inverting input terminal of the fourth comparator. The non-inverting input terminal of the fourth comparator is connected to the ground terminal. The ground terminal is connected to the source of the first NMOS transistor. The source of the first NMOS transistor is connected to the non-inverting input terminal of the third comparator. The output terminal of the third comparator is connected to the third input terminal of the turn-on delay compensation circuit. The third output terminal of the turn-on delay compensation circuit is connected to the input terminal of the third buffer. The output terminal of the third buffer is connected to the gate of the first NMOS transistor. The drain of the first NMOS transistor is connected to the inverting input terminal of the third comparator. The inverting input terminal of the third comparator is connected to the first terminal of the AC input source. The first terminal of the AC input source is connected to the drain of the first PMOS transistor. The drain of the first PMOS transistor is connected to the inverting input terminal of the first comparator.

2. The fast - turn - on delay compensation circuit according to claim 1, characterized in that, The first logic circuit includes a first turn-on delay information acquisition module, a first turn-on delay information classification module, and a first turn-on delay compensation module; The first turn-on delay information acquisition module obtains a first turn-on delay based on the first output signal and the second output signal. The first turn-on delay information classification module generates the turn-on delay information of the second PMOS transistor according to the first turn-on delay and the rising edge signal of the first output signal. The first turn-on delay information classification module generates the turn-on delay information of the first PMOS transistor according to the first turn-on delay and the rising edge signal of the second output signal. The first turn-on delay compensation module generates the first compensation signal according to the turn-on delay information of the first PMOS transistor and the first output signal. The first turn-on delay compensation module generates the second compensation signal according to the turn-on delay information of the second PMOS transistor and the second output signal.

3. The fast - turn - on delay compensation circuit according to claim 2, characterized in that, The first turn-on delay information acquisition module includes a first NOT gate, a second NOT gate, and a first AND gate; The input terminal of the first NOT gate is connected to the first input terminal of the turn-on delay compensation circuit. The output terminal of the first NOT gate is connected to the first input terminal of the first AND gate. The input terminal of the second NOT gate is connected to the second input terminal of the turn-on delay compensation circuit. The output terminal of the second NOT gate is connected to the second input terminal of the first AND gate. The output terminal of the first AND gate outputs the first turn-on delay; The first turn-on delay information classification module includes a first rising edge signal acquisition module, a second rising edge signal acquisition module, a second AND gate, and a third AND gate; The input terminal of the first rising edge signal acquisition module is connected to the first input terminal of the turn-on delay compensation circuit. The output terminal of the first rising edge signal acquisition module is connected to the first input terminal of the second AND gate. The first rising edge signal acquisition module outputs the rising edge signal of the first output signal. The second input terminal of the second AND gate is connected to the output terminal of the first AND gate. The output terminal of the second AND gate outputs the turn-on delay information of the second PMOS transistor. The input terminal of the second rising edge signal acquisition module is connected to the second input terminal of the turn-on delay compensation circuit. The output terminal of the second rising edge signal acquisition module is connected to the first input terminal of the third AND gate. The second rising edge signal acquisition module outputs the rising edge signal of the second output signal. The second input terminal of the third AND gate is connected to the output terminal of the first AND gate. The output terminal of the third AND gate outputs the turn-on delay information of the first PMOS transistor; The first turn-on delay compensation module includes a third NOT gate, a fourth NOT gate, a fourth AND gate, and a fifth AND gate; The input terminal of the third NOT gate is connected to the output terminal of the third AND gate. The output terminal of the third NOT gate is connected to the first input terminal of the fourth AND gate. The second input terminal of the fourth AND gate is connected to the first input terminal of the turn-on delay compensation circuit. The output terminal of the fourth AND gate is connected to the first output terminal of the turn-on delay compensation circuit. The output terminal of the fourth AND gate outputs the first compensation signal. The input terminal of the fourth NOT gate is connected to the output terminal of the second AND gate. The output terminal of the fourth NOT gate is connected to the first input terminal of the fifth AND gate. The second input terminal of the fifth AND gate is connected to the second input terminal of the turn-on delay compensation circuit. The output terminal of the fifth AND gate is connected to the second output terminal of the turn-on delay compensation circuit. The output terminal of the fifth AND gate outputs the second compensation signal.

4. The fast - turn - on delay compensation circuit according to claim 1, characterized in that, The first logic circuit includes a second turn-on delay information acquisition module, a second turn-on delay information classification module, and a second turn-on delay compensation module. The second turn-on delay information acquisition module obtains a second turn-on delay based on the first output signal and the third output signal. The second turn-on delay information classification module generates the turn-on delay information of the first PMOS transistor based on the second turn-on delay and the falling edge signal of the third output signal. The second turn-on delay information classification module generates the turn-on delay information of the first NMOS transistor based on the second turn-on delay and the rising edge signal of the first output signal. The second turn-on delay compensation module generates the first compensation signal based on the turn-on delay information of the first PMOS transistor and the first output signal. The second turn-on delay compensation module generates the second compensation signal based on the turn-on delay information of the first NMOS transistor and the third output signal.

5. The fast - turn - on delay compensation circuit according to claim 4, characterized in that, The second turn-on delay information acquisition module includes a fifth NOT gate and a first NOR gate. The input terminal of the fifth NOT gate is connected to the first input terminal of the turn-on delay compensation circuit. The output terminal of the fifth NOT gate is connected to the first input terminal of the first NOR gate. The second input terminal of the first NOR gate is connected to the third input terminal of the turn-on delay compensation circuit. The output terminal of the first NOR gate outputs the second turn-on delay. The second turn-on delay information classification module includes a first rising edge signal acquisition module, a first falling edge signal acquisition module, a first NAND gate, and a sixth AND gate. The input end of the first rising edge signal acquisition module is connected to the first input end of the turn-on delay compensation circuit. The output end of the first rising edge signal acquisition module is connected to the first input end of the sixth AND gate. The first rising edge signal acquisition module outputs the rising edge signal of the first output signal. The second input end of the sixth AND gate is connected to the output end of the first NOR gate. The output end of the sixth AND gate outputs the turn-on delay information of the first NMOS transistor. The input end of the first falling edge signal acquisition module is connected to the third input end of the turn-on delay compensation circuit. The output end of the first falling edge signal acquisition module is connected to the first input end of the first NAND gate. The first falling edge signal acquisition module outputs the falling edge signal of the third output signal. The second input end of the first NAND gate is connected to the output end of the first NOR gate. The output end of the first NAND gate outputs the turn-on delay information of the first PMOS transistor. The second turn-on delay compensation module includes a first OR gate and a seventh AND gate. The first input end of the seventh AND gate is connected to the output end of the first NAND gate. The second input end of the seventh AND gate is connected to the first input end of the turn-on delay compensation circuit. The output end of the seventh AND gate is connected to the first output end of the turn-on delay compensation circuit. The output end of the seventh AND gate outputs the first compensation signal. The first input end of the first OR gate is connected to the output end of the sixth AND gate. The second input end of the first OR gate is connected to the third input end of the turn-on delay compensation circuit. The output end of the first OR gate is connected to the third output end of the turn-on delay compensation circuit. The output end of the first OR gate outputs the third compensation signal.

6. The fast - turn - on delay compensation circuit according to claim 1, characterized in that, The second logic circuit includes a third turn-on delay information acquisition module, a third turn-on delay information classification module, and a third turn-on delay compensation module. The third turn-on delay information acquisition module obtains the third turn-on delay according to the third output signal and the fourth output signal. The third turn-on delay information classification module generates the turn-on delay information of the second NMOS transistor according to the third turn-on delay and the falling edge signal of the third output signal. The third turn-on delay information classification module generates the turn-on delay information of the first NMOS transistor according to the third turn-on delay and the falling edge signal of the fourth output signal. The third turn-on delay compensation module generates the third compensation signal according to the turn-on delay information of the first NMOS transistor and the third output signal. The third turn-on delay compensation module generates the fourth compensation signal according to the turn-on delay information of the second NMOS transistor and the fourth output signal.

7. The fast - turn - on delay compensation circuit according to claim 6, characterized in that, The third turn-on delay information acquisition module includes an eighth AND gate. The first input end of the eighth AND gate is connected to the third input end of the turn-on delay compensation circuit. The second input end of the eighth AND gate is connected to the fourth input end of the turn-on delay compensation circuit. The output end of the eighth AND gate outputs the third turn-on delay. The third turn-on delay information classification module includes a first falling-edge signal acquisition module, a second falling-edge signal acquisition module, a ninth AND gate, and a tenth AND gate; The input end of the first falling-edge signal acquisition module is connected to the third input end of the turn-on delay compensation circuit. The output end of the first falling-edge signal acquisition module is connected to the first input end of the ninth AND gate. The first falling-edge signal acquisition module outputs the falling-edge signal of the third output signal. The second input end of the ninth AND gate is connected to the output end of the eighth AND gate. The output end of the ninth AND gate outputs the turn-on delay information of the second NMOS transistor. The input end of the second falling-edge signal acquisition module is connected to the fourth input end of the turn-on delay compensation circuit. The output end of the second falling-edge signal acquisition module is connected to the first input end of the tenth AND gate. The second falling-edge signal acquisition module outputs the falling-edge signal of the fourth output signal. The second input end of the tenth AND gate is connected to the output end of the eighth AND gate. The output end of the tenth AND gate outputs the turn-on delay information of the first NMOS transistor; The third turn-on delay compensation module includes a second OR gate and a third OR gate; The first input end of the second OR gate is connected to the output end of the tenth AND gate. The second input end of the second OR gate is connected to the third input end of the turn-on delay compensation circuit. The output end of the second OR gate is connected to the third output end of the turn-on delay compensation circuit. The output end of the second OR gate outputs the third compensation signal. The first input end of the third OR gate is connected to the output end of the ninth AND gate. The second input end of the third OR gate is connected to the fourth input end of the turn-on delay compensation circuit. The output end of the third OR gate is connected to the fourth output end of the turn-on delay compensation circuit. The output end of the third OR gate outputs the fourth compensation signal.

8. A fast turn-on delay compensation circuit according to claim 1, wherein, The second logic circuit includes a fourth turn-on delay information acquisition module, a fourth turn-on delay information classification module, and a fourth turn-on delay compensation module; The fourth turn-on delay information acquisition module obtains a fourth turn-on delay according to the second output signal and the fourth output signal. The fourth turn-on delay information classification module generates the turn-on delay information of the second PMOS transistor according to the fourth turn-on delay and the falling-edge signal of the fourth output signal. The fourth turn-on delay information classification module generates the turn-on delay information of the second NMOS transistor according to the fourth turn-on delay and the rising-edge signal of the second output signal. The fourth turn-on delay compensation module generates the second compensation signal according to the turn-on delay information of the second PMOS transistor and the second output signal. The fourth turn-on delay compensation module generates the fourth compensation signal according to the turn-on delay information of the second NMOS transistor and the fourth output signal.

9. A fast turn-on delay compensation circuit according to claim 8, wherein, The fourth turn-on delay information acquisition module includes a sixth NOT gate and a second NOR gate; The input terminal of the sixth NOT gate is connected to the second input terminal of the turn-on delay compensation circuit, the output terminal of the sixth NOT gate is connected to the first input terminal of the second NOR gate, the second input terminal of the second NOR gate is connected to the fourth input terminal of the turn-on delay compensation circuit, and the output terminal of the second NOR gate outputs the fourth turn-on delay; The fourth turn-on delay information classification module includes a second rising edge signal acquisition module, a second falling edge signal acquisition module, a second NAND gate, and an eleventh AND gate; The input terminal of the second rising edge signal acquisition module is connected to the second input terminal of the turn-on delay compensation circuit, the output terminal of the second rising edge signal acquisition module is connected to the first input terminal of the eleventh AND gate, the second rising edge signal acquisition module outputs the rising edge signal of the second output signal, the second input terminal of the eleventh AND gate is connected to the output terminal of the second NOR gate, and the output terminal of the eleventh AND gate outputs the turn-on delay information of the second NMOS transistor; The input terminal of the second falling edge signal acquisition module is connected to the fourth input terminal of the turn-on delay compensation circuit, the output terminal of the second falling edge signal acquisition module is connected to the first input terminal of the second NAND gate, the second falling edge signal acquisition module outputs the falling edge signal of the fourth output signal, the second input terminal of the second NAND gate is connected to the output terminal of the second NOR gate, and the output terminal of the second NAND gate outputs the turn-on delay information of the second PMOS transistor; The fourth turn-on delay compensation module includes a fourth OR gate and a twelfth AND gate; The first input terminal of the twelfth AND gate is connected to the output terminal of the second NAND gate, the second input terminal of the twelfth AND gate is connected to the second input terminal of the turn-on delay compensation circuit, the output terminal of the twelfth AND gate is connected to the second output terminal of the turn-on delay compensation circuit, and the output terminal of the twelfth AND gate outputs the second compensation signal; the first input terminal of the fourth OR gate is connected to the output terminal of the eleventh AND gate, the second input terminal of the fourth OR gate is connected to the fourth input terminal of the turn-on delay compensation circuit, the output terminal of the fourth OR gate is connected to the fourth output terminal of the turn-on delay compensation circuit, and the output terminal of the fourth OR gate outputs the fourth compensation signal.

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