Sensor devices and distance measuring devices

Abstract

The sensor device according to the present invention includes: a first chip having a first semiconductor substrate and a first wiring layer and having a pixel configured to include a photoelectric conversion element; a first transmission gate element and a second transmission gate element for transmitting stored charge of the photoelectric conversion element; and a second chip having a second semiconductor substrate and a second wiring layer. The sensor device further includes a first wire electrically connected to the first transmission gate element, a second wire electrically connected to the second transmission gate element, and a third wire electrically connected to ground, wherein each of the first, second, and third wires is formed by bonding a first portion formed on the first wiring layer and extending in a first direction and a second portion formed on the second wiring layer and extending in the first direction.

Description

Technical Field

[0001] This technology relates to a sensor device and a distance measuring device that includes the sensor device and measures the distance to an object, and more particularly to wire technology in the sensor device, the sensor device including a pixel, the pixel including a photoelectric conversion element, and a first transmission gate element and a second transmission gate element configured to transmit the accumulated charge of the photoelectric conversion element. Background Technology

[0002] Various distance measurement techniques for measuring distances to objects are known, and in recent years, distance measurement techniques based on the Time-of-Flight (ToF) method have attracted attention. ToF methods are broadly classified into direct ToF methods and indirect ToF methods. Direct ToF methods calculate distance based on measuring the round-trip time of light emitted to the object using a time-to-digital converter (TDC). Indirect ToF methods, on the other hand, calculate distance based on the amount of light received from the object without measuring the round-trip time of the light, as described above.

[0003] In the sensor device used in the indirect Time-of-Flight (ToF) method, reflected light from the object is converted by a photoelectric conversion element, such as a photodiode. The signal charge obtained through photoelectric conversion is distributed to two floating diffusers (floating diffuser regions) through a pair of alternately conducting transmission gate elements.

[0004] In the indirect ToF method, the charge distribution described above is repeated a predetermined number of times, such as several thousand times, in a predetermined light receiving cycle, and thus the distance is calculated based on the difference between the respective signal charges accumulated in the two floating diffusions.

[0005] In addition, as relevant prior art, the following patent document 1 can be cited.

[0006] Reference List

[0007] Patent documents

[0008] Patent Document 1: Japanese Patent Application Publication No. 2009-8537 Summary of the Invention

[0009] The problem to be solved by the present invention

[0010] Here, as in the sensor device used in the indirect ToF method described above, in a sensor device where charge is distributed to two floating diffusers by two transmission gate elements provided for photoelectric conversion elements, for example, if the two transmission gate elements do not operate accurately, the charge distribution to each floating diffuser cannot be properly performed, resulting in a deterioration in ranging performance.

[0011] In view of the above, this technology is proposed, and the purpose of this technology is to improve the accuracy of operation and the distance measurement performance of sensor devices used for distance measurement, such as by indirect ToF methods.

[0012] Solution to the problem

[0013] The sensor device according to the present technology includes: a first chip including a first semiconductor substrate and a first wiring layer and including a pixel, the pixel including a photoelectric conversion element; a first transmission gate element and a second transmission gate element configured to transmit accumulated charge of the photoelectric conversion element; and a second chip including a second semiconductor substrate and a second wiring layer, wherein a first wire electrically connected to the first transmission gate element, a second wire electrically connected to the second transmission gate element, and a third wire electrically connected to ground are formed, and each of the first wire, the second wire and the third wire is formed by joining a first portion formed in the first wiring layer and extending in a first direction and a second portion formed in the second wiring layer and extending in the first direction.

[0014] According to the above configuration, the first wire for the first transmission gate element, the second wire for the second transmission gate element, and the third wire, which serves as a ground wire, are together formed as inter-chip bonding wires for bonding the first chip and the second chip. That is, by forming the first wire, the second wire, and the third wire with wires of the same type as the inter-chip bonding wires, the wire resistances can be made equal.

[0015] In the sensor device according to the present technology described above, it is conceivable to employ a configuration in which the sensor device measures distance using an indirect time-of-flight (ToF) method.

[0016] In the indirect ToF method, the accumulated charge of the photoelectric conversion element is distributed to two floating diffusers through a first transmission gate element and a second transmission gate element.

[0017] In the sensor device according to the present technology described above, it is conceivable to adopt a configuration in which the first part and the second part are connected to each other by copper-copper (Cu-Cu) connections, wherein the first wire, the second wire and the third wire are respectively connected to each other by copper-copper (Cu-Cu) connections.

[0018] From the perspective of performance track record and reliability, Cu-Cu interconnect is the preferred interconnect technology between chips.

[0019] In the sensor device according to the present technology described above, it is conceivable to adopt a configuration in which the first wire and the second wire are arranged symmetrically with a photoelectric conversion element between them.

[0020] Therefore, the first intermediate wire connecting the first transmission gate element and the first wire, and the second intermediate wire connecting the second transmission gate element and the second wire, can have equal wire lengths and equal wire resistances.

[0021] In the sensor device according to the present technology described above, it is conceivable to adopt a configuration in which the first wire, the second wire, and the third wire have substantially the same line width.

[0022] This allows for the equalization of the individual wire resistances of the first, second, and third wires.

[0023] In the sensor device according to the present technology described above, it is conceivable to adopt a configuration in which the cross-sectional areas of the first wire, the second wire, and the third wire are substantially the same.

[0024] This allows for the equalization of the individual wire resistances of the first, second, and third wires.

[0025] In the sensor device according to the present technology described above, it is conceivable to employ a configuration in which at least a portion of the first wire overlaps with the first transmission gate element and at least a portion of the second wire overlaps with the second transmission gate element in a direction perpendicular to the stacking direction of the first chip and the second chip.

[0026] Therefore, for each of the first intermediate wire connecting the first wire and the first transmission gate element, and the second intermediate wire connecting the second wire and the second transmission gate element, it is not necessary to route in a direction perpendicular to the aforementioned stacking direction, and the wire resistance of the two wires can be reduced. Furthermore, the inter-wire capacitance with adjacent wires can also be reduced.

[0027] In the sensor device according to the present technology described above, it is conceivable to employ a configuration in which a first wire and a first transmission gate element, as well as a second wire and a second transmission gate element, are connected by a connection portion including one or more through holes and extending substantially linearly in the stacking direction.

[0028] Therefore, the lengths of the first intermediate wire connecting the first wire and the first transmission gate element and the second intermediate wire connecting the second wire and the second transmission gate element can be set to correspond to the length of the spacing distance between the first wire and the first transmission gate element in the stacking direction and the length of the spacing distance between the second wire and the second transmission gate element in the stacking direction, and the wire resistance of the first and second intermediate wires and the inter-line capacitance with adjacent wires can be minimized.

[0029] In the sensor device according to the present technology described above, it is conceivable to adopt a configuration in which the interval between the first wire and the third wire adjacent to the first wire is substantially equal to the interval between the second wire and the third wire adjacent to the second wire.

[0030] As a result, the inter-line capacitance between the first and third conductors (parasitic capacitance acting on the first conductor) becomes substantially equal to the inter-line capacitance between the second and third conductors (parasitic capacitance acting on the second conductor), the passivation of the driving waveforms of the first and second transmission gate elements does not become unbalanced, and the charge distribution to the two floating diffusions can be accurately performed.

[0031] In the sensor device according to the present technology described above, it is conceivable to adopt the following configuration: in a first wiring forming layer, a conductor layer and an intermediate conductor layer other than the conductor layer are formed, a first portion of the first conductor, the second conductor and the third conductor are formed in the conductor layer, and at least a portion of the third conductor overlaps with the pixel in a direction perpendicular to the stacking direction of the first chip and the second chip, and the third conductor is connected to an intermediate ground conductor in the pixel, the intermediate ground conductor being a conductor formed in the intermediate conductor layer and connected to ground in the pixel.

[0032] This allows for an increase in the cross-sectional area of ​​the third conductor (grounding conductor).

[0033] Furthermore, the distance measuring device according to the present technology includes: a light-emitting unit that emits illumination light onto an object; and a sensor unit that receives reflected light from the illumination light from the object; wherein the sensor unit includes a first chip, the first chip including a first semiconductor substrate and a first wiring layer and including a pixel, the pixel including a photoelectric conversion element and a first transmission gate element and a second transmission gate element configured to transmit accumulated charge of the photoelectric conversion element, and a second chip including a second semiconductor substrate and a second wiring layer, forming a first wire electrically connected to the first transmission gate element, a second wire electrically connected to the second transmission gate element, and a third wire electrically connected to ground, and each of the first wire, the second wire and the third wire is formed by joining a first portion formed in the first wiring layer and extending in a first direction and a second portion formed in the second wiring layer and extending in the first direction.

[0034] Using this distance measuring device, operation similar to that of the sensor device according to the present technology can also be obtained. Attached Figure Description

[0035] Figure 1 This is a block diagram illustrating a configuration example of a distance measuring device according to an embodiment of the present technology.

[0036] Figure 2 This is a block diagram illustrating an example of the internal circuit configuration of a sensor device (sensor unit) as an implementation.

[0037] Figure 3 It is an equivalent circuit diagram of the pixels included in the sensor device as an implementation.

[0038] Figure 4 This is a top view showing a schematic structure of pixels according to an embodiment.

[0039] Figure 5 This is a cross-sectional view showing a schematic structure of a pixel according to an embodiment.

[0040] Figure 6 This is a schematic cross-sectional view showing the chip structure of a sensor device as an embodiment.

[0041] Figure 7 This is an illustration of how wires are used to connect chips.

[0042] Figure 8 It is the equivalent circuit diagram of the circuit system related to the driving of transmission gate elements.

[0043] Figure 9 It is a graph showing the waveform images of the transmission drive signal and the ground potential.

[0044] Figure 10 This is a cross-sectional view used to illustrate the chip-to-chip bonding method of this embodiment.

[0045] Figure 11 This is a diagram illustrating an example of the arrangement of inter-chip bonding wires in a pixel array unit.

[0046] Figure 12 It is used to explain and Figure 11 The diagram shows a schematic cross-sectional structure of the sensor unit corresponding to the example arrangement of the wires shown.

[0047] Figure 13 This is an explanatory diagram of a first variation related to the arrangement of bonding wires between chips.

[0048] Figure 14 This is an explanatory diagram of a second variation related to the arrangement of bonding wires between chips.

[0049] Figure 15 This is an explanatory diagram of a third variation related to the arrangement of bonding wires between chips. Detailed Implementation

[0050] In the following description, embodiments according to the present technology will be described in the following order with reference to the accompanying drawings.

[0051] <1. Configuration of Distance Measuring Device>

[0052] <2. Circuit Configuration of Sensor Unit>

[0053] <3. Circuit configuration of pixel array unit>

[0054] <4. Structure of the sensor unit>

[0055] <5. Chip-to-chip bonding according to the implementation method>

[0056] <6. Variations related to the arrangement of bonding wires between chips>

[0057] <7. Other variations>

[0058] <8. Summary of Implementation Methods>

[0059] <9. This technology>

[0060] <1. Configuration of Distance Measuring Device>

[0061] Figure 1 This is a block diagram used to describe a configuration example of a distance measuring device 10 as an embodiment of the present technology.

[0062] The distance measuring device 10 includes a sensor unit 1, a light-emitting unit 2, a control unit 3, a distance image processing unit 4, and a memory 5. The distance measuring device 10 is a device that performs distance measurement using the time-of-flight (ToF) method. Specifically, the distance measuring device 10 of this example performs distance measurement using an indirect ToF method. The indirect ToF method is a distance measurement method that calculates the distance to an object Ob based on the phase difference between the illumination light Li directed at the object Ob and the reflected light Lr obtained by reflecting the illumination light Li back to the object Ob.

[0063] The light-emitting unit 2 includes one or more light-emitting elements that serve as a light source, and emits illumination light Li towards the object Ob. In this example, the light-emitting unit 2 emits infrared light, for example, with a wavelength in the range of 780 nm to 1000 nm, as the illumination light Li.

[0064] Control unit 3 controls the emission operation of illumination light Li using light-emitting unit 2. In the case of the indirect ToF method, light whose intensity is modulated such that the intensity changes at a predetermined period is used as illumination light Li. Specifically, in this example, pulsed light is repeatedly emitted as illumination light Li at a predetermined period. In the following, this emission period of the pulsed light is referred to as the "emission period Cl". Furthermore, when pulsed light is repeatedly emitted at the emission period Cl, the time interval between the start timing of the light emission of the pulsed light is referred to as "one modulation period Pm" or simply "modulation period Pm".

[0065] The control unit 3 controls the light emission operation of the light emission unit 2 so that it emits illumination light Li only during a predetermined light emission period in each modulation period Pm.

[0066] Here, in the indirect ToF method, the emission period Cl is relatively fast in the range of approximately tens to hundreds of MHz.

[0067] Sensor unit 1 receives the reflected light Lr and outputs ranging information based on the phase difference between the reflected light Lr and the illumination light Li using the indirect ToF method.

[0068] As will be described later, the sensor unit 1 of this example includes a pixel array unit 11 in which a plurality of pixels Px are arranged in two dimensions, including a photoelectric conversion element (photodiode PD), a first transmission gate element (transmission transistor TG-A) and a second transmission gate element (transmission transistor TG-B) for transmitting the accumulated charge of the photoelectric conversion element, and distance measurement information is obtained for each pixel Px by an indirect ToF method.

[0069] It should be noted that, in the following text, the information representing the distance measurement information (distance information) for each pixel Px as described above is referred to as the "distance image".

[0070] Here, as is known, in the indirect ToF method, the signal charge accumulated in the photoelectric conversion element in pixel Px is distributed to two floating diffusers (FDs) through alternately turned-on first and second transmission gate elements. The period during which the first and second transmission gate elements are alternately turned on is the same as the emission period Cl of the light-emitting unit 2. That is, each of the first and second transmission gate elements is turned on once in each modulation period Pm, and the distribution of signal charge to the two floating diffusers as described above is repeated in each modulation period Pm.

[0071] In this example, the transmission transistor TG-A, which serves as the first transmission gate element, is turned on during the emission period of the illumination light Li in the modulation period Pm, and the transmission transistor TG-B, which serves as the second transmission gate element, is turned on during the non-emission period of the illumination light Li in the modulation period Pm.

[0072] As described above, because the emission cycle Cl is relatively fast, the signal charge accumulated in each floating diffuser is relatively small by using the first and second transmission gate elements as described above. Therefore, in the indirect ToF method, the emission of illumination light Li is repeated approximately several thousand to tens of thousands of times for each distance measurement (i.e., when acquiring a distance image of an image), and sensor unit 1 repeatedly distributes the signal charge to each floating diffuser using the first and second transmission gate elements as described above, while illumination light Li is repeatedly emitted in this manner.

[0073] As understood from the above description, in sensor unit 1, the first and second transmission gate elements are driven at a timing synchronized with the emission period of the illumination light Li in each pixel Px. Therefore, a synchronization signal Ss indicating the timing synchronized with the emission period Cl is input from control unit 3 to sensor unit 1 and is used to drive the first and second transmission gate elements in each pixel Px.

[0074] In the distance image processing unit 4, the distance image obtained by the sensor unit 1 is input, for example, and subjected to predetermined signal processing such as compression encoding, and then output to the memory 5.

[0075] For example, memory 5 is a storage device such as flash memory, solid-state drive (SSD) or hard disk drive (HDD), and stores distance images processed by distance image processing unit 4.

[0076] <2. Circuit Configuration of Sensor Unit>

[0077] Figure 2 This is a block diagram illustrating an example of the internal circuit configuration of sensor unit 1.

[0078] As shown in the figure, the sensor unit 1 includes a pixel array unit 11, a transmission gate driving unit 12, a vertical driving unit 13, a system control unit 14, a column processing unit 15, a horizontal driving unit 16, a signal processing unit 17, and a data storage unit 18.

[0079] The pixel array unit 11 has a configuration of multiple pixels Px arranged in a matrix two-dimensionally in the row and column directions. Each pixel Px includes a photodiode PD, described later, as a photoelectric conversion element. It should be noted that reference will be made to... Figure 3 Let's describe the details of pixel Px again.

[0080] Here, the row direction refers to the horizontal arrangement of pixels Px, and the column direction refers to the vertical arrangement of pixels Px. In the accompanying drawings, the row direction is the horizontal direction, and the column direction is the vertical direction.

[0081] It should be noted that in this example, the pixel spacing of the pixels Px in the pixel array unit 11 is 5.0 μm or less. Specifically, in this example, the pixel spacing of the pixels Px is approximately 3.5 μm.

[0082] In pixel array unit 11, relative to the matrix-like pixel array, pixel driving lines 20 are wired along the row direction of each pixel row, and two gate driving lines 21 and two vertical signal lines 22 are wired along the column direction of each pixel column. For example, pixel driving lines 20 transmit driving signals for performing driving when reading signals from pixel Px. Note that in Figure 2In the diagram, the pixel driving line 20 is shown as a line, but is not limited to a line. One end of the pixel driving line 20 is connected to the output terminal corresponding to each row of the vertical driving unit 13.

[0083] The system control unit 14 includes a timing generator that generates various timing signals, and performs drive control of the transmission gate drive unit 12, vertical drive unit 13, column processing unit 15, horizontal drive unit 16, etc. based on the various timing signals generated by the timing generator.

[0084] The transmission gate driving unit 12, under the control of the system control unit 14, drives two transmission gate elements disposed in each pixel Px through two gate driving lines 21 disposed in each pixel column as described above.

[0085] As described above, the two transmission gate elements are alternately switched on in each modulation period Pm. Therefore, the system control unit 14 is based on Figure 1 The synchronization signal Ss described herein controls the on / off timing of the two transmission gate elements through the transmission gate drive unit 12.

[0086] The vertical drive unit 13 includes a shift register, an address decoder, etc., and drives all pixels or rows of pixels in the pixel array unit 11 simultaneously. That is, the vertical drive unit 13, together with the system control unit 14 that controls the vertical drive unit 13, constitutes a drive unit that controls the operation of each pixel Px in the pixel array unit 11.

[0087] The detection signal is output (read) from each pixel Px of the pixel row according to the drive control of the vertical drive unit 13. Specifically, the signal corresponding to the signal charge accumulated in each of the two floating diffusers provided in each pixel Px is input to the column processing unit 15 through the corresponding vertical signal line 22. The column processing unit 15 performs predetermined signal processing on the detection signal read from each pixel Px through the vertical signal line 22, and temporarily holds the detection signal after the signal processing. Specifically, the column processing unit 15 performs noise removal processing, analog-to-digital (A / D) conversion processing, etc. as signal processing.

[0088] Here, for each predetermined number of repetitions of illumination Li (the repetitions of several thousand to tens of thousands of times mentioned above), two detection signals (detection signals for each floating diffusion) are read from each pixel Px.

[0089] Therefore, the system control unit 14 also controls the vertical drive unit 13 based on the synchronization signal Ss used for timing the reading of the detection signal from each pixel Px.

[0090] The horizontal driving unit 16 includes a shift register, an address decoder, etc., and sequentially selects the unit circuits corresponding to the pixel columns of the column processing unit 15. Through the selective scanning of the horizontal driving unit 16, the detection signals that have undergone signal processing in each unit circuit of the column processing unit 15 are output sequentially.

[0091] The signal processing unit 17 has at least arithmetic processing capabilities and performs various types of signal processing based on the detection signal output from the column processing unit 15, such as distance calculation processing corresponding to the indirect ToF method. Note that known methods can be used to calculate distance information based on two types of detection signals (detection signals of each floating diffusion) for each pixel Px using the indirect ToF method, and their description will be omitted here.

[0092] Data storage unit 18 temporarily stores the data required for signal processing in signal processing unit 17.

[0093] The sensor unit 1 configured as described above outputs a distance image indicating the distance to object Ob for each pixel Px. The distance measuring device 10 including such a sensor unit 1 can be applied, for example, to an in-vehicle system that is installed on a vehicle and measures the distance to an object Ob outside the vehicle, or to a gesture recognition device that measures the distance to an object such as a user's hand and recognizes the user's gesture based on the measurement results.

[0094] <3. Circuit configuration of pixel array unit>

[0095] Figure 3 The equivalent circuit of a pixel Px arranged in two dimensions in pixel array unit 11 is shown.

[0096] Pixel Px includes a photodiode PD and an overflow (OF) gate transistor OFG as photoelectric conversion elements. In addition, pixel Px includes two of each of the following as transmission gate elements: a transmission transistor TG, a floating diffuser FD, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL.

[0097] Here, as Figure 3 As shown, when two transmission transistors TG, floating diffuser FD, reset transistor RST, amplification transistor AMP, and selection transistor SEL are respectively set in pixel Px and distinguished from each other, they are represented as transmission transistors TG-A and TG-B, floating diffuser FD-A and FD-B, reset transistor RST-A and RST-B, amplification transistor AMP-A and RST-B, and selection transistor SEL-A and SEL-B.

[0098] The gate transistor OFG, transfer transistor TG, reset transistor RST, amplification transistor AMP, and select transistor SEL include, for example, N-type MOS transistors.

[0099] When the OF gate signal SOFG supplied to the gate is turned on, the OF gate transistor OFG turns on. When the OF gate transistor OFG is turned on, the photodiode PD is clamped at a predetermined reference potential VDD, and the accumulated charge is reset.

[0100] It should be noted that the OF gate signal SOFG is provided, for example, from the vertical drive unit 13.

[0101] When the transfer drive signal STG-A supplied to the gate is turned on, the transfer transistor TG-A is turned on, and the signal charge accumulated in the photodiode PD is transferred to the floating diffuser FD-A. When the transfer drive signal STG-B supplied to the gate is turned on, the transfer transistor TG-B becomes turned on, and the charge accumulated in the photodiode PD is transferred to the floating diffuser FD-B.

[0102] Transmission drive signals STG-A and STG-B are transmitted from the transmission gate drive unit 12 via... Figure 2 Gate driving lines 21-A and 21-B, one of the gate driving lines 21 shown, are supplied.

[0103] Floating diffusers FD-A and FD-B are charge retention units that temporarily retain the charge transferred from the photodiode PD.

[0104] When the reset signal SRST supplied to the gate is turned on, the reset transistor RST-A turns on, resetting the potential of the floating diffuser FD-A to the reference potential VDD. Similarly, when the reset signal SRST supplied to the gate is turned on, the reset transistor RST-B turns on, resetting the potential of the floating diffuser FD-B to the reference potential VDD.

[0105] It should be noted that, for example, a reset signal SRST is supplied from the vertical drive unit 13.

[0106] Amplifying transistor AMP-A has a source connected to vertical signal line 22-A via select transistor SEL-A and a drain connected to reference potential VDD (constant current source) to form a source follower circuit. Amplifying transistor AMP-B has a source connected to vertical signal line 22-B via select transistor SEL-B and a drain connected to reference potential VDD (constant current source) to form a source follower circuit.

[0107] Here, each of the vertical signal lines 22-A and 22-B is set to Figure 2 One of the vertical signal lines 22 shown.

[0108] The select transistor SEL-A is connected between the source of the amplifier transistor AMP-A and the vertical signal line 22-A. When the select signal SSEL supplied to the gate is turned on, it becomes on and outputs the charge held in the floating diffuser FD-A to the vertical signal line 22-A via the amplifier transistor AMP-A.

[0109] The select transistor SEL-B is connected between the source of the amplifying transistor AMP-B and the vertical signal line 22-B. It becomes on when the select signal SSEL supplied to the gate is turned on, and outputs the charge held in the floating diffuser FD-B to the vertical signal line 22-B via the amplifying transistor AMP-A.

[0110] It should be noted that the selection signal SSEL is provided from the vertical drive unit 13 via the pixel drive line 20.

[0111] The operation of pixel Px will be briefly described.

[0112] First, before light reception begins, a reset operation is performed in all pixels to reset the charge in pixel Px. That is, for example, the OF gate transistor OFG, each reset transistor RST, and each transmission transistor TG are turned on (in the on state), and the accumulated charge in the photodiode PD and each floating diffuser FD is reset.

[0113] After resetting the accumulated charge, the optical receiving operation for ranging begins in all pixels. The optical receiving operation described here refers to performing one distance measurement. That is, during the optical receiving operation, the alternating conduction of transmission transistors TG-A and TG-B is repeated a predetermined number of times (in this example, approximately several thousand to tens of thousands of times). Hereinafter, the period of this optical receiving operation for distance measurement will be referred to as the "optical receiving period Pr".

[0114] In the light receiving cycle Pr, within a modulation cycle Pm of the light-emitting unit 2, for example, after the period in which the transmission transistor TG-A is turned on (i.e., the period in which the transmission transistor TG-B is turned off) continuously illuminates the light Li during the light-emitting cycle, the remaining period (i.e., the non-light-emitting period illuminating the light Li) is the period in which the transmission transistor TG-B is turned on (i.e., the period in which the transmission transistor TG-A is turned off). That is, in the light receiving cycle Pr, the operation of distributing the charge of the photodiode PD to the floating diffusers FD-A and FD-B is repeated a predetermined number of times in a modulation cycle Pm.

[0115] Furthermore, at the end of the light receiving cycle Pr, each pixel Px of the pixel array unit 11 is selected row by row. In the selected pixel Px, selection transistors SEL-A and SEL-B are turned on. Therefore, the charge accumulated in the floating diffuser FD-A is output to the column processing unit 15 via the vertical signal line 22-A. In addition, the charge accumulated in the floating diffuser FD-B is output to the column processing unit 15 via the vertical signal line 22-B.

[0116] As described above, an optical receiving operation ends, and the next optical receiving operation, which begins with the reset operation, is executed.

[0117] Here, the reflected light received by pixel Px is delayed based on the timing of the illumination light Li emitted from the light-emitting unit 2 and the distance to the object Ob. The distribution ratio of the charge accumulated in the two floating diffusers FD-A and FD-B changes according to the delay time and the distance to the object Ob. Therefore, the distance to the object Ob can be obtained from the distribution ratio of the charge accumulated in the two floating diffusers FD-I and FD-B.

[0118] <4. Structure of the sensor unit>

[0119] Reference Figures 4 to 6 Describe the structure of sensor unit 1.

[0120] Figure 4 and Figure 5 This is a view illustrating a schematic structure of pixel Px, specifically showing the positional relationship between the photodiode PD, OF gate transistor OFG, transport transistors TG-A and TG-B, and floating diffusers FD-A and FD-B formed in a region of pixel Px in a semiconductor substrate. Figure 4 It's a top view. Figure 5 It is along Figure 4 The diagram shows a cross-sectional view taken by line X-X'. Note that in... Figure 4 and Figure 5 The diagram omits pixel transistors such as the reset transistor RST and the amplification transistor AMP.

[0121] The photodiode PD is formed inside the semiconductor substrate, and when viewed from above, it has a roughly rectangular shape, located approximately in the center of the pixel Px. Here, "in-plane" refers to a plane parallel to the aforementioned horizontal (row) and vertical (column) directions. Note that the horizontal direction corresponds to... Figure 4 and 5 The horizontal direction on the paper. The vertical direction corresponds to... Figure 4 The longitudinal direction on the surface of the paper.

[0122] Transmission transistors TG-A and TG-B are formed on a semiconductor substrate and have a substantially rectangular shape in a top view. The positions of transmission transistors TG-A and TG-B in the plane are close to corresponding end portions of the photodiode PD in either the horizontal or vertical direction. Specifically, in this example, the position of each of the transmission transistors TG-A and TG-B in the plane overlaps with corresponding end portions of the photodiode PD in the horizontal direction (the lateral direction on the paper). The positions of transmission transistors TG-A and TG-B in the vertical direction are substantially aligned with each other.

[0123] Floating diffusers FD-A and FD-B are formed inside the semiconductor substrate and have a generally rectangular shape in a top view. As described above, the floating diffuser FD-A is positioned in the plane to partially overlap with the outer end-side portion of the transmission transistor TG-A (i.e., the end-side portion opposite to the end-side portion overlapping with the photodiode PD). Similarly, the floating diffuser FD-B is positioned in the plane to partially overlap with the outer end-side portion of the transmission transistor TG-B (the end-side portion opposite to the end-side portion overlapping with the photodiode PD). The floating diffusers FD-A and FD-B are substantially aligned with each other in the vertical direction.

[0124] The OF gate transistor (OFG) is formed on a semiconductor substrate and has a generally rectangular shape in a top view. Its position in the plane is such that it partially overlaps with the non-overlapping end portions of the four end portions of the photodiode PD with those of the transfer transistors TG-A and TG-B. That is, in this example, the photodiode PD is positioned to overlap with one end portion of the two end portions of the photodiode PD in the vertical direction.

[0125] Figure 6 This is a schematic cross-sectional view showing the chip structure of sensor unit 1.

[0126] Sensor unit 1 has a structure that bonds a first chip Cp1 and a second chip Cp2 together. The first chip Cp1 is on top. Figure 2 The chip forming the pixel array unit 11 is one of the components of the sensor unit 1 shown. The second chip Cp2 is a chip in which circuit units other than the pixel array unit 11 (i.e., circuit units for pixel driving as the transmission gate driving unit 12, vertical driving unit 13, system control unit 14, column processing unit 15 and horizontal driving unit 16) and circuit units for distance calculation as the signal processing unit 17 and data storage unit 18 are formed.

[0127] The first chip Cp1 includes a first semiconductor substrate Bs1 and a first wiring forming layer Ar1 stacked on the first semiconductor substrate Bs1. The first semiconductor substrate Bs1 and Figure 4 and Figure 5 Corresponding to the semiconductor substrate shown. The first wiring forming layer Ar1 is a layer in which various wires are formed, and is formed by stacking multiple wire layers.

[0128] The second chip Cp2 includes a second semiconductor substrate Bs2 and a second wiring forming layer Ar2 stacked on the second semiconductor substrate Bs2. The second wiring forming layer Ar2 is a layer that forms various wires similarly to the first wiring forming layer Ar1, and is formed by stacking multiple wire layers.

[0129] The sensor unit 1 is formed by bonding the first chip Cp1 and the second chip Cp2 in opposite directions by first wiring forming layer Ar1 of the first chip Cp1 and second wiring forming layer Ar2 of the second chip Cp2.

[0130] <5. Chip-to-chip bonding according to the implementation method>

[0131] In this embodiment, the first chip Cp1 and the second chip Cp2 are joined by connecting the wires formed on the first wiring layer Ar1 and the wires formed on the second wiring layer Ar2.

[0132] Figure 7 This is an explanatory diagram of the chip using this wire bonding method, and schematically shows the state of the cross-section of the region corresponding to a pixel Px in the sensor unit 1.

[0133] In this diagram, inter-chip bonding wires W21-A and W21-B are wires used to bond the first chip Cp1 and the second chip Cp2. Inter-chip bonding wire W21-A forms the gate drive line 21-A for providing the transmission drive signal STG-A to the transmission transistor TG-A (see figure). Figure 3 As part of the chip bonding wire W21-B, a portion of the gate drive line 21-B is formed to provide the transmission drive signal STG-B to the transmission transistor TG-B.

[0134] Inter-chip bonding wire W21-A is formed by joining a first portion p1-A formed in the first wiring forming layer Ar1 of the first chip Cp1 and a second portion p2-A formed in the second wiring forming layer Ar2 of the second chip Cp2. Inter-chip bonding wire W21-B is formed by joining a first portion p1-B formed in the first wiring forming layer Ar1 and a second portion p2-B formed in the second wiring forming layer Ar2.

[0135] In this example, copper-copper bonding (Cu-Cu bonding) is used as the inter-chip bonding technique via inter-chip bonding wires W21-A and W21-B. Cu-Cu bonding is a technique that joins conductive materials containing Cu formed on each chip to ensure electrical conduction between these conductive materials and to achieve physical bonding between the chips.

[0136] Here, in sensor unit 1 at the current stage of development, such as Figure 7 The inter-chip bonding wires W21-A and 21-B shown are applied only to the gate drive lines 21-A and 21-B as wires for bonding the chips, while conventional local and intermediate wires are applied to the ground side wires (Vss wires). Here, the local and intermediate wires are wires formed in a different layer than the layer in the first wiring layer Ar1 where the inter-chip bonding wires are formed. Local lines refer to lines completed within pixels Px, and intermediate lines refer to lines formed between pixels Px.

[0137] In inter-chip bonding wires, the width and cross-sectional area of ​​the wires are much larger than those of local and intermediate wires to ensure bonding strength. Therefore, as described above, when only inter-chip bonding wires are applied to the gate drive lines 21-A and 21-B, a line resistance difference (impedance mismatch) occurs between the drive signal line side and the ground line side of the transmission transistor TG, and the ground potential becomes unstable due to the line resistance difference.

[0138] Figure 8 This is the equivalent circuit diagram of the circuit system related to the driving of the transmission transistor TG.

[0139] exist Figure 8 In the diagram, the boundary between the first chip Cp1 and the second chip Cp2 is schematically represented by a dashed line. A transmission drive signal STG for driving the transmission transistor TG is generated in the transmission drive signal generation circuit (transmission gate drive unit 12) located on the second chip Cp2 side.

[0140] As shown in the equivalent circuit diagram, the capacitance, which serves as the transfer gate capacitance, is generated in the transfer transistor TG. Therefore, as described above, due to the difference in wire resistance between the drive signal line and the ground line—specifically, as shown in the figure, the drive signal line has a lower wire resistance and the ground line has a higher wire resistance—the voltage on the drive signal line side momentarily decreases when the transfer transistor TG is turned off, and simultaneously, charge remains in the transfer gate capacitance. Consequently, on the ground line side, due to the influence of the remaining charge, the ground potential shifts from 0V to the negative side.

[0141] Figure 9 It is a waveform image showing the changes in voltage and ground potential of the transmission drive signals STG-A and STG-B at this time.

[0142] As described above, the ground potential shifts towards the negative side and becomes unstable. Consequently, the voltages of the transmission drive signals STG-A and STG-B also change relatively, reducing the accuracy of the operation of the transmission transistors TG-A and TG-B. Because the transmission transistors TG-A and TG-B do not operate precisely, the accuracy of the charge distribution operation to the two floating diffusers FD-A and FD-B is also impaired, thus leading to a deterioration in ranging performance.

[0143] Therefore, in this embodiment, as Figure 10 As shown in the cross-sectional view, the inter-chip bonding wires are also applied to the ground wire side. It should be noted that... Figure 10 The schematic diagram illustrates the state of a cross-section corresponding to a region of pixel Px in sensor unit 1, as described above. Figure 7 resemblance.

[0144] In the sensor unit 1 of this embodiment, the inter-chip bonding wire Wg in the attached figure is configured as an inter-chip bonding wire electrically connected to ground. The inter-chip bonding wire Wg, like the inter-chip bonding wires W21-A and W21-B, is a Cu-Cu connected inter-chip bonding wire, formed by joining a first portion p1-g formed in the first wiring layer Ar1 and a second portion p2-g formed in the second wiring layer Ar2.

[0145] By also applying the inter-chip bonding wires to the ground side, the drive signal lines and ground lines of the transmission transistor TG include the same type of wires as the inter-chip bonding wires, and the line resistances of the drive signal lines and ground lines are made equal.

[0146] Therefore, it is possible to prevent the accuracy of the operation of the transmission transistors TG-A and TG-B from being compromised due to the unbalanced resistance of the wires between the drive signal line and the ground line (resistance mismatch), and to improve distance measurement performance.

[0147] Here, as Figure 10 As shown, the first wiring forming layer Ar1 of the first chip Cp1 has a wiring layer that forms the first portions (p1-A, p1-B, p1-g) of the inter-chip bonding wires W21-A, W21-B, and Wg, which will be referred to as the "wire layer Lyl" below.

[0148] Furthermore, the second wiring forming layer Ar2 in the second chip Cp2 has a wiring layer in which corresponding second portions (p2-A, p2-B and p2-g) of inter-chip bonding wires W21-A, W21-B and Wg are formed, and this wiring layer is referred to below as "wiring layer Ly2".

[0149] Figure 11An example arrangement of inter-chip bonding wires W21-A, W21-B and Wg in pixel array unit 11 is shown.

[0150] Each inter-chip bonding wire W21-A, W21-B, and Wg is arranged as a wire extending in the vertical direction (column direction) of the pixel array unit 11. In this example, two inter-chip bonding wires Wg are formed so as to pass through each pixel Px. Specifically, as shown in the figure, one inter-chip bonding wire Wg is arranged in the boundary region of adjacent pixels Px in the horizontal direction, forming two inter-chip bonding wires Wg so as to pass through each pixel Px.

[0151] In this example, the linewidths of the inter-chip bonding wires W21-A, W21-B, and Wg are substantially the same. This ensures that the resistances of each wire in the inter-chip bonding wires W21-A, W21-B, and Wg are equal, and prevents imbalances in the resistances of these wires from impairing the operational accuracy of the transfer transistors TG-A and TG-B.

[0152] Furthermore, in this example, the cross-sectional areas of the inter-chip bonding wires W21-A, W21-B, and Wg are substantially the same. This ensures that the resistances of each wire in the inter-chip bonding wires W21-A, W21-B, and Wg are equal, preventing resistance imbalances in the inter-chip bonding wires W21-A, W21-B, and Wg that could impair the operational accuracy of the transfer transistors TG-A and TG-B.

[0153] Furthermore, in this example, the spacing between inter-chip bonding conductor W21-A and the inter-chip bonding conductor Wg adjacent to W21-A is substantially equal to the spacing between inter-chip bonding conductor W21-B and the inter-chip bonding conductor Wg adjacent to W21-B. The term "spacing" between adjacent wires as used herein refers to the spacing between the adjacent ends of two wires. Note that the term "layout spacing" for wires refers to the spacing between the centers of the wires.

[0154] As described above, since the spacing between inter-chip bonding wires W21-A and Wg, and between inter-chip bonding wires W21-B and Wg, are substantially equal, the inter-line capacitance (i.e., the parasitic capacitance acting on inter-chip bonding wire W21-A) between inter-chip bonding wires W21-A and Wg, and the inter-line capacitance (i.e., the parasitic capacitance acting on inter-chip bonding wire W21-B) between inter-chip bonding wires W21-B and Wg, are substantially equal. In the drive signals (drive pulses) of the transmission transistors TG-A and TG-B, waveform passivation occurs due to the inter-line capacitance with inter-chip bonding wire Wg. However, because the inter-line capacitances are substantially equal as described above, the passivation of the drive waveforms of the transmission transistors TG-A and TG-B becomes unbalanced, and charge distribution to the two floating diffusers FD-A and FD-B can be precisely performed.

[0155] Note that, as described above, in this example, since the wire widths of the inter-chip bonding wires W21-A, W21-B, and Wg are basically the same, the spacing between the inter-chip bonding wires W21-A and Wg, as well as the spacing between the inter-chip bonding wires W21-B and Wg, are basically equal as described above, making the arrangement spacing between the inter-chip bonding wires W21-A, W21-B, and Wg basically equal.

[0156] Furthermore, in this example, at least a portion of the inter-chip bonding wire W21-A overlaps with the transfer transistor TG-A, and at least a portion of the inter-chip bonding wire W21-B overlaps with the transfer transistor TG-B in an in-plane direction. Additionally, the in-plane direction can also be rewritten as a direction perpendicular to the stacking direction of the first chip Cp1 and the second chip Cp2.

[0157] The advantages of overlapping a portion of the inter-chip bonding wires W21-A and W21-B with a portion of the transfer transistors TG-A and TG-B in this manner will be described below.

[0158] Figure 12 It is used to explain and Figure 11 The diagram shows a schematic cross-sectional view of the sensor unit 1 corresponding to the example of the wire arrangement, and schematically illustrates the state of the cross-section of the region corresponding to a pixel Px in the sensor unit 1. Specifically, it shows various specific structural examples of the lines connecting the inter-chip bonding wire W21-A and the transmission transistor TG-A in pixel Px, the lines connecting the inter-chip bonding wire W21-B and the transmission transistor TG-B, and the lines connecting the inter-chip bonding wire Wg and ground.

[0159] In the following text, the conductor layer other than the conductor layer Ly1 in the first wiring forming layer Ar1 is referred to as the "intermediate conductor layer Lym".

[0160] Furthermore, the wire connecting the inter-chip bonding wire W21-A to the transfer transistor TG-A is called the "first intermediate wire", and the wire connecting the inter-chip bonding wire W21-B to the transfer transistor TG-B is called the "second intermediate wire".

[0161] In the intermediate conductor layer Lym, local lines and intermediate lines are formed as part of the drive signal lines of each of the transmission transistors TG-A and TG-B, and local lines and intermediate lines are formed as part of the ground line.

[0162] In this example, as described above, at least a portion of the inter-chip bonding wire W21-A overlaps with the transfer transistor TG-A in the in-plane direction. Therefore, as shown by the thick dashed line X in the figure, the first intermediate wire connecting the inter-chip bonding wire W21-A and the transfer transistor TG-A can be formed as a connection portion 30 extending substantially linearly in the stacking direction of the first chip Cp1 and the second chip Cp2. Specifically, the connection portion 30 includes a plurality of vias v penetrating between the intermediate wire layers Lym, and for example, the central axes of the vias v are substantially aligned with each other, such that the connection portion 30 extends substantially linearly in the stacking direction. Note that the number of vias V in the connection portion 30 is not limited to multiple and can be a single one.

[0163] In addition, in this example, at least a portion of the inter-chip bonding wire W21-B also overlaps with the transfer transistor TG-B in the in-plane direction on the side of the transfer transistor TG-B, so reference numerals are omitted. However, the same connection as the connection portion 30 is also made on the side of the transfer transistor TG-B.

[0164] By forming the connection portion 30 extending in a generally straight line along the stacking direction as described above, the wire lengths of the first intermediate wire and the second intermediate wire can be set to lengths corresponding to the spacing distance in the stacking direction between the inter-chip bonding wire W21-A and the transmission transistor TG-A, and lengths corresponding to the spacing distance in the stacking direction between the inter-chip bonding wire W21-B and the transmission transistor TG-B, respectively, and the wire resistance of the first intermediate wire and the second intermediate wire can be minimized.

[0165] Therefore, passivation of the drive waveforms of the transmission transistors TG-A and TG-B can be suppressed, and higher frequency transmission drive signals STG-A and STG-B can be sent.

[0166] Furthermore, in this example, at least a portion of the inter-chip bonding wire W21-A overlaps with the transfer transistor TG-A, and at least a portion of the inter-chip bonding wire W21-B overlaps with the transfer transistor TG-B in the in-plane direction, allowing the connection portion 30 to be formed as described above, extending substantially linearly along the stacking direction. However, this eliminates the need for arranging each of the first and second intermediate wires in the in-plane direction (see...). Figure 11 and Figure 12 This reduces the resistance of both the first and second intermediate conductors. Furthermore, it reduces the inter-line capacitance with adjacent conductors.

[0167] Because it can reduce wire resistance and inter-line capacitance, it can suppress passivation of the drive waveforms of transmission transistors TG-A and TG-B, and can transmit higher frequency transmission drive signals STG-A and STG-B.

[0168] Additionally, in this example, as shown by the thick dashed line Y in the figure, the inter-chip bonding wire Wg is connected to the intermediate ground wire 31 of pixel Px. The intermediate ground wire 31 is a grounded wire formed in the intermediate conductor layer Lym and connected to the ground in pixel Px. In this example, the intermediate ground wire 31 extends in the vertical direction so that its horizontal end in pixel Px extends side by side with the inter-chip bonding wire Wg. Then, in this example, in each pixel Px, the intermediate ground wire 31 and the inter-chip bonding wire Wg, as described above, are connected.

[0169] As described above, since the inter-chip bonding wire Wg is connected to the intermediate ground wire 31 of the pixel Px, the cross-sectional area of ​​the inter-chip bonding wire Wg (ground wire) can be increased.

[0170] Because the cross-sectional area of ​​the grounding wire can be increased, its width can be narrowed without increasing impedance. By narrowing the width of the grounding wire, the inter-line capacitance between the inter-chip bonding wires W21-A and W21-B and the grounding wire can be reduced, and waveform passivation of the drive pulse can be suppressed.

[0171] <6. Variations related to the arrangement of inter-chip bonding wires>

[0172] Figure 13 This is an illustrative diagram of a first variation involving the configuration of inter-chip bonding wires.

[0173] In the first variation, Figure 11 The spacing between the three inter-chip bonding wires per pixel is set to two per pixel.

[0174] Specifically, in this case, the arrangement of the inter-chip bonding wires in the horizontal direction is such that inter-chip bonding wires W21-A and W21-B are arranged alternately, and then inter-chip bonding wire Wg is arranged between inter-chip bonding wires W21-A and W21-B.

[0175] In this case, the arrangement spacing of inter-chip bonding wires W21-A and W21-B is a spacing of every two pixels, and the arrangement spacing of inter-chip bonding wires Wg is a spacing of every pixel.

[0176] As shown in the figure, inter-chip bonding wires W21-A and W21-B are respectively disposed at the boundaries of two adjacent pixels Px in the horizontal direction, forming an overlap with the two adjacent pixels Px. Furthermore, inter-chip bonding wire Wg is disposed at the center of each pixel Px in the horizontal direction. In this example, the wire widths of inter-chip bonding wires W21-A, W21-B, and Wg are substantially the same.

[0177] Note that in the first variation, due to the alternating arrangement of inter-chip bonding wires W21-A and W21-B, a structure is adopted in which the formation positions of transmission transistors TG-A and TG-B are reversed between two adjacent pixels Px in the horizontal direction.

[0178] In the first variation, in each pixel Px, inter-chip bonding wires W21-A and W21-B are symmetrically arranged across a photodiode PD. Specifically, inter-chip bonding wires W21-A and W21-B are symmetrically arranged with respect to the horizontal centerline of the photodiode PD.

[0179] Because the inter-chip bonding wires W21-A and W21-B are arranged symmetrically across the photodiode PD, the wire lengths can be made equal, and the wire resistance can be made equal to the first intermediate wire (represented by the lower left slant line in the figure) connecting the transmission transistor TG-A and the inter-chip bonding wire W21-A, and the second intermediate wire (represented by the lower right slant line in the figure) connecting the transmission transistor TG-B and the inter-chip bonding wire W21-B.

[0180] Therefore, the drive signal is prevented from becoming unbalanced between the transmission transistors TG-A and TG-B, and the charge distribution to the two floating diffusers FD-A and FD-B can be precisely executed.

[0181] Note that, for confirmation purposes, the above... Figure 11 The structure shown also corresponds to the structure in which inter-chip bonding wires W21-A and W21-B are symmetrically arranged with photodiodes PD in between.

[0182] Furthermore, in the first variation, as described above... Figure 11 In this case, the spacing between inter-chip bonding wires W21-A and Wg is basically equal to the spacing between inter-chip bonding wires W21-B and Wg.

[0183] Therefore, in the first variation, the inter-line capacitance between inter-chip bonding wire W21-A and inter-chip bonding wire Wg, and the inter-line capacitance between inter-chip bonding wire W21-B and inter-chip bonding wire Wg, can be made substantially equal.

[0184] Figure 14 This is an explanatory diagram of a second variation related to the configuration of inter-chip bonding wires.

[0185] and Figure 13 The difference in the first variant shown is that the inter-chip bonding wires W21-A and W21-B are configured to overlap with the corresponding transfer transistor TG portions in the horizontal direction. That is, the inter-chip bonding wire W21-A is configured to overlap with the transfer transistor TG-A portions, and the inter-chip bonding wire W21-B is configured to overlap with the transfer transistor TG-B portions.

[0186] As in Figure 13 In the second variation, the condition that the spacing between inter-chip bonding wires W21-A and Wg is substantially equal to the spacing between inter-chip bonding wires W21-B and Wg is also satisfied. Therefore, by configuring the inter-chip bonding wires W21-A and W21-B as described above, the inter-chip bonding wire Wg is not configured at the center of the horizontal direction of pixel Px, but at a position offset from the center of the horizontal direction.

[0187] Figure 15 This is an explanatory diagram of a third variation related to the configuration of inter-chip bonding wires.

[0188] In the third variation, the formation spacing of the inter-chip bonding wires is narrowed to five formation spacings per pixel. That is, in this case, the breaks in the five inter-chip bonding wires of each pixel Px include one inter-chip bonding wire W21-A, W21-B and three inter-chip bonding wires Wg, as shown in the figure. The inter-chip bonding wires W21-A and W21-B are positioned at locations overlapping with the corresponding transmission transistor TG portion, as shown in the figure. Figure 11 In this case, for the inter-chip bonding wire Wg, one is arranged between the inter-chip bonding wires W21-A and W21-B, one is arranged outside the inter-chip bonding wire W21-A, and one is provided outside the inter-chip bonding wire W21-B.

[0189] By narrowing the spacing between bonding wires between chips, the bonding strength between chips can be improved.

[0190] <7. Other variations>

[0191] It should be noted that the implementation methods are not limited to the specific examples described above, and various variations may be adopted.

[0192] For example, an example of inter-chip bonding wires arranged in a horizontal direction has been described above, but inter-chip bonding wires can also be arranged in a vertical direction. Furthermore, each inter-chip bonding wire is shown as a linearly extending wire, but a portion of it may be bent or flexed, or a portion of it may extend in an inclined direction.

[0193] Furthermore, the spacing between bonding wires between chips is not limited to those shown in the examples above.

[0194] Here, as described above, the pixel spacing of this embodiment is less than 5.0 μm, specifically around 3.5 μm. In this case, Figure 11 When the ratio of each pixel shown is 3, the spacing between the inter-chip bonding wires is approximately 1.7 (5.0 + 3) μm or less, specifically approximately 1.2 μm (3.5 + 3). Furthermore, in Figure 13 When the ratio of each pixel shown is 2, the spacing between the inter-chip bonding wires is less than 2.5 (5.0 ÷ 2) μm, specifically about 1.8 μm (3.5 ÷ 2).

[0195] Furthermore, in the above description, an example has been described in which the signal processing unit 17 for performing distance calculations is disposed in the sensor unit 1, but the signal processing unit 17 may be disposed outside the sensor unit 1.

[0196] <8. Summary of Implementation Methods>

[0197] As described above, the sensor device (sensor unit 1) according to this embodiment includes a first chip (Cp1) and a second chip (Cp2). The first chip (Cp1) includes a first semiconductor substrate (Bs1) and a first wiring layer (Ar1) and includes a pixel. The pixel includes a photoelectric conversion element (photodiode PD) and a first transmission gate element (transmission transistor TG-A) and a second transmission gate element (transmission transistor TG-B) configured to transmit the accumulated charge of the photoelectric conversion element. The second chip (Cp2) includes a second semiconductor substrate (Bs2) and a second wiring layer (Ar2).

[0198] Then, a first wire (inter-chip bonding wire W21-A) is electrically connected to a first transmission gate element, a second wire (inter-chip bonding wire W21-B) is electrically connected to a second transmission gate element, and a third wire (inter-chip bonding wire Wg) is electrically connected to ground. The first wire, the second wire, and the third wire are formed by joining a first portion (p1-A, p1-B, p1-g) formed on the first wire layer and extending in a first direction and a second portion (p2-A, p2-B, p2-g) formed on the second wire layer and extending in the first direction.

[0199] According to the above configuration, the first wire for the first transmission gate element, the second wire for the second transmission gate element, and the third wire, which serves as a ground wire, are together formed as inter-chip bonding wires for bonding the first chip and the second chip. That is, by forming the first wire, the second wire, and the third wire with wires of the same type as the inter-chip bonding wires, the wire resistances can be made equal.

[0200] Therefore, it is possible to prevent the accuracy of the operation of the first and second transmission gate elements from being compromised due to the imbalance of wire resistance in the first, second, and third wires, and to improve the performance of distance measurement using the sensor device.

[0201] Furthermore, the sensor device used in this embodiment is a distance measurement sensor using the indirect ToF method.

[0202] In the indirect ToF method, the accumulated charge of the photoelectric conversion element is distributed to two floating diffusers through a first transmission gate element and a second transmission gate element.

[0203] Therefore, by applying this technology, the accuracy of the operation of the first transmission gate element and the second transmission gate element can be prevented from being weakened, thereby improving the ranging performance.

[0204] Furthermore, in the sensor device implemented as an example, the first wire, the second wire, and the third wire are connected to each other by a Cu-Cu connection to form the first part and the second part.

[0205] From the perspective of performance track record and reliability, Cu-Cu interconnect is the preferred interconnect technology between chips.

[0206] Therefore, the ease of implementation of the sensor device in this embodiment can be improved.

[0207] Furthermore, in the sensor device according to this embodiment, the first wire and the second wire are arranged symmetrically with a photoelectric conversion element between them.

[0208] Therefore, the first intermediate wire connecting the first transmission gate element and the first wire, and the second intermediate wire connecting the second transmission gate element and the second wire, can have equal wire lengths and equal wire resistances.

[0209] Therefore, by preventing the drive signal from becoming unbalanced between the first and second transmission gate elements, charge distribution to the two floating diffusers can be accurately performed, and distance measurement performance can be improved.

[0210] Furthermore, in the sensor device according to the embodiment, the line widths of the first wire, the second wire, and the third wire are substantially the same.

[0211] This allows for the equalization of the individual wire resistances of the first, second, and third wires.

[0212] Therefore, it is possible to prevent the accuracy of the operation of the first and second transmission gate elements from being compromised due to the imbalance of wire resistance in the first, second, and third wires, and to improve the performance of distance measurement using the sensor device.

[0213] Furthermore, in the sensor device implemented as an example, the cross-sectional areas of the first wire, the second wire, and the third wire are substantially the same.

[0214] This allows for the equalization of the individual wire resistances of the first, second, and third wires.

[0215] Therefore, it is possible to prevent the accuracy of the operation of the first and second transmission gate elements from being compromised due to the imbalance of wire resistance in the first, second, and third wires, and to improve the performance of distance measurement using the sensor device.

[0216] Furthermore, in the sensor device implemented as an example, in a direction perpendicular to the stacking direction of the first chip and the second chip, at least a portion of the first wire overlaps with the first transmission gate element and at least a portion of the second wire overlaps with the second transmission gate element.

[0217] Therefore, for each of the first intermediate wire connecting the first wire and the first transmission gate element, and the second intermediate wire connecting the second wire and the second transmission gate element, it is not necessary to route in a direction perpendicular to the aforementioned stacking direction, and the wire resistance of the two wires can be reduced. Furthermore, the inter-wire capacitance with adjacent wires can also be reduced.

[0218] Since the resistance of the wires and the capacitance between the wires can be reduced, the passivation of the driving waveforms of the first and second transmission gate elements can be suppressed, and higher frequency transmission drive signals can be transmitted.

[0219] Furthermore, in the sensor device according to the embodiment, the first wire and the first transmission gate element, as well as the second wire and the second transmission gate element, are connected by a connection portion (30) that includes one or more through holes (v) and extends substantially linearly in the stacking direction.

[0220] Therefore, the lengths of the first intermediate wire connecting the first wire and the first transmission gate element and the second intermediate wire connecting the second wire and the second transmission gate element can be set to correspond to the length of the spacing distance between the first wire and the first transmission gate element in the stacking direction and the length of the spacing distance between the second wire and the second transmission gate element in the stacking direction, and the wire resistance of the first and second intermediate wires and the inter-line capacitance with adjacent wires can be minimized.

[0221] Therefore, it is possible to suppress the passivation of the driving waveforms of the first and second transmission gate elements, and to transmit higher frequency transmission drive signals.

[0222] Furthermore, in the sensor device according to this embodiment, the interval between the first wire and the third wire adjacent to the first wire and the interval between the second wire and the third wire adjacent to the second wire are substantially equal.

[0223] As a result, the inter-line capacitance between the first and third conductors (parasitic capacitance acting on the first conductor) and the inter-line capacitance between the second and third conductors (parasitic capacitance acting on the second conductor) become substantially equal, the passivation of the driving waveforms of the first and second transmission gate elements will not become unbalanced, and the charge distribution to the two floating diffusions can be accurately performed.

[0224] Therefore, ranging performance can be improved.

[0225] Furthermore, in the sensor device implemented as an example, a conductor layer and an intermediate conductor layer are formed in the first wiring forming layer. A first conductor, a second conductor, and a first portion of a third conductor are formed in the conductor layer. At least a portion of the third conductor overlaps with a pixel in a direction perpendicular to the stacking direction of the first chip and the second chip. The third conductor is connected to an intermediate ground conductor in the pixel. The intermediate ground conductor is a conductor formed in the intermediate conductor layer and connected to ground in the pixel.

[0226] This allows for an increase in the cross-sectional area of ​​the third conductor (grounding conductor).

[0227] Because the cross-sectional area of ​​the grounding wire can be increased, its width can be narrowed without increasing impedance. By narrowing the grounding wire, the inter-line capacitance between the first and second conductors and the grounding wire can be reduced, waveform passivation of the drive pulse can be suppressed, and higher frequency transmission signals can be achieved.

[0228] Furthermore, the distance measuring device (10) according to the embodiment includes: a light-emitting unit (2) that emits illumination light (Li) toward an object; and a sensor unit (1) that receives reflected light (Lr) from the illumination light of the object; wherein the sensor unit includes a first chip, the first chip including a first semiconductor substrate and a first wiring layer and including a pixel, the pixel including a photoelectric conversion element and a first transmission gate element and a second transmission gate element configured to transmit accumulated charge of the photoelectric conversion element, and a second chip including a second semiconductor substrate and a second wiring layer, forming a first wire electrically connected to the first transmission gate element, a second wire electrically connected to the second transmission gate element, and a third wire electrically connected to ground, and each of the first wire, the second wire and the third wire is formed by joining a first portion formed in the first wiring layer and extending in a first direction and a second portion formed in the second wiring layer and extending in a first direction.

[0229] Even when using a distance measuring device as described in the embodiment, similar operation and effects to those of the sensor device described above as an embodiment can be obtained.

[0230] It should be noted that the effects described in this specification are merely illustrative and not limited, and other effects may be provided.

[0231] <9. This technology>

[0232] Note that this technology can be configured as follows.

[0233] (1) A sensor device, comprising:

[0234] A first chip includes a first semiconductor substrate and a first wiring layer, and includes a pixel, the pixel including a photoelectric conversion element, and a first transmission gate element and a second transmission gate element configured to transport accumulated charge of the photoelectric conversion element; and

[0235] The second chip includes a second semiconductor substrate and a second wiring layer; wherein a first wire electrically connected to the first transmission gate element, a second wire electrically connected to the second transmission gate element, and a third wire electrically connected to ground are formed; and

[0236] Each of the first, second, and third conductors is formed by joining a first portion that is formed in the first wiring forming layer and extends in the first direction, and a second portion that is formed in the second wiring forming layer and extends in the first direction.

[0237] (2) According to the sensor device described in (1) above, wherein,

[0238] The sensor device is a distance measurement sensor that measures distance using the indirect time-of-flight (ToF) method.

[0239] (3) The sensor device according to (1) or (2) above, wherein,

[0240] The first wire, the second wire, and the third wire are formed by connecting the first part and the second part to each other through a copper-copper (Cu-Cu) connection.

[0241] (4) The sensor device according to any one of (1) to (3) above, wherein,

[0242] The first and second wires are arranged symmetrically with the photoelectric conversion element between them.

[0243] (5) The sensor device according to any one of (1) to (4) above, wherein,

[0244] The first, second, and third conductors have basically the same line width.

[0245] (6) The sensor device according to any one of (1) to (5) above, wherein,

[0246] The cross-sectional areas of the first, second, and third conductors are basically the same.

[0247] (7) The sensor device according to any one of (1) to (6) above, wherein,

[0248] In a direction perpendicular to the stacking direction of the first chip and the second chip, at least a portion of the first wire overlaps with the first transmission gate element and at least a portion of the second wire overlaps with the second transmission gate element.

[0249] (8) The sensor device according to (7) above, wherein,

[0250] The first wire and the first transmission gate element, as well as the second wire and the second transmission gate element, are connected by a connection portion that includes one or more through holes and extends substantially linearly in the stacking direction.

[0251] (9) The sensor device according to any one of (1) to (8) above, wherein,

[0252] The spacing between the first conductor and the third conductor adjacent to the first conductor is substantially equal to the spacing between the second conductor and the third conductor adjacent to the second conductor.

[0253] (10) The sensor device according to any one of (1) to (9) above, wherein,

[0254] In the first wiring forming layer, a conductor layer and an intermediate conductor layer other than the conductor layer are formed, and the first portion of the first conductor, the second conductor and the third conductor are formed in the conductor layer;

[0255] At least a portion of the third conductive line overlaps with the pixel in a direction perpendicular to the stacking direction of the first and second chips; and

[0256] The third conductor is connected in the pixel to an intermediate ground conductor, which is a conductor formed in the intermediate conductor layer and connected to ground in the pixel.

[0257] (11) A distance measuring device, comprising:

[0258] The light-emitting unit emits illumination light towards the object; and

[0259] The sensor unit receives reflected light from the illumination light emitted by the object; wherein,

[0260] The sensor unit includes:

[0261] A first chip includes a first semiconductor substrate and a first wiring layer, and includes a pixel, the pixel including a photoelectric conversion element, and a first transmission gate element and a second transmission gate element configured to transport accumulated charge of the photoelectric conversion element; and

[0262] The second chip includes a second semiconductor substrate and a second wiring layer; it forms a first wire electrically connected to the first transmission gate element, a second wire electrically connected to the second transmission gate element, and a third wire electrically connected to ground; and

[0263] Each of the first, second, and third conductors is formed by joining a first portion that is formed in the first wiring forming layer and extends in the first direction, and a second portion that is formed in the second wiring forming layer and extends in the first direction.

[0264] List of reference numerals

[0265] 1. Sensor Unit (Sensor Device)

[0266] 2 light-emitting units

[0267] 10 Distance measuring device

[0268] Ob object

[0269] Li irradiation light

[0270] Lr reflected light

[0271] 11-pixel array unit

[0272] 20 pixel drive line

[0273] 21 Gate drive lines

[0274] 22 Vertical signal lines

[0275] Px pixels

[0276] PD photodiode

[0277] FD floating diffusion

[0278] TG Transmission Transistor

[0279] RST reset transistor

[0280] Cp1 First Chip

[0281] Cp2 Second Chip

[0282] Bs1 First Semiconductor Substrate

[0283] Bs2 Second Semiconductor Substrate

[0284] Ar1 First Wiring Forming Layer

[0285] Ar2 Second Wiring Forming Layer

[0286] Inter-chip bonding wires for W21-A, W21-B, and Wg

[0287] p1-A, p1-B, p1-g Part 1

[0288] p2-A, p2-B, p2-g Part Two

[0289] Lym intermediate conductor layer

[0290] v Through hole

[0291] 30 Connection part

[0292] 31. Intermediate grounding wire.

Claims

1. A sensor device, comprising: A first chip includes a first semiconductor substrate and a first wiring layer and includes a pixel, the pixel including a photoelectric conversion element and a first transmission gate element and a second transmission gate element configured to transmit accumulated charge of the photoelectric conversion element; and The second chip includes a second semiconductor substrate and a second wiring layer, wherein... A first wire electrically connected to the first transmission gate element, a second wire electrically connected to the second transmission gate element, and a third wire electrically connected to ground are formed; and Each of the first, second, and third wires is formed by joining a first portion formed in the first wiring layer and extending in the first direction and a second portion formed in the second wiring layer and extending in the first direction. Wherein, the interval between the first conductor and the third conductor adjacent to the first conductor is equal to the interval between the second conductor and the third conductor adjacent to the second conductor.

2. The sensor device according to claim 1, wherein, The sensor device is a distance measurement sensor that measures distance using the indirect time-of-flight (ToF) method.

3. The sensor device according to claim 1, wherein, The first wire, the second wire, and the third wire are formed by connecting the first part and the second part to each other through a copper-copper (Cu-Cu) connection.

4. The sensor device according to claim 1, wherein, The first and second wires are arranged symmetrically with the photoelectric conversion element located between them.

5. The sensor device according to claim 1, wherein, The first conductor, the second conductor, and the third conductor have the same line width.

6. The sensor device according to claim 1, wherein, The first conductor, the second conductor, and the third conductor have the same cross-sectional area.

7. The sensor device according to claim 1, wherein, In a direction perpendicular to the stacking direction of the first chip and the second chip, at least a portion of the first wire overlaps with the first transmission gate element and at least a portion of the second wire overlaps with the second transmission gate element.

8. The sensor device according to claim 7, wherein, The first wire and the first transmission gate element, and the second wire and the second transmission gate element are connected by a connection portion including one or more through holes and extending linearly in the stacking direction.

9. The sensor device according to claim 1, wherein, In the first wiring forming layer A conductor layer and an intermediate conductor layer other than the conductor layer are formed therein, comprising the first portion of the first conductor, the second conductor and the third conductor. At least a portion of the third conductor overlaps with the pixel in a direction perpendicular to the stacking direction of the first chip and the second chip; and The third conductor is connected in the pixel to an intermediate ground conductor, which is a conductor formed in the intermediate conductor layer and connected to ground in the pixel.

10. A distance measuring device, comprising: The light-emitting unit emits illumination light towards the object; and A sensor unit receives reflected light from the irradiation light emitted from the object; in The sensor unit includes: A first chip includes a first semiconductor substrate and a first wiring layer, and includes pixels, each pixel including a photoelectric conversion element, and a first transmission gate element and a second transmission gate element configured to transport accumulated charge in the photoelectric conversion element; and The second chip includes a second semiconductor substrate and a second wiring layer, forming a first wire electrically connected to the first transmission gate element, a second wire electrically connected to the second transmission gate element, and a third wire electrically connected to ground; and Each of the first wire, the second wire, and the third wire is formed by joining a first portion formed in a first wiring layer and extending in a first direction, and a second portion formed in a second wiring layer and extending in the first direction. Wherein, the interval between the first conductor and the third conductor adjacent to the first conductor is equal to the interval between the second conductor and the third conductor adjacent to the second conductor.

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