Inverter with bridge arm current sensing

Abstract

To allow reliable current measurement of the output current at the switching level of an inverter, especially at a switching frequency in the range of 100 kHz of semiconductor switches, it is set up such that the voltage (u Ln ) at the measuring choke (L) is measured and this voltage (u Ln ) is integrated over time to represent the leg current (i Ln ) at the choke (L), and the time integral (∫u Ln ) is processed in the processing unit (14), where the processed time integral (∫u Ln ) is used in the inverter controller (10) to control the inverter, where the voltage (u I ) at the choke (L) is integrated over time analogously by two series-connected integrator capacitors (C Ln ), where a reset switch (S I ) is provided across each integrator capacitor (C I ) in order to reset the respective integrator capacitor (C I ) alternately.

Description

[0001] The present invention relates to an inverter having a switching stage with at least one switching bridge arm, wherein the switching bridge arm comprises at least two semiconductor switches connected in series and an AC pole between the semiconductor switches connected in series, wherein the AC pole is connected in series to a choke, and wherein a current detection device is arranged to detect the bridge arm current in the choke, wherein the current detection device measures the voltage at the choke using a voltage measuring unit and also integrates the voltage measured at the choke over time using an integrator, wherein the time integral of the voltage at the choke represents the current in the choke, and the current detection device further comprises a processing unit for processing the time integral provided by the integrator, wherein the processed time integral is used in an inverter controller to control the inverter.

[0002] Inverters for converting a DC voltage (direct current voltage) into an AC voltage (alternating current voltage) are well known and are used in many different applications. One possible application is to supply power to an AC grid (single or multi-phase) from a DC power source (e.g., photovoltaic modules, batteries, AC / DC converters, etc.). Typically, an inverter uses a switching stage with multiple semiconductor switches (e.g., IGBTs (insulated gate bipolar transistors) or MOSFETs (metal oxide semiconductor field effect transistors)) to produce the desired inverter AC output voltage and current. The switching stage is typically supplied with DC current by a DC link. The switching of the semiconductor switches is controlled by a switch controller to produce the desired output voltage and / or output current. The switch controller typically uses a PWM (pulse width modulation) control strategy, although there are other possible control strategies. The typical switching frequency of the semiconductor switches in the inverter ranges from 20kHz to 200kHz. Due to inherent hardware limitations, it is not possible to achieve particularly high switching frequencies using IGBT or MOSFET semiconductor switches. In the past few years, new semiconductor switches have emerged, such as GaN (gallium nitride) switches. Such semiconductor switches allow higher switching frequencies to be achieved, i.e., in the range of 100kHz to 400kHz.

[0003] For the operation of the inverter, e.g. for the switching controller to control the semiconductor switches or for overcurrent protection, it is necessary to measure certain voltages and currents of the inverter, e.g. the output current of the switching stage. A problem with existing current measuring devices is that some known current measuring devices (e.g. shunts, current sensors, etc.) can only be used for a given maximum switching frequency, because these devices are not fast enough to provide reliable current measurements at the required switching frequency at the obtained sampling time. Other current measuring devices (e.g. current transformers) can also be used for higher switching frequencies, but due to the high switching frequencies, they will produce high losses.

[0004] US 2015 / 0069990 A1 describes measuring the current through an inductor of a converter by integrating the voltage across the inductor analogously. The integrator is an operational amplifier circuit having an operational amplifier with an integrator capacitor in the feedback branch of the operational amplifier. The integrator uses several capacitors in the feedback branch that are connected in parallel and can be selectively connected into the feedback branch to adjust the integrator gain. The offset of the integration is controlled using a controllable current source that adds a variable current to the input of the integrating operational amplifier. In particular, the required controllable current source makes such current measurement more complicated.

[0005] US 6,304,472 B1 describes current measurement as an alternative to shunts or current transformers. The current measurement is achieved by integrating the voltage across the inductor through an integrator. The integrator is an operational amplifier circuit with an operational amplifier having a single integrator capacitor in the feedback branch of the operational amplifier. In one embodiment, a switch is used to reset the integrator capacitor. Switching the integrator capacitor can cause offset errors in the current measurement, especially at high switching frequencies.

[0006] There is a need for a new simple and reliable current measurement device and method for measuring the output current of a switching stage, in particular at switching frequencies in the 100 kHz range that can be used to control the semiconductor switches of an inverter.

[0007] This object is achieved in that two integrator capacitors connected in series are arranged in an integrator, wherein a reset switch is arranged across each integrator capacitor so as to alternately reset the corresponding integrator capacitor. Alternatively, resetting the integrator capacitor reduces the offset in the analog integration, thereby reducing the drift of the integrator over time. This increases the reliability and accuracy of the integration, so that the current measurement and implementation of the circuit become simple. The integration of the measured voltage can be performed quickly enough so that even high-frequency signals with a frequency in the range of 100kHz can be reliably processed. In addition, integration can be performed with low losses. As a time integral of the voltage measured at the choke corresponding to the bridge arm current, the time integral can be processed directly in a processing unit for controlling the inverter. The processing unit can also be integrated in the inverter controller or can be the inverter controller itself.

[0008] The voltage measurement unit is advantageously implemented as a differential amplifier or instrumentation amplifier using at least one operational amplifier and a resistor. This allows the measured voltage to be scaled down to a voltage level that is more easily handled in subsequent stages.

[0009] In one possible implementation, the integrator is analogically implemented as a series RC circuit using at least one integrator capacitor connected in series with an integrator resistor, or is analogically implemented as an operational amplifier circuit using at least one operational amplifier having at least one integrator capacitor in a feedback branch connecting the output port of the operational amplifier to the input port of the operational amplifier OP.

[0010] In a particularly advantageous implementation, the reset switch is implemented as a toggle switch, preferably as a make-before-break switch, as this allows a further reduction of the offset.Resetting the capacitor or capacitors is also advantageous for possible digital integration.

[0011] Resetting the at least one integrator capacitor or the series-connected integrator capacitors is preferably synchronized with the zero crossing of the bridge arm current.

[0012] Referring to Figures 1 to Fig.11 The present invention will be described in more detail in FIGS. 1 to Fig.11 Exemplary, schematic and non-limiting advantageous embodiments of the present invention are shown. In the drawings:

[0013] Figure 1 shows a typical implementation of an inverter.

[0014] Figure 2 The bridge arm voltage and bridge arm current at the AC pole of the switching bridge arm are shown.

[0015] Figure 3 shows the output current of the inverter as a result of the bridge arm current,

[0016] Figure 4 An inverter having a current detection device of the present invention is shown.

[0017] Figure 5 shows the time integral of the voltage at the choke,

[0018] Figure 6 shows a voltage measurement unit implemented as a differential amplifier,

[0019] Figure 7 shows an analog implementation of an integrator using an operational amplifier and a capacitor in the feedback branch with a reset switch,

[0020] Figure 8 shows an analog implementation of an integrator using an operational amplifier and two capacitors in series in the feedback branch with a reset switch,

[0021] Fig. 9 shows a comparator circuit for detecting overcurrent,

[0022] Fig.10shows the digitization of the time integral, and

[0023] Fig.11 The digital integration of the measured voltage at the choke is shown.

[0024] The inverter 1 is connected at the input to a DC source 2, such as a PV module (photovoltaic module) or a battery storage, and at the output to an electrical load 8, such as a grid. The inverter 1 converts the DC input voltage U DC Converted into AC output voltage u AC and the output current i AC . The inverter 1 can also be implemented bidirectionally, for example for supplying electrical energy from the grid to a battery energy storage (in this case, the input and output of the inverter 1 will be switched). The inverter 1 typically comprises a switching stage 5, which is connected to a DC link 4 at the input stage of the inverter 1. On the input side of the inverter 1, a DC filter 3, for example an EMC (Electromagnetic Compatibility) filter, may optionally be provided. On the output side of the inverter 1, an AC filter 6, for example for smoothing the output voltage u AC and the output current i AC The AC filter 6 may comprise a differential mode filter (usually in the form of a capacitor connected between the phases) and / or an EMC filter (usually in the form of a capacitor connected between the phases and an inductor connected in series to the phases). Between the inverter 1 and the load 8, an AC relay 7 may optionally be provided, which allows the inverter 1 to be disconnected from the electrical load 8. The AC relay 7 may also be integrated in the inverter 1, if present.

[0025] Many different implementations of the inverter 1 are known. Inverters may differ in the number of phases they provide, for example a three-phase inverter for providing electrical energy to a three-phase grid. Inverters 1 may also differ in the implementation of the switching stage 5.

[0026] The switching stage 5 includes at least one switching bridge leg SLn (n≥1), such as SL1 and SL2 in FIG. 1 , which is connected in parallel to the DC link voltage U DL In the switch bridge arm SLn, at least two semiconductor switches Snm (m≥2) (at least one high-side switch and at least one low-side switch) are connected in series, such as switches S11, S12, S21, and S22 in FIG. 1. An AC pole ACPn (such as ACP1 and ACP2 in FIG. 1) is formed between the high-side and low-side semiconductor switches Snm of the switch bridge arm SLn, and an AC bridge arm current i of the switch bridge arm SLn is provided at the AC pole ACPn. Ln and voltage u Ln , for example, i in Figure 1 L1 and u L1Through a high-side semiconductor switch and a low-side semiconductor switch Snm, the AC bridge arm voltage u Ln It is also known that there are switching stages 5 with more than one high-side and low-side semiconductor switch Snm, which allow the AC bridge arm voltage u at the AC pole ACPn to be Ln More than two voltage levels (so called multilevel inverters).

[0027] The inverter 1 may also have a plurality of switch bridge arms SLn for providing an AC output voltage u AC Multiple phases (multiphase inverter), for example, for providing a three-phase output voltage u AC The inverter 1 may also have a plurality of cascaded switching stages 5. The AC poles ACPn of the switching bridge arms SLn of the switching stage 5 may also be connected together to form an output voltage u AC In this case, the bridge arm voltage u of the connected switch bridge arm SLn is Ln It can also be phase-shifted (interleaved inverter).

[0028] However, the actual implementation of the switching stage 5 is irrelevant to the present invention.

[0029] The AC bridge arm current i provided at the AC pole ACPn of the switching bridge arm SLn Ln and voltage u Ln It is usually filtered by a series choke L (inductor) to remove the high frequency components of the AC waveform. Output voltage u AC There is usually at least one choke L for each phase.

[0030] The DC link 4 comprises a parallel connection to the input voltage U DC At least one DC link capacitor C L (optionally after filtering in the DC filter 3). The DC link voltage U DCL is provided at the DC link 4. It is also known to use more link capacitors C in series in the DC link 4 L In this implementation, the two capacitors C in the DC link 4 can be L The poles between are connected to the neutral line at the output of the inverter 1 or the star point of the AC output filter 6 (in the case of three phases, for example).

[0031] The inverter controller 10 is used to operate the inverter 1. For this purpose, different measurement signals M of the inverter 1 can be used, such as measured voltages and / or currents, for example the DC link voltage U DCL 、DC input voltage U DC , output voltage u AC , output current i AC Or the bridge arm current i LnThe bridge arm current i of the switch bridge arm SLn is Ln It can be used, for example, for overcurrent protection and regulation of the semiconductor switches Snm of the switching leg SLn. Voltage and current sensors for measuring the required quantities are well known.

[0032] In the inverter controller 10, a switch controller 11 is implemented, which generates control signals CSnm (such as CS11, CS12, CS21, CS22 in FIG. 1) for switching semiconductor switches Snm in the switching stage 5, so as to generate the required output voltage u of the inverter 1. AC and / or output current i AC The control signal CSnm is usually provided to a well-known gate driver (not shown for simplicity) for each semiconductor switch Snm, for realizing the switching of the semiconductor switch Snm. The gate driver may also be integrated in the switch controller 11.

[0033] The inverter controller 10 can be implemented on microprocessor-based hardware, such as a computer, a microcontroller, a digital signal processor, a programmable logic controller (PLC), etc., which is programmed with control software to operate the inverter 1. In addition, an implementation with an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA), etc. is also possible. The control software is stored in the memory of the inverter controller 10. The switch controller 11 and other functions of the inverter controller 10 can be implemented as software running on the inverter controller 10. The inverter controller 10 and the switch controller 11 can also be implemented as separate hardware. In this case, the switch controller 11 can also be microprocessor-based hardware, such as a microcontroller, a computer, a digital signal processor, a programmable logic controller (PLC), etc., or an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA), etc. However, the inverter controller 10 and / or the switch controller 11 can also be implemented as an analog circuit.

[0034] By way of example only, FIG1 shows a typical design of an inverter 1, in this case a single-phase inverter. In this example, the inverter 1 is supplied with direct current from a direct current source 2 and supplies electrical energy to an electrical load 8 via an AC relay 7. A DC filter 3 is provided at the input of the inverter 1. The DC input voltage U filtered in the DC filter 3 DC is supplied to the DC link 4, which has a DC input voltage U provided by the DC power source 2. DC At least one capacitor C in parallel LThe DC link 4 is followed by a switching stage 5 having a plurality of semiconductor switches S11, S12, S21, S22. In the example of FIG. 1 , the switching stage 5 has two switching legs SL1, SL2, wherein each switching leg SL1, SL2 is connected in parallel to the DC link 4, i.e., to the DC link voltage U DCL In each switching bridge arm SL1, SL2, the high-side semiconductor switch S11, S21 and the low-side semiconductor switch S12, S22 are connected in series. AC poles ACP1, ACP2 are formed between the semiconductor switches S11, S21 and S12, S22 of the switching bridge arms SL1, SL2. An AC bridge arm current i is provided at an AC pole ACP1. L1 . The other AC pole ACP2 serves as a return path for the bridge arm current. For the single-phase inverter 1, the second switching bridge arm SL2 can of course also be omitted in a well-known manner. Using one semiconductor switch S11, S12 each above and below the AC pole ACP, the AC waveform at the AC pole ACP1 can have two voltage levels. The choke L is connected in series to the AC pole ACP1 of the switching bridge arm SL1. An additional second choke L can also be provided in series to the second AC pole ACP2 of the second switching bridge arm SL2 in the return path.

[0035] Due to the switching of the semiconductor switch Snm, Figure 2 As shown in the upper part, an AC bridge arm voltage u having a rising edge and a falling edge is generated at the AC pole ACPn of the switching bridge arm SLn of the switching stage 5. Ln , such as a square wave or a step wave (for example, in the case of a multilevel inverter) waveform. Due to the choke L, such as Figure 2 As shown in the lower part, a bridge arm current i with rising and falling edges is also generated. Ln , for example, a triangular waveform. The frequency of the AC bridge arm voltage and current of the switching bridge arm SLn corresponds to the switching frequency f of the semiconductor switch Snm S (=1 / T S The semiconductor switch Snm is switched, for example, by using PWM, so that the required output voltage u is generated. AC or current i AC , for example a 50Hz sine wave, such as Figure 3 This means that the output current i of one phase of inverter 1 is AC For example, the corresponding bridge arm current i of the switch bridge arm SLn Ln Multiple pulses are synthesized. Figure 2 and Figure 3 In the example, a zero voltage switching strategy is adopted so that in each switching cycle T S Middle bridge arm current i Ln Zero crossing (such as Figure 2 and Figure 3 shown).

[0036] The present invention aims to measure the bridge arm current i of the switch bridge arm SLn of the switch stage 5 of the inverter 1 Ln , the bridge arm current i Ln The current measurement according to the invention allows reliable and low-loss measurement, even of high-frequency currents (frequencies in the range of 100 kHz). Using the current measurement according to the invention, peak value measurements for overcurrent protection can also be performed at such high frequencies.

[0037] Reference Figure 4 , describes a current detection device 9 of the present invention, which is used to measure the AC bridge arm current i flowing through the choke coil L provided at the AC pole ACPn of the switching bridge arm SLn of the switching stage 5 of the inverter 1 Ln The switching leg SLn has at least two semiconductor switches Snm, ie, at least one high-side switch and at least one low-side switch. Figure 4 Only one switching leg SLn is shown in FIG. 1 , but the current measurement can of course be applied to other switching legs SLn of the inverter 1. As already described above, the DC filter 3 and the AC filter 6 (exemplarily showing a possible implementation) are optional.

[0038] The current detection device 9 includes a voltage measurement unit 12, such as a voltage sensor, a differential amplifier, etc., which measures the bridge arm voltage u across the choke coil L of the switching bridge arm SLn. Ln (like Figure 2 The current detection device 9 further comprises an integrator 13, which forms a measured voltage u at the choke coil L. Ln The integral ∫u over time t Ln . Time integral ∫u Ln Supplied to the processing unit 14 for processing.

[0039] Pulse-shaped bridge arm voltage u at the choke coil L Ln The time integral ∫u Ln is a triangular signal ( Figure 5 ). Therefore, the time integral ∫u Ln The shape corresponds to the bridge arm current i flowing through the choke coil L Ln The shape (such as Figure 2 As shown in Figure 2.10, the time integral ∫u Ln Indicates the bridge arm current i Ln This means that by the voltage u at the choke L Ln By integrating over time t, we can obtain the bridge arm current i corresponding to the choke coil L. Ln The measured value of the bridge arm current i Ln With the time integral ∫u LnThe difference between them is the proportional factor P, which depends on the implementation of the voltage measurement unit 12 and the integrator 13, that is, i Ln =P·∫u Ln , and can be considered known. Therefore, the time integral ∫u Ln Corresponding to the bridge arm current i Ln As described below, the time integral ∫u Ln can be evaluated and used in different ways in the processing unit 14. The processing unit 14 can apply a known scaling factor P in order to obtain the time integral ∫u Ln Get the bridge arm current i Ln The current measurement value.

[0040] For example, the voltage measuring unit 12 may be implemented as a well-known differential amplifier (eg, Figure 6 As shown) or an instrumentation amplifier using an operational amplifier OP, where the voltage u across the choke L Ln As input, the voltage measuring unit 12 is an analog circuit in this case. The output of the voltage measuring unit 12 is the voltage u V , which represents the bridge arm voltage u measured at the choke coil L Ln For a differential amplifier, the output voltage u V is the resistor of the circuit and the input u of the differential amplifier Ln The known function f D , that is u V =f D (u Ln ,R1,R2,R3,R4). The same applies to the instrumentation amplifier. Figure 6 Provides reference voltage V Ref , which is a known reference voltage. By using a differential amplifier or instrumentation amplifier, the high voltage u at the choke L Ln The output voltage u of the differential amplifier or instrumentation amplifier can be scaled down (depending on the resistors used) to a lower voltage, such as a voltage range between zero and 5 volts, which can be more easily handled in subsequent stages. V Indicates the bridge arm voltage u Ln The measured value.

[0041] The integrator 13 can also be implemented in a well-known manner as an analog circuit with an operational amplifier OP, such as Figure 7 Typically, the integrator 13 has a capacitor C in a feedback branch connecting the output port of the operational amplifier OP to the input port of the operational amplifier OP. I The output of integrator 13 is the input voltage u V , resistor R I , capacitor C in the feedback branch Iand a known function f of the time Δt between two measurements I , that is, the time integral ∫u Ln =f I (u V , R, C, Δt). In order to avoid that the integrator 13 drifts over time and thus integrates ∫u Ln To increase the offset, capacitor C I It can be reset at a given time. Reset can be done by connecting the two poles of capacitor CI through a reset switch S I to complete (such as Figure 7 The reset time can be related to the bridge arm current i flowing in the choke coil L. Ln For this purpose, a zero crossing detector 9 ( Figure 6 ) to detect the bridge arm current i Ln of zero crossing.

[0042] By closing the switch S I So that the capacitor C I Discharge and open the reset switch S I For capacitor C I It takes some time to recharge, so despite the reset, some offset error will still exist, especially at higher frequencies. Figure 8 As shown, in order to improve the reset, two capacitors C are used for alternate reset according to the present invention. I1 , C I2 .

[0043] exist Figure 8 In this embodiment, a capacitor C I1 With positive voltage u V (∫u Ln The rising edge of the capacitor C I2 With negative voltage u V (∫u Ln The capacitor C I1 , C I2 One of the switches is reset (by the corresponding switch S I1 , S I2 short circuit), the other is charged. Ln At each zero crossing, capacitor C I1 , C I2 The reset and charging are switched. By using two capacitors C I1 , C I2 and two switches S I1 , S I2 , which can reduce the offset introduced by reset.

[0044] Two switches SI1 , S I2 This can be achieved using a changeover switch, such as a single-pole double-throw switch. In such a switch, one of the two output contacts is always connected to the input contact, and by switching, the output contact connected to the input contact changes. In an advantageous embodiment, a make-before-break switch is used as a changeover switch. In a make-before-break switch, a new connection is established before the previous connection is disconnected, so that the input contact is temporarily connected to both output contacts. This avoids the capacitor C I1 , C I2 One of the capacitors C I1 , C I2 The other one in the charging, this is in the two switches S I1 , S I2 When both are open at the same time (which would be the case with a break-before-make switch) this will occur.

[0045] However, the integrator 13 can also be implemented as a well-known simple RC circuit, where the integrator resistor R I connected in series to the two series integrator capacitors C I (like Figure 8 As shown), the two integrator capacitors C I There are two reset switches S I (like Figure 8 As shown) are alternately reset. Across capacitor C I The voltage corresponds to the input voltage u of the RC circuit V The time integral ∫u Ln . Also, in this case, it would be advantageous to use a make-before-break switch.

[0046] In an alternative embodiment (not according to the invention), the integrator 13 may be implemented digitally, such as Fig.11 To this end, the input voltage u is measured by the voltage measuring unit 12. V is supplied to an analog-to-digital converter 16 (A / D converter) for converting the input voltage u V Digitalization. Digital input voltage u V is provided to the digital integrator 13 , for example software running on separate hardware or on the hardware of the controller 10 .

[0047] Then, in the embodiment shown in the controller 10, the bridge arm current i Ln The time integral of the measurement result ∫u Ln It can be processed in the processing unit 14.

[0048] For example, the processing unit 14 may be used for overcurrent protection or current measurement.

[0049] For over-current detection, such as Fig. 9 As shown in the exemplary embodiment, the processing unit 14 can be implemented as a comparator circuit 15. The comparator circuit 15 is an analog circuit using an operational amplifier OP. The comparator circuit 15 is designed to Ln Exceeding the given maximum current ±i Lnmax Output signal is output when the maximum current ±i Lnmax It can be a positive current and / or a negative current. In the embodiment shown, the time integral ∫u obtained from the analog integrator 13 Ln The signal is supplied to a first input port, for example, a positive input port, of a first operational amplifier OP1 of a first comparator of the comparator circuit 15. A second input port (for example, a negative input port) of the first operational amplifier OP1 is supplied with a reference voltage V Ref The values ​​of resistors Ra1 and Rb1 are selected so that when the bridge arm current i Lnn Exceeding the given maximum current i Lmax When the output voltage OV1 of the first operational amplifier OP1 is at a high level. Ln Therefore, a second comparator using an operational amplifier OP2 and resistors Ra2 and Rb2 may be provided in the comparator circuit 15 to detect the negative maximum current -i Lnmax In this case, the time integral ∫u Ln The signal is supplied to a voltage divider formed by resistors Ra2 and Rb2, and the output of the voltage divider is supplied to a first input port, for example, a negative input port, of the operational amplifier OP2. Ref The AC current i Ln Exceeding the given negative maximum current -i Lnmax When , the output voltage OV2 of the second operational amplifier OP2 of the comparator circuit 15 is preferably at a high level.

[0050] The output of the comparator circuit 15 may be provided to and processed by the inverter controller 10. If an overcurrent condition is detected, the inverter controller 10 may trigger an action. In the event of an overcurrent condition, the inverter controller 10 may switch the inverter 1 to a safe mode or reduce the output current i AC .

[0051] The time integral ∫u obtained from the analog integrator 13 Ln The signal can also be digitized using an analog-to-digital converter 16 (A / D converter) and provided to the processing unit 14 (such as Fig.10) (eg, inverter controller 10), where digital signals can be processed, for example, to control overcurrent protection of switching stage 5 of inverter 1. This can be used as bridge arm current i Ln The A / D converter 16 can of course also be integrated in the inverter controller 10, for example as software and / or as hardware.

[0052] A variety of designs of A / D converters 16 are known, and the present invention is not limited to a particular A / D converter. However, the conversion rate of the A / D converter 16 used should be fast enough to capture the measured voltage u in its given frequency band. V Or the bridge arm current i Ln .

Claims

1. An inverter having a switching stage (5) with at least one switching leg (SLn), wherein the at least one switching leg (SLn) comprises at least two semiconductor switches (Snm) connected in series and an AC pole (ACPn) between the semiconductor switches (Snm) connected in series, wherein the AC pole (ACPn) is connected in series to a choke (L), and wherein a current detection device (9) is arranged to detect a leg current (i Ln ), in, The current detection device (9) comprises a device for measuring the voltage (u Ln ) and also includes an integrator (13) for measuring a voltage (u) measured at the choke coil (L) Ln ) is integrated over time (t), where the voltage (u Ln ) time integral (∫u Ln ) represents the bridge arm current (i Ln ), and the current detection device (9) also includes a device for processing the time integral (∫u) provided by the integrator (13) Ln ) processing unit (14), wherein the processed time integral (∫u Ln ) control inverter (1), characterized in that two series-connected integrator capacitors (C I ) is arranged in an integrator (13), wherein across each integrator capacitor (C I )Set the reset switch (S I ) to alternately reset the corresponding integrator capacitors (C I ).

2. The inverter according to claim 1, It is characterized in that The voltage measurement unit (12) is implemented in analog form as a differential amplifier or an instrumentation amplifier using at least one operational amplifier (OP) and resistors (R1, R2, R3, R4).

3. The inverter according to claim 1 or 2, It is characterized in that The integrator (13) is implemented analogously as a series RC circuit using two integrator capacitors connected in series with an integrator resistor, or is implemented analogously as an operational amplifier circuit using at least one operational amplifier (OP) having two series integrator capacitors (C I ), the feedback branch connects the output port of the operational amplifier (OP) to the input port of the operational amplifier (OP).

4. The inverter according to claim 1, It is characterized in that Reset switch (S I ) is implemented as a toggle switch.

5. The inverter according to claim 1, It is characterized in that Reset switch (S I ) is implemented as a make-before-break switch.

6. The inverter according to claim 1 or 2, It is characterized in that and the bridge arm current (i Ln )'s zero crossings synchronously and alternately reset the series integrator capacitor (C I ).

7. The inverter according to claim 1 or 2, It is characterized in that The processing unit (14) is implemented in analog form as a comparator circuit, wherein when the bridge arm current (i Ln ) exceeds the given positive maximum current (i Lnmax ) and / or when the arm current (i Ln ) exceeds the given negative maximum current (-i Lnmax ), the comparator circuit provides an output signal (OV1).

8. The inverter according to claim 1 or 2, It is characterized in that The analog-to-digital converter (16) is configured to convert the time integral (∫u Ln ) is digitized, where the digitized time integral (∫u Ln ) is processed in processing unit (14).

9. A method for operating an inverter (1), the inverter (1) having a switching stage (5) with at least one switching leg (SLn), wherein the at least one switching leg (SLn) comprises at least two semiconductor switches (Snm) connected in series and an AC pole (ACPn) between the semiconductor switches (Snm) connected in series, wherein the AC pole (ACPn) is connected in series to a choke (L), and wherein a leg current (i Ln ), in, Measure the voltage (u) at the choke (L) Ln ) and the voltage (u Ln ) is integrated over time to represent the bridge arm current (i Ln ), and, where the time integral (∫u Ln ) is processed in the processing unit (14), wherein the processed time integral (∫u Ln ) controls the inverter (1), characterized in that two integrator capacitors (C I ) simulates the voltage (u) between the ground and the choke (L) Ln ) is integrated over time, with each integrator capacitor (C I )Set the reset switch (S I ) to alternately reset the corresponding integrator capacitors (C I ).

10. The method according to claim 9, It is characterized in that By having two integrator capacitors (C I ) or an operational amplifier circuit having at least one operational amplifier (OP) to simulate the voltage (u) at the choke (L) to ground. Ln ) integrates over time, the operational amplifier (OP) has two series-connected integrator capacitors (C I ), the feedback branch connects the output port of the operational amplifier (OP) to the input port of the operational amplifier (OP).

11. The method according to claim 9 or 10, It is characterized in that Two integrator capacitors (C I ) in the bridge arm current (i Ln ) are reset alternately at the zero crossings of the 12. The method according to any one of claims 9 to 10, It is characterized in that The time integral (∫u Ln ) and the given maximum positive bridge arm current (i Lnmax ) and / or a given negative maximum bridge arm current (-i Lnmax ) compared to perform over-current protection.

13. The method according to claim 9 or 10, It is characterized in that Integral over time (∫u Ln ) is digitized and provided digitally to a processing unit (14) for processing.

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