Method for forming semiconductor structure and physical vapor deposition device and method

Abstract

A method for forming a semiconductor structure and a physical vapor deposition device and method, the physical vapor deposition device comprising a chamber, a base, a cover ring and a barrier. The base is arranged at the bottom of the chamber. The cover ring surrounds the base and is electrically insulated from the base. The barrier surrounds the chamber wall of the physical vapor deposition device. The barrier comprises a first vertical portion, a second vertical portion and a horizontal portion. The first vertical portion is parallel to the chamber wall of the physical vapor deposition device, the cover ring is located between the first vertical portion and the base, wherein the first vertical portion is spaced from the outer side wall of the cover ring by about 2.3 mm to about 2.7 mm. The second vertical portion is located below the cover ring, wherein the top of the second vertical portion substantially contacts the cover ring. The horizontal portion is located below the cover ring and connects the first bottom end of the first vertical portion and the second bottom end of the second vertical portion.

Description

Technical Field

[0001] The present disclosure relates to a physical vapor deposition device, a method for depositing a thin film, and a method for forming a semiconductor structure. Background Art

[0002] Physical vapor deposition (PVD) is a well-known process for depositing a thin film of material on a substrate and is commonly used in the manufacture of semiconductor devices. The PVD process is carried out under high vacuum in a chamber that receives a substrate (e.g., a wafer) and contains a solid source or plate of material to be deposited on the substrate. The solid source or plate of material is therefore called a PVD target. In the PVD process, the PVD target is physically converted from a solid to a gas. The gas of the target is transported from the PVD target to the substrate, where it is deposited as a thin film on the substrate.

[0003] There are many methods for achieving physical vapor deposition, including evaporation, electron beam evaporation, plasma spray deposition, and sputtering. Currently, sputtering is the most common method for achieving physical vapor deposition. During sputtering, a plasma is generated in a chamber and directed to a physical vapor deposition target. Due to collisions with energetic particles (ions) of the plasma, the plasma physically displaces or erodes (sputters) atoms or molecules from the reactive surface of the physical vapor deposition target into the gas of the target. The gas of the sputtered atoms or molecules of the target is transported to the substrate through a reduced pressure zone and deposited on the substrate to form a thin film containing the target. Summary of the invention

[0004] One aspect of the present disclosure is to provide a physical vapor deposition device including a chamber, a base, a cover ring and a barrier. The base is arranged at the bottom of the chamber. The cover ring surrounds the base and is electrically insulated from the base. The barrier surrounds the chamber wall of the physical vapor deposition device. The barrier includes a first vertical portion, a second vertical portion and a horizontal portion. The first vertical portion is parallel to the chamber wall of the physical vapor deposition device, and the cover ring is located between the first vertical portion and the base, wherein the first vertical portion is separated from the outer side wall of the cover ring by a first distance, and the first distance is between 2.3 mm and 2.7 mm. The second vertical portion is located below the cover ring, wherein the top of the second vertical portion contacts the cover ring. The horizontal portion is located below the cover ring and connects the first bottom end of the first vertical portion and the second bottom end of the second vertical portion.

[0005] Another aspect of the present disclosure is to provide a method for depositing a thin film, comprising the following operations. A wafer is received in a physical vapor deposition apparatus. A process gas is introduced through a gas channel, and the process gas flows from below the base through a recess of a cover ring and through a channel between the barrier and the outer wall of the cover ring, and flows upward into the chamber. Energy is delivered to the chamber to form a plasma from the process gas, wherein the energy is provided by a radio frequency source and a direct current source. The plasma is bombarded with a target in the physical vapor deposition apparatus. A thin film is deposited on the surface of the wafer.

[0006] Another aspect of the present disclosure is to provide a method for forming a semiconductor structure, comprising the following operations. Depositing a dielectric layer on an underlying structure. Forming an opening through the dielectric layer. Forming a work function layer in the opening. Depositing a first cobalt thin film layer in the opening in a physical vapor deposition device, and the first cobalt thin film layer is located on the work function layer, wherein depositing the first cobalt thin film layer includes flowing a process gas through a gap between a barrier and a cover ring at a flow rate between 400 sccm and 450 sccm. Forming a second cobalt thin film layer to cover the first cobalt thin film layer and the sidewalls of the opening. Forming a third cobalt thin film to cover the second cobalt thin film layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The detailed description of the embodiments of the disclosed invention will be fully understood when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the features are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of discussion. Similar features are indicated by the same reference numerals in the specification and drawings.

[0008] Figure 1 A schematic diagram of a physical vapor deposition apparatus according to some embodiments of the present disclosure is shown;

[0009] Figure 2A A three-dimensional schematic diagram of a barrier and a cover ring according to some embodiments of the present disclosure is shown;

[0010] Figure 2B Draw Figure 2A A schematic cross-sectional view along the section line A-A';

[0011] Figure 2C Draw Figure 2B A partial enlarged view of region R;

[0012] Figure 2D , Figure 2E and Figure 2F A diagram showing the relationship between the first distance and the charge distribution according to various embodiments of the present disclosure is shown;

[0013] Figure 2G Another embodiment of the present disclosure is shown in FIG. Figure 2B A partial enlarged view of the middle region R;

[0014] Figure 3 A schematic diagram illustrating a physical vapor deposition apparatus during a process according to certain embodiments of the present disclosure;

[0015] Figure 4 A flow chart showing a method for depositing a thin film according to certain embodiments of the present disclosure is shown;

[0016] Figure 5 , Figure 6 , Figure 7 and Figure 8 Schematic cross-sectional views showing different stages of a method for depositing a thin film according to certain embodiments of the present disclosure;

[0017] Fig. 9 A flow chart illustrating a method of forming a semiconductor structure according to certain embodiments of the present disclosure is shown;

[0018] Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 Schematic cross-sectional views of different stages in a method of forming a semiconductor structure according to certain embodiments of the present disclosure are shown.

[0019]

Explanation of symbols

[0020] 100: Physical vapor deposition device

[0021] 102: Chamber wall

[0022] 104: Chamber

[0023] 110: Base

[0024] 112: Support column

[0025] 120: Cover ring

[0026] 122: Notch

[0027] 124: Bottom corner

[0028] 130: Barrier

[0029] 132: First vertical section

[0030] 134: Second vertical section

[0031] 136: Horizontal part

[0032] 138: Attachment

[0033] 140: Grounding ring

[0034] 150: Sedimentation Ring

[0035] 160: Target

[0036] 170: Power supply

[0037] 180: Pump

[0038] 190: Gas channel

[0039] 210: Arc detection element

[0040] 30: Methods

[0041] 310: Operation

[0042] 320: Operation

[0043] 330: Operation

[0044] 340: Operation

[0045] 350: Operation

[0046] 410: Wafer

[0047] 420:Thin film

[0048] 510: Plasma

[0049] 60: Methods

[0050] 610: Operation

[0051] 620: Operation

[0052] 630: Operation

[0053] 640: Operation

[0054] 650: Operation

[0055] 660: Operation

[0056] 710: Substructure

[0057] 720: Dielectric layer

[0058] 730: Opening

[0059] 740: Work function layer

[0060] 750: First cobalt thin film layer

[0061] 760: Second cobalt thin film layer

[0062] 770: The third cobalt film layer

[0063] 810: Metal gate

[0064] A-A': section line

[0065] D1: First distance

[0066] R: Region

[0067] W1: First width

[0068] W2: Second width

[0069] W3: Third width DETAILED DESCRIPTION

[0070] In order to make the description of the disclosed content more detailed and complete, the following is an illustrative description of the implementation and specific embodiments of the disclosed content; however, this is not the only form of implementing or using the specific embodiments of the disclosed content. The various embodiments disclosed below can be combined or replaced with each other in beneficial situations, and other embodiments can be added to one embodiment without further recording or explanation.

[0071] The following disclosure provides many different embodiments or examples to implement the different features of the multiple embodiments of the disclosure. The following content describes the specific examples of each component and its arrangement to simplify the description. Of course, these specific examples are not intended to be limiting. For example, in the following description, the first component is formed above or on the second component and may include an embodiment in which the first component and the second component are directly contacted through formation, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be directly contacted. In addition, the disclosure may repeat component symbols and / or letters in various examples. This repetition is used for the purpose of simplification and clarity and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0072] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "below," "above," "on," and the like, may be used herein to describe the relationship of one element or component to another element or components as depicted in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 100 degrees or at other orientations) and the spatially relative descriptors used herein interpreted similarly.

[0073] As used herein, terms such as "first", "second", and "third" describe various elements, components, regions, layers, and / or sections, but these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Unless the context clearly indicates otherwise, terms such as "first", "second", and "third" when used herein do not imply a sequence or order.

[0074] Physical vapor deposition is a suitable and widely used process for forming a thin film on a substrate (i.e., a wafer). Typically, an apparatus for performing physical vapor deposition operations includes a chamber and a process kit. The chamber may include chamber walls and a susceptor, and the process kit may be placed in the chamber to avoid undesirable material deposition on chamber components (such as chamber walls and susceptor).

[0075] Typically, the process kit includes a deposition ring, a cover ring, and a shield, but is not limited thereto. The deposition ring is placed on a susceptor. The cover ring is arranged to surround the deposition ring and the susceptor, and may at least partially cover the deposition ring. The wafer may be placed on the susceptor, and the edge of the wafer may overlap at least a portion of the deposition ring. The shield forms a closed space between the cover ring and the chamber wall. During a physical vapor deposition process for forming a film layer (for example, but not limited to) on a wafer, an electric arcing problem may occur. The arcing may be caused by an excessively strong electric field, causing an electrical breakdown of the gas to continue to form a plasma, wherein the reason for the excessively strong electric field is that the charge accumulation exceeds a critical value. It should be noted here that the critical value may vary depending on the impedance of the target material or the distance between the process kits. For example, compared to common metal materials (for example, titanium (Ti) or aluminum (Al)), cobalt materials have a larger resistance, and during the PVD process, the charge accumulation thereof is relatively large, which makes it easy for arcing to occur. Generally speaking, arcing usually occurs at the interface between the cover ring and the barrier. Arcing during physical vapor deposition may cause thicker deposition or undesirable contaminant residues in the local area containing the target film on the wafer. For example, an undesirable local thick film layer may form above the edge of the wafer.

[0076] In some comparative embodiments, a cleaning operation may be additionally performed to remove residues that act as potential arc sources prior to the physical vapor deposition operation. This approach can mitigate arc problems, but reduces overall throughput and increases process costs. In other comparative embodiments, the exhaust time during the physical vapor deposition operation is extended or the exhaust temperature during the physical vapor deposition operation is increased to mitigate arc problems, but reduces physical vapor deposition operation throughput and increases energy consumption. In other comparative embodiments, the discharge power is reduced to reduce charge accumulation, but this approach reduces physical vapor deposition throughput. In summary, although device designers have attempted to prevent arc problems during physical vapor deposition operations by making the above modifications, none of these methods can effectively reduce arcing without increasing process time, energy consumption and cost or reducing overall throughput.

[0077] Therefore, the present disclosure provides a physical vapor deposition apparatus for alleviating arcing problems without reducing physical vapor deposition throughput, increasing process costs, or increasing energy consumption. In some embodiments, by adjusting the distance between the cover ring and the barrier in the physical vapor deposition apparatus, the electron density distribution can be changed, thereby reducing the electric field strength to avoid arcing.

[0078] Figure 1 A schematic diagram of a physical vapor deposition apparatus 100 is shown according to certain embodiments of the present disclosure. It should be understood that although an apparatus is depicted as having components specific to a physical vapor deposition process, aspects of the disclosed apparatus may be applied to any type of processing operation utilizing plasma. For example, aspects of the disclosed apparatus may be applied to a plasma assisted chemical vapor deposition (PECVD) operation or a plasma etching operation.

[0079] like Figure 1 As shown, the physical vapor deposition apparatus 100 includes a chamber wall 102. In some embodiments, the chamber wall 102 may be a vacuum-sealed stainless steel chamber body, and a chamber 104 (or processing area) is formed in the chamber wall 102. The physical vapor deposition apparatus 100 also includes a base 110, a cover ring 120, and a barrier 130. Specifically, the base 110 (also referred to as a wafer stage or substrate support) is disposed at the bottom of the chamber 104. The base 110 is used to support and accommodate a processing object to be processed, such as a wafer. In some embodiments, the base 110 may include a heater (not shown) and / or an electrostatic chuck (ESC) (not shown).

[0080] like Figure 1As shown, the cover ring 120 surrounds the susceptor 110 and is electrically insulated from the susceptor 110. In some embodiments, the cover ring 120 comprises aluminum, stainless steel, or copper. In some embodiments, the cover ring 120 holds the wafer in place on the susceptor 110 when a positive air pressure is applied between the heater and the susceptor 110 so that heat can be efficiently transferred from the heater to the wafer. In some embodiments, the cover ring 120 comprises a notch 122 that is recessed from the lower surface of the cover ring 120 toward the upper surface of the cover ring 120. Therefore, another function of the cover ring 120 is to allow a process gas flow (e.g., argon) to flow from below the susceptor 110 into the chamber 104. In one embodiment, the bottom corner 124 of the notch 122 is not a right angle. In some embodiments, the bottom corner 124 of the notch 122 may be chamfered. Generally speaking, chamfering is a process of making the corners of an object with sharper corners or edges become gentler. A common practice is to process a right-angled edge into a surface with an angle of about 45 degrees. In other alternative embodiments, the bottom angle 124 of the recess 122 can be processed to form a surface with other angles (for example, about 30 degrees to about 60 degrees). When the bottom angle 124 of the recess 122 is processed to form a chamfer, the bottom surface of the recess 122 will be reduced. In detail, the portion adjacent to the opening of the recess 122 has a first width W1, and the portion away from the opening has a second width W2, and the first width W1 is greater than the second width W2.

[0081] In some embodiments, the physical vapor deposition apparatus 100 further includes a deposition ring 150 disposed between the base 110 and the cover ring 120. Figure 1 As shown, the deposition ring 150 is located on the susceptor 110 and surrounds the periphery of the susceptor 110. The deposition ring 150 may be at least partially covered by the cover ring 120. In some embodiments, the deposition ring 150 includes an insulating material, such as aluminum oxide (Al2O3). X O Y ) or aluminum nitride (Al X N Y The deposition ring 150 is used to electrically insulate the base 110 from the cover ring 120 .

[0082] like Figure 1 As shown, the barrier 130 surrounds the chamber wall 102 of the physical vapor deposition apparatus 100. Specifically, the barrier 130 is disposed between the cover ring 120 and the chamber wall 102 to form the chamber 104. The barrier 130 helps prevent or minimize particles sputtered from the target from being deposited on the inner surface of the chamber wall 102. In some embodiments, the barrier 130 comprises aluminum, stainless steel, or copper.

[0083] like Figure 1As shown, the barrier 130 may include a first vertical portion 132, a second vertical portion 134, a horizontal portion 136, and an attachment portion 138. In more detail, the cover ring 120 is located between the first vertical portion 132 and the base 110. In some embodiments, the attachment portion 138 is mounted to the top of the chamber wall 102. The first vertical portion 132 extends downward from the attachment portion 138 and is substantially parallel to the chamber wall 102. The horizontal portion 136 connects the bottom end of the first vertical portion 132 and extends inward. In some embodiments, the angle between the horizontal portion 136 and the first vertical portion 132 is substantially a right angle. The second vertical portion 134 connects one end of the horizontal portion 136 and extends upward. Both ends of the horizontal portion 136 are respectively connected to the bottom end of the first vertical portion 132 and the bottom end of the second vertical portion 134, and are located below the cover ring 120. In some embodiments, the second vertical portion 134 is substantially parallel to the first vertical portion 132. In some embodiments, the second vertical portion 134 is smaller than the first vertical portion 132. In one embodiment, the first vertical portion 132, the second vertical portion 134, the horizontal portion 136, and the attachment portion 138 of the barrier 130 may be integrally formed. In another embodiment, the first vertical portion 132, the second vertical portion 134, the horizontal portion 136, and the attachment portion 138 of the barrier 130 may be assembled by welding.

[0084] Figure 2A A schematic three-dimensional diagram of the barrier 130 and the cover ring 120 according to some embodiments of the present disclosure is shown. Figure 2B Draw Figure 2A Schematic diagram of the cross section along the section line AA'. Figure 2C Draw Figure 2B A partial enlarged view of region R. See also Figure 1 , Figure 2A , Figure 2B and Figure 2C It should be noted that the first vertical portion 132 is spaced apart from the outer sidewall of the cover ring 120 by a first distance D1, and the first distance D1 is between about 2.3 mm and about 2.7 mm. In some embodiments, the first distance D1 may be between about 2.4 mm and about 2.6 mm, between about 2.4 mm and about 2.5 mm, or between about 2.5 mm and about 2.6 mm.

[0085] Figure 2D , Figure 2E and Figure 2F A diagram showing the relationship between the first distance and the charge distribution according to various embodiments of the present disclosure is shown. Figure 2D FIG. 2 shows the charge distribution when the first distance D1 is between about 2.3 mm and about 2.7 mm. Figure 2DIt can be seen that when the first distance D1 is between about 2.3 mm and about 2.7 mm, the charges are evenly distributed. Figure 2E FIG. 2 shows the charge distribution when the first distance D1 is less than about 2.3 mm. Figure 2E It can be seen that when the first distance D1 is less than about 2.3 mm, most of the charges are concentrated and accumulated between the first vertical portion 132 and the outer sidewall of the cover ring 120 , thereby causing an arc to occur. Figure 2F FIG. 2 shows the charge distribution when the first distance D1 is greater than about 2.7 mm. Figure 2F It can be seen that when the first distance D1 is greater than about 2.7 mm, the charges are more sparsely distributed between the first vertical portion 132 and the outer wall of the cover ring 120, making it difficult to generate plasma or requiring increased applied power to generate the required amount of plasma. Accordingly, if the first distance D1 is too large or too small, it will affect the uniformity of charge distribution or the electric field strength, resulting in insufficient plasma or arcing.

[0086] Continue reading Figure 1 , Figure 2A , Figure 2B and Figure 2C The second vertical portion 134 is located below the cover ring 120. In some embodiments, the top of the second vertical portion 134 extends into the recess 122 of the cover ring 120 and substantially contacts the bottom surface of the recess 122. It should be noted that although the top of the second vertical portion 134 substantially contacts the bottom surface of the recess 122, it does not block the flow of process gas (e.g., argon) into the chamber 104. During the physical vapor deposition process, high-energy particles (ions) collide with each other at high speed in the chamber and may hit the process kit (e.g., the barrier 130) in the chamber, causing a slight displacement of the distance between the process kits. By processing the bottom corner 124 of the recess 122 of the cover ring 120 into a chamfer, the displacement of the second vertical portion 134 of the barrier 130 during the physical vapor deposition process is further limited, so that the first distance D1 can be controlled between about 2.3 mm and about 2.7 mm. In one embodiment, the bottom surface of the notch 122 has a second width W2, the second vertical portion has a third width W3, and the second width W2 is substantially greater than or equal to the third width W3. More specifically, the second width W2 is greater than the third width W3 by about 0.1 mm to about 0.4 mm, such as about 0.2 mm to about 0.3 mm.

[0087] Figure 2G Another embodiment of the present disclosure is shown in FIG. Figure 2B FIG. 1 is a partial enlarged view of the middle region R. In some embodiments, the top end of the second vertical portion 134 extends into the recess 122 of the cover ring 120 and does not contact the bottom surface of the recess 122 .

[0088] Please go back Figure 1In some embodiments, the physical vapor deposition apparatus 100 may further include a ring-shaped grounding ring 140 surrounding and mounted on the support column 112 of the base 110. Specifically, the diameter of the grounding ring 140 is greater than the diameter of the support platform of the base 110. In more detail, the grounding ring 140 extends laterally below the horizontal portion 136 of the barrier 130. In some embodiments, the support column 112 includes aluminum, stainless steel, or copper. In some embodiments, the grounding ring 140 includes aluminum, stainless steel, or copper. The grounding ring 140 can lead out excess charges accumulated on the base 110.

[0089] In some embodiments, the physical vapor deposition apparatus 100 further includes a target 160 and a power supply 170. The power supply 170 may be electrically connected to the target 160. In some embodiments, the power supply 170 is a direct current (DC) supply, a radio frequency (RF) supply, or a DC-RF supply. The target 160 includes a material to be deposited on a wafer. In many embodiments, the target 160 may include copper (Cu), titanium (Ti), nickel (Ni), aluminum (Al), cobalt (Co), tungsten (W), tantalum (Ta), silver (Ag), gold (Au), nickel-platinum alloy (Ni-Pt), nickel-titanium alloy (Ni-Ti), or other suitable metals or metal alloys. The power supply 170 may apply a bias voltage to the target 160, and the electric field generated in the chamber 104 by the applied voltage excites the sputtering gas to form a plasma, which actively impacts and bombards the target 160 to sputter out the material from the target 160 and deposit it on the wafer.

[0090] In some embodiments, the physical vapor deposition apparatus 100 further includes one or more pumps 180 to exhaust air from the chamber 104. In many embodiments, the pump 180 may be controlled by a controller (not shown) and may be used to maintain the pressure in the chamber 104 at a desired pressure value. In addition, after the processing process is completed, the pump 180 may be used to evacuate the gas in the chamber 104 in preparation for removing the wafer from the chamber 104. In many embodiments, the pump 180 may include a cryopump, a turbomolecular pump, a mechanical pump, or other suitable pumps.

[0091] In some embodiments, the physical vapor deposition apparatus 100 further includes a gas channel 190. The gas channel 190 has a gas flow control valve (not shown) such as a mass flow controller to allow the process gas to pass through at a set flow rate. The process gas may include an inactive gas that can collide with the target 160 and sputter material from the target 160, such as argon (Ar) or xenon (Xe). Figure 1Only one gas channel 190 is shown, but the present invention is not limited thereto, and the number of gas channels 190 may be increased as required, such as 2, 3 or 4.

[0092] In some embodiments, the physical vapor deposition apparatus 100 further includes an arc detection element 210. The arc detection element 210 is connected to the chamber 104, and a signal is transmitted to the arc detection element 210 through a sensing element (not shown) disposed in the chamber 104. In some embodiments, the arc detection element 210 includes a magnetic field sensor (not shown) and an arc analysis circuit system (not shown). The magnetic field sensor may include a coil made of a conductive material such as copper, aluminum, nickel or other metals or alloys. In some embodiments, the coil is a closed conductive path. The magnetic field sensor is configured to generate a magnetic field signal, such as in the form of a current or voltage, wherein the magnitude of the magnetic field signal is proportional to the magnetic flux through the closed conductive path of the magnetic field sensor. The arc analysis circuit system is configured to evaluate the magnetic field signal and determine whether an arc has occurred in the chamber 104. If an arc is detected, the wafer can be removed and the defects of the wafer can be evaluated, and the power supply 170 can be immediately shut down until the chamber 104 can be tested and / or repaired.

[0093] In some embodiments, the physical vapor deposition apparatus 100 can be controlled and automated by a system controller (not shown). Generally, the system controller includes a central processing unit (not shown), support circuits (not shown), or memory (not shown). The central processing unit can be any type of computer processor that is used to control various system functions, wafer movement, support hardware (e.g., sensors, robotic arms, motors, etc.) and monitor processes (e.g., susceptor temperature, power supply variables, process time, support circuit signals, etc.). The memory is connected to the central processing unit and is a readily accessible memory, such as random access memory (RAM), read-only memory (ROM), hard disk, floppy disk, or any other proximal or remote digital storage. Software instructions and data can be encoded and stored in the memory to instruct the central processing unit. The support circuits are connected to the central processing unit. The support circuits include power supplies, clock circuits, input / output circuits, cache memories, subsystems, etc.

[0094] Figure 3A schematic diagram of a physical vapor deposition apparatus 100 during a process according to certain embodiments of the present disclosure is illustrated. During the physical vapor deposition process, the support column 112 will raise the base 110 and the grounding ring 140 to an operating height. At this time, the grounding ring 140 will touch the barrier 130, thereby making the entire charge loop present a uniform grounding state. At the same time, the deposition ring 150 will also touch the cover ring 120, and the deposition ring 150 is used to electrically insulate the base 110 from the cover ring 120. On the other hand, a process gas (such as argon (Ar) or xenon (Xe)) flows from below the base 110 through the gas channel 190, through the recess 122 of the cover ring 120, and upwardly enters the chamber 104 through the first distance D1 between the first vertical portion 132 and the outer wall of the cover ring 120, as shown in FIG. Figure 3 As shown in the direction of the arrow. Since the process gas will flow through the channel or gap (i.e., the first distance D1) between the first vertical portion 132 and the outer wall of the cover ring 120, the amount of process gas flow will affect the formation of plasma and / or the generation of arcs. In some embodiments, the flow rate of the process gas flowing through the channel or gap (i.e., the first distance D1) may be in the range of about 400 sccm to about 450 sccm. For example, the flow rate of the process gas flowing through the channel or gap (i.e., the first distance D1) may be in the range of about 410 sccm to about 440 sccm or may be in the range of about 420 sccm to about 430 sccm. When the flow rate of the process gas is less than about 400 sccm, the amount of process gas entering the chamber 104 is insufficient, thereby affecting the amount of plasma generated. On the contrary, when the flow rate of the process gas is greater than about 450 sccm, a large amount of charges are likely to accumulate between the first vertical portion 132 and the outer wall of the cover ring 120 (ie, the first distance D1 ) after the plasma is formed, thereby easily generating an arc.

[0095] Figure 4 A flow chart of a method 30 for depositing a thin film according to some embodiments of the present disclosure is shown. Figure 5 , Figure 6 , Figure 7 Figure 8 Schematic cross-sectional views of different stages in a method of depositing a thin film according to certain embodiments of the present disclosure are shown. It should be understood that additional operations may be performed before, during, and after method 30, and that some of the operations may be replaced, eliminated, or moved for additional embodiments of method 30. Method 30 for depositing a cobalt thin film is only an exemplary embodiment, and includes operations 310, 320, 330, 340, and 350.

[0096] See also Figure 5In operation 310 , a wafer 410 is received in a physical vapor deposition apparatus (such as the physical vapor deposition apparatus 100 described above). In some embodiments, the wafer 410 placed on the susceptor 110 is raised to an operating position so that the deposition ring 150 touches the cover ring 120 .

[0097] In operation 320, a process gas is introduced through the gas passage 190. The process gas flows from the bottom of the susceptor 110 through the recess 122 at the bottom of the cover ring 120 and through the passage (i.e., the first distance D1) between the barrier 130 (i.e., the first vertical portion 132) and the outer wall of the cover ring 120, and then flows into the chamber 104. Figure 3 shown.

[0098] See also Figure 6 In operation 330, energy is delivered to the physical vapor deposition apparatus 100 to form a plasma 510. Specifically, the energy is provided by the power supply 170, wherein the power supply 170 is a DC-RF supply. In some embodiments, the pressure in the chamber 104 can be adjusted to a desired pressure by the pump 180. A process gas (such as argon (Ar) or xenon (Xe)) is then introduced into the chamber 104 through the gas channel 190 until the optimal conditions for igniting the plasma 510 are reached.

[0099] See also Figure 7 In operation 340, the plasma 510 is bombarded with the target 160 in the physical vapor deposition apparatus 100. Specifically, the target 160 may be a cobalt target. In some embodiments, the power supply 170 may apply a bias voltage to the target 160, thereby generating atoms, molecules and / or ions from the target 160. The ions in the plasma 510 (such as Ar ions or Xe ions) are accelerated and collide with the target 160. It should be noted that compared to common metal materials (for example, titanium (Ti) or aluminum (Al)), the cobalt material has a larger resistance, and its charge accumulation during the PVD process is relatively large, which makes it easy for arcing to occur. Therefore, it is necessary to limit the first distance D1 (see FIG. 1 ) between the first vertical portion 132 of the barrier 130 and the outer wall of the cover ring 120 in the physical vapor deposition apparatus 100. Figure 1 ).

[0100] See also Figure 8 In operation 350, a thin film 420 is deposited on the surface of the wafer 410. Specifically, the thin film 420 may be a cobalt thin film.

[0101] Fig. 9 A flow chart of a method 60 of forming a semiconductor structure according to some embodiments of the present disclosure is shown. Fig.10 , Fig.11 , Fig.12 , Fig.13, Fig.14 , Fig.15 and Fig.16 Schematic cross-sectional views of various stages of a method 60 for forming a semiconductor structure according to some embodiments of the present disclosure are shown. It should be understood that additional operations may be performed before, during, and after the method 60, and some of the operations may be replaced, eliminated, or moved for additional embodiments of the method 60. The method 60 for forming a semiconductor structure is merely an illustrative embodiment and includes operations 610, 620, 630, 640, 650, and 660.

[0102] See also Fig.10 In operation 610, a dielectric layer 720 is deposited on the underlying structure 710. In various embodiments, the dielectric layer 720 comprises one or more layers of dielectric materials, such as silicon oxide, silicon nitride, titanium nitride, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. In various embodiments, the dielectric layer 720 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or any suitable method.

[0103] In some embodiments, the lower structure 710 is a typical semiconductor substrate having various deposited pre-metal layers or dielectric layers formed thereon. For example, the lower structure 710 may be a silicon substrate having active features, wherein the active features may be one or more layers of polysilicon layers, field effect isolation oxide layers, gate oxide layers, silicon nitride layers, and metallization layers.

[0104] In some embodiments, in order to form the lower structure 710, an extremely pure single crystal silicon wafer is first exposed to high temperature steam and a layer of silicon nitride is formed thereon. Then, a reactive gas, such as brine and ammonia, is deposited on the surface of the silicon nitride layer by CVD. It is worth noting that other deposition steps such as atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), metal organic CVD (MOCVD), PVD, ALD, chemical solution deposition, sputtering, and combinations thereof can all be used. This structure is coated with a photoresist layer, and is patterned by lithography technology and a guide hole is etched by a dry etching process to form a shallow trench isolation (STI) structure. The lower structure 710 includes a variety of structures and layers before the metal layer. Figures 10 to 16 The simplified diagram is shown as a single layer.

[0105] See also Fig.11 , in operation 620, an opening 730 is formed through the dielectric layer 720. More specifically, the opening 730 exposes a portion of the underlying structure 710. In many embodiments, first, a photoresist layer (not shown) can be coated on the dielectric layer 720, and then a patterning process is completed by lithography. In the patterning process, the photoresist layer can be selectively exposed to ultraviolet radiation and developed to form a hole pattern in the photoresist mask (not shown). Then, the opening 730 can be formed through the dielectric layer 720 by dry etching using a reactive gas such as fluoride, oxygen, chlorine, and boron trichloride. In other embodiments, nitrogen, argon, helium, and other gases may sometimes be added to the reactive gas.

[0106] See also Fig.12In operation 630, a work function layer 740 is formed at the bottom of the opening 730. The work function layer 740 is made of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. For an n-channel field-effect transistor (FET), one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the work function layer 740, and for a p-channel FET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used as the work function layer 740. The work function layer 740 can be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. In addition, the work function layer 740 can be formed separately for n-channel FETs and p-channel FETs, and these FETs can use different metal layers.

[0107] See also Fig.13 In operation 640, a first cobalt thin film layer 750 is deposited in a physical vapor deposition apparatus (such as the physical vapor deposition apparatus 100 described above) in the opening 730, and the first cobalt thin film layer 750 is located on the work function layer 740. It should be noted that depositing the first cobalt thin film layer includes flowing a process gas through the gap between the barrier and the cover ring at a flow rate between about 400 sccm and about 450 sccm.

[0108] See also Fig.14 In operation 650, a second cobalt thin film layer 760 is formed to cover the first cobalt thin film layer 750 and a sidewall of the opening 730. In some embodiments, the second cobalt thin film layer 760 is conformally deposited on the first cobalt thin film layer 750 and the sidewall of the opening 730 by a CVD process.

[0109] See also Fig.15 In operation 660, a third cobalt thin film layer 770 is formed to cover the second cobalt thin film layer 760. In some embodiments, the third cobalt thin film layer 770 is formed by electrochemical plating (ECP) to fill the remaining opening 730.

[0110] In some embodiments, after operation 660, a metal gate 810 may be formed by planarizing the second cobalt thin film layer 760 and the third cobalt thin film layer 770, such as Fig.16 As shown in FIG. 1 , the first cobalt thin film layer 750 , the second cobalt thin film layer 760 and the third cobalt thin film layer 770 are all made of cobalt, therefore, in fact, the metal gate 810 does not exist. Fig.16The top surface of the metal gate 810 and the top surface of the dielectric layer 720 may be planarized using, for example, a chemical-mechanical planarization (CMP) process.

[0111] One aspect of the present disclosure is to provide a physical vapor deposition device including a chamber, a base, a cover ring and a barrier. The base is arranged at the bottom of the chamber. The cover ring surrounds the base and is electrically insulated from the base. The barrier surrounds the chamber wall of the physical vapor deposition device. The barrier includes a first vertical portion, a second vertical portion and a horizontal portion. The first vertical portion is substantially parallel to the chamber wall of the physical vapor deposition device, and the cover ring is located between the first vertical portion and the base, wherein the first vertical portion is spaced a first distance from the outer side wall of the cover ring, and the first distance is between 2.3 mm and 2.7 mm. The second vertical portion is located below the cover ring, wherein the top of the second vertical portion substantially contacts the cover ring. The horizontal portion is located below the cover ring and connects the first bottom end of the first vertical portion and the second bottom end of the second vertical portion.

[0112] According to multiple embodiments of the present disclosure, the physical vapor deposition device further includes a deposition ring located between the base and the cover ring, and the deposition ring is configured to electrically insulate the base from the cover ring. According to multiple embodiments of the present disclosure, the cover ring has a recess, which is recessed from the lower surface of the cover ring toward the upper surface of the cover ring. According to multiple embodiments of the present disclosure, a bottom angle of the recess is chamfered. According to multiple embodiments of the present disclosure, the top of the second vertical portion extends into the recess. According to multiple embodiments of the present disclosure, the bottom surface of the recess has a first width, the second vertical portion has a second width, and the first width is substantially greater than or equal to the second width. According to multiple embodiments of the present disclosure, the physical vapor deposition device further includes a grounding ring surrounding the support column of the base, and the diameter of the grounding ring is greater than the diameter of the support platform of the base. According to multiple embodiments of the present disclosure, the grounding ring extends laterally to below the horizontal portion.

[0113] Another aspect of the present disclosure is to provide a method for depositing a thin film, comprising the following operations. A wafer is received in a physical vapor deposition apparatus. A process gas is introduced through a gas channel, and the process gas flows from below the base through a recess of a cover ring and through a channel between the barrier and the outer wall of the cover ring, and flows upward into the chamber. Energy is delivered to the chamber to form a plasma from the process gas, wherein the energy is provided by a radio frequency source and a direct current source. The plasma is bombarded with a target in the physical vapor deposition apparatus. A thin film is deposited on the surface of the wafer.

[0114] Another aspect of the present disclosure is to provide a method for forming a semiconductor structure, comprising the following operations. Depositing a dielectric layer on an underlying structure. Forming an opening through the dielectric layer. Forming a work function layer in the opening. Depositing a first cobalt thin film layer in the opening in a physical vapor deposition apparatus, and the first cobalt thin film layer is located on the work function layer, wherein depositing the first cobalt thin film layer includes flowing a process gas through a gap between a barrier and a cover ring at a flow rate between about 400 sccm and about 450 sccm. Forming a second cobalt thin film layer to cover the first cobalt thin film layer and the sidewalls of the opening. Forming a third cobalt thin film to cover the second cobalt thin film layer.

[0115] The foregoing text summarizes the features of many embodiments so that those with ordinary knowledge in the art can better understand the various embodiments of the present disclosure from various aspects. Those with ordinary knowledge in the art should understand and can easily design or modify other processes and structures based on the various embodiments of the present disclosure, and thereby achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those with ordinary knowledge in the art should also understand that these equivalent structures do not deviate from the spirit and scope of the invention of the various embodiments of the present disclosure. Various changes, substitutions or modifications may be made to the various embodiments of the present disclosure without departing from the spirit and scope of the invention of the various embodiments of the present disclosure.

Claims

1. A physical vapor deposition device, characterized in that: Include: One chamber; A base, disposed at a bottom of the chamber, the base comprising a loading platform and a support column disposed under the loading platform; a target material disposed in the chamber, wherein the target material is a cobalt target material; a grounding ring surrounding the support column, wherein the support column elevates the support platform of the base and the grounding ring surrounding the support column to an operating height; a cover ring surrounding the base and electrically insulated from the base, the cover ring having a recess, the recess comprising a first portion and a second portion, the first portion being adjacent to the opening and having a first width, the second portion being away from the opening and having a second width, and the first width being greater than the second width; and A barrier surrounding a chamber wall of the physical vapor deposition apparatus, the barrier comprising: a first vertical portion parallel to the chamber wall of the physical vapor deposition apparatus, the cover ring being located between the first vertical portion and the susceptor, wherein the first vertical portion is spaced apart from an outer sidewall of the cover ring by a first distance, the first distance being between 2.3 mm and 2.7 mm, a flow rate of a process gas flowing through the first distance being between 400 sccm and 450 sccm, the first distance and the flow rate being configured to make the easily accumulated charge caused by the resistance of the cobalt present a uniform distribution; a second vertical portion, located below the cover ring, wherein a top end of the second vertical portion extends into the second portion and contacts the cover ring; as well as A horizontal portion is located below the cover ring and connects a first bottom end of the first vertical portion and a second bottom end of the second vertical portion.

2. The physical vapor deposition device according to claim 1, characterized in that: The invention also comprises a deposition ring located between the base and the cover ring, wherein the deposition ring is configured to electrically insulate the base from the cover ring.

3. The physical vapor deposition device according to claim 1, characterized in that: The notch is recessed from a lower surface of the cover ring toward an upper surface of the cover ring.

4. The physical vapor deposition device according to claim 3, characterized in that: A bottom corner of the notch is chamfered.

5. The physical vapor deposition device according to claim 4, characterized in that: The base angle has a face of 30 to 60 degrees.

6. The physical vapor deposition apparatus according to claim 3, characterized in that: A bottom surface of the notch has a first width, the second vertical portion has a second width, and the first width is greater than or equal to the second width.

7. The physical vapor deposition apparatus according to claim 1, characterized in that: A diameter of the grounding ring is greater than a diameter of the supporting platform.

8. The physical vapor deposition apparatus according to claim 7, characterized in that: The grounding ring extends laterally to below the horizontal portion.

9. A method for depositing a thin film, characterized in that: Include: Receiving a wafer in the physical vapor deposition apparatus of claim 1, comprising: The target is a cobalt target; and The support column of the base raises the support platform of the base and the grounding ring surrounding the support column to an operating height so that the grounding ring touches the barrier; A process gas is introduced through a gas channel, the process gas flows from below the susceptor through the recess of the cover ring and through a channel between the barrier and an outer side wall of the cover ring, and flows upward into the chamber, the process gas flows through the channel at a flow rate between 400 sccm and 450 sccm, and the channel and the flow rate are configured to make the charge easily accumulated due to the resistance of the cobalt present a uniform distribution; Delivering energy into the chamber to form a plasma from the process gas, wherein the energy is provided by a DC-RF supply; Allowing the plasma to bombard a target in the physical vapor deposition apparatus; and A thin film is deposited onto a surface of the wafer.

10. A method for forming a semiconductor structure, characterized in that: Include: depositing a dielectric layer on the underlying structure; forming an opening through the dielectric layer; forming a work function layer in the opening; Depositing a first cobalt thin film layer in the opening in the physical vapor deposition apparatus as claimed in claim 1, wherein the first cobalt thin film layer is located on the work function layer, wherein the support column of the pedestal raises the support platform of the pedestal and the grounding ring surrounding the support column to an operating height so that the grounding ring touches the barrier, and depositing the first cobalt thin film layer comprises flowing a process gas through a gap between the barrier and the cover ring at a flow rate between 400 sccm and 450 sccm; forming a second cobalt thin film layer to cover the first cobalt thin film layer and a side wall of the opening; and A third cobalt thin film layer is formed to cover the second cobalt thin film layer.

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