A method for low-speed sampling and signal restoration of ultrasonic signals

Abstract

The present invention relates to a low-speed sampling and signal restoration method of ultrasonic signals, and belongs to the technical field of ultrasonic wind speed and flow velocity measurement. The present invention adopts a peak holding circuit to realize the retention of the maximum or minimum value of the signal within a period of time; adopts a zero-crossing comparator to accurately realize the time detection of ultrasonic signals; adopts a hysteresis comparator as a trigger to realize the sampling of the signal extreme points and zero-crossing moments; and then based on the ultrasonic signal mathematical model, completes the restoration of the signal. The steps are: the trigger signal of the hysteresis comparator triggers an AD sampling, and stores the sampled value in the data buffer area, triggers the timer to store the most recent recording time data in the data buffer area, and completes the signal restoration based on the data stored in the current data buffer area and the ultrasonic signal mathematical model. The present invention can complete the extreme point sampling without distortion, while reducing the overall design cost and power consumption of the ultrasonic wind speed and flow velocity measurement device.

Description

Technical Field

[0001] The invention belongs to the technical field of ultrasonic wind speed and flow velocity measurement, and relates to a low-speed sampling and signal restoration method of ultrasonic signals. Background Art

[0002] The ultrasonic time difference method can realize the measurement of wind speed and direction, flow velocity and flow rate. It has the advantages of small influence of ambient temperature, low lower limit, wide range, high accuracy, good linearity and no pressure loss. It is gradually becoming the mainstream technology in the field of meteorology and precision measurement.

[0003] The ultrasonic time difference method requires the calculation of the ultrasonic wave's upstream and downstream transit time. The more commonly used algorithms include the threshold method, variable threshold method, correlation method, and phase difference method. These methods all require sampling of the ultrasonic signal.

[0004] According to Shannon's theorem, the sampling frequency needs to be greater than twice the frequency of the sampled signal. However, in order to obtain signal characteristics more realistically and completely, the sampling frequency of ultrasonic signals is often more than 10 times its own frequency. The increase in frequency will increase costs and power consumption, and due to the existence of the sampling interval, it may also cause distortion in the sampling of the most important characteristic points of ultrasonic signals - extreme points. Summary of the invention

[0005] In view of this, an object of the present invention is to provide a low-speed sampling and signal restoration method for ultrasonic signals, which completes extreme point sampling without distortion and restores the sampled ultrasonic signals at the same time.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] A low-speed sampling and signal recovery method for ultrasonic signals, using a peak holding circuit to achieve the retention of the ultrasonic signal extreme value for a period of time; using a zero-crossing comparator to convert the ultrasonic signal into a square wave signal to achieve signal time detection; using a hysteresis comparator to convert the ultrasonic signal into a square wave signal, setting a trigger signal according to demand, and achieving sampling of the signal extreme value point and zero-crossing moment;

[0008] The method comprises the following steps:

[0009] S1, peak hold circuit keeps the extreme value of ultrasonic signal for a certain period of time;

[0010] S2, the trigger signal of the hysteresis comparator triggers an AD sampling, and the sampling value is stored in the data buffer area. After completion, a reset signal is generated, and the peak holding circuit is reset to prepare for the next acquisition;

[0011] S3, the timer detects the falling edge of the zero-crossing comparator and records the time when the falling edge occurs. The trigger signal of the hysteresis comparator triggers the timer to store the most recently recorded time data into the data buffer area;

[0012] S4. Based on the data stored in the current data buffer and the ultrasonic signal mathematical model, the collected signal is restored through an interpolation algorithm.

[0013] Furthermore, the method can use a sampling frequency of 1 times the ultrasonic frequency for low-speed sampling, and can also use a sampling frequency of 2 times the ultrasonic frequency for low-speed sampling.

[0014] Furthermore, when a sampling frequency of 1 times the ultrasonic frequency is used for low-speed sampling, the signal sampling and recovery steps are as follows:

[0015] S11, the peak hold circuit maintains the maximum value of the ultrasonic signal for a certain period of time;

[0016] S21, the falling edge of the hysteresis comparator is used as a trigger signal to trigger an AD sampling. At this time, the peak hold circuit is in the maximum value holding state, and the sampling value is the peak value V of the previous wave of the ultrasonic signal. Pi , store the sampled value into the data buffer area, and generate a reset signal after completion, and the peak hold circuit is reset to prepare for the collection of the next peak;

[0017] S31, the timer detects the falling edge of the zero-crossing comparator and records the time when the falling edge occurs T Fi , the trigger signal of the hysteresis comparator triggers the timer to store the most recently recorded time data into the data buffer;

[0018] S41, based on the data stored in the current data buffer and the ultrasonic signal mathematical model, the interpolation algorithm is used to complete (T F1 ,T Fn ) ultrasonic signal restoration in the area;

[0019] The mathematical model of ultrasonic signal is:

[0020]

[0021] The mathematical model of ultrasonic signal consists of two parts: A(t) is the amplitude information of the signal. is the phase information of the signal. Implement the interpolation algorithm separately to obtain:

[0022]

[0023] Among them, T Fi ≤t<T F(i+1) ,i∈[1,n-1].

[0024] Furthermore, when a sampling frequency of twice the ultrasonic frequency is used for low-speed sampling, the signal sampling and recovery steps are as follows:

[0025] S12, the peak hold circuit keeps the maximum and minimum values ​​of the ultrasonic signal within a certain period of time;

[0026] S22, the rising edge and falling edge of the hysteresis comparator will trigger an AD sampling, and the absolute value of the sampling value |V Pi |Store in the data buffer area, generate a reset signal after completion, and reset the peak hold circuit to prepare for the next acquisition;

[0027] S32, the timer detects the falling edge of the zero-crossing comparator and records the time when the falling edge occurs T i , the rising edge and falling edge of the hysteresis comparator will trigger the timer to store the most recently recorded time data into the data buffer;

[0028] S42, based on the data stored in the current data buffer and the ultrasonic signal mathematical model, complete (T1, T n ) ultrasonic signal restoration in the area;

[0029] Signal restoration:

[0030] Positive half cycle:

[0031] Negative half cycle:

[0032] Where T i ≤t<T (i+1) .

[0033] Furthermore, the peak holding circuit includes a maximum value holding circuit and a minimum value holding circuit.

[0034] Furthermore, the maximum value holding circuit includes operational amplifiers U1 and U2, diodes D1 and D2, resistors R1 and R2, transistor Q1, and capacitor C2; the positive input terminal of the operational amplifier U1 is connected to the input terminal of the maximum value holding circuit, its output terminal is connected to the cathode of the diode D1 and the anode of the diode D2, its reverse input terminal is connected to the anode of the diode D1, the cathode of the diode D2 is connected to the collector of the transistor Q1, one end of the capacitor C2, and the positive input terminal of the operational amplifier U2, the other end of the capacitor C2 is grounded, the emitter of the transistor Q1 is grounded, and the base is connected to the resistor R2, the output terminal of the operational amplifier U2 is connected to the reverse input terminal and the output terminal of the maximum value holding circuit, and the resistor R1 is connected between the reverse input terminals of the operational amplifiers U1 and U2.

[0035] Further, the minimum value holding circuit includes operational amplifiers U3 and U4, diodes D3 and D4, resistors R3 and R4, transistor Q2, and capacitor C1; the positive input terminal of the operational amplifier U3 is connected to the input terminal of the minimum value holding circuit, its output terminal is connected to the cathode of the diode D3 and the anode of the diode D4, its reverse input terminal is connected to the cathode of the diode D4, the anode of the diode D3 is connected to the collector of the transistor Q2, one end of the capacitor C1, and the positive input terminal of the operational amplifier U4, the other end of the capacitor C1 is grounded, the emitter of the transistor Q2 is grounded, and the base is connected to the resistor R4, the output terminal of the operational amplifier U4 is connected to the reverse input terminal and the output terminal of the minimum value holding circuit, and the resistor R3 is connected between the reverse input terminals of the operational amplifiers U3 and U4.

[0036] The beneficial effects of the present invention are as follows: the present invention utilizes a peak holding circuit, adopts low-speed sampling at one or two times the ultrasonic frequency, and completes the restoration of the ultrasonic signal based on an ultrasonic signal mathematical model. This method can not only complete the extreme point sampling without distortion, but also reduce the overall design cost and power consumption of the ultrasonic wind speed and flow velocity measuring device.

[0037] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0039] Figure 1 It is the principle of low-speed sampling technology;

[0040] Figure 2 It is the logic of low-speed sampling technology;

[0041] Figure 3 It is the step of sampling and restoring the ultrasonic signal;

[0042] Figure 4 Comparison between the original signal and the restored signal sampled at 1 times the ultrasonic frequency;

[0043] Figure 5 Comparison between the original signal and the restored signal sampled at 2 times the ultrasonic frequency;

[0044] Figure 6 It is a maximum value holding circuit;

[0045] Figure 7 This is a circuit for maintaining a minimum value. DETAILED DESCRIPTION

[0046] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0047] The present invention proposes a method for low-speed sampling and signal restoration of ultrasonic signals. A peak holding circuit is used to maintain the extreme value of the signal for a period of time. A zero-crossing comparator is used to accurately detect the time of the ultrasonic signal. A hysteresis comparator is used as a trigger to sample the signal extreme points and zero-crossing moments. The signal is then restored based on the ultrasonic signal mathematical model. The zero-crossing comparator converts the ultrasonic signal into a square wave signal. Due to noise interference, the comparator may be in an uncertain state in areas outside the ultrasonic signal. The hysteresis comparator outputs a square wave signal in the ultrasonic signal area, and a low level signal outside the area. Figure 2 As shown, the rising edge or falling edge can be set as the trigger signal according to the requirements.

[0048] The specific steps of the method are as follows: the trigger signal of the hysteresis comparator triggers an AD sampling, and the sampling value is stored in the data buffer area. After completion, a reset signal is generated, and the peak holding circuit is reset to prepare for the next acquisition; the timer detects the falling edge of the zero-crossing comparator and records the time when the falling edge occurs. The trigger signal of the hysteresis comparator triggers the timer to store the most recent recorded time data in the data buffer area; based on the data stored in the current data buffer area and the ultrasonic signal mathematical model, the collected signal is restored through the interpolation algorithm, such as Figure 1 , 3 shown.

[0049] The low-speed sampling process using 1 times the ultrasonic frequency:

[0050] S101, the peak holding circuit maintains the maximum value of the ultrasonic signal for a certain period of time;

[0051] S102, the falling edge of the hysteresis comparator is used as a trigger signal to trigger an AD sampling. At this time, the peak holding circuit is in the maximum value holding state, and the sampling value is the peak value V of the previous wave of the ultrasonic signal. Pi And store the sampled value into the data buffer area. After completion, a reset signal is generated, and the peak holding circuit is reset to prepare for the collection of the next peak.

[0052] S103, the timer detects the falling edge of the zero-crossing comparator and records the time when the falling edge occurs T Fi The trigger signal of the hysteresis comparator stores the timer's most recent recorded time data into the data buffer.

[0053] S104, based on the data stored in the current data buffer and the ultrasonic signal mathematical model, complete (T F1 ,T Fn ) area.

[0054] The data stored in the data buffer is shown in the following table:

[0055] Table 1 1x sampling data buffer

[0056] Serial number Maximum Zero o'clock 1 <![CDATA[V P1 ]]> <![CDATA[T F1 ]]> 2 <![CDATA[V P2 ]]> <![CDATA[T F2 ]]> 3 <![CDATA[V P3 ]]> <![CDATA[T F3 ]]> 4 <![CDATA[V P4 ]]> <![CDATA[T F4 ]]> n <![CDATA[V Pn ]]> <![CDATA[T Fn ]]>

[0057] The mathematical model of ultrasonic signal is:

[0058]

[0059] The mathematical model of ultrasonic signal consists of two parts: A(t) is the amplitude information of the signal. is the phase information of the signal. Implement the interpolation algorithm separately to obtain:

[0060]

[0061] Among them, T Fi ≤t<T F(i+1) ,i∈[1,n-1]. At this time, the restoration effect of the ultrasonic signal is as follows Figure 4 shown.

[0062] The low-speed sampling process uses 2 times the ultrasonic frequency:

[0063] S111, the peak holding circuit keeps the maximum and minimum values ​​of the ultrasonic signal within a certain period of time;

[0064] S112, the rising edge and falling edge of the hysteresis comparator will trigger an AD sampling, and the absolute value of the sampling value |V Pi |Store in the data buffer area, generate a reset signal after completion, and reset the peak hold circuit to prepare for the next acquisition.

[0065] S113, the timer detects the falling edge of the zero-crossing comparator and records the time when the falling edge occurs T i The rising edge and falling edge of the hysteresis comparator will trigger the timer to store the most recently recorded time data into the data buffer.

[0066] S114, based on the data stored in the current data buffer and the ultrasonic signal mathematical model, complete (T1, T n ) area.

[0067] The data stored in the data buffer is shown in the following table:

[0068] Table 2 2x frequency sampling data buffer

[0069]

[0070]

[0071] Signal restoration:

[0072] Positive half cycle:

[0073] Negative half cycle:

[0074] Where T i ≤t<T (i+1) At this time, the restoration effect of the ultrasonic signal is as follows: Figure 5 shown.

[0075] Figure 6 The figure shows a maximum value holding circuit, including operational amplifiers U1 and U2, diodes D1 and D2, resistors R1 and R2, transistor Q1, and capacitor C2; the positive input terminal of the operational amplifier U1 is connected to the input terminal of the maximum value holding circuit, its output terminal is connected to the cathode of the diode D1 and the anode of the diode D2, its reverse input terminal is connected to the anode of the diode D1, the cathode of the diode D2 is connected to the collector of the transistor Q1, one end of the capacitor C2, and the positive input terminal of the operational amplifier U2, the other end of the capacitor C2 is grounded, the emitter of the transistor Q1 is grounded, and the base is connected to the resistor R2, the output terminal of the operational amplifier U2 is connected to the reverse input terminal and the output terminal of the maximum value holding circuit, and the resistor R1 is connected between the reverse input terminals of the operational amplifiers U1 and U2.

[0076] Figure 7The figure shows a minimum value holding circuit, including operational amplifiers U3 and U4, diodes D3 and D4, resistors R3 and R4, transistor Q2, and capacitor C1; the positive input terminal of the operational amplifier U3 is connected to the input terminal of the minimum value holding circuit, its output terminal is connected to the cathode of the diode D3 and the anode of the diode D4, its reverse input terminal is connected to the cathode of the diode D4, the anode of the diode D3 is connected to the collector of the transistor Q2, one end of the capacitor C1, and the positive input terminal of the operational amplifier U4, the other end of the capacitor C1 is grounded, the emitter of the transistor Q2 is grounded, and the base is connected to the resistor R4, the output terminal of the operational amplifier U4 is connected to the reverse input terminal and the output terminal of the minimum value holding circuit, and the resistor R3 is connected between the reverse input terminals of the operational amplifiers U3 and U4.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A method for low-speed sampling and signal recovery of ultrasonic signals, characterized in that: This method uses a sampling frequency of 1 or 2 times the ultrasonic frequency for low-speed sampling; When using a sampling frequency of 1 times the ultrasonic frequency for low-speed sampling, the signal sampling and recovery steps are as follows: S101, the peak holding circuit maintains the maximum value of the ultrasonic signal for a certain period of time; S102, the falling edge of the hysteresis comparator is used as a trigger signal to trigger an AD sampling. At this time, the peak hold circuit is in the maximum value holding state, and the sampling value is the peak value V of the previous wave of the ultrasonic signal. Pi , store the sampled value into the data buffer area, and generate a reset signal after completion, and the peak hold circuit is reset to prepare for the collection of the next peak; S103, the timer detects the falling edge of the zero-crossing comparator and records the time when the falling edge occurs T Fi , the trigger signal of the hysteresis comparator triggers the timer to store the most recently recorded time data into the data buffer; S104, based on the data stored in the current data buffer and the ultrasonic signal mathematical model, the interpolation algorithm is used to complete (T F1 ,T Fn ) ultrasonic signal restoration in the area; The mathematical model of ultrasonic signal is: The mathematical model of ultrasonic signal consists of two parts: A(t) is the amplitude information of the signal. is the phase information of the signal, and A(t) and Implement the interpolation algorithm separately to obtain: Among them, T Fi ≤t<T F(i+1) ,i∈[1,n*1]; When using a sampling frequency twice the ultrasonic frequency for low-speed sampling, the signal sampling and recovery steps are as follows: S111, the peak holding circuit keeps the maximum and minimum values ​​of the ultrasonic signal within a certain period of time; S112, the rising edge and falling edge of the hysteresis comparator will trigger an AD sampling, and the absolute value of the sampling value |V Pi |Store in the data buffer area, generate a reset signal after completion, and reset the peak hold circuit to prepare for the next acquisition; S113, the timer detects the falling edge of the zero-crossing comparator and records the time when the falling edge occurs T i , the rising edge and falling edge of the hysteresis comparator will trigger the timer to store the most recently recorded time data into the data buffer; S114, based on the data stored in the current data buffer and the ultrasonic signal mathematical model, the interpolation algorithm is used to complete (T1, T n ) ultrasonic signal restoration in the area; Signal restoration: Positive half cycle: Negative half cycle: Where T i ≤t<T (i+1) .

2. The method for low-speed sampling and signal restoration of ultrasonic signals according to claim 1, characterized in that: The peak holding circuit includes a maximum value holding circuit and a minimum value holding circuit.

3. The method for low-speed sampling and signal restoration of ultrasonic signals according to claim 2, characterized in that: The maximum value holding circuit includes operational amplifiers U1 and U2, diodes D1 and D2, resistors R1 and R2, transistor Q1, and capacitor C2; the positive input terminal of the operational amplifier U1 is connected to the input terminal of the maximum value holding circuit, its output terminal is connected to the cathode of the diode D1 and the anode of the diode D2, its reverse input terminal is connected to the anode of the diode D1, the cathode of the diode D2 is connected to the collector of the transistor Q1, one end of the capacitor C2, and the positive input terminal of the operational amplifier U2, the other end of the capacitor C2 is grounded, the emitter of the transistor Q1 is grounded, and the base is connected to the resistor R2, the output terminal of the operational amplifier U2 is connected to the reverse input terminal and the output terminal of the maximum value holding circuit, and the resistor R1 is connected between the reverse input terminals of the operational amplifiers U1 and U2.

4. The method for low-speed sampling and signal restoration of ultrasonic signals according to claim 2, characterized in that: The minimum value holding circuit includes operational amplifiers U3 and U4, diodes D3 and D4, resistors R3 and R4, transistor Q2, and capacitor C1; the positive input terminal of the operational amplifier U3 is connected to the input terminal of the minimum value holding circuit, its output terminal is connected to the cathode of the diode D3 and the anode of the diode D4, its reverse input terminal is connected to the cathode of the diode D4, the anode of the diode D3 is connected to the collector of the transistor Q2, one end of the capacitor C1, and the positive input terminal of the operational amplifier U4, the other end of the capacitor C1 is grounded, the emitter of the transistor Q2 is grounded, and the base is connected to the resistor R4, the output terminal of the operational amplifier U4 is connected to the reverse input terminal and the output terminal of the minimum value holding circuit, and the resistor R3 is connected between the reverse input terminals of the operational amplifiers U3 and U4.

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