A high-resolution variable-frequency damped oscillation signal generator

Abstract

The present application relates to a high-resolution variable-frequency damped oscillation signal generator, characterized in that it includes an FPGA, a 14-bit D / A converter, and a MOSFET switch. The FPGA receives damped oscillation waveform data transmitted from an external source, converts the data into an analog waveform through the 14-bit D / A converter at a conversion rate of 100MHz, and then processes the data through filtering and op amp processing, and outputs the waveform through the MOSFET switch. The present invention achieves a waveform rising edge of 3.49ns under the premise of using a low-bandwidth device (data conversion rate 100MHz). The use of a 14-bit D / A converter effectively ensures the accuracy of the output waveform at low voltage and low frequency, resulting in better consistency in test results. In addition, since the operating frequency of the device used in the present invention is relatively low, the device cost is also relatively low. Moreover, this operating frequency can use a double-sided board, unlike high-speed devices that require a multi-layer board, which greatly reduces the development difficulty and makes the processing technology simple and easy to implement.

Description

Technical Field

[0001] The present application belongs to the technical field of system internal conduction immunity testing in the field of automotive electronics, and in particular relates to a high-resolution variable-frequency damped oscillation signal generator. Background Art

[0002] The electric drive systems used in new energy vehicles typically include high-power, high-frequency switching devices and inductive loads. The extremely short current fluctuations and rapid movement of high-power semiconductor switches can generate strong radiation and electromagnetic interference. Therefore, compared to traditional on-board electronic equipment, EMC testing for new energy vehicle electronics requires additional testing for conducted and radiated RF interference.

[0003] As a typical waveform, variable frequency damped oscillation pulses are listed as test items by many car manufacturers. A variable frequency damped oscillation pulse generator includes a signal generator and an RF power amplifier. For variable frequency damped oscillation pulse signal generators, the Geely standard CEVT8888790454-1, Section 4.1.3, Radiated Disturbance, provides the waveform formula for variable frequency damped oscillation pulses:

[0004]

[0005] Where p1 is the peak current amplitude, p2 is the time constant, is the initial rising edge time, p3 is the initial frequency, p4 is the amplitude attenuation constant, p5 is the frequency attenuation constant, is the amplitude damping factor, is the frequency damping factor.

[0006] From the formula, we can see that the amplitude and frequency of the damped oscillation wave are constantly changing within the cycle. Take p1 = 0.4A, p2 = 6.28*10^8, p3 = 3MHz, p4 = 40, p5 = 60, the leading edge of the variable frequency damped oscillation pulse is:

[0007] Tr=ln(9) / p2=2.19 / (6.28*10^8)=3.49ns,

[0008] The initial frequency p3 of the damped oscillation wave is 3 MHz, but the leading edge of the waveform is only 3.49 ns. These two bandwidths differ significantly. Existing technology uses a high-speed CPLD coupled with a high-speed D / A converter. To meet the 3.49 ns requirement for the waveform's rising edge, the D / A converter's conversion rate must be at least 1 GHz, which in turn requires the CPLD's data port to operate at above 1 GHz. This high-bandwidth device requirement presents two challenges:

[0009] (1) Most D / A converters with a conversion rate above 1 GHz are 8-bit, with very few being 10-bit. The resolution of 10-bit data is only 1024. Low resolution will cause distortion of the low-frequency portion of the damped oscillation wave (the voltage amplitude of the low-frequency component is also low), which will bring uncertainty to the test results.

[0010] (2) High-speed devices are not easy to purchase, and the development tools are relatively complex; PCBs require multi-layer boards, and the wiring and processing techniques are very demanding, making development difficult and costly. Summary of the Invention

[0011] In order to solve the deficiencies in the prior art, the present application designs a variable frequency damped oscillation wave signal generator with high resolution, low cost and easy processing.

[0012] The technical solution adopted by the present invention to solve the above technical problems is:

[0013] A high-resolution variable-frequency damped oscillation signal generator includes an FPGA, a 14-bit D / A converter, and a MOSFET switch. The FPGA receives damped oscillation waveform data transmitted from an external source, converts the data into an analog waveform via the 14-bit D / A converter at a conversion rate of 100 MHz, and then processes the data through filtering and an operational amplifier before outputting the waveform via the MOSFET switch.

[0014] Preferably, in the high-resolution variable frequency damped oscillation signal generator of the present invention, the damped oscillation waveform data transmitted externally needs to be extracted before entering the FPGA. The data extraction method is as follows:

[0015] According to the formula:

[0016] Extract damped oscillation waveform data, where p1 is the peak current amplitude, p2 is the time constant, is the initial rising edge time, p3 is the initial frequency, p4 is the amplitude attenuation constant, p5 is the frequency attenuation constant, is the amplitude damping factor, is the frequency damping factor, and the formula for extracting waveform data is s1(t)=8192-s(t).

[0017] The extracted waveform data s1(t) is written into the FPGA, and the 14-bit D / A converter is driven by the FPGA. The damped oscillation waveform is filtered, added by an operational amplifier, and then inverted.

[0018] Preferably, in the high-resolution variable-frequency damped oscillation signal generator of the present invention, the damped oscillation waveform is inverted and output through the MOSFET switch, and the final waveform is output after passing through the RC filter, and the cutoff bandwidth of the RC filter is 200 MHz.

[0019] Preferably, the high-resolution variable-frequency damped oscillation signal generator of the present invention further includes a MOSFET drive circuit, which includes a transistor, a pulse transformer, and a rectifier diode. The FPGA sends a PWM signal to control the transistor, which drives the pulse transformer. The square wave pulse generated by the pulse transformer passes through the rectifier diode to generate a drive waveform between the G pole and the S pole of the MOSFET switch.

[0020] Preferably, in the high-resolution variable frequency damped oscillation signal generator of the present invention, the output of the variable frequency damped oscillation signal needs to be subject to timing control, and the timing control is as follows.

[0021] Set the time when FPGA starts driving the 14-bit D / A converter to 0, the start time when FPGA sends the PWM signal to T1, the start time of damped oscillation waveform output to T2, the end time of damped oscillation waveform output to T3, and the time when MOSFET is absolutely off to T4. T1 is determined by calculating the delay of each device in the MOSFET drive circuit.

[0022] The FPGA starts driving the 14-bit D / A converter at time 0. From time 0 to T2, the output waveform of the 14-bit D / A converter maintains the initial value.

[0023] Between time periods T1 and T2, the FPGA sends a PWM signal, the MOSFET switch starts to output a damped oscillation waveform at T2, and reaches a peak value at T2. At T3, the FPGA stops sending the PWM signal, and at T4, the FPGA drives the 14-bit D / A converter to adjust the output level to the initial state value.

[0024] The time period of the damped oscillation waveform output by the MOSFET switch is T1 to T3, where T1 to T2 are the leading edge of the waveform and T2 to T3 are the subsequent portion of the waveform.

[0025] Preferably, in the high-resolution variable-frequency damped oscillation signal generator of the present invention, the MOSFET switch is a SiC material MOSFET.

[0026] The present invention has the following beneficial effects: It achieves a waveform rising edge of 3.49ns while using a low-bandwidth device (data conversion rate 100MHz). A 14-bit D / A converter is used, while conventional devices use a maximum 10-bit high-speed D / A. Therefore, the waveform amplitude resolution of the present invention is 2^14 / 2^10=16 times that of conventional devices. This effectively ensures the accuracy of the output waveform at low voltage and low frequency, resulting in better test consistency.

[0027] Because the device used in this invention operates at a relatively low frequency, its cost is also relatively low. Furthermore, this operating frequency allows for the use of double-sided boards, unlike the multi-layer boards required for high-speed devices. This significantly reduces development effort and makes the manufacturing process simple and easy to implement. Overall, the cost is only 20% of that of high-speed device solutions, significantly reducing production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The technical solution of the present application is further described below with reference to the accompanying drawings and embodiments.

[0029] Figure 1 It is a structural principle diagram of an embodiment of the present application;

[0030] Figure 2 It is a timing control simulation waveform diagram corresponding to the structural principle diagram of the embodiment of the present application;

[0031] Figure 3 This is the waveform diagram of the final output of the embodiment of the present application. DETAILED DESCRIPTION

[0032] It should be noted that, unless there is any conflict, the embodiments and features in the embodiments of this application can be combined with each other.

[0033] The technical solution of the present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0034] Example

[0035] This embodiment provides a high-resolution variable frequency damped oscillation signal generator, the principle diagram of which is shown in FIG. Figure 1 As shown, it includes: an FPGA, a 14-bit D / A converter, and a MOSFET switch. The FPGA receives damped oscillation waveform data transmitted from the outside, converts the data into an analog waveform through the 14-bit D / A converter at a conversion rate of 100MHz, and then processes the data through filtering and operational amplifiers and outputs it through the MOSFET switch.

[0036] In the high-resolution variable-frequency damped oscillation signal generator of this embodiment, the damped oscillation waveform data transmitted externally needs to be extracted before entering the FPGA. The data extraction method is as follows:

[0037] Use Matlab software according to the formula in Geely standard CEVT8888790454-1

[0038] Extract damped oscillation waveform data, where p1 is the peak current amplitude, p2 is the time constant, is the initial rising edge time, p3 is the initial frequency, p4 is the amplitude attenuation constant, p5 is the frequency attenuation constant, is the amplitude damping factor, is the frequency damping factor.

[0039] Because the D / A converter used in this system is 14-bit, in order to ensure the integrity of the waveform, the 14-bit waveform data needs to reserve 50% for the positive and negative peaks respectively, that is, 2^13=8192. Therefore, the coefficient value when extracting data is: p1 takes a value of 8192, the time t step rate is 10ns, the number of step segments is 2000, and the formula for extracting waveform data is s1(t)=8192-s(t). This is to invert the output waveform of the 14-bit D / A converter.

[0040] The extracted data also needs to be processed in the following way: the first data in the waveform data array is replaced with the peak value. The purpose of this is to make the waveform output by the 14-bit D / A converter start at the peak value rather than the middle value, so that the waveform can be adjusted at the subsequent op amp.

[0041] The FPGA device selected in this embodiment contains a phase-locked loop, a bidirectional RAM and a PCI standard interface. Figure 1 The external communication interface in the FPGA is the PCI standard interface. The external controller writes the data array s1(t) into the bidirectional RAM of the FPGA through the PCI interface. The bidirectional RAM can write and read data at the same time to ensure the timeliness of data transmission. The FPGA drives the 14-bit D / A converter at a rate of 100MHz through the internal phase-locked loop and counter. The 14-bit D / A converter passes through the RC filter circuit composed of R1 and C1. Figure 1 The waveform obtained at the output of the 14-bit D / A converter ① is as follows Figure 2 Waveform①. Figure 1 The waveform of the 14-bit D / A converter output terminal ① and the waveform of the voltage -U0 at the R3 input terminal ② are added through the op amp. The waveform of the voltage -U0 at the R3 input terminal ② is as follows: Figure 2 The waveform ② in the figure is as follows:

[0042] U3 / R4=-(U1 / R2+U2 / R3),

[0043] Take R2=R3=R4, then U3=-U1-U2, where U1 is the waveform of the 14-bit D / A converter output terminal ①, U2 is the waveform of the voltage of R3 input terminal ②-U0, and U3 is the waveform of the op amp output terminal ③. The waveform corresponding to U3 is as follows Figure 2 The function of the op amp addition operation is to reduce the waveform at the output terminal ① of the 14-bit D / A converter from the reference voltage U0 to 0V and reverse the waveform.

[0044] Accelerating the leading edge processing is the key to achieving the rising edge of the damped oscillation waveform at 3.49ns in this embodiment. The specific operation is as follows: MOSFET is used as a switch. After the switch is turned on, R5 and C2 form an RC filter. Figure 1 The damped oscillation waveform of the final output is generated at the S pole ④ of the MOSFET switch, corresponding to Figure 2 Waveform ④. The rising edge of the waveform depends on the RC filter and the MOSFET switching speed. The RC filter parameters are selected with a cutoff bandwidth of around 200MHz. This can filter the rising edge of the waveform without affecting the subsequent waveforms, because the subsequent waveform frequency is less than 3MHz, which is much smaller than the cutoff frequency.

[0045] The turn-on speed of an ordinary MOSFET is difficult to reach 5ns. In this embodiment, a MOSFET switch made of SiC material with low input capacitance is selected, and the turn-on speed can reach 2ns.

[0046] The high-resolution variable frequency damped oscillation signal generator of this embodiment also includes a MOSFET drive circuit, which includes a transistor, a pulse transformer T, and a rectifier diode. The FPGA sends a PWM signal to control the transistor. The PWM signal corresponds to Figure 2 Waveform ⑤ in the figure is a transistor driving a pulse transformer. The pulse transformer uses a 15V power supply to generate a 15V square wave pulse signal at the secondary of the transformer. This level can effectively drive the MOSFET without damaging the MOSFET. The square wave pulse generated by the driving pulse transformer passes through the rectifier diode and generates a driving waveform between the G and S poles of the MOSFET switch, corresponding to Figure 2 Waveform ⑥ in the circuit; when the voltage amplitude between the G and S poles of the MOSFET switch is greater than 10V, the MOSFET switch can remain on. Therefore, the duty cycle of the PWM signal needs to be adjusted so that the minimum amplitude of the sawtooth wave generated at the rectifier diode ⑥ is not less than 10V.

[0047] In addition, the output of the variable frequency damped oscillation signal of this embodiment needs to be controlled by timing, and the timing control is as follows:

[0048] Set the time when FPGA starts driving the 14-bit D / A converter to 0, the start time when FPGA sends the PWM signal to T1, the start time of damped oscillation waveform output to T2, the end time of damped oscillation waveform output to T3, and the time when MOSFET is absolutely off to T4. Among them, T1 is determined by calculating the delay of each device in the MOSFET drive circuit.

[0049] FPGA starts driving the 14-bit D / A converter at time 0. According to the data processing method of s1(t), the output waveform U1 of the 14-bit D / A converter maintains the initial value at time 0 to T2, as shown in Figure 2 The waveform ① in the figure. The op amp output waveform U3 and the 14-bit D / A converter output waveform U1 are consistent in timing.

[0050] In order to make the damped oscillation waveform generated at the S pole ④ of the MOSFET switch reach its peak at time T2, the switch driving signal needs to be given before T2. If the signal is given too early, the output waveform will have a flat top at the peak; if the signal is given late, the output waveform peak will not reach the maximum value.

[0051] Therefore, before time T2, the FPGA sends a PWM signal, and the MOSFET switch starts to output a damped oscillation waveform at T2, as shown in FIG. Figure 2 Waveform ④ in Figure 4 reaches its peak at time T2. The FPGA stops issuing PWM signals at T3, and at T4, the FPGA drives the 14-bit D / A converter to adjust the output level to its initial value. Furthermore, the FPGA's internal phase-locked loop (PLL) can be used to adjust the delay to ensure the timing accuracy of the PWM drive signal.

[0052] Because the MOSFET is off during time T4, the waveform change at the op amp output terminal ③ does not affect the waveform at the S-pole ④ of the MOSFET. The MOSFET's output damped oscillation waveform occurs from time T1 to T3, with T1 to T2 representing the leading edge of the waveform and T2 to T3 representing the trailing edge.

[0053] The waveform at the S pole ④ of the MOSFET switch is output after passing through the resistor R6. The final output variable frequency damped oscillation waveform is as follows: Figure 3 shown.

[0054] Based on the above-mentioned ideal embodiments of this application, and in accordance with the above description, relevant personnel can make various changes and modifications without departing from the scope of the technical concept of this application. The technical scope of this application is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A high-resolution variable frequency damped oscillation signal generator, characterized in that: The system includes an FPGA, a 14-bit D / A converter, and a MOSFET switch. The FPGA receives externally transmitted damped oscillation waveform data, converts the damped oscillation waveform data into an analog waveform through the 14-bit D / A converter at a conversion rate of 100 MHz, and then processes the waveform through filtering and operational amplifiers before outputting it through the MOSFET switch. The output of the variable frequency damped oscillation signal requires timing control, which is as follows: Set the time when the FPGA starts driving the 14-bit D / A converter to 0, the start time when the FPGA sends the PWM signal to T1, the start time when the damped oscillation waveform output starts to T2, the end time when the damped oscillation waveform output ends to T3, and the time when the MOSFET is in the absolute off state to T4. T1 is determined by calculating the delay of each component in the MOSFET drive circuit; The FPGA starts driving the 14-bit D / A converter at time 0. From time 0 to T2, the output waveform of the 14-bit D / A converter maintains its initial value. Before time T2, the FPGA sends a PWM signal, and the MOSFET switch starts to output a damped oscillation waveform at T2, which reaches a peak at time T2. At T3, the FPGA stops sending the PWM signal, and at T4, the FPGA drives the 14-bit D / A converter to adjust the output level to the initial state value. The time period of the damped oscillation waveform output by the MOSFET switch is T1 to T3, where T1 to T2 are the leading edge of the waveform and T2 to T3 are the subsequent portion of the waveform.

2. The high-resolution variable frequency damped oscillation signal generator according to claim 1, characterized in that: Before the externally transmitted damped oscillation waveform data enters the FPGA, it needs to be extracted. The data extraction method is as follows: According to the formula: Extract damped oscillation waveform data, where p1 is the peak current amplitude, p2 is the time constant, is the initial rising edge time, p3 is the initial frequency, p4 is the amplitude attenuation constant, p5 is the frequency attenuation constant, is the amplitude damping factor, is the frequency damping factor, and the formula for extracting waveform data is s1(t)=8192-s(t); The extracted waveform data s1(t) is written into the FPGA, and the 14-bit D / A converter is driven by the FPGA. The damped oscillation waveform is filtered, added by an operational amplifier, and then inverted.

3. The high-resolution variable frequency damped oscillation signal generator according to claim 2, characterized in that: The damped oscillation waveform is inverted and output through the MOSFET switch, and then outputs the final waveform after passing through the RC filter. The cutoff bandwidth of the RC filter is 200 MHz.

4. The high-resolution variable frequency damped oscillation signal generator according to claim 1, characterized in that: The high-resolution variable-frequency damped oscillation signal generator also includes a MOSFET drive circuit, which includes a transistor, a pulse transformer, and a rectifier diode. The FPGA sends a PWM signal to control the transistor, which drives the pulse transformer. The square wave pulse generated by the pulse transformer passes through the rectifier diode to generate a drive waveform between the G and S poles of the MOSFET switch.

5. The high-resolution variable frequency damped oscillation signal generator according to any one of claims 1 to 4, characterized in that: The MOSFET switch is a SiC material MOSFET.

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