Test circuit

Abstract

A test circuit includes a plurality of normal flip-flops and a modified flip-flop. Each of the plurality of normal flip-flops includes a first input pin, a second input pin, and a first output pin, and is configured to selectively store the input value of the first input pin or the input value of the second input pin according to a scan enable signal. The modified flip-flop includes a third input pin, a fourth input pin, and a second output pin respectively coupled to a black box circuit, the plurality of normal flip-flops, and a plurality of combinational logic circuits, and is configured to selectively store the input value of the third input pin or the input value of the fourth input pin according to a scan test mode signal.

Description

Technical Field

[0001] The present disclosure relates to a test circuit for an integrated circuit, and more particularly to a test circuit for testing an integrated circuit including a memory. Background Art

[0002] With the development of semiconductor manufacturing technology, integrated circuits (ICs) include digital logic circuits and many embedded memories (e.g., TCAM / TCM, RAM, SRAM). Generally, an integrated circuit also includes a memory built-in self-test (MBIST) circuit for testing the embedded memory and a scan chain test circuit for testing the digital logic circuit.

[0003] However, a conventional scan chain test circuit includes a bypass circuit for bypassing the memory and a multiplexer for selectively outputting the output signal of the memory or the output signal of the bypass circuit. The bypass circuit often causes problems of increased circuit area and routing congestion in the integrated circuit, while the multiplexing circuit is prone to delay the output signal of the memory, thereby causing a timing violation problem. Summary of the Invention

[0004] One aspect of the present disclosure is a test circuit. The test circuit is used to test an integrated circuit, where the integrated circuit includes a black box circuit and a plurality of combinational logic circuits. The test circuit includes a plurality of normal flip-flops and an improved flip-flop. Each of the plurality of normal flip-flops includes a first input pin, a second input pin, and a first output pin, and is configured to selectively store the input value of the first input pin or the input value of the second input pin according to a scan enable signal. The improved flip-flop includes a third input pin, a fourth input pin, and a second output pin respectively coupled to the black box circuit, the plurality of normal flip-flops, and the plurality of combinational logic circuits, and is configured to selectively store the input value of the third input pin or the input value of the fourth input pin according to a scan test mode signal.

[0005] In summary, by coupling the improved flip-flop for receiving the scan test mode signal to the output terminal of the memory, the test circuit of the present disclosure can omit the known bypass circuit and the multiplexer coupled to the output terminal of the memory. In this way, the circuit area can be reduced, the problem of wire congestion is not likely to occur, and the output signal of the memory can have reduced latency (avoiding the problem of timing violation). In addition, since the test circuit can still complete the scan test with a reduced number of components, the test yield of the integrated circuit can be improved, and the cost of the scan test can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 FIG. is a schematic diagram of an integrated circuit tested via an automatic test equipment according to some embodiments of the present disclosure.

[0007] Figure 2 FIG. is a schematic diagram of an integrated circuit including a test circuit according to some embodiments of the present disclosure.

[0008] Figure 3 FIG. is a schematic diagram of a memory built-in self-test circuit according to some embodiments of the present disclosure.

[0009] Figure 4 FIG. is a schematic diagram of another integrated circuit including a test circuit according to some other embodiments of the present disclosure.

[0010] Figure 5 FIG. is a schematic diagram of another integrated circuit including a test circuit according to some other embodiments of the present disclosure. DETAILED DESCRIPTION

[0011] The following describes embodiments in conjunction with the accompanying drawings in detail. However, the specific embodiments described are only used to explain the present case and do not limit the present case. The description of the structure and operation is not used to limit the execution order. Any structure recombined by components that produces an apparatus with equivalent effects is within the scope covered by the present disclosure.

[0012] The terms used throughout the specification and the claims, unless otherwise specified, generally have their ordinary meanings as used in this field, in the context of the present disclosure, and in the specific context.

[0013] Regarding the use of "coupled" or "connected" herein, it can refer to two or more components making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other. It can also refer to two or more components operating or acting on each other.

[0014] In addition, the "combinational logic circuit" used in this article refers to a circuit composed of various logic gates, while the "normal flip-flop" and "improved flip-flop" used in this article refer to "sequential logic circuits" different from combinational logic circuits.

[0015] Please refer to Figure 1 , Figure 1 which describes that the integrated circuit 1 on a chip (not shown in the figure) can be tested by an automatic test equipment ATE located outside the chip. As Figure 1 shown, the integrated circuit 1 includes a memory 10, a plurality of combinational logic circuits (for simplicity of illustration, Figure 1 only one combinational logic circuit CL is shown), and a test circuit 50 according to some embodiments of the present disclosure, where the memory 10, the combinational logic circuit CL, and the test circuit 50 are coupled to each other. When testing the integrated circuit 1, the automatic test equipment ATE generates a known test vector TV, inputs the test vector TV into the integrated circuit 1 via the scan input terminal SI on the chip, and receives the scan output value SOV of the test circuit 50 through the scan output terminal SO on the chip to determine whether the combinational logic circuit CL is normal. In addition, the test circuit 50 can also test whether the memory 10 is normal.

[0016] Please refer to Figure 2 , in some embodiments, the test circuit 50 includes a plurality of normal flip-flops (for simplicity of illustration, Figure 2 only five normal flip-flops FF1 to FF5 are shown), at least one improved flip-flop MFF, a memory built-in self-test circuit 20, a multiplexer MUX, and a feedback circuit FB. The test circuit 50 can selectively operate in a scan test mode (to test the combinational logic circuit on the integrated circuit 1) or a memory built-in self-test mode (to test the memory 10 on the integrated circuit 1) according to a scan test mode signal Ms and a built-in self-test mode signal Mb.

[0017] As Figure 2As shown, each of the normal flip - flops FF1 to FF5 includes a first input pin D1, a second input pin SI1, a first enable pin SE1, and a first output pin Q1, and each is configured to selectively latch the input value of the first input pin D1 or the input value of the second input pin SI1 according to a scan enable signal Sen (connected to the first enable pin SE1). The improved flip - flop MFF includes a third input pin D2, a fourth input pin SI2, a second enable pin SE2, and a second output pin Q2, and is configured to selectively latch the input value of the third input pin D2 or the input value of the fourth input pin SI2 according to a scan test mode signal Ms (connected to the second enable pin SE2). When the test circuit 50 operates in the scan test mode, the scan test mode signal Ms is always maintained at a first level (e.g., high level). However, the scan enable signal Sen is set to the first level or the second level (e.g., low level) according to whether the current test circuit 50 is in a shift or a capture phase.

[0018] Structurally, the first input pin D1 of the normal flip - flop FF1 is coupled to the combinational logic circuit CL2, the second input pin SI1 of the normal flip - flop FF1 is coupled to the first output pin Q1 of the normal flip - flop FF3 (for simplicity of illustration, Figure 2 only the first output pin Q1 of the normal flip - flop FF3 is labeled in the figure), the first enable pin SE1 of the normal flip - flop FF1 is used to receive the scan enable signal Sen, and the first output pin Q1 of the normal flip - flop FF1 is coupled to the fourth input pin SI2 of the improved flip - flop MFF.

[0019] The first input pin D1 of the normal flip - flop FF2 is coupled to the combinational logic circuit CL3, the second input pin SI1 of the normal flip - flop FF2 is coupled to the second output pin Q2 of the improved flip - flop MFF, the first enable pin SE1 of the normal flip - flop FF2 is used to receive the scan enable signal Sen, and the first output pin Q1 of the normal flip - flop FF2 is coupled to other combinational logic circuits (not shown in the figure).

[0020] In other partial embodiments, the first output pin Q1 of the normal flip - flop FF2 can be simultaneously coupled to other combinational logic circuits (not shown in the figure) and a subsequent - stage normal flip - flop (not shown in the figure).

[0021] The third input pin D2 of the improved flip-flop MFF is coupled to the output terminal of the memory 10. The fourth input pin SI2 of the improved flip-flop MFF is coupled to the first output pin Q1 of the normal flip-flop FF1. The second enable pin SE2 of the improved flip-flop MFF is used to receive the scan test mode signal Ms, and the second output pin Q2 of the improved flip-flop MFF is coupled to the second input pin SI1 of the normal flip-flop FF2 and the combinational logic circuit CL1.

[0022] In Figure 2 the illustrated embodiment, the built-in self-test circuit 20 of the memory is coupled to the second output pin Q2 of the improved flip-flop MFF and the multiplexer MUX. Please refer to Figure 3 , the built-in self-test circuit 20 of the memory includes a comparison logic circuit 210, a processing circuit 220, and a test vector generator 230. Specifically, the comparison logic circuit 210 is coupled to the second output pin Q2 of the improved flip-flop MFF, the processing circuit 220 is coupled to the comparison logic circuit 210, and the test vector generator 230 is coupled to the processing circuit 220 and the multiplexer MUX.

[0023] For another example, Figure 2 as shown, the first input terminal of the multiplexer MUX is coupled to the built-in self-test circuit 20 of the memory, the second input terminal of the multiplexer MUX is coupled to the combinational logic circuit CL4, and the output terminal of the multiplexer MUX is coupled to the input terminal of the memory 10 and the feedback circuit FB.

[0024] The first input pin D1 of the normal flip-flop FF4 is coupled to the feedback circuit FB. The second input pin SI1 of the normal flip-flop FF4 is coupled to the first output pin Q1 of the normal flip-flop FF5 (for simplicity of illustration, Figure 2 only the first output pin Q1 of the normal flip-flop FF5 is labeled in

[0025] In another embodiment, Figure 2 the combinational logic circuit CL4 in

[0026] Since the memory bypass circuit has been removed, to test the combinational logic circuit CL4 and the multiplexer MUX, the output of the multiplexer MUX is fed back to the first input pin of any normal flip-flop (e.g., normal flip-flop FF4) by adding a feedback circuit FB. The feedback circuit FB is coupled to the output of the multiplexer MUX, the first input pin D1 of the normal flip-flop FF4, and a logic circuit (not shown in the figure), where the logic circuit can be a combinational logic circuit or a normal flip-flop. Specifically, the feedback circuit FB includes a first logic gate L1 and a second logic gate L2. The first input terminal of the first logic gate L1 is used to receive the scan test mode signal Ms, and the second input terminal of the first logic gate L1 is coupled between the output of the multiplexer MUX and the input of the memory 10. The first input terminal of the second logic gate L2 is coupled to the output of the first logic gate L1, the second input terminal of the second logic gate L2 is coupled to the logic circuit, and the output terminal of the second logic gate L2 is coupled to the first input pin D1 of the normal flip-flop FF4.

[0027] Regarding the "normal flip-flop" used in the embodiments, its first input pin (e.g., the first input pin D1) is usually coupled to the previous combinational logic circuit, its second input pin (e.g., the second input pin SI1) is usually coupled to the output pin of the previous flip-flop, its enable pin (e.g., the first enable pin SE1) is usually used to receive the scan enable signal Sen, and its output pin (e.g., the first output pin Q1) is usually coupled to the input pin of the subsequent combinational logic circuit or / and the subsequent flip-flop to form a scan chain.

[0028] Regarding the "improved flip-flop" used in the embodiments, its first input pin (e.g., the third input pin D2) is usually coupled to the output of the memory 10, its second input pin (e.g., the fourth input pin SI2) is usually coupled to the output pin of the previous flip-flop, its enable pin (e.g., the second enable pin SE2) is usually used to receive the scan test mode signal Ms, and its output pin (e.g., the second output pin Q2) is usually coupled to the input pin of the subsequent combinational logic circuit, the subsequent flip-flop, or / and the built-in self-test circuit 20 of the memory.

[0029] In the initial stage of testing, the test circuit 50 first operates in the scan test mode to test all the combinational logic circuits in the integrated circuit 1. When the test circuit 50 operates in the scan test mode, the scan test mode signal Ms has a first level (e.g., high level). Since there are also combinational logic circuits in the built-in self-test circuit 20 of the memory, the level of the built-in self-test mode signal Mb does not need to be particularly restricted.

[0030] When performing a scan test through scan chain technology, the detection process includes a shift and a capture phase. The test vector TV generated by the automatic test equipment ATE is input to a normal flip-flop (not shown in the figure) at the first stage in the test circuit 50 during the shift phase. In some embodiments, the test vector TV is composed of a preset number of "0 (logical zero)" and "1 (logical one)" arranged, and the automatic test equipment ATE determines the arrangement of "0" and "1" according to the values to be set for each flip-flop in the test circuit 50.

[0031] First, the test circuit 50 operates in the shift phase of the scan test mode. At this time, the scan test mode signal Ms has a first level, and the scan enable signal Sen has a first level. In this way, each of the normal flip-flops FF1 to FF5 on the integrated circuit 1 reads the input value of the second input pin SI1 (i.e., the output value of the previous flip-flop) according to the scan enable signal Sen at the first level. The improved flip-flop MFF reads the input value of the fourth output pin SI2 (i.e., the output value of the previous flip-flop) according to the scan test mode signal Ms at the first level. As another example Figure 2 shown, the normal flip-flops FF1 to FF5 and the improved flip-flop MFF all receive the frequency signal CLK. With the triggering of each cycle pulse in the frequency signal CLK, the normal flip-flops FF1 to FF5 and the improved flip-flop MFF will continuously read the output values of the previous flip-flops and at the same time output the originally stored values to the next flip-flop. At the end of the shift phase, the values in the test vector TV for each flip-flop in the test circuit 50 will be set on each flip-flop in the test circuit 50. The action of this phase is to initialize the values of all flip-flops.

[0032] For example, the values in the test vector TV generated by the automatic test equipment ATE for the improved flip-flop MFF and the normal flip-flop FF2 may be [0, 1]. Assume that during one cycle of the frequency signal CLK, the values stored in the normal flip-flop FF3 and the normal flip-flop FF1 are "0" and "1" respectively. In the next cycle, the normal flip-flop FF1 will store the value "0" previously stored in the normal flip-flop FF3, and the improved flip-flop MFF will store the value "1" previously stored in the normal flip-flop FF1. In addition, the normal flip-flop FF2 will store the value previously stored in the improved flip-flop MFF (for example: "0"). In the next next cycle, that is, at the end of the shift phase, the improved flip-flop MFF will store the value "0" previously stored in the normal flip-flop FF1, and the normal flip-flop FF2 will store the value "1" previously stored in the improved flip-flop MFF.

[0033] Next, the test circuit 50 operates in the capture phase of the scan test mode. At the beginning of the capture phase, each combinational logic circuit in the integrated circuit 1 performs operations based on the values set in the shift phase by the previous flip-flop and generates output values. When the test circuit 50 operates in the capture phase of the scan test mode, the scan test mode signal Ms still has the first level, and the scan enable signal Sen has the second level (for example: low level). Different from the shift phase, the normal flip-flops FF1 to FF5 on the integrated circuit 1 respectively read the input values of the first input pin D1 (i.e., the output values of the previous combinational logic circuit) according to the scan enable signal Sen of the second level. With the triggering of the pulses in the frequency signal CLK, the normal flip-flops FF1 to FF5 respectively capture and record the output values of the previous combinational logic circuit, and the improved flip-flop MFF still reads the output value of the normal flip-flop FF1 according to the scan test mode signal Ms of the first level. If the improved flip-flop MFF reads the output value of the memory 10 through the third input pin D2 at this time as in the prior art, unpredictable memory data will be obtained, resulting in a decrease in the fault coverage of the test. Therefore, the present invention changes the enable pin of the improved flip-flop MFF to be coupled to the scan test mode signal Ms to increase the fault coverage of the test.

[0034] Since the memory bypass circuit has been removed, the output values of the combinational logic circuits (e.g., Figure 2 the combinational logic circuit CL4 shown in or the combinational logic circuit in the memory built-in self-test circuit 20) coupled to the input end of the memory 10 cannot be transmitted to the subsequent flip-flop (i.e., the improved flip-flop MFF) through the bypass circuit, thereby causing the automatic test equipment ATE to be unable to test all the combinational logic circuits. It should be noted that the test circuit 50 can feedback the output value of the combinational logic circuit coupled to the input end of the memory 10 to the normal flip-flop FF4 through the feedback circuit FB, so that the automatic test equipment ATE can test the combinational logic circuit coupled to the input end of the memory 10 through the normal flip-flop FF4.

[0035] Specifically, when the test circuit 50 operates in the capture phase, the multiplexer MUX selectively outputs the output value of the combinational logic circuit in the memory built-in self-test circuit 20 or the output value of the combinational logic circuit CL4 according to the built-in self-test mode signal Mb of the first level or the second level. In some embodiments, the first logic gate L1 is an AND gate, and the second logic gate L2 is an OR gate. The first logic gate L1 outputs the output value of the multiplexer MUX according to the scan test mode signal Ms of the first level, and the second logic gate L2 performs operations based on the output value of the first logic gate L1 and the output value of the logic circuit to output a feedback value (not shown in the figure) to the first input pin D1 of the normal flip-flop FF4.

[0036] After the acquisition stage ends, the test circuit 50 will operate in the shift stage again. In this way, the output values of each combinational logic circuit in the integrated circuit 1 can be sequentially transmitted to each flip-flop in the test circuit 50, and finally output via the scan output terminal SO and received by the automatic test equipment ATE to determine whether each combinational logic circuit in the integrated circuit 1 can operate normally. In addition, the feedback value can be sequentially transmitted from the normal flip-flop FF4 to the subsequent stages of flip-flops, so that the automatic test equipment ATE can determine whether the combinational logic circuit coupled to the input end of the memory 10 is normal by receiving the feedback value.

[0037] In some embodiments, while the output values of each combinational logic circuit in the integrated circuit 1 are being output, another set of values in another test vector TV generated by the automatic test equipment ATE can also be sequentially stored into each flip-flop in the integrated circuit 1 from the scan input terminal SI for another test. In other words, before all the combinational logic circuits in the integrated circuit 1 are tested, the test circuit 50 can alternately operate in the shift stage and the acquisition stage.

[0038] After all the combinational logic circuits in the integrated circuit 1 are tested, the test circuit 50 then operates in a memory built-in self-test mode to test the memory 10. When the test circuit 50 operates in the memory built-in self-test mode, the scan test mode signal Ms has a second level, and the built-in self-test mode signal Mb has a first level. As Figure 3 shown, the processing circuit 220 controls the test vector generator 230 to generate a memory test pattern TP. The multiplexer MUX receives and outputs the memory test pattern TP according to the first-level built-in self-test mode signal Mb. The memory 10 receives the memory test pattern TP to output a memory output value MOV. The improved flip-flop MFF reads the input value of the third input pin D2 (i.e., the output value of the memory 10) according to the second-level scan test mode signal Ms to output the memory output value MOV to the memory built-in self-test circuit 20.

[0039] Also, as Figure 3As shown, the comparison logic circuit 210 receives the memory output value MOV, and compares the memory output value MOV with an expected value (not shown in the figure) to generate a comparison result. The processing circuit 220 selectively controls the test vector generator 230 to generate another memory test pattern TP or directly output an error signal Err according to the comparison result. Specifically, when the comparison result indicates that the memory output value MOV is equal to the expected value, the processing circuit 220 controls the test vector generator 230 to generate another memory test pattern TP to further test the memory 10. When the comparison result indicates that the memory output value MOV is different from the expected value, the processing circuit 220 directly outputs the error signal Err to an internal chip buffer (not shown in the figure), and the automatic test equipment ATE can read the content of the internal chip buffer via an I / O bus (not shown in the figure) to obtain the error test result and determine that there is an abnormal condition in the memory 10.

[0040] Please refer to Figure 4 , Figure 4 which shows a schematic diagram of another integrated circuit 2. The integrated circuit 2 has a similar structure to the integrated circuit 1 and can also be tested by an automatic test equipment ATE located outside the chip. Different from the integrated circuit 1, the test circuit 50 on the integrated circuit 2 does not include a feedback circuit FB but also includes a normal flip-flop FF6. To solve the problem that the combinational logic circuit coupled to the input end of the memory 10 cannot be tested, the normal flip-flop FF6 is coupled between the output end of the multiplexer MUX and the input end of the memory 10. Structurally, the first enable pin SE1 of the normal flip-flop FF6 is coupled to the scan enable signal Sen, the first input pin D1 of the normal flip-flop FF6 is coupled to the output end of the multiplexer MUX, and the second input pin SI1 of the normal flip-flop FF6 is coupled to the first output pin Q1 of another normal flip-flop (not shown in the figure). In this way, the output value of the combinational logic circuit coupled to the input end of the memory 10 can be temporarily stored in the normal flip-flop FF6 (through the first input pin D1) during the acquisition stage, and sequentially transmitted to the subsequent cascaded flip-flops during the shift stage, and finally transmitted to the scan output terminal SO so that the automatic test equipment ATE can receive the output value of the combinational logic circuit coupled to the input end of the memory 10. The automatic test equipment ATE can determine whether the combinational logic circuit CL4 and the multiplexer MUX are operating normally according to this output value. Figure 4 The remaining structures and operations of the illustrated embodiment are the same as or similar to those of the foregoing embodiment and will not be elaborated herein.

[0041] In another embodiment, the memory built-in self-test circuit 20 does not need to exist, and the multiplexer MUX coupled to the input end of the memory 10 does not need to exist or can be regarded as incorporated into the combinational logic circuit CL4. These two variations do not affect the present invention Figure 2The proposed improved flip-flop MFF, feedback circuit FB, and Figure 4 the operation of the normal flip-flop FF6 in

[0042] In another embodiment, the memory 10 in the foregoing embodiment may be any circuit that cannot apply a scan chain test (i.e., a black box circuit). For example, the memory 10 may be an analog circuit or a digital circuit that cannot be strung into a scan chain.

[0043] Please refer to Figure 5 , Figure 5 which depicts a schematic diagram of yet another integrated circuit 3. The integrated circuit 3 has a similar structure to the integrated circuit 1 and can also be tested by an automatic test equipment ATE located outside the chip. Different from the integrated circuit 1, the test circuit 50 on the integrated circuit 3, in addition to including an improved flip-flop MFF1 (equivalent to the Figure 2 improved flip-flop MFF shown), further includes another improved flip-flop MFF2 and a normal flip-flop FF7. Structurally, the third input pin D2 of the improved flip-flop MFF2 is coupled to the output terminal of the memory 10, the fourth input pin SI2 of the improved flip-flop MFF2 is coupled to the first output pin Q1 of the normal flip-flop FF7, and the second enable pin SE2 of the improved flip-flop MFF2 is used to receive the scan test mode signal Ms. In addition, the built-in self-test circuit 20 of the memory is changed to be coupled to the second output pin Q2 of the improved flip-flop MFF2 instead of being coupled to the second output pin Q2 of the improved flip-flop MFF1. Figure 5 The remaining structure and operation of the embodiment shown are the same as or similar to those of the foregoing embodiment and will not be elaborated herein.

[0044] In summary, by coupling the improved flip-flop MFF that receives the scan test mode signal Ms to the output terminal of the memory 10, the test circuit 50 of the present disclosure can omit the known bypass circuit and the multiplexing circuit coupled to the output terminal of the memory. In this way, the circuit area of the integrated circuits 1 to 3 can be reduced, the problem of wire congestion is not likely to occur, and the output signal of the memory 10 can be reduced in delay (avoiding the problem of timing violation). In addition, since the test circuit 50 can still complete the scan test with a reduced number of components, the test yield of the integrated circuit can be improved, and the cost of the scan test can be reduced.

[0045] Although the present disclosure has been disclosed as above in an implementation manner, it is not intended to limit the present disclosure. Those of ordinary skill in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be defined by the appended patent application scope.

[0046]

Symbol Explanation

[0047] 1, 2, 3: Integrated Circuit

[0048] 10: Memory

[0049] 20: Memory Built - in Self - Test Circuit

[0050] 50: Test Circuit

[0051] 210: Comparison Logic Circuit

[0052] 220: Processing Circuit

[0053] 230: Test Vector Generator

[0054] ATE: Automatic Test Equipment

[0055] CL, CL1, CL2, CL3, CL4, CL5: Combinational Logic Circuit

[0056] CLK: Frequency Signal

[0057] D1: First Input Pin

[0058] D2: Third Input Pin

[0059] Err: Error Signal

[0060] FF1, FF2, FF3, FF4, FF5, FF6, FF7: Normal Flip - Flop

[0061] FB: Feedback Circuit

[0062] L1: First Logic Gate

[0063] L2: Second Logic Gate

[0064] MFF, MFF1, MFF2: Modified Flip - Flop

[0065] Ms: Scan Test Mode Signal

[0066] Mb: Built - in Self - Test Mode Signal

[0067] MOV: Memory Output Value

[0068] MUX: Multiplexer

[0069] SE1: First Enable Pin

[0070] SE2: Second Enable Pin

[0071] Sen: Scan Enable Signal

[0072] SI: Scan Input Terminal

[0073] SI1: Second input pin

[0074] SI2: Fourth input pin

[0075] SO: Scan output terminal

[0076] SOV: Scan output value

[0077] TV: Test vector

[0078] TP: Memory test pattern

[0079] Q1: First output pin

[0080] Q2: Second output pin.

Claims

1. A test circuit for testing an integrated circuit, wherein the integrated circuit includes a black box circuit and a plurality of combinational logic circuits, and the test circuit includes: A plurality of normal flip - flops, each of the plurality of normal flip - flops including a first input pin, a second input pin, and a first output pin, and configured to selectively latch the input value of the first input pin or the input value of the second input pin according to a scan enable signal; And An improved flip - flop, including a third input pin coupled to the black box circuit, a fourth input pin coupled to one of the plurality of normal flip - flops, and a second output pin coupled to one of the plurality of combinational logic circuits, and configured to selectively latch the input value of the third input pin or the input value of the fourth input pin according to a scan test mode signal.

2. The test circuit according to claim 1, wherein the third input pin is coupled to the output terminal of the black box circuit, the fourth input pin is coupled to the first output pin of a first normal flip - flop among the plurality of normal flip - flops, and the second output pin is coupled to a first combinational logic circuit among the plurality of combinational logic circuits and the second input pin of a second normal flip - flop among the plurality of normal flip - flops.

3. The test circuit according to claim 2, wherein when the test circuit operates in a shift stage of a scan test mode, the scan enable signal has a first level, the scan test mode signal has a first level, the first normal flip - flop latches and outputs the output value of a third normal flip - flop among the plurality of normal flip - flops according to the scan enable signal of the first level, the improved flip - flop latches and outputs the output value of the first normal flip - flop according to the scan test mode signal of the first level, and the second normal flip - flop latches and outputs the output value of the improved flip - flop according to the scan enable signal of the first level.

4. The test circuit according to claim 3, wherein when the test circuit operates in a capture stage of the scan test mode, the scan enable signal has a second level different from the first level of the scan enable signal, the scan test mode signal has the first level, the first normal flip - flop latches the output value of a second combinational logic circuit among the plurality of combinational logic circuits according to the scan enable signal of the second level, the improved flip - flop latches the output value of the first normal flip - flop according to the scan test mode signal of the first level, and the second normal flip - flop latches the output value of a third combinational logic circuit among the plurality of combinational logic circuits according to the scan enable signal of the second level.

5. The test circuit according to claim 2, wherein a fourth combinational logic circuit among the plurality of combinational logic circuits is coupled between the input terminal of the black box circuit and a fourth normal flip - flop among the plurality of normal flip - flops; wherein the fourth combinational logic circuit includes a multiplexer.

6. The test circuit according to claim 5 further includes a feedback circuit, wherein the feedback circuit is coupled to the output terminal of the fourth combinational logic circuit, the first input pin of the fourth normal flip-flop, and a logic circuit; When the test circuit operates in a scan test mode, the feedback circuit calculates a feedback value according to the output value of the fourth combinational logic circuit and the output value of the logic circuit, and outputs the feedback value to the first input pin of the fourth normal flip-flop; When the test circuit does not operate in the scan test mode, the feedback circuit outputs the output value of the logic circuit to the first input pin of the fourth normal flip-flop.

7. The test circuit according to claim 6, wherein the feedback circuit includes a first logic gate and a second logic gate. The first input terminal of the first logic gate receives the scan test mode signal. The second input terminal of the first logic gate is coupled between the output terminal of the fourth combinational logic circuit and the input terminal of the black box circuit. The first input terminal of the second logic gate is coupled to the output terminal of the first logic gate. The second input terminal of the second logic gate is coupled to the logic circuit. The output terminal of the second logic gate is coupled to the first input pin of the fourth normal flip-flop.

8. The test circuit according to claim 5, wherein the first output pin of the fourth normal flip-flop among the plurality of normal flip-flops is coupled to the fourth combinational logic circuit, and a fifth normal flip-flop among the plurality of normal flip-flops is coupled between the output terminal of the fourth combinational logic circuit and the input terminal of the black box circuit; When the test circuit operates in an acquisition stage of a scan test mode, the scan enable signal has a second level, and the fifth normal flip-flop latches the output value of the fourth combinational logic circuit according to the scan enable signal of the second level; When the test circuit operates in a shift stage of a scan test mode, the scan enable signal has a first level different from the second level. A sixth normal flip-flop among the plurality of normal flip-flops is coupled to the second input pin of the fifth normal flip-flop, and the fifth normal flip-flop latches and outputs the output value of the sixth normal flip-flop according to the scan enable signal of the first level.

9. The test circuit according to claim 2, wherein the black box circuit is a memory; The test circuit further includes an on-chip memory self-test circuit for outputting a test pattern for testing the memory and is coupled to the improved flip-flop; The test circuit further includes another improved flip-flop, including a fifth input pin, a sixth input pin, and a third output pin, and is configured to selectively latch the input value of the fifth input pin or the input value of the sixth input pin according to the scan test mode signal.

10. The test circuit according to claim 9, wherein the fifth input pin is coupled between the output terminal of the memory and the third input pin of the improved flip-flop, the sixth input pin is coupled to the first output pin of a seventh normal flip-flop among the plurality of normal flip-flops, and the third output pin is coupled to the on-chip memory self-test circuit; The test circuit further includes a multiplexer, wherein a first input terminal of the multiplexer is coupled to the memory built-in self-test circuit to receive the test pattern, and a second input terminal of the multiplexer is coupled to a fourth combinational logic circuit among the plurality of combinational logic circuits.

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