A Bandgap Reference Circuit with a Wide Power Supply Voltage Range

Abstract

The present invention discloses a bandgap reference circuit with a wide power supply voltage range. In the present invention, it includes a bias circuit independent of the power supply voltage, a positive temperature coefficient voltage generation circuit, and a reference voltage generation circuit. The bias circuit independent of the power supply voltage eliminates the influence of the magnitude of the power supply voltage on the overall circuit and provides a stable bias current for the overall circuit. The positive temperature coefficient voltage generates a voltage signal proportional to temperature through two groups of NPN transistors. The reference voltage generation circuit receives the positive temperature coefficient voltage signal and generates a reference voltage. The reference voltage is not affected by temperature changes or power supply voltage, and a reference voltage with high precision and high stability is obtained.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and specifically relates to a bandgap reference circuit with a wide power supply voltage range. Background Art

[0002] With the rapid development of integrated circuits, more and more industries are moving towards the direction of informatization and intelligence. As an important part of integrated circuits, the bandgap reference circuit provides an important guarantee for the normal operation of other circuits, and its performance indicators affect the performance and quality of the entire chip. High-precision comparators, flash memories, analog / digital converters, and digital / analog converters all have high requirements for the bandgap reference circuit.

[0003] In the CMOS process, the base-emitter voltage of the NPN transistor has a negative temperature coefficient, while the base-emitter voltage difference has a positive temperature coefficient. By superimposing these two voltages with different temperature coefficients, a bandgap reference voltage can be generated. In the existing circuit, the bases and collectors of the Q0 transistor and the Q1 transistor are connected. The emitter-base area ratio of the Q1 transistor and the Q2 transistor is n:1. Therefore, the base-emitter voltage difference between the Q0 transistor and the Q1 transistor provides a voltage that is positively correlated with temperature, and this voltage is ΔV BE =V T ln n. On the other hand, the base-emitter voltage of the Q1 transistor has a negative temperature coefficient, and this voltage is denoted as V BE1 . The positive terminal of the operational amplifier is connected to the collector of the Q0 transistor, and the connection point is denoted as point A; the negative terminal of the operational amplifier is connected between the R2 resistor and the R0 resistor, and the connection point is denoted as point B. Therefore, points A and B have the same voltage. The current flowing through the R0 resistor is Therefore, the expression for the bandgap reference voltage VBG can be obtained as:

[0004] From the derivation of the above bandgap reference circuit, it can be seen that if a stable VBG bandgap reference voltage is to be obtained, the temperature coefficient needs to be carefully adjusted. However, since the Q1 transistor not only provides a negative temperature coefficient but also generates a voltage difference with a positive temperature coefficient together with the Q0 transistor, it is difficult to adjust the high-stability bandgap reference voltage. Summary of the Invention

[0005] The purpose of the present invention is to provide a bandgap reference circuit with a wide power supply voltage range in order to solve the above-mentioned problems.

[0006] The technical solution adopted by the present invention is as follows: The bandgap reference circuit with a wide power supply voltage range includes a positive temperature coefficient generation circuit, a bandgap reference voltage generation circuit, and a bias circuit independent of the power supply voltage. Its circuit structure is as Figure 1 shown;

[0007] The positive temperature coefficient generating circuit includes six PMOS transistors MP7 - MP12, two NMOS transistors MN4 and MN5, two NPN transistors Q1 and Q2, and a resistor R10; the MP7 and MP8 transistors are connected in series, and the drain of the MP8 transistor is connected to the collector of the Q1 transistor;

[0008] The bandgap reference voltage generating circuit includes three PMOS transistors MP13 - MP15, four resistors R0 - R3, and an NPN transistor Q0; the MP13 transistor and the MP14 transistor are connected in series, and the drain of the MP14 transistor is connected to the source of the MP15 transistor;

[0009] The power - supply - independent bias circuit includes seven PMOS transistors MP0 - MP6, four NMOS transistors MN0 - MN3, and six resistors R4 - R9; the MP0 transistor, the MP1 transistor, and the MP2 transistor generate a bias voltage.

[0010] In a preferred embodiment, the MP11 and MP12 transistors are connected in series, connected to the R10 resistor, and the other end of the R10 resistor is connected to the drain of the MN5 transistor, such that the MP11 transistor and the MP12 transistor provide a stable bias for the MN15 transistor, and the gate of the MN15 transistor is connected to the collector of the Q1 transistor.

[0011] In a preferred embodiment, the drain of the MN5 transistor is connected to the gate of the MP15 transistor to control the operation of the MP15 transistor; the R0 resistor is connected to the drain of the MP14 transistor, the R1 and R2 resistors are connected in series with the R0 resistor, the base and the collector of the Q0 transistor are connected and connected to the R2 resistor, the emitter of the Q0 transistor is connected to the R3 resistor, and the other end of the R3 resistor is connected to the ground; the base of the Q2 transistor is connected between the R0 resistor and the R1 resistor, and the base of the Q1 transistor is connected between the R1 resistor and the R2 resistor.

[0012] In a preferred embodiment, the MN0 transistor, the MN1 transistor, and the MN3 transistor form a feedback loop.

[0013] In a preferred embodiment, the MP9 and MP10 transistors are connected in series, and the drain of the MP10 transistor is connected to the collector of the Q2 transistor.

[0014] In a preferred embodiment, the drain of the MP15 transistor is connected to the ground, so that the MP13 transistor and the MP14 transistor provide a bias current for the MP15 transistor.

[0015] In summary, due to the adoption of the above technical solutions, the beneficial effects of the present invention are as follows:

[0016] 1. In the present invention, the positive temperature coefficient generating circuit and the bandgap reference generating circuit are separated from each other, so that the magnitudes of the currents flowing through the Q1 and Q2 transistors can be set independently of the magnitude of the current flowing through the Q0 transistor. Therefore, the base-emitter voltage differences of the Q1 and Q2 transistors and the base-emitter voltage of Q0 do not affect each other, making the adjustment of the bandgap reference voltage simple.

[0017] 2. In the present invention, the bias circuit in the form of feedback enables the bias current to remain stable when the power supply voltage fluctuates within a large range, and can maintain the stability of the bias within the power supply voltage range of 1.5V to 7V. The MN0 transistor and the MN1 transistor control the magnitude of the resistance connected to the circuit by detecting the magnitude of the power supply voltage, ensuring the stability of the magnitude of the bias current. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is the circuit diagram of the bandgap reference circuit with a wide power supply voltage range of the present invention;

[0019] Figure 2 is the curve diagram of the change of the bandgap reference voltage with temperature when the power supply voltage is 1.5V in the present invention;

[0020] Figure 3 is the curve diagram of the change of the bandgap reference voltage with temperature when the power supply voltage is 7V in the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0022] Refer to Figures 1-3 ,

[0023] Embodiment:

[0024] A bandgap reference circuit with a wide power supply voltage range proposed by the present invention includes a positive temperature coefficient voltage generating circuit, a bandgap reference voltage generating circuit, and a bias circuit independent of the power supply voltage.

[0025] The structure included in the positive temperature coefficient generating circuit is as follows: six PMOS transistors MP7 - MP12, two NMOS transistors MN4 and MN5, two NPN transistors Q1 and Q2, and a resistor R10. The MP7 transistor and the MP8 transistor are connected in series, and the drain of the MP8 transistor is connected to the collector of the Q1 transistor to provide a stable current bias for the Q1 transistor. The MP9 transistor and the MP10 transistor are connected in series, and the drain of the MP10 transistor is connected to the collector of the Q2 transistor to provide a stable current bias for the Q2 transistor. The emitters of the Q1 transistor and the Q2 transistor are connected together and are both connected to the drain of the MN4 transistor, and the gate of the MN4 transistor is connected to the collector of the Q2 transistor, so that the collector voltage of the Q2 transistor controls the operation of the MN4 transistor. The MP11 transistor and the MP12 transistor are connected in series and connected to the R10 resistor, and the other end of the R10 resistor is connected to the drain of the MN5 transistor, so that the MP11 transistor and the MP12 transistor provide a stable bias for the MN15 transistor, and the gate of the MN15 transistor is connected to the collector of the Q1 transistor, so that the collector voltage of the Q1 transistor controls the operation of the MN5 transistor. The bias currents provided by the MP7 transistor, the MP8 transistor and the MP9 transistor, the MP10 transistor are equal in magnitude, and the bias current provided by the MP11 transistor and the MP12 transistor is twice the current provided by the MP7 transistor and the MP8 transistor. Therefore, after the MN4 transistor receives the currents of the Q1 transistor and the Q2 transistor, the current magnitude is equal to the current flowing through the MN5 transistor. As the input pair transistors MN4 and MN5 of the operational amplifier, they provide the same voltage magnitude for the collectors of the Q1 transistor and the Q2 transistor. Therefore, the Q1 transistor and the Q2 transistor operate under the same conditions. Since the base - emitter area ratio of the Q1 transistor and the Q2 transistor is N:1, it can be concluded that the base voltage difference between the Q1 transistor and the Q2 transistor exhibits a characteristic that is positively correlated with temperature.

[0026] The magnitude of the current flowing through the collector of the transistor:

[0027] I C The relationship with the base - emitter voltage V BE is as follows:

[0028] I C = I S exp(V BE / V T );

[0029] The base - emitter voltage V BE can be calculated and expressed as follows:

[0030]

[0031] Therefore, the base-emitter voltage difference between the Q1 transistor and the Q2 transistor is:

[0032]

[0033] Taking the partial derivative with respect to temperature gives the following equation:

[0034]

[0035] It can be seen that the base-emitter voltage difference between the Q1 transistor and the Q2 transistor exhibits a positive temperature coefficient, and this temperature coefficient is independent of both the temperature itself and the magnitude of the collector current. The emitter voltages of the Q1 transistor and the Q2 transistor are the same, so the base voltage difference between the Q1 transistor and the Q2 transistor is a voltage with a positive temperature coefficient.

[0036] The structure included in the bandgap reference voltage generation circuit is as follows: three PMOS transistors MP13 - MP15, four resistors R0 - R3, and one NPN transistor Q0. The MP13 transistor and the MP14 transistor are connected in series. The drain of the MP14 transistor is connected to the source of the MP15 transistor. The drain of the MP15 transistor is connected to the ground terminal, enabling the MP13 transistor and the MP14 transistor to provide a bias current for the MP15 transistor. The drain of the MN5 transistor is connected to the gate of the MP15 transistor to control the operation of the MP15 transistor. The R0 resistor is connected to the drain of the MP14 transistor. The R1 and R2 resistors are connected in series with the R0 resistor. The base and the collector of the Q0 transistor are connected and connected to the R2 resistor. The emitter of the Q0 transistor is connected to the R3 resistor, and the other end of the R3 resistor is connected to the ground terminal. The base of the Q2 transistor is connected between the R0 resistor and the R1 resistor. The base of the Q1 transistor is connected between the R1 resistor and the R2 resistor.

[0037] In this way, a bandgap reference voltage is generated at the drain of MP14: V BG .

[0038] A voltage with a positive temperature coefficient is applied across the R1 resistor, and the resulting current is:

[0039]

[0040] Therefore, the bandgap reference voltage is:

[0041]

[0042] In the expression of the bandgap reference voltage V BG , V T ln n has a positive temperature coefficient, V BE0It has a negative temperature coefficient and can generate a reference voltage independent of temperature through resistance adjustment.

[0043] The bias circuit independent of the power supply voltage includes the following structures: seven PMOS transistors MP0 - MP6, four NMOS transistors MN0 - MN3, and six resistors R4 - R9. The gate and drain of the MP0 transistor are connected. The R7 resistor is connected to the drain of the MP0 transistor. The drain of the MN0 transistor is connected to the drain of the MP0 transistor. The R6 resistor is connected to the source of the MN0 transistor. Therefore, the MN0 transistor controls the resistance value connected to the drain of the MP0 transistor. The drain of the MP1 transistor is connected to the source of the MP2 transistor. The gate of the MP1 transistor is connected to the drain of the MP2 transistor. The gate of the MP2 transistor is connected to the gate of the MP0 transistor. The MP1 and MP2 transistors connected in this way provide bias for the subsequent parallel PMOS transistors. The R9 resistor is connected to the drain of the MP2 transistor. The drain of the MN1 transistor is connected to the drain of the MP2 transistor. The R8 resistor is connected to the source of the MN1. Therefore, the MN1 transistor controls the resistance value connected to the drain of the MP2 transistor. The drain of the MP3 transistor is connected to the source of the MP4 transistor. The gate of the MP3 transistor is connected to the gate of the MP1 transistor. The gate of the MP4 transistor is connected to the gate of the MP2 transistor. The R4 resistor is connected to the drain of the MP4 transistor. The gate and drain of the MN2 transistor are connected. The other end of the R4 resistor is connected to the drain of the MN2 transistor. The R5 resistor is connected to the source of the MN2 transistor. The MP3 transistor and the MP4 transistor provide bias for the R4 resistor and the MN2 transistor. The drain of the MP5 transistor is connected to the source of the MP6 transistor. The gate of the MP5 transistor is connected to the gate of the MP1 transistor. The gate of the MP6 transistor is connected to the gate of the MP2 transistor. The drain of the MN3 transistor is connected to the source of the MP6 transistor. The gate of the MN3 transistor is connected to the drain of the MP4 transistor. The source of the MN3 transistor is connected to the source of the MN2 transistor. The MP5 transistor and the MP6 transistor provide bias for the MN3 transistor.

[0044] The bias current provided by the MP3 and MP4 transistors is equal to the bias current provided by the MP5 and MP6 transistors. This bias current is denoted as I bias , and the voltage from the drain of the MP4 transistor to the source of the MN2 transistor has the following expression:

[0045]

[0046] where the size ratio of the MN2 transistor to the MN3 transistor is 4:1, that is Substituting this relationship into the above expression, we can get:

[0047]

[0048] It can be seen that the bias current is independent of the magnitude of the power supply voltage and is only related to the device size of the NMOS transistor and the magnitude of the resistance value. The bias current formed in this way gets rid of the influence of the power supply voltage on the bias current.

[0049] The gates of the MN0 transistor and the MN1 transistor are connected to the drain of the MP6 transistor, enabling the drain voltage of the MP6 transistor to control the operation of the MN0 transistor and the MN1 transistor. The formed feedback loop can achieve the stability of the bias current within a wide power supply voltage range. The resistance value of the R7 resistor is greater than that of the R6 resistor, and the resistance value of the R9 resistor is greater than that of the R8 resistor. When the power supply voltage is as low as 1.5V, the small-value resistors R6 and R8 serve as the main load resistors of the MP0 transistor and the MP2 transistor respectively. At this time, the current flowing through the R7 resistor and the R9 resistor is very small; when the power supply voltage is as high as 7V, the R6 resistor and the R7 resistor jointly serve as the load of the MP0 transistor, and the R8 resistor and the R9 resistor jointly serve as the load of the MP2 transistor. When the power supply voltage is between 1.5V and 7V, the drain voltage of the MP6 transistor dynamically adjusts the gate voltages of the MN0 transistor and the MN1 transistor to achieve the stability of the bias current within a wide power supply voltage range.

[0050] The simulation results are as Figure 2 and Figure 3 shown. It can be seen from the simulation results that whether the power supply voltage is as low as 1.5V or as high as 7V, the bandgap reference voltage exhibits good stability, and the deviation between its maximum and minimum values is about 1mV, with high accuracy.

[0051] The present invention adopts the method of isolating the positive temperature coefficient voltage generation circuit from the bandgap reference voltage generation circuit, and adopts the feedback loop method to stabilize the bias circuit, realizing the stability of the bandgap reference voltage within a wide power supply voltage range. Among them, the bandgap reference voltage has a deviation of only 1mV within the temperature range of -55°C to 170°C.

[0052] A bandgap reference circuit with a wide power supply voltage range proposed by the present invention is applicable to analog circuits and mixed-signal circuits, meeting the requirement of providing an accurate bandgap reference voltage within a wide power supply voltage range.

[0053] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A bandgap reference circuit with a wide power supply voltage range, characterized in that: The bandgap reference circuit with a wide power supply voltage range includes a positive temperature coefficient generating circuit, a bandgap reference voltage generating circuit, and a bias circuit independent of the power supply voltage. The bandgap reference circuit with a wide power supply voltage range contains a positive temperature coefficient generating circuit, which includes six PMOS transistors MP7 - MP12, two NMOS transistors MN4 and MN5, two NPN bipolar transistors Q1 and Q2, and a resistor R10. The sources of MP7, MP9, and MP11 transistors are connected to the power supply voltage VDD. The gates of MP7, MP9, and MP11 transistors are connected together. The gates of MP8, MP10, and MP12 transistors are connected together. The drain of MP7 transistor is connected to the source of MP8 transistor. The drain of MP9 transistor is connected to the source of MP10 transistor. The drain of MP11 transistor is connected to the source of MP12 transistor. The drain of MP8 transistor is connected to the collector of transistor Q1 and the gate of MN5 transistor. The drain of MP10 transistor is connected to the collector of transistor Q2 and the gate of MN4 transistor. The drain of MP12 transistor is connected to the upper end of resistor R10. The drain of MN4 transistor is connected to the emitters of transistor Q1 and transistor Q2. The drain of MN5 transistor is connected to the lower end of resistor R10. The sources of MN4 and MN5 transistors are connected to the power supply GND. The bandgap reference circuit with a wide power supply voltage range contains a bandgap reference voltage generating circuit, which includes three PMOS transistors MP13 - MP15, four resistors R0 - R3, and an NPN bipolar transistor Q0. The source of MP13 transistor is connected to the power supply VDD. The drain of MP13 transistor is connected to the source of MP14 transistor. The drain of MP14 transistor is connected to the source of MP15 transistor and the upper end of resistor R0. The drain voltage of MP14 transistor is the bandgap reference voltage. The gate of MP15 transistor is connected to the drain of MN5 transistor. The drain of MP15 transistor is connected to the power supply GND. The lower end of resistor R0 is connected to the upper end of resistor R1 and the base of transistor Q2. The lower end of resistor R1 is connected to the upper end of resistor R2 and the base of transistor Q1. The lower end of resistor R2 is connected to the base and the collector of transistor Q0. The emitter of transistor Q0 is connected to the upper end of resistor R3. The lower end of resistor R3 is connected to the power supply GND. The bandgap reference circuit with a wide power supply voltage range contains a bias circuit, which includes seven PMOS transistors MP0 - MP6, four NMOS transistors MN0 - MN3, and six resistors R4 - R9. The source of MP0 transistor is connected to the power supply VDD. The gate of MP0 transistor is connected to the drain of MP0 transistor, the drain of MN0 transistor, the upper end of resistor R7, and the gates of MP2, MP4, MP6, MP8, MP10, MP12, and MP14 transistors.The source of the MP1 transistor is connected to the power supply VDD. The gate of the MP1 transistor is connected to the drain of the MP2 transistor, the drain of the MN1 transistor, the upper end of the resistor R9, and the gates of the MP3 transistor, MP5 transistor, MP7 transistor, MP9 transistor, MP11 transistor, and MP13 transistor. The source of the MP2 transistor is connected to the drain of the MP1 transistor. The source of the MN0 transistor is connected to the upper end of the resistor R6. The lower end of the resistor R6 is connected to the power supply GND. The lower end of the resistor R7 is connected to the power supply GND. The source of the MN1 transistor is connected to the upper end of the resistor R8. The lower end of the resistor R8 is connected to the power supply GND. The lower end of the resistor R9 is connected to the power supply GND. The source of the MP3 transistor is connected to the power supply VDD. The drain of the MP3 transistor is connected to the source of the MP4 transistor. The drain of the MP4 transistor is connected to the upper end of the resistor R4 and the gate of the MN3 transistor. The lower end of the resistor R4 is connected to the gate and the drain of the MN2 transistor. The source of the MN2 transistor is connected to the upper end of the resistor R5 and the source of the MN3 transistor. The lower end of the resistor R5 is connected to the power supply GND. The source of the MP5 transistor is connected to the power supply VDD. The drain of the MP5 transistor is connected to the source of the MP6 transistor. The drain of the MP6 transistor is connected to the drain of the MN3 transistor, the gate of the MN0 transistor, and the gate of the MN1 transistor.

Images