Controller and its operation method

Abstract

This disclosure relates to a controller for controlling a memory device and a method of operating the controller. The controller may include: a host interface adapted to acquire a write command received from a host; and a processor adapted to control a write operation of the memory device in response to the acquired write command, wherein, when the workload of the processor's background operations is greater than the workload of the host write operation, the host interface is further adapted to: determine a delay time amount, and provide the completion response to the host after delaying the write command by the delay time amount.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0031640, filed on March 10, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of this disclosure relate to a controller and a method of operating the same. Background Technology

[0004] The computing environment paradigm has shifted to ubiquitous computing, enabling users to access computing systems anytime, anywhere. Consequently, the use of portable electronic devices such as mobile phones, digital cameras, and laptops has grown rapidly. These portable electronic devices typically utilize memory systems with one or more memory devices for storing data. The memory system can serve as either the main memory device or an auxiliary memory device in the portable electronic device.

[0005] Because memory systems have no moving parts, they offer advantages such as excellent stability and durability, high data access speeds, and low power consumption. Examples of memory systems with these advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces, and solid-state drives (SSDs). Summary of the Invention

[0006] Various embodiments of this disclosure relate to a controller that can improve the quality of service of a memory system in response to requests from a host, and a method of operating the controller.

[0007] According to embodiments of the present disclosure, a controller for controlling a memory device may include: a host interface adapted to acquire a write command received from a host; and a processor adapted to control a write operation of the memory device in response to the acquired write command, wherein, when the workload of the processor's background operations is greater than the workload of the host write operation, the host interface is further adapted to: determine a delay time amount, and provide the completion response to the host after delaying the completion response to the write command by the delay time amount.

[0008] The host interface may include: a host interface layer (HIL) core, which is adapted to determine the amount of delay and generate a completion response; and a command status scheduler, which is adapted to delay the completion response by the amount of delay time and then provide the delayed completion response to the host.

[0009] The HIL core can be further adapted to: receive write data associated with write commands from the host and output completion responses to the command status scheduler.

[0010] The host interface can determine the amount of latency based on the size of the free buffer and the estimated required buffer size.

[0011] The host interface can be further adapted to determine the estimated required buffer size based on the number of commands received from the host but not fetched, the ratio of write commands among the most recently fetched commands, and the data size of the fetched write commands.

[0012] The controller may further include a host write buffer, wherein the host interface is further adapted to determine the size of the free buffer based on the size of the host write buffer, the size of the allocated buffer, and the estimated required buffer size.

[0013] When the size of the free buffer is equal to or greater than the threshold buffer size, the host interface can set the latency to "0".

[0014] The controller may further include a host write buffer, wherein the size of the threshold buffer is determined based on the size of the host write buffer and the data size, the size of the host write buffer and the data size being simultaneously programmable into the memory device.

[0015] The processor can be further adapted to set a background flag by comparing the workload of a background operation with the workload of a host write operation, and the host interface can be further adapted to determine whether the workload of a background operation is greater than the workload of a host write operation by referring to the background flag.

[0016] The processor can set the background flag by comparing the number of valid pages that will be copied from the sacrifice block to the target block during a garbage collection operation with the number of pages that are stored in the memory device in response to write commands from the host during a garbage collection operation.

[0017] According to an embodiment of the present disclosure, a method for operating a controller to control a memory device includes: acquiring a write command received from a host; controlling a write operation of the memory device in response to the acquired write command; determining a delay time amount when the workload of a background operation of the controller is greater than the workload of a write operation of the host; and providing the completion response to the host after delaying the write command by the delay time amount.

[0018] The operation method may further include receiving write data associated with the write command from the host, wherein a completion response is provided after the write data is received.

[0019] The operation method may further include determining the amount of delay time based on the size of the free buffer and an estimated required buffer size.

[0020] The operating method may further include determining the estimated required buffer size based on the number of commands received from the host but not fetched, the ratio of write commands among the most recently fetched commands, and the data size of the fetched write commands.

[0021] The operating method may further include determining the free buffer size based on the size of the host write buffer included in the controller, the size of the allocated buffer, and an estimated required buffer size.

[0022] When the size of the free buffer is equal to or greater than the size of the threshold buffer, the delay time can be set to "0".

[0023] The threshold buffer size can be determined based on the size of the host write buffer included in the controller and the data size, which can be programmed into the memory device simultaneously.

[0024] The operation method may further include: setting a background flag by comparing the workload of the background operation with the workload of the host write operation; and determining whether the workload of the background operation is greater than the workload of the host write operation by referring to the background flag.

[0025] The background flag can be set by comparing the number of valid pages copied from the sacrifice block to the target block during a garbage collection operation with the number of pages stored in the memory device in response to write commands from the host during a garbage collection operation.

[0026] According to embodiments of this disclosure, a controller operation method may include: responding to a first write command, simultaneously buffering first write data into a buffer and controlling a memory device to perform a write operation and a background operation using second write data buffered in the buffer; and responding to a delay amount when the background operation workload is greater than the write operation workload and the available capacity of the buffer is less than a threshold capacity, while controlling the memory device to perform the background operation for at least the delay amount, wherein the available capacity is calculated using equation A:

[0027] [Equation A]

[0028] (Free buffer size)

[0029] =(host write buffer size)-(allocated buffer size)+(estimatedrequired buffer size)

[0030] Where "Free buffer size" is the available capacity, "host write buffer size" is the total capacity of data written within the buffer, "allocated buffer size" is the allocated buffer capacity, and "estimated-required buffer size" is the estimated required buffer capacity calculated using equation B:

[0031] [Equation B]

[0032] (Estimated required buffer size)

[0033] = (#of unfetched CMD) × (fetched write CMD ratio) × (datasize of fetched write CMD) In ​​this equation, "#of unfetched CMD" represents the number of commands waiting to be queued, "fetched write CMD ratio" is the ratio of queued write commands to a predetermined number of queued commands, and "data size of fetched write CMD" is the write data size of one of the queued write commands. The latency is calculated using equation C.

[0034] [Equation C]

[0035]

[0036] In this context, "delay" is the delay amount, "threshold buffer size" is the threshold capacity, and "C" is a predetermined constant. Attached Figure Description

[0037] Figure 1 This is a schematic diagram illustrating an example of a data processing system including a memory system according to an embodiment of the present disclosure.

[0038] Figure 2 This is a diagram illustrating the operation of the command queue interface according to an embodiment of the present disclosure.

[0039] Figure 3 References are shown according to embodiments of the present disclosure. Figure 1 Detailed diagram of the controller described.

[0040] Figure 4 This is a diagram illustrating the operation of a controller according to an embodiment of the present disclosure.

[0041] Figures 5 to 9 This is a detailed diagram illustrating the operation of the controller according to an embodiment of the present disclosure. Detailed Implementation

[0042] In the following description, various embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0043] However, this disclosure is not limited to the embodiments disclosed below, but may be implemented in various other forms. The disclosed embodiments are provided to complete this disclosure and to enable those skilled in the art to practice it.

[0044] Figure 1 This is a block diagram illustrating a data processing system 100 including a memory system 110 according to an embodiment of the present invention.

[0045] Reference Figure 1 The data processing system 100 may include a host 102 operatively connected to the memory system 110.

[0046] The host 102 may include any of a variety of portable electronic devices such as mobile phones, MP3 players and laptop computers, or any of a variety of non-portable electronic devices such as desktop computers, game consoles, televisions (TV) and projectors.

[0047] Host 102 may include at least one operating system (OS) that can manage and control all functions and operations of host 102 and provide communication between host 102 and users using data processing system 100 or memory system 110. The OS may support functions and operations corresponding to the user's purpose and intended use. For example, based on the mobility of host 102, the OS may be classified as a general-purpose OS and a mobile OS. Based on the user's environment, a general-purpose OS may be classified as a personal OS and an enterprise OS.

[0048] For example, personal operating systems configured to support functions for providing services to general users may include Windows and Chrome, while enterprise operating systems configured to achieve and support high performance may include Windows Server, Linux, and Unix. Furthermore, mobile operating systems configured to support functions for providing mobile services to users and system power-saving features may include Android, iOS, and Windows Mobile. Host 102 may include multiple operating systems and run an operating system to perform operations on storage system 110 corresponding to user requests.

[0049] The memory system 110 can operate in response to a request from the host 102 to store data of the host 102. Non-limiting examples of the memory system 110 may include solid-state drives (SSDs), multimedia cards (MMCs), secure digital cards (SDs), universal serial bus (USB) devices, universal flash memory (UFS) devices, compact flash memory (CF) cards, smart media cards (SMCs), PCMCIA cards, and memory sticks. MMCs may include embedded MMCs (eMMCs), reduced-size MMCs (RS-MMCs), micro MMCs, etc. SD cards may include mini SD cards and micro SD cards.

[0050] The memory system 110 can be implemented by various types of memory devices. Examples of these memory devices may include, but are not limited to, volatile memory devices such as dynamic random access memory (DRAM) and static RAM (SRAM), and non-volatile memory devices such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric RAM (FRAM), phase-change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM or ReRAM), and flash memory. Flash memory may have a three-dimensional (3D) stacked structure.

[0051] The memory system 110 can communicate with the host 102 using a command queuing interface that supports protocols such as NVMe. The command queuing interface can support the interface connection between the host 102 and the memory system 110 based on queue pairs, which include a submission queue for entering requested commands and a completion queue for recording the processing results of the commands. (See reference...) Figure 2 The interface connection between host 102 and memory system 110 is described in detail.

[0052] The memory system 110 may include a controller 130 and a memory device 150. The memory device 150 may store data from the host 102, and the controller 130 may control the storage of data into the memory device 150.

[0053] The controller 130 and memory device 150 can be integrated into a single semiconductor device. For example, the controller 130 and memory device 150 can be integrated into a single semiconductor device to form a solid-state drive (SSD). When the memory system 110 is used as an SSD, the operating speed of the host 102 connected to the memory system 110 can be improved. Alternatively, the controller 130 and memory device 150 can be integrated into a single semiconductor device to form a memory card. For example, the controller 130 and memory device 150 can form memory cards such as: PCMCIA cards, compact flash (CF) cards, smart media (SM) cards, memory sticks, MMCs including miniature multimedia cards (RS-MMC) and micro MMCs, SD cards including mini secure digital cards (mini SD), micro SD cards and SDHC cards, or universal flash memory (UFS) devices.

[0054] Non-limiting application examples of the memory system 110 may include computers, ultra-mobile PCs (UMPCs), workstations, netbooks, personal digital assistants (PDAs), portable computers, network tablets, tablet computers, cordless phones, mobile phones, smartphones, e-books, portable multimedia players (PMPs), portable game consoles, navigation systems, black boxes, digital cameras, digital multimedia broadcasting (DMB) players, 3D televisions, smart televisions, digital audio recorders, digital audio players, digital picture recorders, digital picture players, digital video recorders, digital video players, storage devices constituting data centers, devices capable of transmitting / receiving information in a wireless environment, various electronic devices constituting home networks, various electronic devices constituting computer networks, various electronic devices constituting telematics networks, radio frequency identification (RFID) devices, or various components constituting computing systems.

[0055] Memory device 150 may be a non-volatile memory device, and can retain stored data even without power supply. Memory device 150 can store data provided from host 102 via programming operations, and provide the stored data to host 102 via read operations. Memory device 150 may include multiple memory blocks, each of which may include multiple pages, and each of the multiple pages may include multiple memory cells connected to word lines. In an embodiment, memory device 150 may be flash memory. Flash memory may have a three-dimensional (3D) stacked structure.

[0056] Memory device 150 may include a flash memory device. The flash memory device can store data in an array of memory cells including memory cell transistors. The flash memory device may have a hierarchical structure of memory dies, planes, blocks, and pages. A memory die can receive one command at a time. The flash memory may include multiple memory dies. A memory die may include multiple planes, and the multiple planes can process commands received by the memory dies in parallel. Each plane may include multiple blocks. A block may correspond to the smallest unit of an erase operation. A block may include multiple pages. A page may correspond to the smallest unit of a write operation.

[0057] The controller 130 can control the memory device 150 in response to requests from the host 102. For example, the controller 130 can provide data read from the memory device 150 to the host 102 and store data provided from the host 102 into the memory device 150. For this operation, the controller 130 can control read operations, program operations, and erase operations of the memory device 150.

[0058] When host 102 provides a command to controller 130, controller 130 can retrieve the command and queue it into an internal command queue. After processing the retrieved command, controller 130 can provide a completion response to host 102 and remove the queued command from the command queue. For example, controller 130 can retrieve a write command received from host 102. Controller 130 can retrieve write data from host 102 in response to the retrieved write command and buffer the write data into a buffer included in memory system 110. After completing the buffered write data, controller 130 can provide a completion response to host 102.

[0059] Even after providing a completion response to a command to host 102, controller 130 can still perform operations on the command. For example, controller 130 can control memory device 150 to program buffered write data. Controller 130 can perform background operations for managing memory system 110 and foreground operations in response to commands from host 102.

[0060] When a completion response is received from controller 130, host 102 may provide controller 130 with a command for the next operation. For example, the number of commands that can be queued in the command queue may be limited by a predetermined queue depth. When a completion response is received from controller 130, host 102 may provide controller 130 with a next command, which may not be able to be provided to controller 130 because the command queue is full.

[0061] When host 102 provides a command to controller 130, controller 130 needs to provide a completion response to host 102 within a time limit to meet the quality of service required by host 102. When the controller 130 receives the next command from host 102 under heavy internal workload, command processing may be delayed, and it may be difficult to provide a completion response to host 102 within the scheduled processing time.

[0062] According to an embodiment, controller 130 can perform write throttling operations to delay the completion response to commands from host 102 based on internal workload. Specifically, when the workload of background operations is greater than that of foreground operations, controller 130 can delay the completion response. For example, when the time limit is 1100us and controller 130 completes the processing of a command within 600us, controller 130 can meet the quality of service (QoS) of the command, even if the completion response is delayed by 500us.

[0063] When the response is delayed, the host 102 may also delay providing the next command to the controller 130. The controller 130 can reduce its internal workload by performing foreground and background operations without receiving the next command during the delay period. When the controller 130 receives the next command after its internal workload has been reduced, delays in processing the corresponding command can be prevented. Therefore, the controller 130 can provide the host 102 with a complete response to the next command within the time limit and meet the quality of service required by the host 102.

[0064] Reference Figures 2 to 9 Detailed description of controller 130 according to embodiments of the present disclosure.

[0065] Figure 2 This is a diagram illustrating the operation of the command queue interface according to an embodiment of the present disclosure.

[0066] Host 102 can generate queue pairs including a submission queue 1022 and a completion queue 1024. When multiple cores exist in host 102, queue pairs of submission queue 1022 and completion queue 1024 can be generated to correspond to one of the multiple cores. According to an embodiment, the queue pairs can be stored in the memory of host 102.

[0067] Memory system 110 may include doorbell register 202 to perform command queue interface operations. Memory system 110 communicates with host 102 using a doorbell-based host interface that allows host 102 to place descriptors on the memory ring of the memory system and issue pointer update write requests to memory system 110. The pointer update write request is referred to as a "doorbell".

[0068] The doorbell register 202 may be a register used to control the queue pairs generated by the host 102. Figure 2 A doorbell register 202 is shown as an example, but when multiple cores exist in host 102, memory system 110 may include the same number of doorbell registers 202 as the number of cores. Doorbell registers 202 may store a submit queue tail pointer 2022 indicating the tail of submit queue 1022 and a completion queue head pointer 2024 indicating the head of completion queue 1024. Memory system 110 can access submit queue 1022 and completion queue 1024 by referring to doorbell registers 202 to perform command queue interface operations with host 102.

[0069] In operation S1, host 102 may queue a command in submission queue 1022 to request memory system 110 to execute the command. In operation S2, host 102 may update the tail pointer 2022 of the submission queue and provide the updated tail pointer 2022 to memory system 110. Memory system 110 may store the updated tail pointer 2022 in doorbell register 202.

[0070] In operation S3, memory system 110 can retrieve commands from submission queue 1022. In operation S4, memory system 110 can process the retrieved commands.

[0071] In operation S5, after the command has been processed, the memory system 110 can record the completion of command processing in the completion queue 1024. For example, the memory system 110 can write a completion queue entry to the completion queue 1024. In this case, the completion queue head pointer 2024 can be incremented. In operation S6, the memory system 110 can generate an interrupt signal.

[0072] In operation S7, host 102 can complete the command. In operation S8, host 102 can provide the updated completion queue head pointer 2024 to memory system 110. For example, memory system 110 can store the updated completion queue head pointer 2024 in doorbell register 202.

[0073] Figure 3 References are shown according to embodiments of the present disclosure. Figure 1 Detailed diagram of the controller 130 described.

[0074] The controller 130 may include a host interface (I / F) 132, a processor 134, an error correction code (ECC) component 138, a power management unit (PMU) 140, a memory interface (I / F) 142, and a memory 144, all of which are operatively connected via an internal bus.

[0075] The host I / F 132 can be configured to process commands and data from the host 102 and can communicate with the host 102 through one or more of the following communication standards or interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and Electronic Integrated Drive (IDE).

[0076] The host I / F 132 may include a host interface layer (HIL) core 222 and a command state scheduler (CSS) 224. The HIL core 222 can drive firmware known as the HIL and support references. Figure 2 The command queue interface is described. The command status scheduler 224, under the control of the HIL core 222, can selectively delay the completion response to a command and provide the completion response to the host 102.

[0077] Memory I / F 142 can serve as a memory / storage device interface that enables the controller 130 and memory device 150 to interface, allowing the controller 130 to control the memory device 150 in response to requests from the host 102. When the memory device 150 is flash memory, or specifically NAND flash memory, the memory I / F 142 can generate control signals for the memory device 150 and process data to be provided to the memory device 150 under the control of the processor 134. Memory I / F 142 can serve as an interface (e.g., a NAND flash interface) for processing commands and data between the controller 130 and the memory device 150. Specifically, the memory I / F 142 can support data transfer between the controller 130 and the memory device 150.

[0078] The memory I / F 142 can be driven by firmware known as the Flash Interface Layer (FIL) to exchange data with the memory device 150.

[0079] Processor 134 can control all operations of memory system 110. Processor 134 can drive firmware to control all operations of memory system 110. Firmware may be referred to as flash translation layer (FTL). Moreover, processor 134 may be implemented as a microprocessor or central processing unit (CPU).

[0080] Processor 134 can drive the FTL and perform foreground operations corresponding to requests received from host 102. For example, processor 134 can control write operations of memory device 150 in response to write requests from the host, and control read operations of memory device 150 in response to read requests from the host.

[0081] Furthermore, the controller 130 can perform background operations on the memory device 150 via a processor 134, which is implemented as a microprocessor or a CPU. For example, background operations performed on the memory device 150 may include garbage collection (GC) operations, wear leveling (WL) operations, map sweep operations, or bad block management operations.

[0082] Processor 134 may include one or more FTL cores 242. When processor 134 includes multiple FTL cores 242, each of the FTL cores 242 can drive the FTL and control the allocated memory dies. Host interface 132 can allocate commands received from host 102 and provide the allocated commands to each of the FTL cores 242, thereby improving parallel processing performance. For example, host interface 132 can allocate commands based on logical addresses (e.g., logical block addresses (LBAs)) included in the commands. Each of the FTL cores 242 can control parallel operation on the memory dies by interleaving the commands to be provided to the allocated memory dies.

[0083] Memory 144 can be used as working memory for memory system 110 and controller 130, and stores data used to drive memory system 110 and controller 130. Controller 130 can control memory device 150 to perform read operations, program operations, and erase operations in response to requests from host 102. Controller 130 can provide data read from memory device 150 to host 102, and can store data provided from host 102 into memory device 150. Memory 144 can store data required by controller 130 and memory device 150 to perform these operations.

[0084] Memory 144 can be implemented using volatile memory. For example, memory 144 can be implemented using static random access memory (SRAM) or dynamic random access memory (DRAM). Memory 144 can be located within or outside the controller 130. Figure 1 A memory 144 disposed within the controller 130 is shown. In an embodiment, the memory 144 may be implemented as an external volatile memory device, and the memory 144 may have a memory interface for inputting data to and outputting data from the controller 130.

[0085] The memory 144 may include a doorbell register 202, a command queue (CMDQ) 204, and a buffer 206.

[0086] You can refer to doorbell register 202 to perform command queue interface operations with host 102, such as referring to... Figure 2 As described. For example, host interface 132 can detect commands received from host 102 and retrieve the received commands by referring to doorbell register 202.

[0087] Command queue 204 can queue commands acquired by host interface 132. Processor 134 can acquire and process queued commands from command queue 204. When processor 134 acquires a queued command, host interface 132 can provide a completion response to host 102.

[0088] Buffer 206 can store data to be programmed into memory device 150, or data read from memory device 150. According to an embodiment, buffer 206 may include a host write buffer for storing write data received from host 102, a host read buffer for storing read data requested from host 102, and a background buffer for storing data for background operations.

[0089] ECC component 138 can detect and correct errors contained in data read from memory device 150. ECC component 138 can perform an error correction decoding process on the data read from memory device 150 using the ECC value used during the ECC encoding process. Based on the result of the error correction decoding process, ECC component 138 can output a signal, such as an error correction success / failure signal. When the number of error bits exceeds a threshold of correctable error bits, ECC component 138 may choose not to correct the error bits and instead output an error correction failure signal.

[0090] The power management unit 140 can provide and manage power to the controller 130. The power management unit 140 may include a capacitor to provide emergency power, allowing the memory system 110 to terminate normally in the event of a sudden power outage. For example, in the event of a sudden power outage, the controller 130 can use emergency power to store the write data of the buffer 206 in the memory device 150 and terminate the memory system 110.

[0091] Figure 4 This is a diagram illustrating the operation of the controller 130 according to an embodiment of the present disclosure.

[0092] In operation S402, host 102 can provide write commands to host interface 132. Host interface 132 can receive commands received from host 102.

[0093] In operation S404, host interface 132 can receive write data corresponding to the write command from host 102 and buffer the write data in memory 144.

[0094] In operation S406, host interface 132 can provide write commands to processor 134. For example, host interface 132 can queue acquired write commands into command queue 204, so that processor 134 can obtain the acquired write commands.

[0095] In operation S408, the HIL core 222 of the host interface 132 can determine whether to delay the completion response to a write command based on the workload of the foreground and background operations of the processor 134. When the HIL core 222 determines to delay the completion response, it can determine the amount of delay based on the size of the free buffer in the buffer 206 and the buffer size required to process the write command. (See also...) Figure 5 Describe in detail the methods used by HIL core 222 to determine whether to delay the completion of a response and the method for determining the amount of delay time.

[0096] When HIL core 222 determines that the completion response is delayed, in operation S410, HIL core 222 can provide the completion response to command status scheduler 224 and control command status scheduler 224 to delay the completion response by the determined delay time.

[0097] When the determined delay time has elapsed, in operation S412, the command status scheduler 224 can provide a completion response to the host 102.

[0098] Figures 5 to 9 This is a detailed diagram illustrating the operation of the controller 130 according to an embodiment of the present disclosure.

[0099] Figure 5 This refers to the operations included in operation S408, which determines whether to delay the completion of the response and the amount of delay. Operation S408 may include operations S502, S504, S506, S508, S510, and S512.

[0100] In operation S502, HIL core 222 can determine whether the workload of background operations is greater than the workload of host write operations.

[0101] For example, FTL core 242 can determine whether the workload of background operations is greater than the workload of host write operations, and set the background flag based on this determination. Referring to the background flag, HIL core 222 can determine whether the workload of background operations is greater than the workload of host write operations. (See reference...) Figure 3As described, processor 134 may include multiple FTL cores 242. The multiple FTL cores 242 can independently execute foreground and background operations associated with different logical addresses. Each of the multiple FTL cores 242 can set a background flag. HIL core 222 can determine whether to delay the completion response to a corresponding write command by referring to the background flag of the FTL core 242 corresponding to the logical address of the write command. (See reference...) Figure 6 This section provides a detailed example of how to set the background flag on the FTL core 242.

[0102] When the workload of the background operation is equal to or less than the workload of the host write operation (i.e., "No" in operation S502), in operation S504, HIL core 222 can determine the latency amount as "0".

[0103] When the workload of background operations exceeds the workload of host write operations (i.e., "Yes" in operation S502), in operation S506, HIL core 222 can determine an estimated required buffer size. The estimated required buffer size can refer to the estimated buffer size needed to process a write command provided from host 102 to controller 130 but not yet received. As the estimated required buffer size increases, HIL core 222 can determine that the latency of the currently processed write command is longer. (See also...) Figure 7 Provide a detailed example of a method for determining the estimated required buffer size.

[0104] In operation S508, HIL core 222 can determine the size of the free buffer capable of buffering write data received from host 102. (See reference...) Figure 8 Provide a detailed example of a method for determining the size of the free buffer.

[0105] In operation S510, HIL core 222 can determine whether the size of the free buffer is less than the threshold buffer size.

[0106] The threshold buffer size can be predetermined. As an example, the threshold buffer size can be determined to be 65% to 75% of the host write buffer size. As another example, the threshold buffer size can be determined based on the host write buffer size, the stripe size, and the number of FTL cores 242. The stripe size, which can be controlled to allow the FTL cores 242 to program data simultaneously, can be determined based on the number of planes on which parallel operations are performed and the number of bits that can be stored in the memory cells. Equation 1 below is an example of an equation used to determine the threshold buffer size.

[0107] [Equation 1]

[0108] (Threshold buffer size) = (host write buffer size) - (stripe size) × (#ofFTL cores) × 3. In Equation 1, "threshold buffer size" can refer to the threshold buffer size, "host write buffer size" can refer to the host write buffer size, "stripe size" can refer to the stripe size, and "#ofFTL cores" can refer to the number of FTL cores 242.

[0109] When the size of the free buffer is equal to or greater than the threshold buffer size (i.e., "No" in operation S510), in operation S504, HIL core 222 can determine that the size of the free buffer is sufficient and set the delay time amount to "0".

[0110] When the free buffer size is less than the threshold buffer size (i.e., "Yes" in operation S510), in operation S512, the HIL core 222 can calculate the delay amount and set the delay amount for the command status scheduler 224. The delay amount can be determined based on an estimated required buffer size and the free buffer size. (Refer to...) Figure 9 Provide a detailed example of a method for calculating the delay time.

[0111] Figure 6 This illustrates an example of setting a background flag using the FTL core 242 according to an embodiment of this disclosure.

[0112] FTL core 242 can perform garbage collection by selecting any one of the storage blocks containing data as a sacrifice block, loading the valid data of the selected sacrifice block into buffer 206, and storing the loaded valid data in the target block.

[0113] After performing garbage collection on the previous sacrifice block, in operation S602, FTL core 242 can select the next sacrifice block.

[0114] In operation S604, FTL core 242 can determine the workload of background operations and host write operations during the garbage collection operation for the previous sacrificed block. For example, the workload of the garbage collection operation can be determined as the workload of background operations. The workload of the garbage collection operation can be determined as the number of valid pages copied from the previous sacrificed block to the target block. The workload of the host write operation can be determined as the number of pages stored in memory device 150 in response to host write commands during the garbage collection operation for the previous sacrificed block.

[0115] In S606 operation, FTL core 242 can determine whether the workload of background operations is greater than the workload of host write operations.

[0116] When the workload of background operations is greater than the workload of host write operations (i.e., "Yes" in operation S606), the FTL core 242 can enable the background flag in operation S608.

[0117] When the workload of the background operation is equal to or less than the workload of the host write operation (i.e., "No" in operation S606), the FTL core 242 can disable the background flag in operation S610.

[0118] Figure 6 The illustration shows a method for setting a background flag according to an embodiment of the present disclosure, using the example of updating the background flag whenever the FTL core 242 completes garbage collection for the previous sacrifice block and selects the next sacrifice block. However, the time period for updating the background flag is not limited to the one described above. Figure 6 Example of the description.

[0119] Figure 7 This is a detailed diagram illustrating an example of a method for determining the estimated required buffer size using HIL core 222 according to an embodiment of this disclosure.

[0120] Operation S506 may include operations S702, S704, S706 and S708.

[0121] In operation S702, the HIL core 222 can determine the number of unfetched commands. For example, the HIL core 222 can determine the number of unfetched commands based on the positions of the tail and head of the submission queue 1022. The buffer required for unfetched commands can be determined based on whether the command is a write command and the size of the data associated with the command. However, before a command is fetched, the HIL core 222 has difficulty knowing accurately whether the corresponding command is a write command and the size of the data associated with the command. Therefore, the HIL core 222 can estimate the number of unfetched write commands and the size of the write data associated with the unfetched write commands based on the ratio of the data size of previously fetched write commands to the data size of already fetched write commands.

[0122] In operation S704, the HIL core 222 can determine the ratio of previously acquired write commands. The ratio of previously acquired write commands can refer to the ratio of write commands among a predetermined number of previously acquired commands. For example, the HIL core 222 can count the total number of acquired commands and the number of write commands within that total number whenever a command is acquired, and determine the ratio of acquired write commands based on the total command count and the write command count whenever a predetermined number of commands are acquired.

[0123] In operation S706, HIL core 222 can determine the data size of the most recently acquired write command. According to the implementation, the data size can be expressed as the number of 4KB data chunks.

[0124] In operation with S708, HIL core 222 can determine the estimated required buffer size based on the number of unfetched commands, the ratio of fetched write commands, and the data size of the most recently fetched command. Equation 2 below is an example of an equation used to determine the estimated required buffer size.

[0125] [Equation 2]

[0126]

[0127] In Equation 2, "estimated-required buffer size" can refer to the estimated required buffer size, "#ofunfetched CMD" can refer to the number of unfetched commands, "fetched write CMD ratio" can refer to the ratio of fetched write commands, and "data size of fetched write CMD" can refer to the data size of fetched write commands.

[0128] Figure 8 This is a detailed diagram illustrating an example of a method for determining the size of a free buffer using HIL core 222 according to an embodiment of this disclosure.

[0129] In S802 operation, HIL core 222 can determine the size of the free buffer based on the host write buffer size, the allocated buffer size, and the estimated required buffer size.

[0130] The HIL core 222 can allocate host write buffers to buffer data associated with fetched write commands. Additionally, the HIL core 222 can pre-allocate host write buffers for write commands that have not yet been fetched, with the pre-allocated amount corresponding to the estimated required buffer size. Therefore, the HIL core 222 can determine the free buffer size based on the host write buffer size, the allocated buffer size, and the estimated required buffer size. Equation 3 below is an example of an equation used to determine the free buffer size.

[0131] [Equation 3]

[0132] (Free buffer size)

[0133] =(host write buffer size)-(allocated buffer size)+(estimatedrequired buffer size)

[0134] In Equation 3, "free buffer size" can refer to the size of the free buffer, "host write buffer size" can refer to the size of the host write buffer, "allocated buffer size" can refer to the size of the allocated buffer, and "estimated-required buffer size" can refer to the estimated required buffer size.

[0135] Figure 9 This is a detailed diagram illustrating an example of a method for determining the amount of delay time according to an embodiment of the present disclosure, using HIL core 222.

[0136] In operation S902, HIL core 222 can determine the amount of delay time based on the size of the free buffer and the estimated required buffer size. Equation 4 below is an example of an equation used to determine the amount of delay time.

[0137] [Equation 4]

[0138]

[0139] In Equation 4, "delay" can refer to the amount of delay time, "threshold buffer size" can refer to the threshold buffer size, "free buffer size" can refer to the free buffer size, "estimated-required buffer size" can refer to the estimated required buffer size, and "C" can refer to a predetermined constant.

[0140] Referring to Equation 4, the delay time can be adjusted by multiplying by a predetermined constant, and the constant can be determined based on the time that the memory system 110 may take to process the write command when the host 102 determines that the queue depth of the command queue 204 is "1" and provides a write command.

[0141] According to this embodiment, when a delay is anticipated in processing a command to be received from host 102, controller 130 may delay the completion response to the processed write command. Examples of situations where a delay in processing the received command is anticipated may include situations where processing resources for processing host write commands become insufficient due to background operations, where the size of the free buffer in buffer 206 for host write data becomes insufficient, or where a large amount of buffer space is anticipated due to the pending write command. When delaying the completion response to the processed write command, controller 130 may determine the amount of delay based on an estimated required buffer size and a free buffer size. Controller 130 may acquire processing resources for processing the host write command by performing internal operations while delaying the completion response to the currently processed write command, and receive the write command from host 102 after acquiring the free buffer. Therefore, controller 130 can prevent delays in processing the received command and provide the required quality of service to host 102.

[0142] According to embodiments of this disclosure, the controller and its operating method can improve the quality of service of the memory system in response to requests from the host.

[0143] Although the controller and its operation methods have been described with reference to specific embodiments, these are merely examples, and this disclosure is not limited thereto, but should be interpreted as having the broadest scope of the basic ideas disclosed herein. Those skilled in the art can perform unspecified embodiments by combining and substituting the disclosed embodiments, but these will not depart from the scope of this disclosure. Furthermore, those skilled in the art can readily change or modify the disclosed embodiments based on this specification, and obviously, such changes or modifications also fall within the scope of this disclosure.

[0144] Although the teachings have been shown and described with reference to specific embodiments, it will be apparent to those skilled in the art, based on this disclosure, that various changes and modifications may be made without departing from the spirit and scope of the disclosure as defined by the appended claims. Furthermore, embodiments may be combined to form other embodiments.

Claims

1. A controller that controls a memory device, the controller comprising: Host interface, which receives write commands from the host; as well as A processor that controls write operations on the memory device in response to a received write command. Wherein, when the workload of the processor's background operations is greater than the workload of the host write operations, the host interface further: Determine the delay time, and The completion response is provided to the host after a delay of the specified delay time. The host interface determines the latency amount based on the free buffer size and the estimated required buffer size, and The host interface further determines the estimated required buffer size based on the number of commands received from the host but not acquired, the ratio of write commands among the most recently acquired commands, and the data size of the acquired write commands.

2. The controller according to claim 1, wherein, The host interface includes: The host interface layer core, or HIL core, determines the latency amount and generates the completion response; and A command status scheduler that delays the completion response by the specified delay amount before providing the delayed completion response to the host.

3. The controller according to claim 2, wherein, The HIL core further: Receive write data associated with the write command from the host, and The completion response is output to the command status scheduler.

4. The controller of claim 1, further comprising a host write buffer, in, The host interface further determines the free buffer size based on the size of the host write buffer, the allocated buffer size, and the estimated required buffer size.

5. The controller according to claim 1, wherein, When the size of the free buffer is equal to or greater than the size of the threshold buffer, the host interface sets the latency to "0".

6. The controller of claim 5, further comprising a host write buffer, in, The threshold buffer size is determined based on the size of the host write buffer that can be simultaneously programmed into the memory device and the data size.

7. The controller according to claim 1, wherein, The processor further sets a background flag by comparing the workload of the background operation with the workload of the host write operation, and The host interface further determines whether the workload of the background operation is greater than the workload of the host write operation by referring to the background flag.

8. The controller according to claim 7, wherein, The processor sets the background flag by comparing the number of valid pages copied from the sacrificial block to the target block during a garbage collection operation with the number of pages stored in the memory device in response to a write command from the host during the garbage collection operation.

9. A method of operating a controller, the controller controlling a memory device, the method comprising: Retrieve write commands received from the host; The write operation of the memory device is controlled in response to the acquired write command; When the workload of the controller's background operations is greater than the workload of the host write operations, the delay time is determined; as well as The completion response is provided to the host after a delay of the specified delay time. The delay time is determined based on the size of the free buffer and the estimated required buffer size. The estimated required buffer size is determined based on the number of commands received from the host but not acquired, the ratio of write commands among the most recently acquired commands, and the data size of the acquired write commands.

10. The operating method according to claim 9, further comprising: Receive write data associated with the write command from the host. Specifically, after receiving the written data, the process of providing the completion response is executed.

11. The operating method according to claim 9, further comprising: The size of the free buffer is determined based on the size of the host write buffer included in the controller, the size of the allocated buffer, and the estimated required buffer size.

12. The operating method according to claim 9, wherein, When the size of the free buffer is equal to or greater than the size of the threshold buffer, the delay time is set to "0".

13. The operating method according to claim 12, wherein, The size of the threshold buffer is determined based on the size of the host write buffer included in the controller, which can be simultaneously programmed into the memory device, and the data size.

14. The operating method according to claim 9, further comprising: The background flag is set by comparing the workload of the background operation with the workload of the host write operation, and The workload of the background operation is determined by referring to the background flag to determine whether it is greater than the workload of the host write operation.

15. The operating method according to claim 14, wherein, The background flag is set by comparing the number of valid pages copied from the sacrificial block to the target block during a garbage collection operation with the number of pages stored in the memory device in response to a write command from the host during the garbage collection operation.

16. A method of operating a controller, the method comprising: In response to the first write command, the first write data is buffered into a buffer and the memory device is controlled to perform a write operation and a background operation using the second write data buffered in the buffer. as well as When the background operation workload is greater than the write operation workload and the available capacity of the buffer is less than the threshold capacity, the delay time corresponding to the response delay is adjusted, and the memory device is controlled to execute the background operation at least during the delay time period. The available capacity is calculated using equation A: [Equation A] Where "Free buffer size" is the available capacity, "host write buffer size" is the total capacity of data written within the buffer, "allocated buffer size" is the allocated buffer capacity, and "estimated-required buffer size" is the estimated required buffer capacity calculated using Equation B: [Equation B] Where "# of unfetched CMD" is the number of commands waiting to be queued, "fetched write CMD ratio" is the ratio of queued write commands to a predetermined number of queued commands, and "data size of fetched write CMD" is the write data size of one of the queued write commands. The delay time is calculated using equation C: [Equation C] Where "delay" is the delay time, "threshold buffer size" is the threshold capacity, and "C" is a predetermined constant.

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