Network mapping methods, data processing methods and apparatus, devices, systems and media

Abstract

This disclosure provides a network mapping method, a data processing method, and apparatus, device, system, and medium. The many-core system includes multiple processing cores interconnected via an on-chip network. The on-chip network includes a storage and computing unit. The network mapping method includes: determining the operational attribute value of each operator among multiple operators of a neural network to be mapped; mapping operators with operational attribute values ​​less than or equal to an operational attribute threshold to the storage and computing unit; and mapping operators with operational attribute values ​​greater than the operational attribute threshold to the processing cores in the many-core system. Embodiments of this disclosure can improve the computational efficiency of neural networks.

Description

Technical Field

[0001] This disclosure relates to the field of computer processing technology, and in particular to a network mapping method, data processing method, apparatus, device, system, and medium. Background Technology

[0002] Many-core architecture is an important technological direction for accelerating the operation of intelligent algorithms such as neural networks in the era of intelligence. Generally speaking, each core in a many-core architecture is responsible for performing the main computing functions and exchanges data through a network-on-chip (NoC) between cores.

[0003] Neural networks typically consist of large-scale linear computations, non-linear activation function computations, and other smaller but diverse computations. Mapping a neural network to a many-core architecture allows the entire neural network's computation to be completed within that architecture. When computing neural networks using a many-core architecture, it is necessary to improve the computational efficiency of the neural network. Summary of the Invention

[0004] This disclosure provides a network mapping method, a data processing method, and an apparatus, device, system, and medium.

[0005] In a first aspect, this disclosure provides a network mapping method based on a many-core system. The many-core system includes multiple processing cores, which are connected via an on-chip network. The on-chip network is equipped with a storage and computing unit. The method includes: determining the operational attribute value of each operator among multiple operators of the neural network to be mapped; mapping operators whose operational attribute values ​​are less than or equal to an operational attribute threshold to the storage and computing unit; and mapping operators whose operational attribute values ​​are greater than the operational attribute threshold to the processing cores in the many-core system.

[0006] Secondly, this disclosure provides a data processing method based on a many-core system. The many-core system includes multiple processing cores, which are interconnected via an on-chip network. The on-chip network includes a storage and computing unit. The method includes: in response to an operator mapping request, allocating each of the multiple operators of a received neural network to a target processing unit in the many-core system; wherein the target processing unit allocated to the operator whose operational attribute value is less than or equal to an operational attribute threshold is a storage and computing unit, and the target processing unit allocated to the operator whose operational attribute value is greater than the operational attribute threshold is a processing core in the many-core system; executing the operator whose operational attribute value is less than or equal to the operational attribute threshold through the target processing unit; and executing the operator whose operational attribute value is greater than the operational attribute threshold through the processing core in the many-core system.

[0007] Thirdly, this disclosure provides a network mapping device based on a many-core system. The device includes: an attribute value determination module for determining the operational attribute value of each operator among multiple operators of a neural network to be mapped; a first mapping module for mapping operators whose operational attribute values ​​are less than or equal to an operational attribute threshold to the storage computing unit; and a second mapping module for mapping operators whose operational attribute values ​​are greater than the operational attribute threshold to the processing cores in the many-core system.

[0008] Fourthly, this disclosure provides a data processing apparatus, comprising: an allocation module, configured to, in response to an operator mapping request, allocate each of a plurality of operators of a received neural network to a target processing unit in a many-core system; wherein the target processing unit allocated to operators whose operational attribute values ​​are less than or equal to an operational attribute threshold is a storage computing unit, and the target processing unit allocated to operators whose operational attribute values ​​are greater than the operational attribute threshold is a processing core in the many-core system; a first operation module, configured to execute the operators whose operational attribute values ​​are less than or equal to the operational attribute threshold through the target processing unit; and a second operation module, configured to execute the operators whose operational attribute values ​​are greater than the operational attribute threshold through the processing core in the many-core system.

[0009] Fifthly, this disclosure provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores one or more computer programs executable by the at least one processor, the one or more computer programs being executed by the at least one processor to enable the at least one processor to perform the network mapping method described above.

[0010] In a sixth aspect, this disclosure provides a many-core system, comprising: multiple processing cores, an on-chip network, and multiple storage computing units located on the on-chip network; the on-chip network is configured to interact with data between the multiple processing cores and external data; wherein, the processing cores are configured to receive and execute operators whose operation attribute values ​​are greater than an operation attribute threshold; and the storage computing units are configured to receive and execute operators whose operation attribute values ​​are less than or equal to the operation attribute threshold.

[0011] In a seventh aspect, this disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor / processor core, implements the network mapping method or data processing method described above.

[0012] In the embodiments provided in this disclosure, among the multiple operators of the neural network to be mapped, operators with operational attribute values ​​greater than the operational attribute threshold have a greater demand for computing resources and can therefore be mapped to the processing cores in the many-core system to obtain sufficient computing resources. Operators with operational attribute values ​​less than or equal to the operational attribute threshold have a smaller demand for computing resources and can therefore be mapped to the storage computing unit located on the on-chip network in the many-core system for computation, thereby reducing the waste of idle computing time of the processing core caused by the smaller computing resources required for computation when the operator is mapped to the processing core. Furthermore, since the storage computing unit is located on the on-chip network, the computation time of the storage computing unit for the corresponding operator and the time used by the on-chip network for inter-core communication will overlap to a certain extent, thereby shortening the overall computation time of the many-core system for computing the neural network and improving the computational efficiency of the neural network.

[0013] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0014] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0015] Figure 1 This is a schematic diagram of a many-core architecture according to an embodiment of the present disclosure;

[0016] Figure 2 This is a schematic diagram of the mapping processing of the neural network on a many-core architecture according to an embodiment of the present disclosure;

[0017] Figure 3 A schematic diagram illustrating the processing flow of a neural network with edge operators in a many-core architecture according to an embodiment of this disclosure;

[0018] Figure 4 A flowchart of the network mapping method provided in this embodiment of the disclosure;

[0019] Figure 5 This is a schematic diagram of the many-core system architecture according to an embodiment of this disclosure;

[0020] Figure 6 This is a schematic diagram of the processing flow of the network mapping method according to an embodiment of the present disclosure;

[0021] Figure 7 This is a flowchart of a data processing method according to an embodiment of the present disclosure;

[0022] Figure 8 A block diagram of a network mapping apparatus provided in an embodiment of this disclosure;

[0023] Figure 9 A block diagram of a data processing apparatus provided in embodiments of this disclosure;

[0024] Figure 10 A block diagram of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0025] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0026] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0027] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, they specify the presence of features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0029] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0030] Figure 1 A schematic diagram of a many-core architecture according to an embodiment of this disclosure is shown. Figure 1In this architecture, the many-core architecture may include multiple processing cores (hereinafter referred to as cores) 110 and an on-chip network 120. Each processing core 110 includes: a control unit 101, a storage unit 102, a computing unit 103, and a routing unit 104; the arrows between the processing cores 110 indicate the routing paths between the processing cores 110 of the on-chip network 120.

[0031] In some embodiments, the many-core architecture can be implemented as a system-on-chip (SoC), which uses on-chip networking as its communication architecture. Since the core idea of ​​on-chip networking technology is to port computer network communication technology to chip design, thereby replacing the traditional bus communication architecture, many-core SoCs have characteristics such as high parallelism, strong scalability, and controllable power consumption, thus enabling their widespread application in fields such as high-density computing.

[0032] In some embodiments, a many-core system-on-a-chip (SoC) can be a many-core system acceleration chip. In the architecture of a many-core system acceleration chip, the processing core 110 can be accelerated through specially designed hardware circuits. For example, taking convolution operation as an example, the core of convolution operation is multiplication-accumulation operation. Therefore, the convolutional neural network hardware acceleration circuit can use a single multiplication-accumulation array structure to accelerate the multiplication-accumulation operation. As another example, in some scenarios, adders can be used to replace multipliers for hardware acceleration of convolution operations, which can effectively reduce the resource consumption of hardware circuits and increase the processor operating frequency, thereby achieving the goal of reducing hardware chip costs and improving computing performance.

[0033] In some embodiments, the processing core 110 may also include a hierarchical structure such as shared memory; Figure 1 The form of on-chip network can be diverse; for example, the form of on-chip network can be one of the following: 2Dmesh structure, 2DTorus structure, octagon structure, SPIN structure and three-dimensional topology structure. Figure 1 The on-chip network shown is only one form; the specific configuration can be set according to actual processing needs, and this disclosure does not impose any specific limitations.

[0034] Figure 2 This diagram illustrates the mapping processing of a neural network on a many-core architecture according to an embodiment of the present disclosure. Figure 2 and Figure 1 The same labels in the same text indicate the same structure. Figure 2 In the neural network 130, there are one or more operators, such as operator 1, operator 2, operator 3 and operator 4. Operators can be regarded as operation functions, such as convolution, pooling, etc. The arrows between the operators of the neural network indicate the processing order between the operators of the neural network.

[0035] It should be understood that Figure 2 The relationships and processing order between operators in a neural network are merely illustrative. In practical applications, the processing order between operators in a neural network can be understood as the compilation order or compilation and execution order of the operators in the computation graph of the neural network.

[0036] In some embodiments, the processing order between operators in a neural network can be determined based on the connection method between operators in the computation graph of the neural network. For example, the connection method between operators can include: series connection, parallel connection, or a combination of series and parallel connection; as another example, multiple operators can also form a multi-branch structure, such as a tree structure, a directed acyclic graph, etc., that is, multiple branches can exist.

[0037] Continue to refer to Figure 2 The operators in the neural network 130 are mapped to the many-core system 100. The processing cores 110 in the many-core system 100 can cooperate to complete the calculation of the entire neural network, while the on-chip network 120 is responsible for processing the data transmission between the cores 110.

[0038] In some embodiments, the operators in the neural network 130 are diverse. For example, there may be a variety of operators in the neural network, but the computational load is not large (less than a preset computational load threshold). The computation of operators in the neural network may be unbalanced. For example, if the computational resource requirement of an operator in the neural network is less than or equal to the computational resource available for the processing core, it will cause a decrease in the utilization rate of computational resources.

[0039] In some embodiments, computing resources may include computing resources for processing cores to meet various computing needs, and computing resources can be measured by a variety of metrics. Metrics may include at least one of the following metrics for a processing core: computational load, operations per second (OPS), and power consumption. This disclosure does not limit the type of metrics for measuring computing resources; they can be selected according to actual needs in practical application scenarios.

[0040] For ease of description, in the following description of the embodiments, the operator in the neural network that satisfies the first preset threshold condition can be referred to as an edge operator. The first preset threshold condition includes: the computing power resource requirement is less than or equal to the computing power resource available of the processing core in the many-core system, and / or, the ratio of the computing power resource requirement to the sum of the computing power resource requirements of all operators in the neural network is less than or equal to a predetermined ratio threshold.

[0041] For ease of description, in the following embodiments, the operator in the neural network that satisfies the second preset threshold condition is referred to as the central operator. The second preset threshold condition includes: the computing power resource requirement is greater than the computing power resource available from the processing cores in the many-core system, and / or, the ratio of the computing power resource requirement to the sum of the computing power resource requirements of all operators in the neural network is less than or equal to a predetermined proportion threshold. In practical application scenarios, the predetermined proportion threshold can be customized in advance according to actual computing needs, and this disclosure does not impose specific limitations.

[0042] For example, the central operator can be an operator used for large-scale linear computation.

[0043] The following is combined Figure 3 We analyze the computational latency of many-core architecture when computing neural networks with edge operators.

[0044] Figure 3 A schematic diagram illustrating the processing flow of a many-core architecture computing a neural network with edge operators according to an embodiment of the present disclosure is shown. Figure 3 and Figure 1 The same labels in the same way indicate the same structure; Figure 3 In this model, square nodes are used to represent edge operators, and circular nodes are used to represent center operators. For example... Figure 3 As shown, the neural network may include, for example, operators 5, 6, 7 and 8; wherein operators 5 and 7 are center operators, and operators 6 and 8 are edge operators.

[0045] refer to Figure 3 The operators mentioned above in the neural network can be mapped to multiple processing cores in the many-core system through neural network mapping. For example, operator 5 can be mapped to processing core 1, operator 6 to processing core 5, operator 7 to processing core 6, and operator 8 to processing core 9.

[0046] exist Figure 3 Within a single instruction execution time tick, the processing core can fully utilize its computing power when calculating the central operator. For example, when processing core 1 calculates operator 5 (the central operator), and when processing core 6 calculates operator 7 (the central operator), the computation delays of operators 5 and 7, which are central operators, can each fully utilize the spare computation time of the corresponding processing core's computing power. However, when processing core 5 calculates operator 6 (the edge operator), and when processing core 9 calculates operator 8 (the edge operator), the computation delays of operators 6 and 8, which are edge operators, cannot fully utilize the spare computation time of the corresponding processing core's computing power.

[0047] The instruction execution time clock is used to characterize the time clock during which the processing core in a many-core system executes the assigned operator.

[0048] pass Figure 3 It can be seen that the reasons for wasted time in many-core architecture when computing neural networks may include at least one of the following: long latency of data transmission between cores, and the idle computing time that cannot be fully utilized by the small computing power requirements of edge operators.

[0049] This disclosure proposes a network mapping method and data processing method based on a many-core system, which can reduce the time wasted by data transmission between many cores and edge operator computation, thereby shortening the overall computation time of the neural network and improving the computational efficiency of the neural network.

[0050] The network mapping method and data processing method based on a many-core system according to embodiments of this disclosure can be executed by electronic devices such as terminal devices or servers. The terminal device can be an in-vehicle device, user equipment (UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, in-vehicle device, wearable device, etc. The method can be implemented by a processor calling computer-readable program instructions stored in memory. Alternatively, the method can be executed by a server.

[0051] Figure 4 A flowchart illustrating a network mapping method based on a many-core system provided in this disclosure embodiment. In this disclosure embodiment, the many-core system may include multiple processing cores, which are interconnected via an on-chip network. The on-chip network includes a storage and computing unit. (Refer to...) Figure 4 The method includes the following steps.

[0052] S410, determine the operational attribute value of each operator among the multiple operators of the neural network to be mapped.

[0053] S420 maps operators whose operation attribute values ​​are less than or equal to the operation attribute threshold to storage computing units.

[0054] S430 maps operators whose operation attribute values ​​are greater than the operation attribute threshold to the processing cores in the many-core system.

[0055] Through the steps S410-S430 above, among the multiple operators of the neural network to be mapped, operators with operation attribute values ​​greater than the operation attribute threshold have a greater demand for computing resources and can therefore be mapped to the processing cores in the many-core system to obtain sufficient computing resources; operators with operation attribute values ​​less than or equal to the operation attribute threshold have a smaller demand for computing resources and can therefore be mapped to the storage computing unit located on the on-chip network in the many-core system for computation, thereby reducing the waste of idle computation time of the processing core when the operator is mapped to the processing core for computation but the computational resources required for computation are small; furthermore, since the storage computing unit is located on the on-chip network, the computation time of the storage computing unit for the corresponding operator and the time used by the on-chip network for inter-core communication will overlap to a certain extent, thereby shortening the overall computation time of the many-core system for computing the neural network and improving the computational efficiency of the neural network.

[0056] To facilitate understanding, the following will be explained... Figure 5 and Figure 6 This document describes the many-core system architecture and network mapping method according to embodiments of the present disclosure. Figure 5 This diagram illustrates a many-core system architecture according to an embodiment of the present disclosure. Figure 6 A schematic diagram illustrating the processing flow of the network mapping method according to an embodiment of this disclosure is shown. Figure 5 and Figure 1 The same labels in the same way indicate the same structure; Figure 6 and Figure 3 The same labels in the text indicate the same structure.

[0057] exist Figure 5 In this embodiment, the architecture of the many-core system 100 includes multiple processing cores 110 and an on-chip network 120; the multiple processing cores 110 are connected to each other through the on-chip network 120, and the on-chip network 120 is provided with a storage computing unit 121; that is, the many-core system in this embodiment is a many-core on-chip network computing architecture based on the storage computing unit.

[0058] In some embodiments, the storage computing unit 121 is a memory array; the memory array includes at least one of a resistive random access memory (RRAM) array, a phase-change random access memory (PCRAM) array, and a magnetic random access memory (MRAM) array. This disclosure does not limit this.

[0059] The memory arrays shown in the embodiments of this disclosure are all non-volatile memory arrays; for example, at least one of NAND flash memory arrays, NOR flash memory arrays, and variable resistance memory arrays. This disclosure does not limit the scope of the disclosure.

[0060] In some embodiments, the memory array may further include: a volatile memory array; for example: at least one of random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), and synchronous dynamic random access memory (SDRAM).

[0061] In this embodiment of the disclosure, the volatile memory array requires power to maintain the stored data and execute operators; the non-volatile memory can provide persistent data and execute operators by retaining the stored data when not powered. In practical applications, the appropriate method can be chosen based on actual needs. This disclosure does not impose any limitations on this.

[0062] For the sake of simplicity, the following embodiments use an RRAM array as an example to illustrate the specific processing method of the network mapping. However, this description should not be construed as limiting the scope or implementation possibilities of this solution; the processing methods for other types of memory arrays besides RRAM arrays are consistent with those for RRAM arrays.

[0063] In some embodiments, RRAM is a high-density storage device that can be used in in-memory computing scenarios, such as matrix multiplication. Taking matrix multiplication as an example, one matrix (e.g., a weight matrix) is set as the resistance value of the RRAM, and another matrix is ​​used as the input data at one end of the RRAM. The other end can then quickly obtain the output data of the matrix multiplication. With appropriate processing at the output end, RRAM can also perform nonlinear operations such as linear rectified functions, such as rectified linear units (ReLU) activation functions.

[0064] Because RRAM has low computational latency and small footprint, this embodiment of the present disclosure uses RRAM arrays in on-chip networks with many-core architectures, for example, by arranging them on routing paths to perform simple calculations during transmission. When data passes through the RRAM array of the on-chip network, it completes a certain degree of calculation through the corresponding RRAM array.

[0065] like Figure 6As shown, edge operators (such as operator 6 and operator 8) can be assigned to the on-chip network 120 for computation. Within the processing time of each computation instruction execution time tick, the computation time of the edge operators and the communication time between the processing core 110 will overlap to a certain extent, thereby shortening the overall computation time of the network and improving computation efficiency.

[0066] exist Figure 6 Within one instruction execution time tick, the processing core can fully utilize the computing power of the corresponding processing core when computing the central operator. For example, when processing core 1 is computing operator 5 (central operator), and when processing core 6 is computing operator 7 (central operator), the computation delay of operator 5 and operator 7, which are central operators, can respectively fill the spare computation time of the corresponding processing core's computing power.

[0067] Continue to refer to Figure 6 Operator 6 (edge ​​operator) is assigned to the first storage computing unit on the on-chip network 120, which is located on the routing path between processing core 1 and processing core 5. Operator 8 (edge ​​operator) is assigned to the second storage computing unit on the on-chip network 120, which is also located on the routing path between processing core 5 and processing core 8. Operator 6 (edge ​​operator) is computed through the first storage computing unit, and operator 8 (edge ​​operator) is computed through the second storage computing unit. Since the computation speed of the storage computing unit is close to the transmission speed (the speed difference is less than a predetermined speed threshold), mapping the edge operator to the storage computing unit, such as RRAM, can make full use of the computing resources of the storage computing unit, reduce the wasted idle time, and help speed up the processing, shorten the overall network computation time, and improve computation efficiency.

[0068] In some embodiments, the plurality of operators includes a first operator, and the computing power resource requirement of the first operator meets a first preset threshold condition; step S420 may specifically include: mapping the first operator whose operation attribute value is less than or equal to the operation attribute threshold to the storage computing unit; step S430 may specifically include: mapping the operator whose operation attribute value is greater than the operation attribute threshold to the processing core in the many-core system.

[0069] In some embodiments, the first preset threshold condition includes: the computing power resource requirement of the first operator is less than or equal to the computing power resource availability of the processing core in the many-core system, and / or, the ratio of the computing power resource requirement of the first operator to the sum of the computing power resource requirements of all operators in the neural network is less than or equal to a predetermined ratio threshold.

[0070] Through the above steps S11-S12, if the operation attribute value of the first operator is less than or equal to the operation attribute threshold that the storage computing unit can bear, the first operator can be mapped to the storage computing unit on the on-chip network to reduce the waste of idle computing time on the processing core caused by mapping to the processing core, and shorten the overall computing time of the neural network in the many-core system; if the operation attribute value of the first operator is greater than the operation attribute threshold that the storage computing unit can bear, the first operator can be mapped to the processing core to ensure that the first operator can obtain sufficient computing power resources.

[0071] In some embodiments, the computational attribute value includes at least one of computational load, computational power consumption, and computation time; the computational attribute threshold includes at least one of the computational load threshold, computational power consumption threshold, and computation time threshold corresponding to the computational attribute value.

[0072] In this embodiment of the disclosure, by providing a variety of different operation attribute values, the operation attribute values ​​can be selected according to the computational needs in the actual computational scenario. This makes the comparison result of the operation attribute value of the first operator and the operation attribute threshold that the storage computing unit can bear more in line with the computational needs in the actual computational scenario, thereby mapping each operator in the neural network to be mapped to the processing unit that meets the computational needs.

[0073] In some embodiments, the neural network further includes a second operator among the multiple operators; wherein the computational resource requirement of the second operator meets a second preset threshold condition; the network mapping method may further include: mapping the second operator to multiple processing cores in a many-core system, so that the corresponding processing cores execute the second operator.

[0074] In some embodiments, the second preset threshold condition includes: the computing power resource requirement of the second operator is greater than the computing power resource available from the processing cores in the many-core system, and / or, the ratio of the computing power resource requirement of the second operator to the sum of the computing power resource requirements of all operators in the neural network is greater than a predetermined ratio threshold.

[0075] In this embodiment of the disclosure, the plurality of operators include a first operator and a second operator; wherein, the computing power resource requirement of the first operator meets the aforementioned first preset threshold condition, and the computing power resource requirement of the second operator meets the aforementioned second preset threshold condition; the first operator in the plurality of operators of the neural network includes, for example, the edge operator described in the above embodiments; the second operator may include, for example, the central operator described in the above embodiments; each central operator in the neural network can be mapped to a processing core in a many-core system; so that when the second operator is executed, it can obtain sufficient computing power resources in the corresponding processing core.

[0076] The following specific embodiments illustrate the detailed process by which the first operator is mapped to the storage computing unit. In some embodiments, step S420 may include the following steps.

[0077] S21, the processing kernels mapped to the many-core system corresponding to the two adjacent second operators are taken as the two corresponding processing kernels.

[0078] S22, the first operator located between two adjacent second operators and whose operation attribute value is less than or equal to the operation attribute threshold is mapped to the storage computing unit on the corresponding routing path between the two processing cores.

[0079] By mapping the first operator to the storage computing unit located on the routing path between two adjacent second operators through the above steps S21 to S22, it is possible to realize that when the on-chip network communicates and transmits data between two adjacent second operators, the storage computing unit located on the on-chip network executes the operation of the first operator. The communication transmission time and the computation time of the first operator have a certain degree of overlap, which helps to shorten the overall computation time of the many-core system's neural network and improve the computation efficiency of the neural network.

[0080] In some embodiments, step S430 may further include: mapping a first operator located between two adjacent second operators and whose operation attribute value is greater than the operation attribute threshold to a specified processing kernel; wherein, the specified processing kernel is any processing kernel among the processing kernels corresponding to at least one routing path between the two corresponding processing kernels.

[0081] In this embodiment, among the processing cores corresponding to at least one routing path between the two corresponding processing cores, the designated processing core is a different processing core from the two corresponding processing cores. This processing core can enable the first operator whose operation attribute value is greater than the operation attribute threshold to obtain sufficient computing power resources.

[0082] In this embodiment of the disclosure, the first operator in the neural network is located between two second operators, and the two central operators can be referred to as the two adjacent second operators of the first operator; wherein, the two adjacent second operators are mapped to the corresponding processing cores in the many-core system, and can be referred to as the two corresponding processing cores, and there can be multiple routing paths between the two corresponding processing cores.

[0083] For example, in Figure 6In this diagram, operator 6 is the first operator, and operators 5 and 7 are two adjacent second operators of operator 6. Operator 5 is mapped to core 1, and operator 7 is mapped to core 5. There are multiple routing paths between core 1 and core 5 (e.g., including but not limited to: the routing path corresponding to core 1 reaching core 5 via core 2, or the routing path corresponding to core 1 reaching core 5 via core 4, or the routing path corresponding to core 1 reaching core 5 via core 4, core 7, and core 8, etc.). When the operation attribute value of the first operator located between two adjacent second operators is greater than the operation attribute threshold (e.g., the computational amount of operator 6 located between operators 5 and 7 exceeds the preset threshold of the computational amount that the on-chip network can carry), the first operator can be mapped to any processing core located between the processing cores where the two adjacent second operators are located and which is located in at least one routing path. That is, the first operator can be mapped to a processing core near the processing cores where the two adjacent second operators are located (e.g., core 2, core 4, core 7, or core 8).

[0084] In some embodiments, the specified processing core is a processing core other than the two corresponding processing cores (the processing cores corresponding to the two adjacent second operators of the first operator respectively), and the specified processing core has a communication connection relationship with at least one of the two corresponding processing cores.

[0085] In some embodiments, the communication connection may be a direct communication connection or an indirect communication connection, wherein the indirect communication connection includes a communication connection established through fewer than a predetermined number of cores.

[0086] In this embodiment of the disclosure, mapping the first operator to any processing core among the processing cores corresponding to at least one routing path between the two adjacent second operators helps to reduce the time wasted by data transmission between the cores, thereby shortening the overall computation time of the neural network and improving the computational efficiency of the neural network.

[0087] In some embodiments, step S430 may further include: mapping a first operator whose operation attribute value is greater than the operation attribute threshold to any processing core in the many-core system.

[0088] In the embodiments disclosed herein, the first operator can be mapped to any processing core in the many-core system, thereby providing multiple implementation methods for mapping the first operator to processing cores in the many-core system. In practical application scenarios, the specific implementation method for mapping the first operator to processing cores in the many-core system can be selected according to actual needs.

[0089] For ease of understanding, in conjunction with the above... Figure 6The specific flow of the network mapping method according to exemplary embodiments of this disclosure is described. In embodiments of this disclosure, the first operator is an edge operator, and the second operator is a center operator. In some embodiments, the network mapping method may include the following steps.

[0090] S601, Obtain the neural network to be mapped.

[0091] S602 divides the operators of neural networks into edge operators and center operators.

[0092] S603 maps all central operators to multiple cores of the many-core system.

[0093] S604 sets the threshold for the amount of computation that the on-chip network between cores can carry, and maps the edge operators between two adjacent central operators to the storage computing units of the on-chip network they pass through.

[0094] In this step, two adjacent central operators are assigned to two processing cores in the many-core system.

[0095] S605, if the computational load of the on-chip network's storage computing unit for the edge operator exceeds the threshold of the on-chip network's computational load capacity, then the corresponding edge operator will be mapped to a nearby core.

[0096] In this step, the nearby core is the designated processing core in this embodiment of the disclosure. For the processing cores in the many-core system that correspond to two adjacent second operators, any of the other processing cores corresponding to at least one routing path between the two corresponding processing cores.

[0097] For example in Figure 6 In this system, cores 1 to 9 are the processing cores in the many-core system. For example, operators 5 and 7 are central operators, and operators 6 and 8 are edge operators. Operator 6 is located between operators 5 and 7, and operator 8 is located after operator 7. Operator 5 is mapped to core 1 for computation via core 1; operator 7 is mapped to core 5 for computation via core 5; operator 6 is mapped to a storage computing unit on the on-chip network traversed by cores 1 and 5. This storage computing unit is located on one of the multiple routing paths between cores 1 and 5 on the on-chip network. When the on-chip network transmits data, this storage computing unit on the on-chip network performs computation on operator 6, thereby shortening the overall computation time of the many-core system for computing the neural network and improving the computational efficiency of the neural network.

[0098] Continue to refer to Figure 6When the computational load of operator 6 exceeds the preset threshold for the computational load that the on-chip network can bear, operator 6 can be mapped to a designated processing core. The designated processing core is any of the other processing cores corresponding to the routing path between core 1 and core 5. For example, if the processing cores corresponding to the routing path between core 1 and core 5 include core 2 and core 4, then core 2 and core 4 are cores located near core 1 and core 5. Operator 6 is mapped to core 2 or core 4 so that operator 6 can obtain sufficient computing power resources in the corresponding processing core.

[0099] According to the network mapping method of the embodiments of this disclosure, edge operators in the neural network whose operational attribute values ​​are greater than the operational attribute threshold can be mapped to the processing cores in the many-core system for computation, thereby ensuring that the first operator obtains sufficient computing power resources in the processing core. Edge operators in the neural network whose operational attribute values ​​are less than or equal to the operational attribute threshold can also be allocated to the storage computing unit for computation, thereby reducing the waste of idle computing time in the processing core when these edge operators are mapped to the processing core for computation due to the smaller computing power resources required. Furthermore, since the storage computing unit is located on the on-chip network, the computation time of the storage computing unit for the corresponding operator and the time used by the on-chip network for inter-core communication will overlap to a certain extent, thereby shortening the overall computation time of the many-core system for computing the neural network and improving the computational efficiency of the neural network.

[0100] It is understood that the various method embodiments mentioned above in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0101] Figure 7 A flowchart illustrating a data processing method based on a many-core system according to an embodiment of this disclosure is provided. In this embodiment, the many-core system may include multiple processing cores, which are interconnected via an on-chip network. The on-chip network includes a storage and computing unit. Figure 7 As shown, the data processing method may include the following steps.

[0102] S710, in response to the operator mapping request, each of the multiple operators of the received neural network is assigned to a target processing unit in the many-core system; wherein, the target processing unit assigned to the operator whose operation attribute value is less than or equal to the operation attribute threshold is a storage computing unit, and the target processing unit assigned to the operator whose operation attribute value is greater than the operation attribute threshold is a processing core in the many-core system; S720, the operator whose operation attribute value is less than or equal to the operation attribute threshold is executed by the target processing unit; S730, the operator whose operation attribute value is greater than the operation attribute threshold is executed by the processing core in the many-core system.

[0103] In this embodiment of the disclosure, the neural network includes a first operator and a second operator among its multiple operators; the computational resource requirement of the first operator meets a first preset threshold condition, and the computational resource requirement of the second operator meets a second preset threshold condition.

[0104] In some embodiments, the first preset threshold condition includes: the computing power resource requirement of the first operator is less than or equal to the computing power resource availability of the processing core in the many-core system, and / or, the ratio of the computing power resource requirement of the first operator to the sum of the computing power resource requirements of all operators in the neural network is less than or equal to a predetermined ratio threshold.

[0105] In some embodiments, the second preset threshold condition includes: the computing power resource requirement of the second operator is greater than the computing power resource available from the processing cores in the many-core system, and / or, the ratio of the computing power resource requirement of the second operator to the sum of the computing power resource requirements of all operators in the neural network is greater than a predetermined ratio threshold.

[0106] In this embodiment of the disclosure, the data processing method can be executed by a processing core in a many-core system or a dedicated control unit. Through the data processing method of this embodiment, the processing core in the many-core system processes edge operators in the neural network whose operational attribute values ​​are greater than the operational attribute threshold. Processing operators whose operational attribute values ​​are greater than the operational attribute threshold using the processing core in the many-core system ensures that the operator receives sufficient computing power resources from the processing core. Processing operators whose operational attribute values ​​are less than or equal to the operational attribute threshold using the storage computing unit on the on-chip network reduces the waste of idle computing time in the processing core caused by the small computing power resources required for the operator's computation. Furthermore, since the storage computing unit is located on the on-chip network, the computation time of the storage computing unit for the corresponding operator and the time used for inter-core communication on the on-chip network will overlap to a certain extent, thereby shortening the overall computation time of the many-core system for computing the neural network and improving the computational efficiency of the neural network.

[0107] It should be clarified that the data processing method of this disclosure is not limited to the specific configuration and processing described in the above embodiments and shown in the figures. For the sake of convenience and brevity, detailed descriptions of known methods are omitted here, and the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes of the network mapping methods in the foregoing method embodiments, which will not be repeated here.

[0108] Figure 8 A block diagram of a network mapping apparatus provided in an embodiment of this disclosure.

[0109] Reference Figure 8 This disclosure provides a network mapping device 800 based on a many-core system. The many-core system includes multiple processing cores, which are connected to each other via an on-chip network. The on-chip network is equipped with a storage computing unit. The network mapping device 800 includes the following modules.

[0110] The attribute value determination module 810 is used to determine the operational attribute value of each operator among multiple operators of the neural network to be mapped.

[0111] The first mapping module 820 is used to map operators whose operation attribute values ​​are less than or equal to the operation attribute threshold to the storage computing unit.

[0112] The second mapping module 830 maps operators whose operation attribute values ​​are greater than the operation attribute threshold to the processing cores in the many-core system.

[0113] In some embodiments, the neural network includes a first operator among multiple operators, and the computational resource requirement of the first operator meets a first preset threshold condition; the first mapping module 820 is specifically used to map the first operator whose operation attribute value is less than or equal to the operation attribute threshold to the storage computing unit; the second mapping module 830 is specifically used to map the first operator whose operation attribute value is greater than the operation attribute threshold to the processing core in the many-core system.

[0114] In some embodiments, the neural network includes a second operator among the multiple operators, and the computational resource requirement of the second operator meets a second preset threshold condition; the network mapping device 800 further includes a third mapping module for mapping the second operator to multiple processing cores in a many-core system, so that the corresponding processing cores execute the second operator.

[0115] In some embodiments, the first mapping module 820 is specifically used to: map the processing cores corresponding to the two adjacent second operators in the many-core system as the two corresponding processing cores; and map the first operator located between the two adjacent second operators and whose operation attribute value is less than or equal to the operation attribute threshold to the storage computing unit on the routing path between the two corresponding processing cores.

[0116] In some embodiments, the second mapping module 830 is specifically used to: map a first operator located between two adjacent second operators and whose operation attribute value is greater than the operation attribute threshold to a specified processing core; wherein, the specified processing core is any processing core among the processing cores corresponding to at least one routing path between the two corresponding processing cores.

[0117] In some embodiments, the second mapping module 830 is further configured to: map a first operator whose operation attribute value is greater than the operation attribute threshold to any processing core in the many-core system.

[0118] In some embodiments, the neural network includes a first operator and a second operator among its multiple operators; wherein the computing power resource requirement of the first operator meets a first preset threshold condition, and the computing power resource requirement of the second operator meets a second preset threshold condition.

[0119] The first preset threshold conditions include: the computing power resource requirement of the first operator is less than or equal to the computing power resource available from the processing cores in the many-core system, and / or the ratio of the computing power resource requirement of the first operator to the sum of the computing power resource requirements of all operators in the neural network is less than or equal to a predetermined ratio threshold.

[0120] In some embodiments, the computational attribute value includes at least one of computational load, computational power consumption, and computation time; the computational attribute threshold includes at least one of the computational load threshold, computational power consumption threshold, and computation time threshold corresponding to the computational attribute value.

[0121] In some embodiments, the storage computing unit on the on-chip network is a memory array; the memory array includes at least one of resistive random access memory (RRAM) array, phase-change random access memory (PCRAM) array, and magnetic random access memory (MRAM) array.

[0122] Through the network mapping apparatus of this disclosure embodiment, among the multiple operators of the neural network to be mapped, operators with operation attribute values ​​greater than the operation attribute threshold have a greater demand for computing resources and can therefore be mapped to the processing cores in the many-core system to obtain sufficient computing resources; operators with operation attribute values ​​less than or equal to the operation attribute threshold have a smaller demand for computing resources and can therefore be mapped to the storage computing unit located on the on-chip network in the many-core system for computation, thereby reducing the waste of idle computation time of the processing core caused by the small computing resources required for computation when the operator is mapped to the processing core; furthermore, since the storage computing unit is located on the on-chip network, the computation time of the storage computing unit for the corresponding operator and the time used by the on-chip network for inter-core communication will overlap to a certain extent, thereby shortening the overall computation time of the many-core system for computing the neural network and improving the computational efficiency of the neural network.

[0123] Figure 9A block diagram of a data processing apparatus provided in an embodiment of this disclosure.

[0124] Reference Figure 9 This disclosure provides a data processing apparatus, which includes the following modules.

[0125] The allocation module 910 is used to allocate each of the multiple operators of the received neural network to a target processing unit in the many-core system in response to an operator mapping request; wherein, the target processing unit allocated to the operator whose operation attribute value is less than or equal to the operation attribute threshold is a storage computing unit, and the target processing unit allocated to the operator whose operation attribute value is greater than the operation attribute threshold is a processing core in the many-core system; the first operation module 920 is used to execute the operator whose operation attribute value is less than or equal to the operation attribute threshold through the target processing unit; the second operation module 930 is used to execute the operator whose operation attribute value is greater than the operation attribute threshold through the processing core in the many-core system.

[0126] According to the data processing apparatus of this disclosure, the processing core in the many-core system can be used to process edge operators in the neural network whose operational attribute values ​​are greater than the operational attribute threshold, so as to ensure that the corresponding operators obtain sufficient computing power resources in the processing core; the storage computing unit on the on-chip network processes operators whose operational attribute values ​​are less than or equal to the operational attribute threshold, so as to reduce the waste of idle computing time of the processing core caused by the small computing power resources required for the corresponding operators when they are mapped to the processing core for computing; and since the storage computing unit is located on the on-chip network, the computing time of the storage computing unit for the corresponding operators and the time of the on-chip network for inter-core communication will overlap to a certain extent, thereby shortening the overall computing time of the many-core system for computing the neural network and improving the computing efficiency of the neural network.

[0127] It should be clarified that this disclosure is not limited to the specific configurations and processes described in the foregoing embodiments and shown in the figures. For the sake of convenience and brevity, detailed descriptions of known methods are omitted here, and the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0128] Figure 10 A block diagram of an electronic device provided in an embodiment of this disclosure.

[0129] Reference Figure 10This disclosure provides an electronic device comprising: at least one processor 1001; at least one memory 1002; and one or more I / O interfaces 1003 connected between the processor 1001 and the memory 1002; wherein the memory 1002 stores one or more computer programs executable by the at least one processor 1001, the one or more computer programs being executed by the at least one processor 1001 to enable the at least one processor 1001 to perform the network mapping method described above.

[0130] This disclosure also provides a many-core system, including: multiple processing cores 1101, an on-chip network 1102, and multiple storage computing units 1103 located on the on-chip network; the on-chip network 1102 is configured to interact with data between the multiple processing cores 1101 and external data; wherein, the processing cores are configured to receive and execute operators whose operation attribute values ​​are greater than the operation attribute threshold; the storage computing units are configured to receive and execute operators whose operation attribute values ​​are less than or equal to the operation attribute threshold.

[0131] In some embodiments, the electronic device may be a neuromorphic chip. Since neuromorphic chips can employ vectorized computation and require external memory, such as Double Data Rate (DDR) synchronous dynamic random access memory, to load parameters such as weights of the neural network model, the batch processing method used in this embodiment offers higher computational efficiency.

[0132] This disclosure also provides a computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor / processor core, implements the aforementioned network mapping method or data processing method. The computer-readable storage medium may be volatile or non-volatile.

[0133] The electronic devices and computer-readable storage media provided in the embodiments of this disclosure can be used to implement any of the network mapping methods provided in this disclosure. The corresponding technical solutions and descriptions are the same as those described in the method section and will not be repeated here.

[0134] This disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code. When the computer-readable code is run in the processor of an electronic device, the processor in the electronic device executes the above-described network mapping method or data processing method.

[0135] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer storage media (or non-transitory media) and communication media (or transient media).

[0136] As is known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable program instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technologies, portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable program instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0137] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0138] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0139] The computer program product described herein can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0140] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0141] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0142] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0143] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0144] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A network mapping method based on a many-core system, characterized in that, The many-core system includes multiple processing cores, which are interconnected via an on-chip network. The on-chip network includes a storage and computing unit. The method includes: Determine the operational attribute value of each operator among multiple operators in the neural network to be mapped, wherein the operational attribute value is used to reflect the operator's demand for computing resources; Operators whose operational attribute values ​​are less than or equal to the operational attribute threshold are mapped to the storage computing unit; Operators whose operational attribute values ​​are greater than the operational attribute threshold are mapped to processing cores in the many-core system; The plurality of operators include a first operator and a second operator, wherein the computing power resource requirement of the first operator is less than that of the second operator; The step of mapping operators whose operational attribute values ​​are less than or equal to the operational attribute threshold to the storage computing unit includes: The processing cores mapped to the many-core system that correspond to the two adjacent second operators are respectively regarded as the two corresponding processing cores; The first operator located between the two adjacent second operators, and whose operation attribute value is less than or equal to the operation attribute threshold, is mapped to the storage computing unit on the corresponding routing path between the two processing cores; The first operator located between the two adjacent second operators, and whose operation attribute value is greater than the operation attribute threshold, is mapped to a designated processing core; wherein, the designated processing core is any processing core among the processing cores corresponding to at least one routing path between the two corresponding processing cores.

2. The method according to claim 1, characterized in that, The plurality of operators includes a first operator, and the computing power resource requirement of the first operator meets a first preset threshold condition; wherein, the first preset threshold condition includes: the computing power resource requirement of the first operator is less than or equal to the computing power resource available of the processing core in the many-core system, and / or, the ratio of the computing power resource requirement of the first operator to the sum of the computing power resource requirements of all operators of the neural network is less than or equal to a predetermined ratio threshold. The step of mapping operators whose operational attribute values ​​are less than or equal to the operational attribute threshold to the storage computing unit includes: Map the first operator whose operation attribute value is less than or equal to the operation attribute threshold to the storage computing unit; The step of mapping operators whose operational attribute values ​​are greater than the operational attribute threshold to processing cores in the many-core system includes: The first operator whose operational attribute value is greater than the operational attribute threshold is mapped to the processing core in the many-core system.

3. The method according to claim 1, characterized in that, The plurality of operators includes a second operator, the computing power resource requirement of the second operator meeting a second preset threshold condition; wherein the second preset threshold condition includes: the computing power resource requirement of the second operator is greater than the computing power resource available from the processing cores in the many-core system, and / or, the ratio of the computing power resource requirement of the second operator to the sum of the computing power resource requirements of all operators in the neural network is greater than a predetermined proportion threshold; the method further includes: The second operator is mapped to multiple processing cores in the many-core system so that the corresponding processing cores execute the second operator.

4. The method according to claim 1, characterized in that, The step of mapping operators whose operational attribute values ​​are greater than the operational attribute threshold to processing cores in the many-core system includes: The first operator whose operation attribute value is greater than the operation attribute threshold is mapped to any processing core in the many-core system.

5. The method according to any one of claims 1-4, characterized in that, The computational attribute values ​​include at least one of the following: computational load, computational power consumption, and computation time; The computational attribute threshold includes at least one of the following: computational amount threshold, computational power consumption threshold, and computation time threshold corresponding to the computational attribute value; The storage computing unit on the on-chip network is a memory array; the memory array includes at least one of resistive random access memory (RRAM) array, phase change random access memory (PCRAM) array, and magnetic random access memory (MRAM) array.

6. A network mapping device based on a many-core system, characterized in that, The many-core system includes multiple processing cores, which are interconnected via an on-chip network. The on-chip network includes a storage and computing unit, comprising: The attribute value determination module is used to determine the operational attribute value of each operator among multiple operators in the neural network to be mapped; The first mapping module is used to map operators whose operation attribute values ​​are less than or equal to the operation attribute threshold to the storage computing unit; The second mapping module is used to map operators whose operation attribute values ​​are greater than the operation attribute threshold to the processing cores in the many-core system. The many-core system uses the network mapping method as described in any one of claims 1-5 to perform the mapping of the operator.

7. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores one or more computer programs that can be executed by the at least one processor, the one or more computer programs being executed by the at least one processor to enable the at least one processor to perform the network mapping method as described in any one of claims 1-5.

8. A many-core system, characterized in that, include: Multiple processing cores, an on-chip network, and multiple storage computing units located on the on-chip network; The on-chip network is configured to interact with data between the multiple processing cores and external data; The processing core is configured to receive and execute operators whose operation attribute values ​​are greater than the operation attribute threshold; The storage computing unit is configured to receive and execute operators whose operation attribute values ​​are less than or equal to the operation attribute threshold; The many-core system is used to execute the network mapping method as described in any one of claims 1-5.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the network mapping method as described in any one of claims 1-5.

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