Voltage distribution reference voltage-based voltage binning calibration

Abstract

This application relates to voltage bin calibration based on a voltage distribution reference voltage. A current memory access voltage distribution is measured for a memory page of a block family associated with a first voltage bin of a plurality of voltage bins at a memory device. The first voltage bin is associated with a first voltage offset. A current value of a reference voltage is determined based on the current memory access voltage distribution measured for the memory page. A voltage shift amount for the memory page is determined based on the current value of the reference voltage and a previous value of the reference voltage. The previous value of the reference voltage is associated with a previous memory access voltage distribution of the memory page. In response to determining that the voltage shift amount satisfies a voltage shift criterion, the block family is associated with a second voltage bin of the plurality of voltage bins. The second voltage bin is associated with a second voltage offset.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory subsystems, and more specifically, to voltage grading calibration based on a voltage distribution reference voltage. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Typically, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] According to an aspect of this application, a method is provided. The method includes: measuring a current memory access voltage distribution of memory pages of a block family associated with a first voltage segment of a plurality of voltage segments at a memory device, wherein the first voltage segment is associated with a first voltage offset; determining a current value of a reference voltage based on the current memory access voltage distribution measured for the memory page; determining a voltage shift amount of the memory page based on the current value of the reference voltage and a previous value of the reference voltage, wherein the previous value of the reference voltage is associated with a previous memory access voltage distribution for the memory page; and in response to determining that the voltage shift amount satisfies a voltage shift criterion, associating the block family with a second voltage segment of the plurality of voltage segments, wherein the second voltage segment is associated with a second voltage offset.

[0004] According to another aspect of this application, a system is provided. The system includes: a memory device associated with a plurality of voltage gradations, each voltage gradation corresponding to a specific voltage offset; and a processing device coupled to the memory device, the processing device performing operations including: applying a programming voltage to a first plurality of memory cells of the memory device to program a first memory page of a block family; determining a memory access voltage distribution offset of the block family based on the programming voltage and a first memory access voltage associated with one or more of the first memory cells, wherein each of the one or more first memory cells is associated with a specific quantile of the first memory access voltage distribution of the first memory page; determining a second memory access voltage associated with one or more of the second memory cells of a second plurality of memory cells of the second memory page in response to measuring a second memory access voltage distribution of a second memory page of the block family, wherein each of the one or more second memory cells is associated with the specific quantile of the second memory access voltage distribution; determining a voltage shift amount of the second memory page based on the second voltage and the memory access voltage distribution offset; and assigning the block family to a corresponding voltage gradation among the plurality of voltage gradations, taking into account the determined voltage shift amount of the second memory page.

[0005] According to another aspect of this application, a non-transitory computer-readable storage medium is provided. The non-transitory computer-readable storage medium includes instructions that, when executed by a processing device, cause the processing device to perform operations comprising the following steps: measuring a current memory access voltage distribution of memory pages of a block family associated with a first voltage segment of a plurality of voltage segments at a memory device, wherein the first voltage segment is associated with a first voltage offset; determining a current value of a reference voltage based on the current memory access voltage distribution measured for the memory pages; determining a voltage shift amount of the memory pages based on the current value of the reference voltage and a previous value of the reference voltage, wherein the previous value of the reference voltage is associated with a previous memory access voltage distribution for the memory pages; and, in response to determining that the voltage shift amount satisfies a voltage shift criterion, associating the block family with a second voltage segment of the plurality of voltage segments, wherein the second voltage segment is associated with a second voltage offset. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof. However, the drawings should not be used to limit this disclosure to the particular embodiments, but are merely for explanation and understanding.

[0007] Figure 1An instance computing system including a memory subsystem is described according to some embodiments of this disclosure.

[0008] Figure 2 According to some embodiments of this disclosure, time-voltage shift caused by slow charge loss exhibited by a three-level memory cell is illustrated.

[0009] Figure 3 Example graphs illustrating the dependence of threshold voltage offset on time since programming (i.e., the time elapsed since the block was programmed) are depicted according to some embodiments of this disclosure.

[0010] Figure 4 A set of predefined threshold voltage offset brackets is illustrated schematically according to embodiments of the present disclosure.

[0011] Figure 5 The block family management operations performed by the block family manager component are described according to embodiments of this disclosure.

[0012] Figure 6 The selection of a block family for calibration is illustrated schematically according to embodiments of this disclosure.

[0013] Figure 7 This is a flowchart of an example method for voltage grading calibration based on a voltage distribution reference voltage according to some embodiments of the present disclosure.

[0014] Figures 8A to 8B Examples of using memory access to voltage distribution reference voltage to detect voltage shift are illustrated according to some embodiments of this disclosure.

[0015] Figures 9A to 9B Another example of using a memory to access a voltage distribution reference voltage to detect voltage shift is also described according to some embodiments of this disclosure.

[0016] Figure 10 This is a flowchart of another example method for voltage grading calibration based on a voltage distribution reference voltage, according to some embodiments of this disclosure.

[0017] Figure 11 The present disclosure describes, according to embodiments, the change in the width of the memory access voltage distribution during operation of the memory device.

[0018] Figure 12 This is a block diagram of an example computer system that is operable according to an embodiment of the present disclosure. Detailed Implementation

[0019] This disclosure pertains to voltage grading calibration based on a voltage distribution reference voltage. The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. The following is combined with… Figure 1Describe examples of storage devices and memory modules. Typically, a host system may utilize a memory subsystem that includes one or more memory components (such as memory devices for storing data). The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0020] The memory subsystem may utilize one or more memory devices, comprising different types of non-volatile memory devices and / or any combination of volatile memory devices, to store data provided by the host system. In some embodiments, the non-volatile memory devices may be provided by NAND flash memory devices. The following is in conjunction with... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. Planes may be divided into logic units (LUNs). For some types of non-volatile memory devices (e.g., "NAND" devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. A "block" herein should refer to a set of contiguous or non-contiguous memory pages. An example of a "block" is an "erasable block," which is the smallest erasable unit of memory, while a "page" is the smallest writable unit of memory. Each page contains a set of memory cells. A memory cell is an electronic circuit that stores information.

[0021] Data operations can be performed by the memory subsystem. Data operations can be host-initiated operations. For example, the host system can initiate data operations (e.g., write, read, erase, etc.) on the memory subsystem. The host system can send access requests (e.g., write commands, read commands) to the memory subsystem, such as storing data on a memory device at the memory subsystem and reading data from a memory device at the memory subsystem. The data to be read or written as specified in the host request is referred to hereinafter as "host data". The host request may contain logical address information (e.g., logical block address (LBA), namespace) of the host data, which is the location associated between the host system and the host data. The logical address information (e.g., LBA, namespace) may be part of the metadata of the host data. The metadata may also include error handling data (e.g., ECC codeword, parity check code), data version (e.g., the year used to distinguish written data), a validity bitmap (which LBA or logical transfer unit contains valid data), etc.

[0022] A memory device comprises multiple memory cells, each of which may store one or more bits of information, depending on the memory cell type. A memory cell can be programmed (written) by applying a specific voltage, causing the memory cell to retain a charge, thereby allowing modulation of the voltage distribution generated by the memory cell. Furthermore, precise control of the amount of charge stored in the memory cell allows the establishment of multiple threshold voltage levels corresponding to different logic levels, thus effectively allowing a single memory cell to store multiple bits of information: with 2... n Memory cells operating at different threshold voltage levels can store n bits of information. In this paper, "threshold voltage" refers to the voltage level that defines the boundary between two adjacent voltage distributions corresponding to two logic levels. Therefore, a read operation can be performed by comparing the measured voltage presented by the memory cell with one or more reference voltage levels to distinguish between two logic levels in a single-level cell and multiple logic levels in a multi-level cell.

[0023] Due to a phenomenon known as slow charge loss, the threshold voltage of a memory cell changes over time as the cell's charge degrades; this is called "time-voltage shift" (because the degraded charge causes the voltage distribution to shift along the voltage axis toward a lower voltage level). The threshold voltage changes rapidly at first (immediately after the memory cell is programmed), and then slows down in an approximately logarithmic linear fashion with respect to the time elapsed since the cell programming event. Therefore, failure to mitigate the time-voltage shift caused by slow charge loss can lead to an increased bit error rate in read operations.

[0024] However, various common implementations fail to adequately address time-voltage shifts or employ inefficient strategies, resulting in high bit error rates and / or other drawbacks. Embodiments of this disclosure address these and other shortcomings by implementing a memory subsystem employing a block-family-based error avoidance strategy, thereby significantly improving the bit error rate exhibited by the memory subsystem.

[0025] According to embodiments of this disclosure, time-voltage shifts are selectively tracked for groups of programmable memory cells grouped by block families, and an appropriate voltage offset based on block affiliation with a particular block family is applied to a base read level to perform a read operation. As used herein, a “block family” refers to a potentially discontinuous group of memory cells programmed within a specified time window and a specified temperature window (which may reside in one or more complete and / or partial blocks, the latter referred to herein as “partitions”), and is therefore expected to exhibit similar or related changes in their corresponding data state metrics with respect to slow charge loss. Block families can be composed of any granularity, containing only entire codewords, entire pages, entire superpages, or entire superblocks, or any combination thereof. As used herein, a “data state metric” refers to a quantity measured or inferred from the state of data stored on a memory device. Specifically, a data state metric may reflect the state of time-voltage shifts, the degree of read interference, and / or other measurable functions of data state. A composite data state metric is a function (e.g., a weighted sum) of a set of component state metrics.

[0026] In these embodiments, the block family uses a polymerization temperature to experience a defined temperature range, which may be changed or defined based on a temperature metric in different embodiments. For example, in response to a timer reaching a soft closure value, the memory subsystem controller may execute a soft closure of the block family (i.e., signal the block family manager that the block is about to end and prepare for the opening time of the block family's hard closure). Alternatively, the controller may similarly execute a soft closure of the block family in response to a polymerization temperature (based on a temperature value received from a temperature sensor of the memory device) being greater than or equal to a defined threshold temperature.

[0027] After performing a soft closure, the memory subsystem can continue programming partially written blocks until a timer reaches the hard closure value or the block family meets the hard closure criterion. In this way, the memory subsystem has an extended time before the hard closure, during which the writing of partially written blocks is completed, and a decision is made whether to partition the block or write virtual data to the unwritten portion of the block after the hard closure. After a block family is hard-closed (i.e., the memory subsystem controller no longer writes data to the block family), further programming of the memory device die is for newly opened block families. Assuming wear leveling keeps blocks with similar program-erase counts, the elapsed time and temperature after programming are the main factors affecting the time voltage shift, and assuming all blocks and / or partitions within a single block family exhibit a similar distribution of threshold voltages in the memory cells, and therefore require the same voltage offset to be applied to the base read level for read operations. "Base read level" herein refers to the initial threshold voltage level exhibited by the memory cell immediately after programming. In some embodiments, the base read level may be stored in the memory device's metadata.

[0028] Block families can be created asynchronously relative to block programming events. In an illustrative example, a new block family threshold can be created whenever a specified time period (e.g., a predetermined number of minutes) has elapsed since the last block family was created, or when the reference temperature of a memory cell has changed beyond a specified threshold. The memory subsystem controller can maintain identifiers for valid block families, which are associated with one or more blocks when they are programmed.

[0029] The memory subsystem controller may periodically perform a calibration process (e.g., a calibration scan) to associate each die of each block family with one of a predefined threshold voltage offset bracket (referred to as a voltage bracket), which in turn is associated with the voltage offset to be applied to a read operation. In one embodiment, the association of a page or block with a block family, and the association of a block family and die with a voltage bracket, may be represented by metadata stored in a corresponding metadata table maintained by the memory subsystem controller.

[0030] Even when the memory device is powered off, the threshold voltage of each memory cell can continue to shift. Depending on the duration of the power outage, the time voltage shift for each block family can be significant. Therefore, when the memory device is powered back on, the block family classification stored in the corresponding metadata table before the power outage may be inaccurate. In some cases, the memory subsystem does not have a timer or clock to track the duration of the memory device power outage. Therefore, when the memory device is powered back on, the memory subsystem controller is unaware of the duration of the power outage and thus unaware of the time voltage shift that occurred for each block family. Consequently, the memory subsystem controller cannot adjust the voltage classification of the block family without calibrating at least some pages or blocks.

[0031] The memory subsystem controller can periodically perform scans of the memory device to calibrate the threshold voltage offset to be applied to each block family (referred to as a calibration scan). In some instances, the memory subsystem controller can perform a calibration scan by executing a set of read operations against a block family using a voltage offset associated with each voltage level of the memory device. The memory subsystem controller can identify previously executed read operations that resulted in optimal data state metrics (e.g., minimum bit error rate, which is the number of received bits that changed due to errors at the memory subsystem) and determine the voltage offset applied to the identified read operations. In one instance, the memory subsystem controller can perform a calibration scan on each block of each block family on each die of the memory device. Since the memory device can contain hundreds or sometimes thousands of pages or blocks, periodically performing a full scan of the memory device can be time-consuming and consume significant system resources.

[0032] This disclosure addresses the aforementioned and other deficiencies by calibrating voltage gradations at a memory device based on voltage shifts detected using a reference voltage for memory access voltage distributions (i.e., threshold voltage distributions). The reference voltage may correspond to a specific point (e.g., the tail) or a specific quantile (e.g., the 50th percentile) of the voltage distribution of a corresponding logic level of a memory cell at the memory device. Immediately or shortly after a block family is programmed, memory pages of the block family may be associated with a specific memory access voltage distribution (referred to as the previous memory access voltage distribution). In one example, the reference voltage may correspond to the voltage of a memory cell at the tail of the voltage distribution. The memory access voltage of the memory cell associated with the tail of the previous memory access voltage distribution may approximately correspond to the threshold voltage (referred to as the programming voltage) used by the memory subsystem controller to program data into the memory cell. Thus, the reference voltage value associated with the previous memory access voltage distribution (referred to as the previous value of the reference voltage) corresponds to the programming voltage of the memory cell. In another example, the reference voltage may correspond to the voltage of a memory cell at a specific quantile (e.g., the 50th percentile) of the voltage distribution.

[0033] During operation of the memory device, the memory subsystem controller measures the memory access voltage distribution (referred to as the current memory access voltage distribution) of the memory cells of the memory pages of a block. The memory subsystem controller determines a current value of a reference voltage based on the current memory access voltage distribution and compares the current value with a previous value of the reference voltage. For example, the memory subsystem controller can determine the difference between the current voltage of a memory cell associated with a specific point (e.g., the tail end) or a specific quantile (e.g., the 50th percentile) of the current memory access voltage distribution and the previous value of the corresponding point or quantile of a memory cell associated with a previous memory access voltage distribution. The difference between the current and previous values ​​of the reference voltage corresponds to the amount of voltage shift in the block since the memory subsystem controller programmed the memory pages of the block, either immediately or shortly thereafter. The voltage shift may depend on the amount of time elapsed since the memory subsystem controller programmed the memory pages, temperature changes since the programming time, and / or the number of program / erase (PE) cycles performed on the memory. The controlled memory subsystem can associate the block with an appropriate voltage band corresponding to the determined voltage shift amount.

[0034] The advantages of this disclosure include, but are not limited to, reducing the amount of memory subsystem resources consumed during calibration scans of the memory device. Instead of performing read operations at hundreds or thousands of pages or blocks to determine the appropriate voltage offset for each block family, the memory subsystem controller can detect the amount of voltage shift of a block family of memory pages based on the difference between the current value and a previous value of a reference voltage associated with the voltage distribution measured for the memory pages. By performing a single measurement operation on a memory page instead of multiple read operations on hundreds or thousands of pages or blocks, a significant amount of memory subsystem resources can be used for other processes at the memory subsystem. Therefore, the overall efficiency of the memory subsystem is improved and the overall latency of the memory subsystem is reduced. Furthermore, by using the programming voltage of the memory cell to determine the previous value of the reference voltage, the memory subsystem controller does not measure the voltage distribution of the memory pages immediately or shortly after programming. Memory subsystem resources can therefore be allocated to perform memory access operations on host data, which improves the overall performance of the memory subsystem (e.g., efficiency, latency, throughput, etc.).

[0035] Figure 1 An example computing system 100 including a memory subsystem 110 is described according to some embodiments of this disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0036] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0037] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transportation), Internet of Things (IoT) enabled device, embedded computer (e.g., computer contained in a vehicle, industrial equipment or networked commercial device), or such computing device containing memory and processing devices.

[0038] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intermediate components), whether wired or wireless, and includes, for example, electrical, optical, magnetic, and other connections.

[0039] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120, for example, uses memory subsystem 110 to write data to and read data from memory subsystem 110.

[0040] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Bus Accessory (SATA) interfaces, PCIe interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Double Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM socket interfaces supporting DDR), etc. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize a high-speed NVM (NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Typically, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0041] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0042] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and in-situ write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory cells can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash memory-based memories, crosspoint non-volatile memory can perform in-situ write operations, where non-volatile memory cells can be programmed without pre-erasing them. For example, NAND-type flash memory includes two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0043] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include SLC portions and MLC portions, TLC portions, QLC portions, or PLC portions of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0044] Although non-volatile memory components, such as 3D cross-point arrays of non-volatile memory cells and NAND-type flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0045] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include, for example, hardware of one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0046] The memory subsystem controller 115 may include processing means configured to execute instructions stored in local memory 119, such as one or more processors (processors 117). In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0047] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0048] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to enable desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry translates commands received from the host system into command instructions to access the memory device 130 and translates responses associated with the memory device 130 into information for the host system 120.

[0049] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0050] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that is the original memory device 130, having on-die control logic (e.g., local controller 132) and a controller for media management (e.g., memory subsystem controller 115) within the same memory device package. An example of a managed memory device is a managed NAND device.

[0051] Memory subsystem 110 includes block family manager component 113, which can select threshold voltage offset brackets (referred to as voltage brackets or brackets) to associate with block families at a memory device. In some embodiments, memory subsystem controller 115 includes at least a portion of block family manager component 113. For example, memory subsystem controller 115 may include processor 117 (processing device) configured to execute instructions stored in local memory 119 to perform the operations described herein. In some embodiments, block family manager component 113 is part of host system 110, an application, or an operating system. Further details regarding block families and block family manager component 113 are described below.

[0052] Figure 2 According to some embodiments of this disclosure, time-voltage shift caused by slow charge loss exhibited by a three-level memory cell is illustrated. Although Figure 2 The illustrative example uses a three-level cell, but the same observations can be made, and therefore the same remedy applies to single-level cells, multi-level cells, and any other fractional or integer bits / cell (e.g., 3.5 bits / cell, etc.) to compensate for slow charge loss.

[0053] As mentioned above, a memory cell can be programmed (written) by applying a specific voltage, causing the memory cell to retain a charge, thus allowing modulation of the voltage distribution generated by the memory cell. Precise control of the amount of charge stored in the memory cell allows for the establishment of multiple threshold voltage levels corresponding to different logic levels, thus effectively allowing a single memory cell to store multiple bits of information: with 2... n Memory cells operating at different threshold voltage levels can store n bits of information.

[0054] exist Figure 2 In the diagram, each graph 220A to 220N illustrates the voltage distribution generated by a memory cell programmed with a corresponding write level (which may be assumed to be located at the midpoint of the distribution) to encode a corresponding logic level (e.g., "000" to "111" in the case of TLC). To distinguish adjacent distributions (corresponding to two different logic levels), a read threshold voltage level (shown by a vertical dashed line) is defined such that any measured voltage falling below the threshold level is associated with one of the pair of adjacent distributions, while any measured voltage greater than or equal to the threshold level is associated with the other of the pair of adjacent distributions.

[0055] As can be seen from comparative examples Graphs 210 and 230 (which respectively reflect the time period immediately following programming and the corresponding number of hours following programming), the voltage distribution changes over time due to slow charge loss, resulting in a drift in the read threshold voltage level (shown by the vertical dashed line). In various embodiments of this disclosure, time-shifted voltage is selectively tracked for programmed pages or blocks grouped by block family, and an appropriate voltage offset based on the page or block dependency of a particular block family is applied to the base read level to perform a read operation.

[0056] Figure 3 Example graphs illustrating the dependence of threshold voltage offset on time since programming (i.e., the time elapsed since the page was programmed) are depicted according to some embodiments of this disclosure. Figure 3 To illustrate, the memory device's block families are grouped into subclasses 330A to 330N, such that each block family contains one or more pages or blocks that have been programmed within a specified time window and a specified temperature window. As described above, the elapsed time and temperature since programming are the primary factors affecting time-voltage shift; therefore, it is assumed that all pages, blocks, and / or partitions within a single block family 310 exhibit similar threshold voltage distributions in the memory cells, and thus require the same voltage change for read operations.

[0057] Block families can be created asynchronously relative to page programming events. In an illustrative example, block families are created whenever a specified time period (e.g., a predetermined number of minutes) has elapsed since the creation of the last block family, or whenever the reference temperature of a memory cell updated at specified time intervals has changed more than a specified threshold since the creation of the current block family. Figure 1 The memory subsystem controller 115 can create new block families.

[0058] Newly created block families can be associated with specific partitions (e.g., partition 0, partition 1, etc.). The memory subsystem controller can then periodically perform a calibration process to associate each die in each block family with a predefined voltage partition (…). Figure 3 The predefined voltage level is associated with one of the voltage levels (0 to 7) in the illustrative example, and this predefined voltage level is in turn associated with the voltage offset to be applied to the read operation. The association between blocks and block families, as well as between block families and dies and voltage levels, can be stored in the corresponding metadata tables maintained by the memory subsystem controller.

[0059] Figure 4 A set of predefined threshold voltage offset brackets (referred to herein as voltage brackets or brackets) is illustrated schematically according to embodiments of this disclosure. Figure 4 To illustrate, the threshold voltage offset curve can be subdivided into multiple voltage increments, such that each voltage increment corresponds to a predetermined range of threshold voltage offset. Although Figure 4The illustrative example defines ten voltage levels for a single valley value, but in other implementations, various other numbers of voltage levels may be used.

[0060] Based on a periodically executed calibration process, the memory subsystem controller can associate each die of each block family with a voltage band. The calibration process defines a set of threshold voltage offsets that are applied to a base voltage read level to perform a read operation. In some embodiments, the calibration process involves performing read operations with different threshold voltage offsets relative to a predetermined number of randomly selected pages or blocks within the block being calibrated, and selecting a threshold voltage offset that minimizes the bit error rate (e.g., bit error rate) of the read operation. In other or similar embodiments, the calibration process involves sampling the memory pages of the block family (i.e., measuring the access voltage distribution of memory cells in the memory pages) and determining the amount of voltage distribution shifted from the access voltage distribution of the block family immediately or shortly after programming. Regarding Figure 7 and 10 Further details regarding the calibration process are provided.

[0061] Figure 5 The block family management operation performed by the block family manager component 113 of the memory subsystem controller 115 is illustrated schematically according to embodiments of this disclosure. Figure 5 As an illustration, the block family manager component 113 may maintain an identifier 520 for a valid block family in a memory variable, which is associated with one or more pages or blocks of the cursor when the cursors 530A to 530K are programmed. The term "cursor" should be broadly referred to herein as the location on the memory device where data is being written.

[0062] The memory subsystem controller can utilize a power-on minute (POM) clock to track the creation time of block families. In some implementations, in addition to the POM clock, a less accurate clock that continues to operate while the controller is in various low-power states can be used, allowing the POM clock to be updated based on the less accurate clock when the controller wakes up from a low-power state.

[0063] Therefore, when initializing each block family, the block family manager component 113 stores the current time 540 in a memory variable as the block family start time 550. When a page or block is programmed, the block family manager component 113 compares the current time 540 with the block family start time 550. In response to detecting that the difference between the current time 540 and the block family start time 550 is greater than or equal to a specified time period (e.g., a predetermined number of minutes), the block family manager component 113 updates the valid memory variable, the block family identifier 520, to store the next block family number (e.g., the next consecutive integer), and the memory variable storing the block family start time 550 is updated to store the current time 540.

[0064] The block family manager component 113 also maintains two memory variables to store the high and low reference temperatures of selected dies for each memory device. Upon initialization of each block family, the high-temperature variable 560 and the low-temperature variable 570 store the current temperature value of the selected die of the memory device. During operation, while the valid block family identifier 520 remains constant, temperature measurements are periodically obtained and compared with the stored high-temperature value 560 and low-temperature value 570, which are updated accordingly: if a temperature measurement is found to be greater than or equal to the value stored by the high-temperature variable 560, the latter is updated to store the temperature measurement; conversely, if a temperature measurement is found to have decreased below the value stored by the low-temperature variable 570, the latter is updated to store the temperature measurement.

[0065] Block family manager component 113 can further periodically calculate the difference between high temperature 560 and low temperature 570. In response to determining that the difference between high temperature 560 and low temperature 570 is greater than or equal to a specified temperature threshold, block family manager component 113 can close an existing block family and create a new valid block family: the memory variable storing the valid block family identifier 520 is updated to store the next block family number (e.g., the next consecutive integer), the memory variable storing the block family start time 550 is updated to store the current time 540, and the high temperature variable 560 and low temperature variable 570 are updated to store the current temperature value of the selected die of the memory device. When programming a block, block family manager component 113 associates the block with the currently valid block family. The association of each block with its corresponding block family is reflected in block family metadata 580.

[0066] As previously described, based on a periodically performed calibration process (e.g., calibration scan), the block family manager component 113 associates each die of each block family with a voltage band that defines a set of threshold voltage offsets to be applied to a reference voltage read level to perform a read operation. In some embodiments, the calibration process involves sampling memory cells of memory pages of the block family to measure the current memory access voltage distribution of the memory pages (referred to herein as the current voltage distribution). In some embodiments, the current voltage distribution may correspond to an average distribution of a set of sampled memory cells. In other or similar embodiments, the current voltage distribution may be a different aggregate metric. The block family manager component 113 may determine a current value of a reference voltage based on the current voltage distribution and compare the current value of the reference voltage with a previous value of the reference voltage. The previous value of the reference voltage is associated with a previous memory access voltage distribution of the block family (referred to as the previous voltage distribution) at a time instance prior to measuring the current memory access voltage distribution of the memory pages (e.g., when data on the memory pages is programmed at the memory device). Block family manager component 113 uses the current and previous values ​​of a reference voltage to determine the amount of voltage shift in the block family since the time instance associated with the previous reference value. The determined voltage shift may correspond to a previously determined threshold voltage offset (e.g., based on experimental data) to minimize the bit error rate of operations such as read operations performed on the block family. Block family manager 113 may determine a specific voltage band corresponding to the threshold voltage offset and update the block family's metadata to correspond to the determined voltage band.

[0067] In some embodiments, the frequency at which the memory subsystem controller performs a calibration process for each voltage band may be based on the age of the block family associated with the voltage band. (As previously mentioned...) Figure 3 As described, newly created block families can be associated with voltage class 0, and older block families on the memory device can be associated with subsequently numbered voltage classes. The time-voltage shift of block families in newer voltage classes is faster than the time-voltage shift of block families associated with older voltage classes. Figure 4 The explanation is that because the voltage offset of voltage band 0 shifts at a faster rate than the voltage offset of older voltage bands (e.g., voltage bands 9, 8, 7, etc.), the memory subsystem controller can perform the calibration process for the blocks associated with voltage band 0 at a higher frequency than for the blocks associated with voltage band 9, in order to associate each block with the appropriate voltage band.

[0068] Figure 6According to embodiments of this disclosure, the selection of block families for calibration is illustrated. Due to slow charge loss, the oldest block family in a voltage bracket will migrate to the next voltage bracket before any other block family in the current bracket. Thus, the memory subsystem controller can restrict the calibration operation to the oldest block family in the bracket (e.g., block family 610 in bracket 0 and block family 620 in bracket 1). In some embodiments, the memory subsystem controller can identify the oldest block family in a voltage bracket based on bracket boundaries. A bracket boundary may represent the boundary between two adjacent block families, each associated with a different bracket. The memory subsystem controller can use a block family metadata table to identify bracket boundaries for a specific voltage bracket.

[0069] Return to reference Figure 1 Taking into account the amount of time-varying voltage shift, the block family manager component 113 can be configured to periodically calibrate memory devices 130, 140 to associate blocks with appropriate voltage gradations. A block family can be associated with a first voltage distribution during a first time period (e.g., immediately or shortly after data is programmed or written to a memory page of the block family). According to some embodiments of this disclosure, the first voltage distribution is referred to as a previous memory access voltage distribution. In some embodiments, the block family manager component 113 can obtain the first voltage distribution by measuring one or more memory pages of the block family during the first time period. In other or similar embodiments, the block family manager component 113 can determine the first voltage distribution based on experimental or manufacturing data obtained for the memory device (e.g., before or during installation and / or initialization of the memory device at the memory subsystem). A first value of a reference voltage (also referred to herein as a previous value) can be determined based on the first voltage distribution. The reference voltage refers to the voltage at a specific point (e.g., the tail end) or a specific quantile (e.g., the 50th quantile, the 25th quantile, etc.) of the voltage distribution. In some embodiments, the voltage at the quantile associated with the highest amount of slow charge loss can be selected as the reference voltage.

[0070] In a second time period following the first time period, the block family manager component 113 can perform a calibration scan on the block family by measuring one or more memory pages to obtain a second voltage distribution. According to some embodiments of this disclosure, the second voltage distribution is referred to as the current voltage distribution. The block family manager component 113 can compare a second value of a reference voltage (also referred to herein as the current value) with a first value of the reference voltage to determine the amount of time voltage shift of the block family since the first time period. The block family manager component 113 can associate the block family with an appropriate voltage bracket associated with a time voltage offset corresponding to the determined amount of time voltage shift. Figures 7 to 11 Further details regarding the calibration process are provided.

[0071] Figure 7This is a flowchart of an example method 700 for voltage grading calibration based on a voltage distribution reference voltage according to some embodiments of the present disclosure. Method 700 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 700 is performed by… Figure 1 The block family manager component 113 performs the operation. In other or similar embodiments, one or more operations of method 700 are performed by another component of the memory subsystem controller (e.g., the block family manager). Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0072] At block 710, processing logic measures the current voltage distribution of the memory pages of a block family. In some embodiments, the block family is associated with a first voltage bracket, which is associated with a first voltage offset at the memory device. According to some embodiments, the processing logic may measure the current voltage distribution of the memory pages in response to determining a block family to be calibrated. For example, the processing logic may determine to calibrate a block family in response to determining that a corresponding threshold criterion has been met. In one embodiment, the processing logic determines that the threshold criterion is met when a threshold number of programming and erasing operations have been performed for the block family and / or the memory device (i.e., a threshold number of program / erase (P / E) cycles have occurred). In some embodiments, the processing logic may select memory pages of a block family for measurement according to a calibration strategy associated with the memory device. In other or similar embodiments, the processing logic may select memory pages of a block family for measurement due to random memory page selection operations performed during the calibration process.

[0073] The processing logic can measure the current voltage distribution of a memory page by sampling the memory page to determine the memory access voltage associated with one or more cells of the memory page. In some embodiments, the processing logic can measure the voltage distribution by sampling each memory cell of the memory page. In other or similar embodiments, the processing logic can measure the voltage distribution by sampling a subgroup of memory cells of the memory page (i.e., fewer than all memory cells of the memory page). The current voltage distribution can represent the difference between the memory access voltages of the cells of the memory page during the time period in which the block family's measurement values ​​were obtained.

[0074] Figure 8A and 9AThe embodiments of this disclosure illustrate the current voltage distribution 810, 820 measured for a memory page. (See also: Regarding...) Figure 2 As described, memory cells can be programmed to encode corresponding logic levels via appropriate write levels. In one example, voltage distributions 810 and 820 can be measured during a sampling operation performed on a TLC memory cell of a memory page. In such an example, voltage distribution 820 may correspond to the voltage distribution of the highest logic level (e.g., "111") associated with the TLC memory cell, and voltage distribution 810 may correspond to the voltage distribution of the second highest logic level (e.g., "110") associated with the TLC memory cell.

[0075] Return to reference Figure 7 At block 720, the processing logic determines the current value of the reference voltage based on the current voltage distribution measured for the memory page. As described above, the reference voltage refers to the voltage at a specific point (e.g., the tail end of the distribution) or a specific quantile (e.g., the 50th quantile, the 25th quantile, etc.) of the voltage distribution. In some embodiments, the reference voltage may be defined for the memory device before or during initialization of the memory device (e.g., by the memory device operator or programmer). In other or similar embodiments, the reference voltage may be selected taking into account performance metrics associated with the block family and / or the memory device (e.g., bit error rate), as described in further detail below.

[0076] As described above, in some embodiments, the reference voltage may correspond to the voltage at a specific point in the voltage distribution. For example, the reference voltage may correspond to the tail end of the voltage distribution. Figure 8A As explained, voltage 812 may correspond to the voltage measured at the end of voltage distribution 810, and voltage 822 may correspond to the voltage measured at the end of voltage distribution 822. Thus, the current value of voltage 822 may be the current value of a reference voltage associated with the highest logic level of the TLC memory cell of the memory page. Similarly, the current value of voltage 812 may be the current value of a reference voltage associated with the second highest logic level of the TLC memory cell of the memory page.

[0077] In other or similar embodiments, the reference voltage may correspond to the voltage at a specific quantile of the voltage distribution. For example, the reference voltage may correspond to the 50th quantile of the voltage distribution. Figure 9AAs described, voltage 910 may correspond to the voltage measured at the 50th percentile of voltage distribution 810, and voltage 920 may correspond to the voltage measured at the 50th percentile of voltage distribution 820. Thus, the current value of voltage 920 may be the current value of a reference voltage associated with the highest logic level of the TLC memory cell of the memory page. Similarly, the current value of voltage 910 may be the current value of a reference voltage associated with the second highest logic level of the TLC memory cell of the memory page. It should be noted that although some embodiments and examples of this disclosure mention processing logic using the 50th percentile of the voltage distribution as a reference voltage (e.g., block family manager component 113), the processing logic may use any percentile of the voltage distribution as a reference voltage. For example, the processing logic may use the 25th percentile, 30th percentile, 40th percentile, 75th percentile, etc., of the voltage distribution as a reference voltage.

[0078] Return to reference Figure 7 In block 730, the processing logic determines the voltage shift amount of the memory page based on the current value and a previous value of the reference voltage. The previous value of the reference voltage may be associated with the voltage distribution of the memory page over a period of time prior to the current memory access voltage distribution of the memory page measured by the processing logic at block 710 (i.e., the previous voltage distribution). In some embodiments, the previous voltage distribution may correspond to the voltage distribution of the memory page immediately or shortly after data of the memory page and / or block family is programmed (i.e., written) to the memory device. In other or similar embodiments, the previous voltage distribution may correspond to the voltage distribution at any time prior to the current voltage distribution of the memory page measured by the processing logic.

[0079] Figure 8B and 9B According to embodiments of this disclosure, a previous voltage distribution 860, 870 for a memory page is described. In some embodiments, the previous voltage distribution 860, 870 may be specific to each memory page of each block family at a memory device. In other or similar embodiments, the previous voltage distribution 860, 870 may be specific to each block family at a memory device. For example, processing logic may associate the previous voltage distribution 860, 870 with a specific block family, and therefore, each memory page of the block family is thus associated with the previous voltage distribution 860, 870. It should be noted that although some embodiments and examples of this disclosure refer to the previous voltage distribution 860, 870 associated with a memory page measured at block 710, the previous memory distribution 860, 870 may be associated with a group of memory pages of any granularity (e.g., block family, voltage band, memory device, etc.).

[0080] According to the previously described embodiments and examples, the previous voltage distributions 860 and 870 may each correspond to the voltage distributions of different logic levels of the memory cells of the memory page. For example, voltage distribution 870 may correspond to the previous voltage distribution of the highest logic level associated with the memory cell (e.g., a TLC memory cell), and voltage distribution 860 may correspond to the previous voltage distribution of the second highest logic level associated with the memory cell.

[0081] Considering the previous voltage distributions 860, 870 associated with the memory page, the processing logic can determine the previous value of the reference voltage. As described above, the reference voltage may correspond to the voltage at a specific point in the voltage distribution. For example, the reference voltage may correspond to the voltage at the tail end of the voltage distribution. In some embodiments, the voltage at the tail end of the previous voltage distribution may correspond to the voltage applied to the memory cell (referred to as the programming voltage or write voltage) during a programming operation performed by the memory subsystem controller 115 to write data to the memory page. Figure 8B As explained, voltage 872 corresponds to the programming voltage (also known as the programming verification (PV) voltage) used by the memory subsystem controller 115 to program data at the highest logic level at the memory cell of the memory page (e.g., the PV voltage of level 7 for a TLC memory cell). Voltage 874 corresponds to the voltage associated with the tail end of the voltage distribution 870 for a period of time immediately or shortly after programming the memory page. Figure 8B As seen, the value of voltage 874 approximately corresponds to the value of voltage 872. Since the value of voltage 874 approximately corresponds to the value of voltage 872, the processing logic can use the programming voltage of the highest logic level of the memory cell in the memory page as a reference voltage. Therefore, the processing logic can determine that the previous value of the reference voltage of the highest logic level of the memory cell in the memory page corresponds to voltage 872.

[0082] Voltage 862 corresponds to the programming voltage (i.e., the PV voltage) used by the memory subsystem controller 115 to program data at a second highest logic level at a memory cell of a memory page (e.g., the PV voltage of level 6 of a TLC memory cell). Voltage 864 corresponds to the voltage associated with the tail end of the voltage distribution 860 for a period of time immediately or shortly after the memory is programmed. Since the value of voltage 864 approximately corresponds to the value of voltage 862, the processing logic can similarly use the programming voltage of the highest logic level of the memory cell of the memory page as a reference voltage. Therefore, the processing logic can determine that the previous value of the reference voltage of the second highest logic level of the memory cell of the memory page corresponds to voltage 862.

[0083] By using the programming voltage as a prior value of the reference voltage for voltage distributions 860, 870, the processing logic can determine the prior value of the reference voltage without measuring the voltage distribution of the memory pages immediately or shortly after programming. For example, immediately or shortly after programming, the processing logic can store an indication of the voltage used to program the memory pages in the memory of the memory subsystem controller 115 (e.g., local memory 119). According to the embodiments described herein, during a calibration scan, the processing logic can access the memory of the memory subsystem controller 115 to determine the programming voltage of the memory pages and use said programming voltage as a prior value of the reference voltage.

[0084] As described above, the processing logic can determine the voltage shift amount of the memory page based on the current value and the previous value of the reference voltage. Figure 8A The processing logic can determine the voltage shift amount 878 of voltage distribution 820 based on the difference between voltage 822 (i.e., the current value of the reference voltage associated with the highest logic memory cell level) and voltage 872 (i.e., the previous value of the reference voltage associated with the highest logic memory cell level). Similarly, the processing logic can determine the voltage shift amount 868 of voltage distribution 810 based on the difference between voltage 812 (i.e., the current value of the reference voltage associated with the second highest logic memory cell level) and voltage 862 (i.e., the previous value of the reference voltage associated with the second highest logic memory cell level).

[0085] In other or similar embodiments, the reference voltage of the voltage distribution may correspond to the voltage at a specific quantile of the voltage distribution. For example, the reference voltage may correspond to the voltage at the 50th quantile of the voltage distribution. In such instances, the processing logic may determine a previous value of the reference voltage based on an offset representing the difference between the voltage at the tail end of the voltage distribution and the voltage at the 50th quantile of the voltage distribution immediately or shortly after programming a memory page. As described above, the voltage at the tail end of the voltage distribution may approximately correspond to the programming voltage associated with programming a memory cell at the corresponding logic level. For example, as in Figure 9B As explained, voltage 872 may correspond to the programming voltage associated with programming the memory cell at the highest logic level, and voltage 862 may correspond to the programming voltage associated with programming the memory cell at the second highest logic level.

[0086] In some embodiments, the processing logic may determine the voltage at the 50th percentile of the voltage distribution based on experimental and / or manufacturing data collected for the memory device. For example, experimental and / or manufacturing data may be collected for the memory device before it is installed or initialized at a memory subsystem (e.g., at a memory device manufacturing system, a memory device testing system, etc.). The experimental and / or manufacturing data collected for the memory device may correspond to the voltage distribution of a memory page immediately or shortly after each logic level is programmed into a memory cell of the memory device. Thus, for each logic level, the experimental and / or manufacturing data may indicate the voltage at the tail end of the voltage distribution and the voltage at the 50th percentile of the voltage distribution immediately or shortly after the memory page is programmed. In some embodiments, the operator of the testing system and / or manufacturing system may store the experimental and / or manufacturing data collected for the memory device into a memory (e.g., local memory 119) associated with the memory subsystem controller 115. In such embodiments, the processing logic may determine, for each logic level, the difference between the voltage at the tail end of the voltage distribution and the voltage at the 50th percentile of the voltage distribution (referred to as the voltage distribution offset). In other or similar embodiments, the operator may store the voltage distribution offset of each logic level in a memory associated with the memory subsystem controller 115.

[0087] The processing logic can determine the previous value of the reference voltage for the corresponding logic level of the memory cell based on the programming voltage associated with the corresponding logic level and the voltage distribution offset of the corresponding logic level. For example, in Figure 9B As explained, voltage 922 may correspond to the voltage at the 50th percentile of voltage distribution 870. The processing logic may determine the value of voltage 922 based on voltage 872 (i.e., the programming voltage associated with the highest logic level of the memory cell in the memory page) and the voltage distribution offset of the highest logic level of the memory cell. Voltage 912 may correspond to the voltage at the 50th percentile of voltage distribution 860. The processing logic may determine the value of voltage 912 based on voltage 862 (i.e., the programming voltage associated with the second highest logic level of the memory cell in the memory page) and the voltage distribution offset of the second highest logic level of the memory cell. Therefore, the processing logic can use the values ​​of voltages 912 and 922 as previous values ​​of reference voltages without needing to measure the voltage distribution of the memory page immediately or shortly after programming at the memory device.

[0088] refer to Figure 9AThe processing logic can determine the voltage shift amount 924 of voltage distribution 820 based on the difference between voltage 920 (i.e., the current value of the reference voltage associated with the highest logic memory cell level) and voltage 922 (i.e., the previous value of the reference voltage associated with the highest logic memory cell level). Similarly, the processing logic can determine the voltage shift amount 914 of voltage distribution 810 based on the difference between voltage 910 (i.e., the current value of the reference voltage associated with the second highest logic memory cell level) and voltage 912 (i.e., the previous value of the reference voltage associated with the second highest logic memory cell level).

[0089] Return to reference Figure 7 In block 740, the processing logic determines whether the voltage shift amount of a memory page satisfies a voltage shift criterion. In some embodiments, the processing logic determines that the memory page satisfies the voltage shift criterion in response to determining that the voltage shift amount determined in block 730 satisfies or exceeds a threshold voltage shift amount. Similarly, the processing logic may determine that the memory page does not satisfy the voltage shift criterion in response to determining that the voltage shift amount does not exceed a threshold voltage shift amount. In response to determining that the voltage shift amount does not satisfy the voltage shift criterion, method 700 continues to block 750, where the processing logic associates a block family with a first voltage bracket at the memory device. In response to determining that the voltage shift amount satisfies the voltage shift criterion, method 700 continues to block 760. In block 760, the processing logic associates a block family with a second voltage bracket at the memory device associated with a second voltage offset. In some embodiments, the processing logic may associate a block family with a second voltage bracket by updating pointers to voltage bracket boundaries of the second voltage bracket, as previously described. For example, the processing logic can update the metadata table of a block family containing memory pages to indicate that the pointers used for the second voltage bracket correspond to the block family.

[0090] In some embodiments, the processing logic may modify the reference voltage from a first type to a second type during operation of the memory subsystem. For example, the processing logic may use a voltage associated with the tail end of a voltage distribution as the reference voltage. During operation of the memory subsystem 110, the processing logic may monitor the execution of operations at each family of blocks in the memory device and maintain a performance metric (e.g., bit error rate) for each family of blocks. In some embodiments, the processing logic may determine that the performance metric of a family of blocks meets a performance criterion (e.g., drops below a performance metric threshold). In such embodiments, according to the previously described embodiments, the processing logic may use a voltage associated with a specific quantile (e.g., the 50th percentile) of the voltage distribution as the reference voltage.

[0091] Figure 10This is a flowchart of another example method 1000 for voltage grading calibration based on a voltage distribution reference voltage, according to some embodiments of this disclosure. Method 1000 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 1000 is performed by… Figure 1 The block family manager component 113 performs the operation. In other or similar embodiments, one or more operations of method 1000 are performed by another component of the memory subsystem controller (e.g., the block family manager). Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0092] In block 1010, the processing logic applies a programming voltage to a first set of memory cells of the memory device to program a first memory page of the block family. The processing logic applies the programming voltage to the first set of memory cells in response to determining that a memory access voltage distribution offset calibration criterion is met. In some embodiments, the processing logic may determine that the voltage distribution offset calibration criterion is met in response to determining that an amount of time since the memory device was initialized exceeds a threshold amount of time. In other or similar embodiments, the processing logic may determine that the voltage distribution offset calibration criterion is met by determining that the width of the current voltage distribution of the memory page exceeds a threshold width.

[0093] Such as about Figure 7 As described, the processing logic may use a voltage at a specific quantile (e.g., 50th percentile) of the voltage distribution as a reference voltage. A previous value of the reference voltage may be determined based on the programming voltage and voltage distribution offset associated with the corresponding logic level of the memory cell at the memory page. The voltage distribution offset corresponds to the difference between the voltage at the tail end of the voltage distribution and the voltage at the 50th percentile of the voltage distribution immediately or shortly after programming the memory cell at the corresponding logic level. The voltage distribution offset may be determined based on experimental and / or manufacturing data of the memory device immediately or shortly after programming, and the voltage distribution offset corresponds to the width of the voltage distribution of the memory device immediately or shortly after programming. In some embodiments, the width of the voltage distribution at the corresponding logic level changes during operation of the memory device, and the voltage distribution offset no longer corresponds to the distribution width.

[0094] Figure 11The present disclosure describes the change in the width of a voltage distribution during operation of a memory device. As described above, voltage distribution 820 represents the current voltage distribution associated with the highest logic level of a memory cell of a memory page, and voltage distribution 810 represents the current voltage distribution associated with the second highest logic level of a memory cell of a memory page. Voltage 922 corresponds to a previous value of a reference voltage for voltage distribution 820, and voltage 912 corresponds to a previous value of a reference voltage for voltage distribution 810. Voltage 1120 represents the current value of a reference voltage for voltage distribution 820, and voltage 1110 corresponds to a previous value of a reference voltage for voltage distribution 810. Voltages 1120 and 1110 are measured by processing logic according to the previously described embodiments.

[0095] As in Figure 11 As seen, voltage 1120 does not approximately correspond to voltage 920; the voltage represents the current value of the reference voltage for voltage distribution 820, as per [reference to voltage distribution 820]. Figure 9A As described. This indicates that the width of voltage distribution 820 is changing during operation of the memory device. Similarly, voltage 1110 does not approximately correspond to voltage 910, which represents the current value of the reference voltage of voltage distribution 810, as per [reference to...]. Figure 9A As described, the width of the indicated voltage distribution 810 also increases during memory device operation. In response to determining that the difference 1112 between voltage 910 and voltage 1110 and / or the difference 1122 between voltage 920 and voltage 1120 exceeds a threshold difference, the processing logic can determine that a voltage distribution offset calibration criterion is met. Determining that the difference between voltage 910 and voltage 1110 and / or the difference between 920 and 1120 indicates that the width of the corresponding voltage distribution exceeds a threshold width and that the current voltage distribution offset no longer applies to voltage distributions 810 and 820.

[0096] In some embodiments, in response to determining that a voltage distribution offset calibration criterion is met, the processing logic may measure the voltage distribution of the memory pages and / or blocks immediately or shortly after performing a programming operation (e.g., a write operation) on the memory pages and / or blocks. For example, the processing logic may issue an instruction to the memory subsystem controller 115 instructing that measurements of the memory pages and / or blocks be obtained immediately or shortly after data received from the host system 120 is scheduled to be programmed into the memory pages and / or blocks. The instruction may cause the memory subsystem controller 115 to measure the memory pages and / or blocks in response to determining that host data has been programmed into the memory pages and / or blocks. In another example, the processing logic may detect that the memory subsystem controller 115 has completed the operation of programming host data into the memory pages and / or blocks, and may subsequently measure the voltage distribution of the memory cells in the memory pages and / or blocks.

[0097] In block 1020, the processing logic determines a voltage distribution offset (also referred to as voltage distribution offset) of a block family based on the programming voltage and a first memory access voltage associated with one or more first memory cells of the first group of memory. One or more first memory cells may be associated with a specific quantile (e.g., 50th percentile) of the first voltage distribution of a memory page. As described above, the processing logic may determine the first voltage distribution of a memory page based on measurements performed on the memory page and / or block family. In some embodiments, the processing logic determines the voltage distribution offset by: determining the difference between the programming voltage used to program data to the memory page and / or block family and the first memory access voltage associated with a memory cell at a specific quantile of the first voltage distribution of the memory page. In some embodiments, according to the embodiments described above, the first memory access voltage may correspond to a previous value of a reference voltage.

[0098] In block 1030, the processing logic measures the second voltage distribution of the second memory page of the block family. According to... Figure 7 In the described embodiments, the processing logic can measure a second voltage distribution of a second memory page. For example, the processing logic can measure the second voltage distribution of the second memory page over a period of time after a programming voltage is applied to program memory cells of the memory page and / or block family. At block 1040, the processing logic determines a second memory access voltage associated with one or more second memory cells in a second group of memory cells of the second memory page. Each of the second memory cells is associated with a specific quantile (e.g., 50th percentile) of the second voltage distribution. In some embodiments, according to the previously described embodiments, the second memory access voltage may correspond to the current value of a reference voltage.

[0099] In block 1050, the processing logic determines the voltage shift amount of the second memory page based on a second voltage and a voltage distribution offset. As described with respect to block 1020, the voltage distribution offset corresponds to the difference between the programming voltage used to program data into the memory page and / or block family and the first memory access voltage associated with the memory cell at a specific quantile. According to the embodiments described herein, the processing logic may determine the voltage shift amount of the second memory page based on the difference between the second voltage and the voltage distribution offset.

[0100] In block 1060, taking into account the voltage shift amount of the second memory page, the processing logic assigns the block family to the corresponding voltage bracket in a set of voltage brackets. As described above, the processing logic can assign a block family to a corresponding voltage bracket by associating the block family with the corresponding voltage bracket corresponding to the determined voltage shift amount of the second memory page. For example, the processing logic can update the pointers for the voltage bracket boundaries used for the corresponding voltage brackets to correspond to the block family.

[0101] In some embodiments, the processing logic may determine to perform a calibration scan on the block family again (e.g., in response to determining that a threshold number of P / E cycles have occurred). In such embodiments, the processing logic may be based on information about... Figure 7 The described embodiments perform a calibration scan. According to some embodiments, during the calibration scan, the processing logic may use the voltage distribution offset determined in block 1020 as the voltage distribution offset, instead of the voltage distribution offset determined based on experimental and / or manufacturing data.

[0102] Figure 12 An example machine illustrating computer system 1200 is described, within which a set of instructions for causing the machine to perform any one or more of the methods discussed herein is executable. In some embodiments, computer system 1200 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of the block family manager component 113). In alternative embodiments, the machine may connect (e.g., network) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0103] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) specifying actions to be performed by the machine. Furthermore, while a single machine is described, the term "machine" should also be considered as encompassing any collection of machines that individually or jointly execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0104] Example computer system 1200 includes processing device 1202 communicating with each other via bus 1230, main memory 1204 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or RDRAM), static memory 1206 (e.g., flash memory, static random access memory (SRAM) and the like), and data storage system 1218.

[0105] Processing device 1202 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing combinations of instruction sets. Processing device 1202 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 1202 is configured to execute instructions 1226 for performing the operations and steps discussed herein. Computer system 1200 may further include a network interface device 1208 for communication via network 1220.

[0106] Data storage system 1218 may include machine-readable storage medium 1224 (also referred to as computer-readable medium) storing instructions 1226 or software embodying one or more sets of the methods or functions described herein. Instructions 1226 may also reside wholly or at least partially within main memory 1204 and / or processing device 1202 during execution of the instructions by computer system 1200, both of which also constitute machine-readable storage media. Machine-readable storage medium 1224, data storage system 1218, and / or main memory 1204 may correspond to... Figure 1 The memory subsystem 110.

[0107] In one embodiment, instruction 1226 includes a component for implementing a voltage gradation boundary (e.g., Figure 1 The block family manager component 113) contains functional instructions. Although the machine-readable storage medium 1224 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered as including a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered as including any medium capable of storing or encoding sets of instructions for machine execution and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered as including (but not limited to) solid-state memory, optical media, and magnetic media.

[0108] Some parts of the foregoing detailed description have been presented in terms of the symbolic representation of algorithms and data bit operations within computer memory. These algorithms are described and represented in a manner used by those skilled in the art of data processing to communicate the nature of their work to others skilled in the art. Algorithms are hereby and generally considered to be a self-consistent sequence of operations that leads to a desired result. Operations are those that require physical manipulation of physical quantities. Typically, but not necessarily, these quantities may take the form of electrical or magnetic signals that can be stored, combined, compared, or otherwise manipulated. Referring to these signals as bits, values, elements, symbols, characters, items, numbers, etc., has sometimes proven convenient (primarily for reasons of commonality).

[0109] However, it should be remembered that all these terms and similar terms are associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure can refer to the operation and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0110] This disclosure also relates to an apparatus for performing the operations described herein. Such an apparatus may be specifically constructed for a particular purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0111] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the program based on the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of various such systems will be described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of this disclosure as described herein.

[0112] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processing according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory components, etc.

[0113] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the embodiments of the present disclosure without departing from the broader spirit and scope set forth in the appended claims. Therefore, the description and drawings should be considered illustrative rather than restrictive.

Claims

1. A method for voltage range calibration, the method comprising: The current memory access voltage distribution of memory pages of a block family associated with a first voltage level among a plurality of voltage levels at the memory device is measured, wherein the first voltage level is associated with a first voltage offset. The current value of the reference voltage is determined based on the current memory access voltage distribution measured for the memory page; The voltage shift amount of the memory page is determined based on the current value of the reference voltage and the previous value of the reference voltage, wherein the previous value of the reference voltage is associated with a previous memory access voltage distribution for the memory page; and In response to determining that the voltage shift amount satisfies the voltage shift criterion, the block family is associated with a second voltage segment among the plurality of voltage segments, wherein the second voltage segment is associated with a second voltage offset.

2. The method of claim 1, wherein the previous memory access voltage distribution of the memory page corresponds to the memory access voltage distribution of the memory page when data of the memory page is written to the memory device.

3. The method of claim 1, wherein the previous value of the reference voltage corresponds to a previous memory access voltage associated with one or more memory cells of the plurality of memory cells of the memory page.

4. The method of claim 3, wherein determining the current value of the reference voltage includes obtaining the current voltage of the one or more memory cells, and wherein determining the voltage shift amount includes determining the voltage difference between the current memory access voltage of the one or more memory cells and the previous memory access voltage of the one or more memory cells.

5. The method of claim 3, wherein the prior memory access voltage corresponds to a threshold voltage value associated with programming data into the memory page of the block family.

6. The method of claim 3, wherein determining the current value of the reference voltage comprises: Determine the current memory access voltage associated with a current group of memory cells at a specific quantile of the current memory access voltage distribution associated with the memory page in the plurality of memory cells, wherein determining the voltage shift amount of the memory page includes: determining the difference between the current memory access voltage associated with the current group of memory cells and a previous memory access voltage associated with a previous group of memory cells, the previous group of memory cells being associated with the specific quantile of the previous memory access voltage distribution of the memory page.

7. The method of claim 6, wherein the previous memory access voltage associated with the previous set of memory cells at a specific quantile of the previous memory access voltage distribution is determined based on the previous value of the reference voltage and experimental data collected for the memory device prior to initialization of the memory device.

8. The method of claim 1, wherein measuring the current memory access voltage distribution of the memory page comprises: Select the memory page from the plurality of memory pages of the block family; and One or more memory cells of the memory page are sampled.

9. The method of claim 1, wherein the current memory access voltage distribution and the previous memory access voltage distribution each correspond to at least one of a read voltage distribution or a write voltage distribution.

10. A computing system comprising: A memory device associated with multiple voltage levels, each of which corresponds to a specific voltage offset; and A processing device coupled to the memory device performs operations including the following steps: A programming voltage is applied to a first plurality of memory cells of the memory device to program a first memory page of a block family; The memory access voltage distribution offset of the block family is determined based on the programming voltage and the first memory access voltage associated with one or more of the first memory cells in the plurality of memory cells, wherein each of the one or more first memory cells is associated with a specific quantile of the first memory access voltage distribution of the first memory page. In response to measuring the second memory access voltage distribution of the second memory page of the block family, a second memory access voltage associated with one or more second memory cells of a second plurality of memory cells of the second memory page is determined, wherein each of the one or more second memory cells is associated with a specific quantile of the second memory access voltage distribution; The voltage shift amount of the second memory page is determined based on the offset between the second memory access voltage and the memory access voltage distribution; and Taking into account the determined voltage shift amount of the second memory page, the block family is assigned to the corresponding voltage segment among the plurality of voltage segments.

11. The computing system of claim 10, wherein the processing means performs an operation including the step of applying the programming voltage to a first plurality of memory cells of the memory device to execute the first memory page of the block family in response to determining that a memory access voltage distribution offset calibration criterion is satisfied.

12. The computing system of claim 11, wherein determining whether the memory access voltage distribution offset calibration criterion is satisfied comprises: It is determined that the amount of time since the memory device was initialized exceeds a threshold amount of time.

13. The computing system of claim 11, wherein the operation further comprises: Before applying the programming voltage to the first plurality of memory cells of the memory device to program the first memory page of the block family, a third memory access voltage distribution of the first memory page is measured, wherein determining that the memory access voltage distribution offset calibration criterion is satisfied includes determining that the width of the third memory access voltage distribution exceeds a threshold width.

14. The computing system of claim 10, wherein the operation further comprises: In response to applying the programming voltage to the first plurality of memory cells of the memory device, the first memory access voltage distribution of the first memory page is measured.

15. The computing system of claim 10, wherein the first memory access voltage distribution and the second memory access voltage distribution each correspond to at least one of a read voltage distribution or a write voltage distribution.

16. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means, cause the processing means to perform an operation comprising the following steps: The current memory access voltage distribution of memory pages of a block family associated with a first voltage level among a plurality of voltage levels at the memory device is measured, wherein the first voltage level is associated with a first voltage offset. The current value of the reference voltage is determined based on the current memory access voltage distribution measured for the memory page; The voltage shift amount of the memory page is determined based on the current value of the reference voltage and the previous value of the reference voltage, wherein the previous value of the reference voltage is associated with a previous memory access voltage distribution for the memory page; and In response to determining that the voltage shift amount satisfies the voltage shift criterion, the block family is associated with a second voltage segment among the plurality of voltage segments, wherein the second voltage segment is associated with a second voltage offset.

17. The non-transitory computer-readable storage medium of claim 16, wherein the previous memory access voltage distribution of the memory page corresponds to the memory access voltage distribution of the memory page when data on the memory page is written to the memory device.

18. The non-transitory computer-readable storage medium of claim 16, wherein the previous value of the reference voltage corresponds to a previous memory access voltage associated with one or more memory cells of a plurality of memory cells of the memory page.

19. The non-transitory computer-readable storage medium of claim 18, wherein determining the current value of the reference voltage includes obtaining the current voltage of the one or more memory cells, and wherein determining the voltage shift amount includes determining the voltage difference between the current memory access voltage of the one or more memory cells and the previous memory access voltage of the one or more memory cells.

20. The non-transitory computer-readable storage medium of claim 18, wherein the prior memory access voltage corresponds to a threshold voltage value associated with programming data into the memory page of the block family.

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