Heater devices for microelectronic devices and related microelectronic devices, modules, systems, and methods

Abstract

The present application relates to heater devices for microelectronic devices and related microelectronic devices, modules, systems, and methods. A memory device includes at least one die and a heater device. The heater device includes a first switching element electrically connected to a power connection and the at least one die, a second switching element electrically connected to the first switching element, and a resistive element electrically connected to the second switching element and a ground connection. A method includes configuring the first switching element of the heater device to electrically connect the second switching element of the heater device to a power connection, configuring the second switching element to electrically connect one of a first resistor or a second resistor of the resistive element to the first switching element, and applying a voltage across the first resistor or the second resistor electrically connected to the first switching element.

Description

[0001] Priority requirements

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 160,209, filed March 12, 2021, entitled “Heater Devices for Microelectronic Devices and Related Microelectronic Devices, Modules, Systems and Methods”. Technical Field

[0003] Embodiments of this disclosure generally relate to heater devices for microelectronic devices to simulate operating conditions of a given system incorporating such microelectronic devices, microelectronic devices incorporating such heater devices, modules containing such microelectronic devices, methods for simulating operating conditions of such microelectronic devices using heating devices to predict the effects of such conditions on a given system utilizing them, and related systems and methods. Background Technology

[0004] Microelectronic devices in the form of semiconductor dies are conventionally formed in large-area wafers and other bulk substrates, allowing hundreds or thousands of identical individual dies to be fabricated simultaneously. Such dies can include diodes, transistors, metal-oxide-semiconductor field-effect transistors, insulated-gate bipolar transistors, and the like. Semiconductor dies are used individually in various memory devices (e.g., conventional volatile memory, such as conventional dynamic random-access memory (DRAM)) and in combinations incorporating control logic dies (e.g., hybrid memory cubes (HMCs) and host (e.g., processor) devices, such as high-bandwidth memory (HBM) devices, and conventional non-volatile memory, such as conventional NAND and / or NOR memory). Such memory devices are used within memory modules of computing systems (e.g., desktop computers, laptop computers, servers, mobile devices, etc.). These systems also incorporate other different functionalities of semiconductor dies, such as central processing units (CPUs) in microprocessor configurations, and dies combining processing and memory functions, such as graphics processing units (GPUs) and application-specific integrated circuits (ASICs). Summary of the Invention

[0005] Some embodiments of this disclosure include a memory device. The memory device may include: at least one die; and a heater device located on or within the at least one die. The heater device may include: a first switching element electrically connected to a power supply connection and the at least one die; a second switching element electrically connected to the first switching element; and a resistive element electrically connected to the second switching element and a ground connection.

[0006] One or more embodiments of this disclosure may include a memory module. The memory module may include a plurality of memory devices operatively coupled to a substrate. Each memory device may include at least one die and a heater device operatively coupled to the at least one die. The heater device may include: a first switching element electrically connected to a power connection of the substrate and the at least one die; a second switching element electrically connected to the first switching element; and a resistive element electrically connected to the second switching element and a ground connection of the substrate.

[0007] Embodiments of this disclosure may include a method comprising: configuring a first switching element of a heater assembly of a memory device to electrically connect a second switching element of the heater assembly to a power supply connection; configuring the second switching element of the heater assembly to electrically connect one of a first resistor or a second resistor of a resistive element of the heater assembly to the first switching element; and applying a voltage to the memory device and across the resistive element to the first resistor or the second resistor electrically connected to the first switching element.

[0008] Some embodiments of this disclosure include a heater device for a memory device. The heater device may include: a first switching element electrically connected to a power connection of the heater device and configured to electrically connect at least one die of the memory device to the power connection; a second switching element electrically connected to the first switching element; and a resistive element electrically connected to the second switching element and a ground connection of the memory device. Attached Figure Description

[0009] Figure 1 A schematic diagram illustrating a memory device comprising a die, a heater assembly, and an optional packaging substrate according to one or more embodiments of the present disclosure;

[0010] Figure 2 A schematic diagram showing a memory device including a heater device according to one or more embodiments of the present disclosure;

[0011] Figure 3A A schematic cross-sectional view of a resistor according to one or more embodiments of the present disclosure is shown;

[0012] Figure 3B exhibit Figure 3A A schematic top view of a resistor;

[0013] Figure 4 A schematic diagram illustrating a memory module comprising multiple memory devices according to one or more embodiments of the present disclosure;

[0014] Figure 5 A schematic diagram illustrating a memory module comprising multiple memory devices according to one or more embodiments of the present disclosure;

[0015] Figure 6 A flowchart of a method for simulating the power and thermal operating conditions of a system according to one or more embodiments of the present disclosure, and optionally measuring the power and thermal operating conditions of the system; and

[0016] Figure 7 This is a flowchart of a method for simulating the power and thermal operating conditions of a system according to one or more embodiments of the present disclosure, and optionally measuring the power and thermal operating conditions of the system. Detailed Implementation

[0017] The descriptions presented herein are not actual views of any particular heater device, memory device, or memory module, but are merely idealized representations for describing exemplary embodiments of this disclosure. The following description provides specific details of embodiments of this disclosure in order to provide a thorough description thereof. However, those skilled in the art will understand that embodiments of this disclosure can be practiced without such specific details. In fact, embodiments of this disclosure can be practiced in conjunction with conventional techniques used in the industry. Furthermore, the description provided below does not include all elements forming a complete structure or assembly. Only those process actions and structures necessary for understanding embodiments of this disclosure are described in detail below. Additional conventional actions and structures may be used. It should also be noted that any accompanying drawings are for illustrative purposes only and are therefore not drawn to scale. Additionally, elements shared between the drawings may have corresponding numerical designations.

[0018] As used herein, the terms “comprising,” “including,” and their grammatical equivalents are inclusive or open terms that do not exclude additional unlisted elements or method steps, and also include the more restrictive terms “consisting of” and “substantially consisting of” and their grammatical equivalents.

[0019] As used herein, the term “may” in relation to materials, structures, features, or methodological actions indicates that such materials are intended for use in implementing embodiments of this disclosure, and such terms are preferred over the more restrictive term “yes” in order to avoid any implication that they correspond to or must exclude other compatible materials, structures, features, and methods that may be used in combination with them.

[0020] As used herein, the term “configuration” refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device in order to facilitate the operation of one or more of the structure and device in a predetermined manner.

[0021] As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” are intended to include the plural forms as well.

[0022] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0023] As used herein, the term "generally" with respect to a given parameter, property, or condition means, and is included, the degree to which a given parameter, property, or condition is satisfied with deviations (e.g., within acceptable manufacturing tolerances) as would be understood by one of ordinary skill in the art. By way of example, depending on the particular parameter, property, or condition that is generally satisfied, it may be satisfied with at least 90.0%, at least 95.0%, at least 99.0%, or even at least 99.9%.

[0024] As used herein, the term "semiconductor material" refers to a material having a conductivity between that of electrically insulating materials and that of electrically conductive materials. For example, a semiconductor material may have a conductivity of about 10 at room temperature (e.g., between about 20 degrees Celsius and about 25 degrees Celsius). -8 Siemens per centimeter (S / cm) and 10 4 Between S / cm. Examples of semiconductor materials include elements found in column IV of the periodic table, such as silicon (Si), germanium (Ge), and carbon (C). Other examples of semiconductor materials include compound semiconductor materials, such as, but not limited to, binary compound semiconductor materials (e.g., gallium arsenide (GaAs)) and ternary compound semiconductor materials (e.g., Al). X Ga 1-X As) and quaternary compound semiconductor materials (e.g., Ga) X In 1-X AsYP 1-Y Compound semiconductor materials may contain, but are not limited to, combinations of elements from columns III and V of the periodic table (III-V semiconductor materials) or from columns II and VI of the periodic table (II-VI semiconductor materials). Semiconductor devices typically contain crystalline semiconductor materials. By way of non-limiting examples, transistors and diodes contain crystalline semiconductor materials.

[0025] As used herein, the term "single-crystal semiconductor material" refers to a semiconductor material comprising particles (e.g., atoms, molecules) arranged in a generally continuous crystal lattice, said lattice being substantially free of grain boundaries within the semiconductor material. The substrate of the semiconductor material may comprise a single-crystal semiconductor material, such as single-crystal silicon. Substrates comprising single-crystal semiconductor materials can serve as substrate materials for the various devices and structures disclosed herein.

[0026] As used herein, the term "polycrystalline semiconductor material" refers to a semiconductor material comprising multiple crystals (sometimes referred to as microcrystals or grains). Compared to monocrystalline semiconductor materials, polycrystalline semiconductor materials contain grain boundaries within the semiconductor material. Polycrystalline silicon, also known as "polysilicon / poly," is an example of a polycrystalline semiconductor material.

[0027] As used herein, the term "doped semiconductor material" refers to a semiconductor material having a higher concentration of impurities (e.g., dopants) introduced therein than a semi-semiconductor material (e.g., a higher concentration of impurities than the concentration of electrons and holes generated by heat at room temperature). Doped semiconductor materials may be primarily doped with donor impurities, such as, but not limited to, phosphorus (P), antimony (Sb), bismuth (Bi), or arsenic (As). Each donor impurity in the lattice of the semiconductor material adds a free electron, which increases the conductivity of the semiconductor material relative to its intrinsic form. Doped semiconductor materials that are primarily doped with donor impurities are referred to herein as "N-type semiconductor materials." Doped semiconductors may be substantially doped with trivalent or acceptor impurities, such as, but not limited to, boron (B), indium (In), aluminum (Al), and gallium (Ga). Each trivalent or acceptor impurity in the lattice of the semiconductor material adds an electron-hole (referred to herein as a "hole"), which increases the conductivity of the semiconductor material relative to its intrinsic form. Doped semiconductor materials that are primarily doped with trivalent or acceptor impurities are referred to herein as "P-type semiconductor materials."

[0028] As used herein, the terms “vertical” and “horizontal” refer to directions that are substantially perpendicular to and parallel to the surface of a substrate on which or in which a semiconductor device is formed, respectively. For example, a “vertical” stack or a “vertically oriented” stack of materials on a substrate refers to a stack of materials in which a first material is positioned between a second material and a substrate, a first material and a second material are positioned between a third material and a substrate, and so on, such that each successive material is further away from the substrate than the previous material. Conversely, a “horizontal” stack or a “horizontally oriented” stack of materials refers to a stack of materials in which the boundaries between the materials are each at substantially the same distance from the substrate. As used herein, the term “wafer” means and is included in materials on which or in which structures with feature dimensions comprising micrometer and nanometer scales are partially or completely fabricated. Such materials include conventional semiconductor (e.g., silicon) wafers as well as other semiconductor materials and bulk substrates of other materials. For convenience, such materials will be referred to as “wafers” below. Examples of structures formed on such materials may include, for example, integrated circuits (active and passive), MEMS devices, and combinations thereof.

[0029] As used herein, the term "memory device" means and includes, but is not limited to, microelectronic devices that exhibit memory functionality. In other words, by way of example only, the term "memory device" means and includes not only conventional memory (e.g., conventional volatile memory, such as conventional dynamic random access memory (DRAM); conventional non-volatile memory, such as conventional NAND and / or NOR memory), but also application-specific integrated circuits (ASICs) (e.g., system-on-a-chip (SoC)), microelectronic devices combining logic and memory, and graphics processing units (GPUs) incorporating memory.

[0030] As used herein, the term "module" means and includes an assembly of one or more microelectronic devices (e.g., semiconductor dies) mounted and operatively coupled to a substrate. Non-limiting examples of modules include a combination of one or more volatile and non-volatile memory devices, optionally having logic mounted to a substrate (e.g., a circuit board) for interaction with a higher-level package (e.g., a motherboard).

[0031] When developing, manufacturing, testing, and / or implementing systems (e.g., computing devices with processing power (e.g., laptops, desktops, servers, computer clusters, etc.)), the system designers, manufacturers, and operators (collectively, “operators”) typically want to determine and / or analyze (e.g., test) the power and thermal operating conditions of the system before acquiring one or more components (e.g., ASICs, memory controllers, etc.), or predict the impact of these power and thermal operating conditions during the design process. For example, operators typically want to measure the heat generated by various components during system operation for anticipated power draw and associated processing loads, and test the thermal effects to predict, design, and implement the desirability of other methods for heat sinks, fans, or control systems to handle anticipated power draw and associated processing loads. Additionally, operators may want to determine and / or analyze (e.g., test) the power and thermal operating conditions of a system for upcoming but unavailable microelectronic devices, such as memory devices (e.g., next-generation dynamic access memory (DRAM)). As a non-limiting example, an operator may want to test parameters such as power delivery, airflow, and heat dissipation affected by upgrades or other changes to memory devices for a given or proposed system and architecture. Furthermore, an operator may want to test power delivery, airflow, and heat dissipation before completing the system design (e.g., informing the design (e.g., determining how shut-down memory devices can be positioned next to each other while still operating within the given airflow and thermal constraints of the system enclosure)).

[0032] Conventionally, software simulations and models have been used to model airflow, heat generation, and power delivery; however, actual hardware testing can be more convincing and provide more accurate data. Previous methods for physically testing the power and thermal conditions of memory devices in attempts to simulate the physical conditions of a system involved constructing a physical heater package (e.g., a package with only fixed resistance) based at least in part on some parameters of a given system and a varying voltage applied to the heater package to raise its temperature. The heater package was then placed in a wind tunnel to test the extent to which it cooled in response to a given airflow. The resulting data could be provided to an operator who could then apply it to their own system. However, the data is not always sufficiently specific to the operator's system and typically does not model other factors of the operator's system that may affect its power and thermal operating conditions, such as the presence of other components, the cross-section of the airflow region through the system package, heat transfer capabilities, or constraints of the module substrate or motherboard. Furthermore, constructing a physical heater package for each intended system is time-consuming, relatively expensive, and not specific to each proposed installation.

[0033] Embodiments of this disclosure include, for example, memory devices having a heater device comprising a resistive element (e.g., a built-in resistive element) that can be used to simulate the power consumption and heat generation of the memory device when it is not in operation. For example, embodiments of this disclosure include memory devices (e.g., DRAM, NAND, NOR) that include a resistive element formed therein or on. Furthermore, the memory device includes a switching circuit system and / or a fuse that allows the memory device to exhibit a purely resistive load. By providing a purely resistive load, the memory device can be used to draw a desired amount of operating current (e.g., nominal or maximum current) and generate heat to simulate desired operating conditions. Therefore, the memory device can simulate desired power and thermal operating conditions before the system is completed and operational or before a suitable memory controller is available. Additionally, the memory device can simulate desired power and thermal operating conditions before allocating or giving a processing load. For example, the memory device may be installed in a memory module and used in a desired system environment (e.g., a desktop computer, laptop computer, server). Therefore, the heater device of the memory device allows for the simulation and testing of the power and thermal conditions of the system without the need for additional software or custom test systems. Therefore, the system's power and thermal conditions can be measured and tested on-site by the system operator. Furthermore, the memory device's heater configuration allows the operator to adjust (e.g., fine-tune) operating parameters (e.g., fan speed, airflow, etc.) and / or system configuration (e.g., heat sink, etc.) based on simulated power and thermal conditions, without having a complete system and / or before having a fully functional system.

[0034] Figure 1This is a schematic diagram of a memory device 100 including a die 102 (e.g., a die formed from a wafer) and a thermal and heat testing device 104. In some embodiments, the memory device 100 may optionally include a packaging substrate 106 according to one or more embodiments of this disclosure. For example, the memory device 100 may include any of the memory devices described above (e.g., DRAM, NAND, NOR, etc.) and may include any conventional functional design of the die 102 associated with and / or conventionally utilized by any of the memory devices described above. As noted above, the memory device 100 may include a thermal and heat testing device 104 (hereinafter referred to as “heater device 104”). In some embodiments, the heater device 104 may be disposed on and / or within the die 102 of the memory device 100 (e.g., a die stack). For example, the heater device 104 may be disposed between the wafer material of the die 102 and logic die material or processing die material that may be associated with the die 102 during actual system operation. Additionally, the heater device 104 may be formed within the metallization (e.g., back-end process (BEOL) metallization) of the die 102. In some embodiments, the heater device 104 may be located on or within an active surface of the die 102 surrounding a memory array of at least one die. Alternatively, the heater device 104 may be fabricated separately and disposed on top of the die 102, for example, as part of a redistribution layer (RDL) or interposer for redistributing pin leads of the die 102. In another embodiment, the die 102 may be disposed on a package substrate 106, and the heater device 104 may be disposed on the package substrate 106 and may be at least partially separable from the die 102. The following relates to... Figure 2 Sections 3 and 4 describe the location and form of the heater assembly 104 in more detail.

[0035] As discussed in more detail below, memory device 100 may include system-ready components. For example, memory device 100 may be ready to be coupled to a memory controller (e.g., a motherboard) and used with a system (e.g., a desktop computer). In other words, memory device 100 equipped with heater device 104 may be a "plug-and-play" component. Furthermore, as described in more detail below, heater device 104 allows the system operator to temporarily and without operation of memory device 100 to turn memory device 100 into a resistive element, supply power to the resistive element, and easily test the power and thermal conditions of the system affected by the energized resistive element, without requiring the availability of the complete system or even the memory controller. For example, heater device 104 of memory device 100 may be used to draw and consume a selected amount of energy (e.g., current, voltage), which may be selected based on the expected processing load (e.g., active power and / or standby power) and generate heat. Therefore, heater device 104 can simulate the typical operating power drawdown and typical operating heat generation (e.g., thermal environment) that the system will experience during operation (e.g., due to processing requirements (i.e., high processing capabilities)). Furthermore, heater device 104 can simulate the power and thermal conditions of the system prior to having the complete system or specific memory controllers or other components that can be used to bootstrap processing functions. Additionally, heater device 104 of memory device 100 allows for the simulation and testing of the system's power and thermal conditions without the need for additional software or custom test systems.

[0036] Figure 2 This is a schematic diagram of a memory device 200 including a heater assembly 104 according to one or more embodiments of the present disclosure. The memory device 200 may include at least one die 202 (e.g., a body of a semiconductive material (e.g., a silicon die)) and a heater assembly 104. The heater assembly 104 may include a resistive element 204, a first switching element 206, a second switching element 208, a power connection 211, and a ground connection 212. The at least one die 202 may include any conventional die used in the memory device (e.g., a typical die of DRAM, NAND, or NOR memory). The power connection 211 may be configured to be electrically connected to a power source 210 when the memory device 200 is mounted to a substrate (e.g., a memory module) mounted within a system (e.g., a desktop or laptop computer, tablet computer, smartphone, etc.). As noted above, in one or more embodiments, the resistive element 204 of the heater device 104 may be disposed on or within at least one die 202, and in other embodiments, the resistive element 204 of the heater device 104 may be separate from at least one die 202 and located elsewhere within the memory device 200 (e.g., RDL, interposer).

[0037] In some embodiments, resistive element 204 may include a first resistor 214 and a second resistor 216, and the first resistor 214 and the second resistor 216 may exhibit different resistances relative to each other. For example, in some embodiments, the first resistor 214 may exhibit a resistance of about 4.0 ohms (Ω), and the second resistor 216 may exhibit a resistance of about 24.0 ohms (Ω). Although specific resistors are described herein, this disclosure is not limited thereto; rather, the first resistor 214 and the second resistor 216 may each include resistances in the range of about 0.5 ohms (Ω) to about 30.0 ohms (Ω). As described in further detail below, in some embodiments, the first resistor 214 may represent a selected resistance simulating the active power state of the system (e.g., a relatively high processing load), and the second resistor 216 may represent a selected resistance simulating the standby power state of the system (e.g., a relatively low processing load). Furthermore, in some embodiments, resistive element 204 may include only one resistor exhibiting a resistance within the range described above. In alternative embodiments, the resistive element 204 may include more than two available resistors, for example, three, four, five, ten or more resistors with different resistances.

[0038] In some embodiments, the power supply 210 may include a V-shaped power supply. DD The power supply 210 may be a voltage source of the form of a power supply pin of the memory module, a positive voltage power supply, a drain power supply, or any other conventional power supply for the memory module. As will be understood by those skilled in the art, the power supply 210 may and conventionally be decoupled from the memory device 200. In some embodiments, the power supply 210 may be configured to provide a voltage in the range of about 0.8V to about 2.5V via a power connection 211. Furthermore, the voltage provided by the power supply 210 may be optional (i.e., the power supply may be variable).

[0039] In some embodiments, the first switching element 206 may be electrically connected to a power connector 211, at least one die 202, and a second switching element 208. In other words, the heater assembly 104 may include electrical connections between the power connector 211 and the first switching element 206, between the first switching element 206 and at least one die 202, and between the first switching element 206 and the second switching element 208. Similarly, the second switching element 208 may be electrically connected to the first switching element 206 and a resistive element 204, which in turn may be electrically connected to a ground connection 212. For example, the heater assembly 104 may include an electrical connection between the second switching element 208 and the resistive element 204, and an electrical connection between the resistive element 204 and the ground connection 212.

[0040] Generally, the first switching element 206 can be configured to switch between electrically connecting at least one die 202 to the power connector 211 while creating an open circuit with the resistive element 204, and electrically connecting the resistive element 204 to the power supply 210 while creating an open circuit with at least one die 202. Additionally, when the memory device 200 is coupled to a memory module (e.g., a dual data rate (DDR) 4 memory module), and the memory module is coupled to a memory controller (e.g., a motherboard memory controller (e.g., an integrated memory controller (IMC), memory chip controller (MCC), memory controller unit (MCU), memory management unit (MMU), etc.)), the first switching element 206 can be configured to be operatively coupled to the system's memory controller, such that the operation of the first switching element 206 can be implemented by and / or through the memory controller. For example, the memory device 200 may form a portion of an unregistered memory module. In other embodiments, the memory device 200 may be installed within a registered memory module (described below), and the first switching element 206 may be configured to be operatively coupled to a register of the memory module such that operation of the first switching element 206 may be implemented by or through the register.

[0041] As a non-limiting example, in some embodiments, the first switching element 206 may include a fuse element and a fuse arrangement configured to melt the fuse element, such that the first switching element 206 exhibits a "melted fuse configuration". In some embodiments, the fuse element may include one or more of a fuse (e.g., a laser-fusible link comprising polysilicon or a metal covered by a uniform dielectric material (e.g., silicon dioxide)) or an anti-fuse (e.g., a capacitor fuse exhibiting high impedance or an open circuit that can be melted when a relatively high voltage is applied across the capacitor plates). For example, when manufactured, the anti-fuse operates as an open circuit. By applying a larger voltage to the anti-fuse structure, the anti-fuse becomes "programmed". The programmed anti-fuse operates as a conductor or link in a closed circuit, thereby allowing current to flow through said portion of the circuit. In contrast, when manufactured, the fuse operates as a link in a closed circuit. The fuse can be manufactured and selectively melted by methods well known to those skilled in the art, such as by current or laser. Once the fuse is melted, its operation is an open circuit. Alternatively, the fuse element may comprise a polymer positive temperature coefficient (PPTC) thermistor or a thermal fuse. For example, the first switching element 206 may comprise any conventional fuse element and fuse assembly.

[0042] In operation, in some embodiments, to “flip” the first switching element 206 and electrically connect the resistive element 204 to the power supply 210, the fuse device may apply a relatively high current (e.g., 10mA) DC pulse to melt (e.g., cut off) the fuse. For example, the fuse may be melted via any conventional means. Melting the fuse may create a relatively high resistance or an open circuit between at least one die and the power supply 210, which in turn may electrically connect the resistive element 204 to the power supply 210 or at least direct energy (e.g., voltage) supplied by the power supply 210 to the resistive element 204.

[0043] In an additional embodiment, the first switching element 206 may include a switching circuit system configured to switch between electrically connecting at least one die 202 to power connector 211 while creating an open circuit with resistor element 204, and electrically connecting resistor element 204 to power connector 211 while creating an open circuit with at least one die 202, in response to an input and / or write command. For example, the first switching element 206 may be configured to receive and / or control commands from a memory controller via Mode Register Set (MRS) commands and / or chip select or select pin commands. For example, the MRS commands and / or chip select or select pin commands may include configuration commands to switch (e.g., configure) the first switching element 206 between electrically connecting at least one die 202 to power connector 211 while creating an open circuit with resistor element 204 and electrically connecting resistor element 204 to power connector 211 while creating an open circuit with at least one die 202.

[0044] As noted above, the second switching element 208 may be electrically connected to the first switching element 206 and electrically connected to the resistor element 204. Furthermore, the resistor element 204 may be electrically connected to the ground connection 212. In some embodiments, the second switching element 208 may be operatively coupled to both the first resistor 214 and the second resistor 216, and includes a switching circuitry configured to switch back and forth between electrically connecting the first resistor 214 to the first switching element 206 and electrically connecting the second resistor 216 to the first switching element 206 in response to receiving an input and / or write command. For example, the second switching element 208 may be configured to receive and / or be controlled from a memory controller via an MRS command and / or a chip select or select pin command. For example, the second switching element 208 may be configured to electrically connect power supply 210 to the first resistor 214 in response to a first MRS command and / or a chip select or select pin command, and to electrically connect power supply 210 to the second resistor 216 in response to a second MRS command and / or a chip select or select pin command.

[0045] As mentioned above, heater device 104 can be used to test the power and thermal operating conditions of a system utilizing memory device 200. For example, heater device 104 can be used to simulate expected power consumption and heat generation within the system during operation. Therefore, during operation and during the simulation of power and thermal conditions, first switching element 206 can be switched (e.g., configured) to electrically connect power connection 211 (and power supply 210) to second switching element 208, and second switching element 208 can be switched (e.g., configured) to electrically connect power connection 211 (and power supply 210) to one of first resistor 214 or second resistor 216. In some embodiments, which resistor, first resistor 214 or second resistor 216, is selected and electrically connected to power supply 210 may be based on whether the test intends to simulate an active power mode or a standby power mode of the system.

[0046] Voltage can be supplied from power supply 210 via power connector 211; furthermore, the voltage supplied by power supply 210 may depend on the power mode being tested (e.g., active power mode or standby power mode). Therefore, a voltage can be applied across first resistor 214 or second resistor 216 to dissipate power and heat generated by the simulated (e.g., analog) operation of the memory device 200 within the system. Furthermore, as discussed in more detail below, based on the heat generated via resistive element 204, the operator of the system can observe and measure the power and thermal operating conditions of the system when operating in one or more power modes of the memory device 200. Furthermore, as discussed in more detail below, based on the measured power and thermal operating parameters, the operator of the system can adjust one or more operating parameters of the system, change the structure or configuration of the system or system package, change the location of system components, and / or make other changes to the design of the system.

[0047] Figure 3A This is a schematic cross-sectional view of a resistor device 300 according to one or more embodiments of the present disclosure. Figure 3B This is a schematic top view of resistor device 300. Resistor device 300 may be formed within or on the die of a memory device (e.g., memory device 200) or elsewhere within the memory device 200. Furthermore, resistor device 300 may form a resistor (e.g., first resistor 214 and / or second resistor 216) of a resistive element (e.g., resistive element 204) of the memory device 200.

[0048] In some embodiments, the resistor device 300 may include a substrate 302 of a die comprising a semiconductor material of the memory device 200, and the substrate 302 may define a trench 304 therein. The resistor device 300 may also include an oxide material 309 and at least one resistive material 306 disposed within the trench 304. As used herein, the term "resistive material" refers to the material intended for use as a resistive element in a resistor in an electronic device (e.g., a device, semiconductor device).

[0049] In one or more embodiments, at least one resistive material 306 may comprise one or more portions oriented in series. For example, at least one resistive material 306 may be formed in a serpentine pattern. A serpentine pattern in a resistor can be used to provide the desired length of at least one resistive material 306 within a limited semiconductor chip area to achieve a desired resistance value. Resistors with this shape are sometimes referred to as serpentine resistors because their lateral zigzag pattern may resemble that of a snake. A serpentine pattern can occupy a relatively large area of ​​the semiconductor chip, which can reduce the availability of that area for other devices.

[0050] In some embodiments, the resistor device 300 may comprise multiple layers (i.e., lines) of resistive material, such as in a BEOL structure or in a region of the active surface of a die surrounding a memory array or other active circuitry. These layers are stacked on top of each other with an electrically insulating material between the resistive materials, and the ends of the multiple layers of resistive material are coupled through conductive vias at alternating ends to provide a vertical serpentine resistor arrangement. In one or more embodiments, at least one resistive material 306 may comprise a polycrystalline semiconductor material, such as a doped polycrystalline semiconductor material. For example, at least one resistive material 306 may comprise polycrystalline silicon, such as doped polycrystalline silicon. Additionally, the electrically insulating material may comprise an oxide material (e.g., silicon dioxide (SiO2)). In other embodiments, at least one resistive material may comprise a resistive metal material, such as tungsten or tin.

[0051] Factors affecting the resistance of a resistive material include its cross-sectional area, length, and dopant concentration. Therefore, the target resistance of the resistive material 306 can be customized during the manufacture of the resistor device 300 by taking into account the cross-sectional area, length, and dopant concentration or metal type of the first resistive material 306.

[0052] Resistor device 300 includes electrical contacts 308 electrically connected (e.g., electrically coupled) to resistive material 306. Electrical contacts 308 may comprise a conductive material. Electrical traces (not shown) on resistor device 300 may be used for electrical connections to electrical contacts 308. By means of a non-limiting example, the desired total resistance of resistor device 300 can be achieved by forming the resistive material to have the desired configuration and composition.

[0053] Figure 4 For inclusion Figure 2 A schematic diagram of a memory module 400 (e.g., a RAM integrated circuit) comprising multiple memory devices 200. For example, memory module 400 may include dual data rate (DDR) fourth generation synchronous dynamic random access memory (DDR4 SDRAM), and each of the memory devices 200 may include DRAM. Memory module 400 may further include multiple input / output pins 404. In embodiments including unregistered memory, each of the memory devices 200 may include a corresponding line (e.g., a connection) configured to be directly electrically connected to a memory controller (e.g., the memory controller of the module or the motherboard), such that the memory controller can control (e.g., drive) each of the memory devices 200. The line (e.g., the connection) may be operatively coupled to one or more of the multiple input / output pins 404. In embodiments including registered memory (e.g., buffered memory), memory module 400 may include a register or buffer chip between the memory devices 200 and the memory controller.

[0054] Figure 5 For inclusion Figure 2 A schematic diagram of a memory module 500 (e.g., a RAM integrated circuit) comprising multiple memory devices 200. For example, the memory module may include dual data rate (DDR) fifth generation synchronous dynamic random access memory (DDR5 SDRAM), and each of the memory devices 200 may include DRAM. The memory module 500 may further include a plurality of input / output pins 504. In embodiments including unregistered memory, each of the memory devices 200 may include a corresponding line (e.g., a connection) configured to be directly electrically connected to a memory controller (e.g., the memory controller of the module or the motherboard), such that the memory controller can control (e.g., drive) each of the memory devices 200. The line (e.g., the connection) may be operatively coupled to one or more of the plurality of input / output pins 504. In embodiments including registered memory (e.g., buffered memory), the memory module 500 may include a register or buffer chip between the memory devices 200 and the memory controller.

[0055] Figure 6 A flowchart depicts a method 600 for simulating the power and thermal operating conditions of a system according to one or more embodiments of the present disclosure, and optionally measuring the power and thermal operating conditions of the system. In some embodiments, method 600 may include fusing a fuse of memory device 200 to activate a resistance mode of heater device 104 of memory device 200, such as... Figure 6As illustrated in action 602. For example, the fuse of the memory device 200 may include applying a DC pulse of a relatively high current (e.g., 10mA) to blow (e.g., cut off) the fuse. For example, the fuse may have two logic states, including a first state as logic "zero" and a second state as logic "one" (e.g., a programming state), where the fuse produces high resistance or an open circuit. Alternatively, the fuse of the memory device 200 may include blowing the fuse by any conventional means. When the memory device 200 is coupled (e.g., mounted) to a memory module (e.g., memory module 400), the fuse of the memory device 200 (e.g., producing high resistance or an open circuit) will be powered by power supply 210 (e.g., V). DD Any power supplied is directed to the resistive element 204 (e.g., a lower resistance). In some embodiments, the fuse of the fuse-breaking memory device 200 may include components via the above-mentioned... Figure 2 The fuse of the first switching element (e.g., first switching element 206) of the memory device 200 is to be blown in any manner as described.

[0056] In some embodiments, method 600 may optionally include mounting memory device 200 to memory module (e.g., memory module 400, 500), such as Figure 6 As illustrated in action 604. For example, in some embodiments, method 600 may include blowing a fuse on the memory device 200 (e.g., DRAM) before mounting it into a memory module (e.g., DDR4). As discussed in more detail below, blowing the fuse on the memory device 200 before mounting it allows the memory device 200 to be sold as an individual component that can later be mounted into the memory module. The memory device 200 can be mounted into the memory module via any conventional method.

[0057] Method 600 may further include supplying voltage to the memory device 200 via power supply 210 (e.g., energizing the memory device 200) in a resistive mode in response to fusing the fuse of the memory device 200 and activating the heater device 104 of the memory device 200, such as... Figure 6As illustrated in action 606. For example, method 600 may include applying an input voltage to memory device 200. In some embodiments, the input voltage may be in the range of about 0.8V to about 2.5V and may be selected at least in part based on the type of memory device 200 (e.g., DRAM, NAND, NOR) and the type of memory module (e.g., DDR4, DDR5, etc.). Additionally, the input voltage may be selected at least in part based on the power mode of the memory device 200 to be simulated (e.g., active power mode or standby power mode). Furthermore, in some embodiments, the input voltage may be varied (e.g., switched) to simulate different operating conditions. Moreover, as noted above, because the fuse of memory device 200 blows (e.g., blows, essentially creating an open circuit with the die of memory device 200), a voltage may be applied (e.g., directed) to the resistive element 204 of memory device 200.

[0058] Additionally, method 600 may include selecting a high or low resistance mode for the resistive element 204 of the memory device 200, such as... Figure 6 As illustrated in action 608. For example, method 600 may include selecting whether to apply an input voltage across a first resistor (e.g., first resistor 214) or a second resistor (e.g., second resistor 216). In some embodiments, selecting a high-resistance mode or a low-resistance mode may include inputting one or more of an MRS command or a chip (e.g., pin) select command to a switch (e.g., second switching element 208) of memory device 200 to apply an input voltage across the selected resistor. For example, method 600 may include generating one or more MRS commands and / or chip (e.g., pin) select commands and sending them to memory device 200 to select one of the first resistor 214 or the second resistor 216 via a switch (e.g., generating a circuit with the selected resistor). In one or more embodiments, this may be achieved via the above description regarding... Figure 2 Any of the described methods is used to select either a high-resistance mode or a low-resistance mode, and to operate the second switching element 208.

[0059] In one or more embodiments, selecting a high or low resistance mode for the resistive element 204 of the memory device 200 may include switching between a high resistance mode and a low resistance mode while supplying voltage to the memory device 200 at least substantially continuously. In other words, selecting a high or low resistance mode for the resistive element 204 of the memory device 200 may include switching back and forth between a high resistance mode and a low resistance mode to simulate active power mode and standby power mode for a period of time sufficient to obtain reliable data, stress test other components of the system, or both.

[0060] In some embodiments, the selection of a high-resistance mode or a low-resistance mode may depend at least in part on the expected power draw during operation of the memory device 200 within a given system (e.g., the expected amount of power to be consumed during operation of the memory device 200). Furthermore, the expected power draw may be determined at least in part based on the expected processing load of the memory device 200 with a given system. For example, in some embodiments, the power draw may be in the range of about 100 milliwatts (mW) to about 500 milliwatts (mW). Therefore, a resistor (e.g., a resistor) may be selected to at least substantially simulate the expected power draw (e.g., operating conditions) of the memory device 200.

[0061] In response to an input voltage applied across resistive element 204 (i.e., the first resistor 214 or the second resistor 216 of resistive element 204), heater device 104 may consume power and generate heat, as shown in action 609. Therefore, in some embodiments, method 600 may optionally include measuring the power and thermal conditions of a given system as a result of the power consumption and heat generation of memory device 200, such as... Figure 6 As illustrated in action 610. For example, method 600 may include measuring the temperature around the memory device 200 while it is subjected to airflow (e.g., a fan providing airflow above or around the memory device 200) and consuming a selected amount of power. In some embodiments, method 600 may include measuring the temperature around the memory device 200 while it is subjected to a range of airflow and consuming a range of selected amounts of power. In one or more embodiments, method 600 may include measuring the temperature around multiple memory devices 200 or multiple memory modules having memory devices 200 while they are oriented close to each other, subjected to airflow or a range of airflow, and consuming a selected amount of power or a range of power. Additionally, system designers may measure inlet and outlet airflow to verify sufficient airflow and analyze the performance of other components / systems upstream and / or downstream of the memory device 200. In other embodiments, method 600 may include measuring the effect of the memory device 200 drawing a selected amount of power from other components of a given system.

[0062] Additionally, in one or more embodiments, method 600 may include adjusting and / or selecting one or more operating parameters and / or one or more structural parameters of a given system, at least in part, based on measured power and thermal conditions of the given system, such as... Figure 6As illustrated in action 612. For example, method 600 may include selecting, at least in part, the airflow rate to be generated, the airflow direction to be generated, the fan speed of one or more fans to be included, and / or the number of fans to be included in the given system, or the number, configuration, and location of one or more heat sinks, based on measured power and thermal conditions of the given system. Furthermore, method 600 may include selecting an inlet temperature to ensure sufficient cooling capacity for the system, data center, and / or environment. Additionally, method 600 may include selecting and / or changing the distance between adjacent memory modules and / or the distance between memory modules and other structures of the system, based at least in part on measured power and thermal conditions of the given system.

[0063] Figure 7 A flowchart depicts a method 700 for simulating the power and thermal operating conditions of a system according to one or more embodiments of the present disclosure, and optionally measuring the power and thermal operating conditions of the system. In some embodiments, method 700 may include coupling a memory module including a memory device 200 (e.g., at least one memory device) to a memory controller of the system, such as... Figure 7 As shown in action 702. For example, method 700 may include coupling a dual data rate (DDR) module containing one or more DRAMs to the motherboard of the system.

[0064] Additionally, method 700 may include a switch (e.g., first switch 206) of a heater device (e.g., heater device 104) that transmits commands to at least one memory device 200 to activate a resistance mode of heater device 104, such as... Figure 7 As illustrated in action 704. For example, method 700 may include writing an MRS command to memory device 200 to create an open circuit with the die of memory device 200, and coupling the power supply 210 of the system to the resistive element 204 of the heater device 104 of memory device 200 via power connector 211. For example, method 700 may include writing an MRS command to memory device 200 to configure (e.g., toggle) a switch to couple the power supply 210 of the system to the resistive element 204 of the heater device 104 of memory device 200 via power connector 211.

[0065] Method 700 may further include supplying voltage to memory device 200 via power source 210 (e.g., energizing memory device 200), such as Figure 7As illustrated in action 706. For example, method 700 may include applying an input voltage to memory device 200. In some embodiments, the input voltage may be in the range of about 0.8V to about 2.5V, and may be selected at least in part based on the type of memory device 200 (e.g., DRAM, NAND, NOR) and the type of memory module (e.g., DDR4, DDR5, etc.). Additionally, the input voltage may be selected at least in part based on the power mode (e.g., active power mode or standby power mode) of the memory device 200 to be simulated. Furthermore, in some embodiments, the input voltage may be varied (e.g., switched) to simulate different operating conditions. Moreover, as described above, because the MRS command initiates the resistive mode of memory device 200, the input voltage may be applied (e.g., directed) to the resistive element 204 of memory device 200.

[0066] Additionally, method 700 may include selecting a high or low resistance mode for the resistive element 204 of the memory device 200, such as... Figure 7 As illustrated in action 708. For example, method 700 may include selecting whether to apply an input voltage across a first resistor (e.g., first resistor 214) or a second resistor (e.g., second resistor 216). In some embodiments, selecting a high-resistance mode or a low-resistance mode may include inputting one or more of an MRS command or a chip (e.g., pin) select command to a switch (e.g., second switching element 208) of memory device 200 to apply an input voltage across the selected resistor. For example, method 700 may include generating one or more MRS commands and / or chip (e.g., pin) select commands and sending them to memory device 200 to select one of the first resistor 214 or the second resistor 216 via a switch (e.g., generating a circuit with the selected resistor). In one or more embodiments, this may be achieved via the above description regarding... Figure 2 Any of the described methods is used to select either a high-resistance mode or a low-resistance mode, and to operate the second switching element 208.

[0067] In one or more embodiments, selecting a high or low resistance mode for the resistive element 204 of the memory device 200 may include switching between a high resistance mode and a low resistance mode while at least substantially continuously supplying voltage to the memory device 200. In other words, selecting a high or low resistance mode for the resistive element 204 of the memory device 200 may include switching back and forth between a high resistance mode and a low resistance mode to simulate an active power mode and a standby power mode.

[0068] In some embodiments, as noted above, the selection of a high-resistance mode or a low-resistance mode may depend at least in part on the expected power draw during operation of the memory device 200 within a given system (e.g., the expected amount of power to be consumed during operation of the memory device 200). Furthermore, the expected power draw may be determined at least in part based on the expected processing load of the memory device 200 with a given system. For example, in some embodiments, the power draw may be in the range of about 100 milliwatts (mW) to about 500 milliwatts (mW). Therefore, a resistor (e.g., a resistor) may be selected to at least substantially simulate the expected power draw (e.g., operating conditions) of the memory device 200.

[0069] In response to an input voltage applied across resistive element 204 (i.e., the first resistor 214 or the second resistor 216 of resistive element 204), heater device 104 can consume power and generate heat, such as Figure 7 As illustrated in action 709. Therefore, in some embodiments, similar to method 600, method 700 may optionally include measuring the power and thermal conditions of a given system due to the power consumption of the memory device 200, such as... Figure 7 As shown in action 710. For example, method 700 may include measuring the above-mentioned... Figures 1 to 6 Either of the power and thermal conditions discussed.

[0070] Additionally, in one or more embodiments, method 700 may include adjusting and / or selecting one or more operating parameters and / or one or more structural parameters of the given system, at least in part, based on measured power and thermal conditions of the given system, such as Figure 7 As shown in action 712. For example, Figure 7 Action 712 may include any of the actions described above regarding action 612 of method 600.

[0071] The memory device and heater device of embodiments of this disclosure offer advantages over conventional methods that attempt to simulate the thermal operating conditions of a system (e.g., a desktop computer, laptop computer, server). For example, unlike heater dies used in a wind tunnel and not connectable to a given system, the memory device of this disclosure includes system-ready components. For example, the memory device is ready to be coupled to a memory module and memory controller (e.g., a motherboard) and used with a system (e.g., a desktop computer). In other words, the memory device is configured as a "plug-and-play" component for testing purposes. Furthermore, the heater device allows the system operator to temporarily convert the memory device into a resistive element, supplying power to the resistive element, and easily test the system's power and thermal conditions without requiring a complete system or even a specific memory controller to be available. Additionally, the heater device 104 can simulate the power and thermal conditions of a system prior to having a complete system or a specific memory controller or other components available for controlling processing functions. For example, when an operator and / or system lacks sufficient infrastructure to locally access and / or drive the processing capabilities of memory device 200 (e.g., the memory device die) but still wants to test power and thermal operating conditions, heater device 104 enables the operator and / or system to simulate power and thermal operating conditions. Furthermore, heater device 104 of memory device 100 allows for the simulation and testing of system power and thermal conditions without the need for additional software or test systems. Therefore, the system's power and thermal conditions can be measured and tested on-site by the system operator. Additionally, the heater device of the memory device allows the operator to adjust (e.g., fine-tune) operating parameters (e.g., fan speed, airflow, etc.) and / or system configuration based on simulated power and thermal conditions, without having a complete system and / or before having a fully functional system.

[0072] Furthermore, because the memory device can be manufactured to include a heater assembly, it can be produced and sold as an individual component that can be coupled to a memory module substrate or other higher-level packages. Alternatively, the memory device can be coupled to a substrate to provide a test memory module and then sold. Moreover, compared to conventional heater dies used in wind tunnels, the memory device and heater assembly provide a test method that utilizes a native voltage to initiate the test process.

[0073] While embodiments of this disclosure have been described in the context of memory devices, those skilled in the art will recognize and understand that other microelectronic devices (i.e., semiconductor dies and assemblies thereof) may incorporate or be associated with heater devices. For example, heater devices may be incorporated into or associated with logic devices configured as controllers, microprocessor devices, graphics processing units (GPUs), and application-specific integrated circuits (ASICs) incorporating processor and memory functionality. Furthermore, solid-state drives (SSDs) in the form of, for example, NAND flash or 3D Xpoint memory, may be configured with memory dies equipped with heater devices and a virtual controller for testing purposes to simulate the power and thermal effects of a real-time SSD. Of course, SSDs equipped with other memory configurations may also be equipped with heater devices. To simulate the operating thermal and power conditions of any multi-die module, it is considered that each die of the module would be equipped with an integrated heater device or auxiliary heating device operatively coupled to the die.

[0074] Some embodiments of this disclosure include a memory device. The memory device may include: at least one die; and a heater device located on or within the at least one die. The heater device may include: a first switching element electrically connected to a power supply connection and the at least one die; a second switching element electrically connected to the first switching element; and a resistive element electrically connected to the second switching element and a ground connection.

[0075] One or more embodiments of this disclosure may include a memory module. The memory module may include a plurality of memory devices operatively coupled to a substrate. Each memory device may include at least one die and a heater device operatively coupled to the at least one die. The heater device may include: a first switching element electrically connected to a power connection of the substrate and the at least one die; a second switching element electrically connected to the first switching element; and a resistive element electrically connected to the second switching element and a ground connection of the substrate.

[0076] Embodiments of this disclosure may include a method comprising: configuring a first switching element of a heater assembly of a memory device to electrically connect a second switching element of the heater assembly to a power supply connection; configuring the second switching element of the heater assembly to electrically connect one of a first resistor or a second resistor of a resistive element of the heater assembly to the first switching element; and applying a voltage to the memory device and across the resistive element to the first resistor or the second resistor electrically connected to the first switching element.

[0077] Some embodiments of this disclosure include a heater device for a memory device. The heater device may include: a first switching element electrically connected to a power connection of the heater device and configured to electrically connect at least one die of the memory device to the power connection; a second switching element electrically connected to the first switching element; and a resistive element electrically connected to the second switching element and a ground connection of the memory device.

[0078] Embodiments of this disclosure further include:

[0079] Example 1. A memory device comprising: at least one die; and a heater device located on or in the at least one die, the heater device comprising: a first switching element electrically connected to a power supply connection and the at least one die; a second switching element electrically connected to the first switching element; and a resistive element electrically connected to the second switching element and a ground connection.

[0080] Example 2. The memory device according to Example 1, wherein the resistive element comprises: at least one first resistor having a first resistance; and at least one second resistor having a second different resistance.

[0081] Example 3. The memory device according to Example 2, wherein one or more of at least a first resistor and at least a second resistor comprises polycrystalline silicon or a resistive metal material.

[0082] Example 4. A memory device according to any one of Examples 2 and 3, wherein at least one first resistor has a resistance of about 4.0 ohms (Ω) and at least one second resistor has a resistance of about 24 ohms (Ω).

[0083] Example 5. A memory device according to any one of Examples 2 to 4, wherein the second switching element is configured to switch between electrically connecting at least one first resistor to the first switching element and connecting at least one second resistor to the first switching element.

[0084] Example 6. A memory device according to any one of Examples 1 to 5, wherein the resistive element comprises more than two different resistors with different resistances.

[0085] Example 7. A memory device according to any one of Examples 1 to 6, wherein a first switching element is configured to switch between electrically connecting at least one die to a power connector and connecting a second switching element to a power connector.

[0086] Example 8. A memory device according to any one of Examples 1 to 7, wherein a heater device is located on or in an active surface of at least one die surrounding a memory array of the at least one die.

[0087] Example 9. A memory device according to any one of Examples 1 to 8, wherein the heater device is separated from and discontinuous with at least one die in a redistribution layer (RDL) or interposer operatively coupled to at least one die.

[0088] Example 10. A memory device according to any one of Examples 1 to 9, wherein the memory device includes one or more of DRAM, NAND or NOR dies.

[0089] Example 11. A memory device according to any one of Examples 1 to 10, wherein the first switching element includes a fuse and a fuse device configured to selectively blow the fuse.

[0090] Example 12. A memory device according to any one of Examples 1 to 11, wherein the first switching element includes a switching circuit system configured to operate via one or more of an MRS command or a chip select command.

[0091] Example 13. A memory device according to any one of Examples 1 to 12, wherein the second switching element includes a switching circuit system configured to operate via one or more of an MRS command or a chip select command.

[0092] Example 14. A memory module comprising: a plurality of memory devices operatively coupled to a substrate, each memory device including at least one die and a heater device operatively coupled to the at least one die, the heater device including: a first switching element electrically connected to a power connection of the substrate and the at least one die; a second switching element electrically connected to the first switching element; and a resistive element electrically connected to the second switching element and a ground connection of the substrate.

[0093] Example 15. The memory module according to Example 14, wherein the resistive element of each of the memory devices includes: at least one first resistor exhibiting a first resistance; and at least one second resistor exhibiting a second different resistance.

[0094] Example 16. The memory module according to Example 15, wherein at least one first resistor exhibits a resistance of about 4.0 ohms (Ω) and at least one second resistor exhibits a resistance of about 24 ohms (Ω).

[0095] Example 17. A memory module according to any of Examples 15 and 16, wherein the second switching element is configured to switch between electrically connecting at least one first resistor to the first switching element and connecting at least one second resistor to the first switching element.

[0096] Example 18. A memory module according to any one of Examples 14 to 17, wherein a first switching element is configured to switch between a power connection that electrically connects at least one die to a substrate and a power connection that connects a second switching element to the substrate.

[0097] Example 19. A memory module according to any one of Examples 14 to 18, wherein a heater device is located on or within an active surface of at least one die.

[0098] Example 20. A memory module according to any of Examples 14 to 19, wherein the heater device is located in a redistribution layer (RDL) or interposer operatively coupled to at least one die.

[0099] Example 21. A memory module according to any one of Examples 14 to 20, wherein the memory device includes one or more of DRAM, NAND or NOR dies.

[0100] Example 22. A memory module according to any one of Examples 14 to 21, wherein the first switching element includes a fuse and a fuse device configured to selectively cut off the fuse.

[0101] Example 23. A memory module according to any of Examples 14 to 22, wherein the first switching element includes a switching circuit system configured to be controlled by one or more of an MRS command or a chip select command.

[0102] Example 24. A memory module according to any of Examples 14 to 23, wherein the second switching element includes a switching circuit system configured to operate by one or more of an MRS command or a chip select command.

[0103] Example 25. A method comprising: configuring a first switching element of a heater assembly of a memory device to electrically connect a second switching element of the heater assembly to a power supply connection; configuring the second switching element of the heater assembly to electrically connect one of a first resistor or a second resistor of a resistive element of the heater assembly to the first switching element; and applying a voltage to the memory device and across the first resistor or the second resistor electrically connected to the first switching element.

[0104] Example 26. The method according to Example 25, wherein applying voltage to the memory device includes switching between voltage values ​​to alternatively simulate the standby power draw and the active power draw of the memory device.

[0105] Example 27. The method according to any of Examples 25 and 26, wherein a first switching element of the heater device of the memory device is configured to electrically connect a second switching element of the heater device to a power supply connector including a fuse for blowing the first switching element.

[0106] Example 28. The method according to any of Examples 25 to 27, wherein configuring a first switching element of the heater device of the memory device to electrically connect a second switching element of the heater device to a power connector includes one or more of an input MRS command or a chip select command.

[0107] Example 29. The method according to any of Examples 25 to 28, wherein configuring a second switching element of the heater device to electrically connect one of the first resistor or the second resistor of the resistive element of the heater device to the first switching element includes one or more of an input MRS command or a chip select command.

[0108] Example 30. The method according to any one of Examples 25 to 29 further includes mounting the memory device onto the substrate of the memory module after configuring the first switching element and before configuring the second switching element.

[0109] Example 31. The method according to any one of Examples 25 to 30, further comprising measuring one or more operating conditions of the system in which a memory device is mounted in response to the application of the voltage.

[0110] Example 32. The method according to Example 31 further includes adjusting one or more of the system's operating parameters or design based at least in part on one or more measured operating conditions of the system.

[0111] Example 33. A heater device for a memory device, comprising: a first switching element electrically connected to a power supply connection of the heater device and configured to electrically connect at least one die of the memory device to the power supply connection; a second switching element electrically connected to the first switching element; and a resistive element electrically connected to the second switching element and a ground connection of the memory device.

[0112] Example 34. The heater device according to Example 33, wherein the resistive element comprises: at least one first resistor; and at least one second resistor having a resistance different from that of the first resistor.

[0113] Example 35. The heater device according to Example 34, wherein the second switching element is configured to switch between electrically connecting at least one first resistor to the first switching element and connecting at least one second resistor to the first switching element.

[0114] Example 36. A heater device according to any one of Examples 34 and 35, wherein a first switching element is configured to switch between electrically connecting at least one die to a power connector and connecting a second switching element to a power connector.

[0115] Example 37. A heater device according to any one of Examples 33 to 36, wherein the first switching element includes a fuse and a fuse device adapted to selectively cut off the fuse.

[0116] Example 38. A heater device according to any of Examples 33 to 37, wherein the first switching element includes a switching circuit system configured to operate via one or more of an MRS command or a chip select command.

[0117] Example 39. A heater device according to any one of Examples 33 to 38, wherein the second switching element includes a switching circuit system configured to operate via one or more of an MRS command or a chip select command.

[0118] Example 40. A semiconductor structure comprising: at least one wafer; and a heater device located on or in the at least one wafer, the heater device comprising: a first switching element electrically connected to a power supply connection and the at least one wafer; a second switching element electrically connected to the first switching element; and a resistive element electrically connected to the second switching element and a ground connection.

[0119] Example 41. The semiconductor structure according to Example 40, wherein the resistive element comprises: at least one first resistor having a first resistance; and at least one second resistor having a second different resistance.

[0120] Example 42. The semiconductor structure according to Example 41, wherein one or more of at least one first resistor and at least one second resistor comprises polycrystalline silicon or a resistive metal material.

[0121] Example 43. The semiconductor structure according to Example 41, wherein the second switching element is configured to switch between electrically connecting at least one first resistor to the first switching element and connecting at least one second resistor to the first switching element.

[0122] Example 44. A semiconductor structure according to any of Examples 40 to 43, wherein the resistive element comprises more than two different resistors with different resistances.

[0123] While this disclosure has been described with respect to certain illustrative embodiments, those skilled in the art will recognize and understand that this disclosure is not limited thereto. In fact, many additions, deletions, and modifications can be made to the illustrated embodiments without departing from the scope of the invention as claimed, including its legal equivalents. Furthermore, features from one embodiment can be combined with features from another embodiment while still being covered within the scope of this disclosure as contemplated by the inventors. Moreover, embodiments of this disclosure are applicable to a wide variety of tool types and configurations.

Claims

1. A memory device comprising: at least one die; and a heater device on or in the at least one die, the heater device comprising: a first switching element electrically connected to a power connection and the at least one die; a second switching element electrically connected to the first switching element; and a resistive element electrically connected to the second switching element and a ground connection, wherein the first switching element is configured to switch between electrically connecting the at least one die to the power connection and connecting the second switching element to the power connection.

2. The memory device of claim 1, wherein the resistive element comprises: at least one first resistor having a first resistance; and at least one second resistor having a second, different resistance.

3. The memory device of claim 2, wherein one or more of the at least one first resistor and the at least one second resistor comprise a polysilicon or a resistive metal material.

4. The memory device of claim 2, wherein the at least one first resistor has a resistance of 4.0 Ohms (Ω) and the at least one second resistor has a resistance of 24 Ohms (Ω).

5. The memory device of claim 2, wherein the second switching element is configured to switch between electrically connecting the at least one first resistor to the first switching element and connecting the at least one second resistor to the first switching element.

6. The memory device of any one of claims 1-5, wherein the resistive element comprises more than two different resistors having different resistances.

7. The memory device of any one of claims 1-5, wherein the heater device is on or in an active surface of the at least one die that is peripheral to a memory array of the at least one die.

8. The memory device of any one of claims 1-5, wherein the heater device is separate and discontinuous from the at least one die in a redistribution layer (RDL) or an interposer operably coupled to the at least one die.

9. The memory device of any one of claims 1-5, wherein the memory device comprises one or more of a DRAM, NAND, or NOR die.

10. The memory device of any one of claims 1-5, wherein the first switching element comprises a fuse and a fuse device configured to selectively blow the fuse.

11. The memory device of any one of claims 1-5, wherein the first switching element comprises switching circuitry configured to operate via one or more of a MRS command or a chip select command.

12. The memory device of any one of claims 1-5, wherein the second switching element comprises switching circuitry configured to operate via one or more of a MRS command or a chip select command.

13. A memory module comprising: ​ a plurality of memory devices operably coupled to a substrate, each memory device comprising: at least one die; and a heater device operably coupled to the at least one die, the heater device comprising: a first switch element electrically connected to a power connection of the substrate and the at least one die; a second switch element electrically connected to the first switch element; and a resistive element electrically connected to the second switch element and a ground connection of the substrate, wherein the first switch element is configured to switch between electrically connecting the at least one die to the power connection of the substrate and connecting the second switch element to the power connection of the substrate.

14. The memory module of claim 13, wherein the resistive element of each of the memory devices comprises: at least one first resistor exhibiting a first resistance; and at least one second resistor exhibiting a second, different resistance.

15. The memory module of claim 14, wherein the at least one first resistor exhibits a resistance of 4.0 Ohms (Q) and the at least one second resistor exhibits a resistance of 24 Ohms (Q).

16. The memory module of claim 14, wherein the second switch element is configured to switch between electrically connecting the at least one first resistor to the first switch element and connecting the at least one second resistor to the first switch element.

17. The memory module of any one of claims 13-16, wherein the heater device is located on or within an active surface of the at least one die.

18. The memory module of any one of claims 13-16, wherein the heater device is located in a re-distribution layer (RDL) or an interposer operably coupled to the at least one die.

19. The memory module of any one of claims 13-16, wherein the memory devices comprise one or more of DRAM, NAND, or NOR dies.

20. The memory module of any one of claims 13-16, wherein the first switch element comprises a fuse and a fuse device configured to selectively cut the fuse.

21. The memory module of any one of claims 13-16, wherein each first switch element comprises switch circuitry configured to be controlled by one or more of a MRS command or a chip select command.

22. The memory module of any one of claims 13-16, wherein the second switch element comprises switch circuitry configured to be operated by one or more of a MRS command or a chip select command.

23. A method for operating a memory device, comprising: configuring a first switch element of a heater device of a memory device to selectively switch between electrically connecting a second switch element of the heater device to a power connection and electrically connecting at least one die to the power connection; the second switch element of the heater device to electrically connect one of a first resistor or a second resistor of the resistance element of the heater device to the first switch element, the second resistor having a resistance different from a resistance of the first resistor; and applying a voltage across the first resistor or the second resistor of the resistance element electrically connected to the first switch element to the memory device.

24. The method of claim 23, wherein applying the voltage to the memory device comprises switching between voltage values to alternatively simulate a standby power draw of the memory device and an active power draw of the memory device.

25. The method of claim 23, wherein configuring the first switch element of the heater device of the memory device to selectively switch between electrically connecting the second switch element of the heater device to the power connection and electrically connecting the at least one die to the power connection comprises blowing a fuse of the first switch element.

26. The method of claim 23, wherein configuring the first switch element of the heater device of the memory device to selectively switch between electrically connecting the second switch element of the heater device to the power connection and electrically connecting the at least one die to the power connection comprises inputting one or more of a MRS command or a chip select command.

27. The method of any one of claims 23-26, wherein configuring the second switch element of the heater device to electrically connect one of the first resistor or the second resistor of the resistance element of the heater device to the first switch element comprises inputting one or more of a MRS command or a chip select command.

28. The method of any one of claims 23-26, further comprising mounting the memory device to a substrate of a memory module after configuring the first switch element and before configuring the second switch element.

29. The method of claim 23, further comprising measuring one or more operating conditions of a system in which the memory device is mounted in response to applying the voltage.

30. The method of claim 29, further comprising adjusting one or more of an operating parameter or a design of the system based at least in part on the measured one or more operating conditions of the system.

31. A heater device of a memory device, comprising: a first switch element electrically connected to a power connection of the heater device and configured to electrically connect at least one die of the memory device to the power connection; a second switch element electrically connected to the first switch element; and a resistance element electrically connected to the second switch element and a ground connection of the memory device, the resistance element comprising: at least one first resistor; and at least one second resistor having a resistance different from a resistance of the at least one first resistor. ​ ​ wherein the second switching element is configured to switch between electrically connecting the at least one first resistor to the first switching element and connecting the at least one second resistor to the first switching element.

32. The heater apparatus of claim 31, wherein the first switching element is configured to switch between electrically connecting the at least one die to the power connection and connecting the second switching element to the power connection.

33. The heater apparatus of any one of claims 31-32, wherein the first switching element comprises a fuse and a fuse device adapted to selectively cut the fuse.

34. The heater apparatus of any one of claims 31-32, wherein the first switching element comprises switching circuitry configured to operate via one or more of an MRS command or a chip select command.

35. The heater apparatus of any one of claims 31-32, wherein the second switching element comprises switching circuitry configured to operate via one or more of an MRS command or a chip select command.

36. A semiconductor structure comprising: at least one wafer; and a heater apparatus located on or in the at least one wafer, the heater apparatus comprising: a first switching element electrically connected to a power connection and the at least one wafer; a second switching element electrically connected to the first switching element; and a resistive element electrically connected to the second switching element and a ground connection, wherein the resistive element comprises: at least one first resistor having a first resistance; and at least one second resistor having a second, different resistance, wherein the second switching element is configured to switch between electrically connecting the at least one first resistor to the first switching element and connecting the at least one second resistor to the first switching element.

37. The semiconductor structure of claim 36, wherein one or more of the at least one first resistor and the at least one second resistor comprises a polysilicon or a resistive metal material.

38. The semiconductor structure of claim 36, wherein the resistive element comprises more than two different resistors having different resistances.

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