Split-Gate Memory Cell with Improved Control-Gate Capacitance Coupling and Method of Manufacturing the Same

Abstract

The present invention is titled "Split-gate flash memory cell with improved control gate capacitance coupling and method of manufacturing the same". The present invention discloses a method of forming a memory device, the method comprising: forming a first insulating layer, a first conductive layer, and a second insulating layer on a semiconductor substrate; forming a trench in the second insulating layer to expose the upper surface of the first conductive layer; performing an oxidation process and an angled etching process to re-form the upper surface into a concave shape; forming a third insulating layer on the re-formed upper surface; forming a conductive spacer on the third insulating layer; removing a portion of the first conductive layer, leaving a floating gate that is located below the conductive spacer, wherein the re-formed upper surface terminates at a side surface at a sharp edge; and forming a word line gate that is laterally adjacent to and insulated from the floating gate. The conductive spacer includes a lower surface that faces the re-formed upper surface and matches the shape of the re-formed upper surface.

Description

Technical Field

[0001] The present invention relates to non-volatile memory arrays. Background Art

[0002] Split-gate non-volatile memory cells and arrays of such cells are well known. For example, U.S. Patent 5,029,130 (the “’130 patent”) discloses an array of split-gate non-volatile memory cells and is incorporated herein by reference in its entirety for all purposes. The memory cells are shown in Figure 1 . Each memory cell 10 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 therebetween. A floating gate 20 is formed above and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is formed above a portion of the drain region 16. The control gate 22 has a first portion 22a and a second portion 22b, the first portion being disposed above and insulated from (and controlling the conductivity of) a second portion of the channel region 18, and the second portion extending upward along and above the floating gate 20. The floating gate 20 and the control gate 22 are insulated from the substrate 12 by a gate oxide 26.

[0003] By placing a high positive voltage on the control gate 22, the memory cell is erased (wherein electrons are removed from the floating gate 20), causing electrons on the floating gate 20 to tunnel through the intermediate insulator 24 from the floating gate 20 to the control gate 22 via the Fowler-Nordheim tunneling effect.

[0004] By placing a positive voltage on the control gate 22 and a positive voltage on the drain region 16, the memory cell is programmed (wherein electrons are placed on the floating gate 20). An electron current flows from the source region 14 to the drain region 16. The electrons are accelerated and heated when they reach the gap between the control gate 22 and the floating gate 20. Due to the electrostatic attraction from the floating gate 20, some of the heated electrons are injected onto the floating gate 20 through the gate oxide 26.

[0005] The memory cell is read by placing a positive read voltage on the drain region 16 and the control gate 22, which turns on the portion of the channel region 18 that is under the control gate 22. If the floating gate 20 is positively charged (i.e., electrons are erased and capacitively coupled from the positive voltage of the drain region 16), then the portion of the channel region 18 that is under the floating gate 20 is also turned on, and current will flow through the channel region 18, which is sensed as the erased state or the "1" state. If the floating gate 20 is negatively charged (i.e., programmed with electrons), then the portion of the channel region 18 that is under the floating gate 20 is mostly or completely turned off, and current will not (or very little current) flow through the channel region 18, which is sensed as the programmed state or the "0" state. Those skilled in the art understand that the source and drain can be interchangeable, where the floating gate can partially extend over the source region 14 instead of the drain region 16, as Figure 2 shown. Figure 2 Also shown is a floating gate 20 having a concave upper surface that terminates at the side surface of the floating gate 20 in a sharp edge facing the control gate 22 to achieve better erase tunneling efficiency.

[0006] Split-gate memory cells having more than two gates are also known. For example, U.S. Patent 8,711,636 ("the '636 patent") (incorporated herein by reference for all purposes) discloses a memory cell having an additional coupling gate disposed above and insulated from the source region to better capacitively couple to the floating gate. See, for example Figure 3 which shows a coupling gate 24 disposed above the source region 14.

[0007] Four-gate memories are disclosed in U.S. Patent 6,747,310 ("the '310 patent"), which is incorporated herein by reference for all purposes. For example, as Figure 4 shown, memory cells 10 each have a source region 14 and a drain region 16 separated by a channel region 18, where a floating gate 20 is disposed above and insulated from a first portion of the channel region 18, a select gate 28 is disposed above and insulated from a second portion of the channel region 18, a control gate 22 is disposed above and insulated from the floating gate 20, and an erase gate 30 is disposed above and insulated from the source region 14. Programming is shown by hot electrons from the channel region 18 that inject themselves onto the floating gate 20. Erasure is shown by electrons tunneling from the floating gate 20 to the erase gate 30.

[0008] Figure 1 and Figure 2 The memory cells of have been successfully used as flash memories at several technology nodes. It is relatively easy to implement with a low-cost process and good performance. Figure 4The memory cells have been successfully used as embedded flash memories for several advanced technology nodes. It has very good quality and a competitive cell size. Figure 3 The memory cells of Figure 4 are less complex than those of

[0009] As the size of the memory cell 10 is scaled down, it becomes more difficult to achieve the desired capacitive coupling between the floating gate and the control gate, but the occurrence of unwanted capacitive coupling between the floating gate and other gates is avoided, which may adversely affect the performance. It is necessary to improve the performance at a reasonable cost. SUMMARY OF THE INVENTION

[0010] The foregoing need is addressed by a method of forming a memory device, the method comprising: forming a first insulating layer on an upper surface of a semiconductor substrate; forming a first conductive layer on the first insulating layer; forming a second insulating layer on the first conductive layer; forming a trench in the second insulating layer, the trench exposing an upper surface portion of the first conductive layer; performing an oxidation process and an angled etching process to re - shape the upper surface portion of the first conductive layer from a planar shape to a concave shape at the bottom of the trench; forming a third insulating layer on the re - shaped upper surface portion of the first conductive layer at the bottom of the trench; forming conductive spacers in the trench and on the third insulating layer; and removing a portion of the first conductive layer, leaving a floating gate of the first conductive layer that is located below the conductive spacers and includes an upper surface portion having a concave shape that terminates at a sharp edge at a side surface of the floating gate, wherein the conductive spacers include a lower surface that faces the upper surface portion of the floating gate, has a shape that matches the concave shape of the upper surface portion of the floating gate, and is insulated from the upper surface portion of the floating gate by a portion of the third insulating layer having a uniform thickness; forming a word line gate that is laterally adjacent and insulated from the floating gate; and forming spaced - apart source regions and drain regions in the semiconductor substrate, wherein a channel region of the semiconductor substrate extends between the source regions and the drain regions, wherein the floating gate is disposed above and insulated from a first portion of the channel region for controlling the conductivity of the first portion of the channel region, and wherein the word line gate is disposed above and insulated from a second portion of the channel region for controlling the conductivity of the second portion of the channel region.

[0011] The memory cell includes: spaced-apart source and drain regions located in a semiconductor substrate, with a channel region of the semiconductor substrate extending between the source and drain regions; a floating gate disposed over a first portion of the channel region and insulated therefrom for controlling the conductivity of the first portion of the channel region, wherein the floating gate includes an upper surface having a concave shape that terminates at a sharp edge at a side surface of the floating gate; a word line gate including a first portion, a second portion, and a notch, the first portion disposed over a second portion of the channel region and insulated therefrom for controlling the conductivity of the second portion of the channel region, the second portion at least partially disposed over the floating gate, the notch facing the sharp edge of the floating gate; and a coupling gate disposed over the floating gate and insulated therefrom, and including a lower surface facing the upper surface of the floating gate, having a shape matching the concave shape of the upper surface of the floating gate, and insulated from the upper surface of the floating gate by an insulating layer of uniform thickness.

[0012] The memory cell includes: spaced-apart source and drain regions located in a semiconductor substrate, with a channel region of the semiconductor substrate extending between the source and drain regions; a floating gate disposed over a first portion of the channel region and insulated therefrom for controlling the conductivity of the first portion of the channel region, wherein the floating gate includes an upper surface having a concave shape that terminates at a sharp edge at a side surface of the floating gate; a word line gate disposed over a second portion of the channel region and insulated therefrom for controlling the conductivity of the second portion of the channel region; a coupling gate disposed over the floating gate and insulated therefrom, and including a lower surface facing the upper surface of the floating gate, having a shape matching the concave shape of the upper surface of the floating gate, and insulated from the upper surface of the floating gate by an insulating layer of uniform thickness; and an erase gate disposed over the floating gate and the coupling gate and insulated therefrom, and including a notch facing the sharp edge of the floating gate.

[0013] Other objects and features of the present invention will become apparent by referring to the specification, claims, and drawings. Description of the Drawings

[0014] Figure 1 Is a cross-sectional view of a conventional dual-gate memory cell.

[0015] Figure 2 Is a cross-sectional view of a conventional dual-gate memory cell.

[0016] Figure 3 Is a cross-sectional view of a conventional triple-gate memory cell.

[0017] Figure 4 Is a cross-sectional view of a conventional quadruple-gate memory cell.

[0018] Figures 5 to 15 A cross-sectional view showing the steps of forming a memory cell pair.

[0019] Figure 16 A schematic diagram showing the configuration of an array of memory cell pairs.

[0020] Figure 17 A table of exemplary non-limiting operating voltages and currents for a memory cell pair.

[0021] Figures 18 to 21 A cross-sectional view showing the steps of forming a memory cell pair according to an alternative embodiment.

[0022] Figure 22 A schematic diagram showing the configuration of an array of memory cell pairs according to an alternative embodiment.

[0023] Figure 23 A table of exemplary non-limiting operating voltages and currents for a memory cell pair according to an alternative embodiment. Detailed Description

[0024] Embodiments of the present invention provide a new memory cell design and a method of manufacturing the same. Figures 5 to 15 The formation of a memory cell on a semiconductor substrate is shown. It should be understood that although the formation of a pair of memory cells is shown in the drawings and described below, the simultaneous formation of multiple such pairs of memory cells may also be performed. The process first forms a (first) insulating layer 42, such as silicon dioxide (referred to herein as "oxide"), on the upper surface 40a of a semiconductor substrate 40, such as silicon. A (first) conductive layer 44, such as polysilicon, is formed on the insulating layer 42. A (second) insulating layer 46, such as silicon nitride (also referred to herein as "nitride"), is formed on the conductive layer 44, as Figure 5 shown.

[0025] A masking step is performed (i.e., a photoresist 48 is deposited and portions of the photoresist 48 are selectively exposed and removed), followed by etching to form a trench 50 in the insulating layer 46, thereby exposing an upper surface portion 45 of the conductive layer 44 at the bottom of the trench 50, as Figure 6 shown. The upper surface portion 45 of the conductive layer 44 is planar. At this time, appropriate implantation into the conductive layer 44 can be performed. After removing the photoresist 48, multiple processes are performed to re-form the upper surface portion 45 of the conductive layer 44 from a planar shape to a curved concave shape at the bottom of the trench 50, as Figure 7As shown. Specifically, an oxidation process (e.g., thermal oxidation) is performed to oxidize the upper surface portion 45 of the conductive layer 44 at the bottom of the trench 50, where the oxidation consumes more of the conductive layer 44 at the center of the trench 50 than near the sides of the trench 50. Then, the oxidized portion of the conductive layer 44 is removed using oxide etching. Then, an angled etching process is performed, which removes material from the conductive layer 44 at a greater rate at the center of the trench 50 than near the sides of the trench 50. The combination of the oxidation process and the angled etching process achieves a significant curvature in the upper surface portion 45 of the conductive layer 44 at the bottom of the trench 50. It should be understood that the order of the processes may be reversed, whereby the angled etching process is performed first and then the oxidation process.

[0026] An insulating spacer 52, also referred to as a first insulating spacer 52, such as an oxide, is formed on the sides of the trench 50 through insulation deposition and insulation etching. The formation of the spacer involves depositing material over the profile of the structure, followed by an anisotropic etching process, whereby the material is removed from the horizontal surfaces of the structure while the material remains largely intact on the vertically oriented surfaces of the structure (often with a rounded upper surface). A (third) insulating layer 54, such as an oxide, is formed on the structure by depositing an insulating material, which also thickens the spacer 52. At least a portion of the insulating layer 54 on the upper surface portion 45 of the conductive layer 44 has a uniform thickness. A conductive spacer 56, such as polysilicon, is formed in the trench 50 through deposition and etching, as Figure 8 shown. Then, one or more etchings are performed to remove the exposed portions of the insulating layer 54, the conductive layer 44, and the insulating layer 42 from the bottom of the trench 50 (i.e., between the conductive spacers 56), thereby exposing the upper surface 40a of the semiconductor substrate 40. The height of the conductive spacers 56 is also reduced by these etchings. In one example, the conductive spacers 56 are reduced such that the upper surface of the conductive spacers 56 is substantially flush with the upper surface of the portion of the conductive layer 44 below the insulating layer 46. An optional insulating layer may be formed on the exposed upper surface 40a of the semiconductor substrate 40. Then, implantation is performed to form source regions 58 in the semiconductor substrate 40 below the trench 50, as Figure 9 shown.

[0027] Then, the trench 50 is filled with an insulating material 60, such as an oxide, through deposition, followed by back etching or CMP (chemical mechanical polishing) such that the insulating layer 46 is exposed. Optionally, further back etching is used to lower the upper surface of the insulating material 60 below the level defined by the insulating layer 46. Then, an etching is performed to remove the insulating layer 46, as Figure 10As shown. Then, anisotropic etching is performed to remove the exposed portions of the conductive layer 44. Optionally, non-selective etching is used to remove both the insulating material 60 and the conductive layer 44, in which case the height of the insulating material 60 is reduced. Then, implantation may be performed through the exposed portions of the insulating layer 42 and into the semiconductor substrate 40 to form word line channel implants. Then, etching is performed to remove the exposed portions of the insulating layer 42 and to lower the upper surface of the insulating material 60 (in one non-limiting example, to expose the conductive spacer 56, i.e., such that the upper surface of the insulating material 60 is substantially flush with the upper surface of the conductive spacer 56), as Figure 11 shown.

[0028] Insulating spacers 62 (also described as second insulating spacers 62, such as oxides) are formed on the sides of the structure by deposition and etching. A (fourth) insulating layer 64, such as an oxide (e.g., by depositing an insulating material), is formed on the structure, which also thickens the insulating spacers 62. A (second) conductive layer 66, such as polysilicon, is formed on the insulating layer 64 and the insulating spacers 62, as Figure 12 shown. A photoresist 68 is formed above the conductive layer 66, and the photoresist is removed, except for a plurality of blocks of the photoresist 68, each of which is vertically positioned above one of the sidewalls of the conductive layer 44. Then, etching is used to remove portions of the conductive layer 66, except for portions that are laterally and indirectly adjacent to the conductive layer 44 and are located below the photoresist 68, as Figure 13 shown. After removing the photoresist 68, implantation is performed to form a drain region 70 in the semiconductor substrate 40 adjacent to the remaining portions of the conductive layer 66. The structure is covered with an insulating material 72, such as an interlayer dielectric (ILD) oxide, and a contact 74 is formed through the insulating material 72 and to the drain region 70 by a masking step that etches through the insulating material 72 to form a contact hole exposing the drain region 70 and fills the contact hole with a conductive material, as Figure 14 shown. In one embodiment, contacts are formed similar to each of the conductive layer 66 and the conductive spacer 56 while forming the contact 74.

[0029] The final memory cell structure is shown in Figure 15In the middle. Memory cell pairs 76 are formed, where each memory cell 76 includes: a shared source region 58 and corresponding drain regions 70, with a channel region 78 of the semiconductor substrate 40 extending between the source and drain regions; a floating gate 44a (the remaining part of the conductive layer 44), which is disposed above a first part of the channel region 78 and controls the conductivity of the first part (and is disposed above a part of the source region 58); a word line gate 66a (the remaining part of the conductive layer 66), which is disposed above a second part of the channel region 78 and controls the conductivity of the second part; and a coupling gate 56a (the remaining part of the conductive spacer 56), which is disposed above the floating gate 44a. The floating gate 44a has an inclined concave upper surface 44b (the remaining part of the upper surface portion 45), which terminates at a side surface 44c in a sharp edge 44d. The coupling gate 56a has a lower surface 56b, which matches the concave shape of the upper surface 44b of the floating gate 44a and is separated from the upper surface by the remaining part of the insulating layer 54. The word line gate 66a has: a first part 66b, which is laterally and indirectly adjacent to the floating gate 44a (and is disposed above the second part of the channel region 78 and controls the conductivity of the second part); a second part 66c, which is at least partially disposed above the floating gate 44a (i.e., there is at least some vertical overlap between the second part 66c and the floating gate 44a) and is at least partially disposed above the coupling gate 56a (i.e., there is at least some vertical overlap between the second part 66c and the coupling gate 56a); and a notch 66d, which faces the sharp edge 44d of the floating gate 44a (for enhancing tunneling during erasure).

[0030] Figure 16 The architecture of a memory array formed by the memory cells 76 is schematically shown. The memory cell pairs 76 are arranged in rows and columns, where the memory cell pairs 76 are shaped end-to-end to form columns. For each row of memory cells 76, the word line gates 66a are formed as a continuous line connecting all the word line gates 66a of the entire row of memory cells 76, and the coupling gates 56a are formed as a continuous line connecting all the coupling gates 56a of the entire row of memory cells 76. For each row of memory cell pairs, the source region 58 is formed as a continuous diffusion region (or connected to a continuous line) connecting all the source regions 58 of the entire row of memory cell pairs 76. Each column of memory cells 76 includes a bit line 80, which is electrically connected to all the contacts 74 of all the memory cells 76 in the column (and thus electrically connected to all the drain regions 70).

[0031] Figure 17 Shows respectively for Figure 16Exemplary non - limiting examples of the voltages and currents for read, erase, and program operations of various lines of memory cells 76 that are included (i.e., marked as "selected") or not included (i.e., marked as "not selected") for an operation. To erase the selected memory cells 76 (where electrons are removed from the floating gate 44a), a positive voltage is placed on the word - line gate 66a while maintaining zero voltage on each of the bit - line 80, source region 58, and coupling gate 56a. This causes electrons on the floating gate 44a to tunnel through the intermediate insulator to the word - line gate 66a via Fowler - Nordheim tunneling effect. An entire row of memory cells 76 is erased simultaneously. To program the selected memory cells 76 (where electrons are placed on the floating gate 44a), a positive voltage is placed on the word - line gate 66a, coupling gate 56a, and source region 58. An electron current will flow from the source region 58 to the drain region 70, and some of the electrons will be injected onto the floating gate 44a through the intermediate insulator provided by the insulating layer 64. To read the selected memory cells 76, a positive read voltage is placed on the drain region 70 (connected to the bit - line 80), the word - line gate 66a (which turns on the channel region below the word - line gate 66a), and the coupling gate 56a, and zero voltage is placed on the source region 58. If the floating gate 44a is positively charged (erased), current will flow through the channel region 78, which is sensed as the erased or "1" state. If the floating gate 44a is negatively charged (programmed), current will not (or very little current) flow through the channel region 78, which is sensed as the programmed state or "0" state.

[0032] The memory cell 76 and its formation have many advantages. Matching the shape of the lower surface 56b of the coupling gate 56a to the upper surface 44b of the floating gate 44a (with an insulating layer 54 of uniform thickness therebetween) enhances the capacitive coupling between the coupling gate 56a and the floating gate 44a for better read and program operation performance. The insulating spacer 62 can be made thick enough to reduce the capacitive coupling between the floating gate 44a and the word - line gate 66a for better read, program, and erase operation performance. There is no conductive gate between the floating gate 44a and the coupling gate 56a in the region above the source region 58, which may cause unwanted capacitive coupling between the gates of different memory cells 76 and / or the common source region 58. Using both an oxidation process and an angled etching process to form the floating gate 44a results in the upper surface 44b of the floating gate 44a having a more pronounced curved or concave shape (and thus a sharper edge 44d) for better erase performance. The side surfaces of the floating gate 44a and the coupling gate 56a (facing away from the word - line gate 66a and above the source region 58) are self - aligned with each other (i.e., the side surface of the coupling gate 56a determines the position of the etching of the conductive layer 44 that produces the side surface of the floating gate 44a above the source region 58, see Figures 8 to 9 )

[0033] Figures 18 to 21Shows an alternative embodiment for forming memory cell 76. This embodiment starts from Figure 12 the structure shown (after forming conductive layer 66). As Figure 18 shown, etching is used to remove conductive layer 66, except for the (third) conductive spacer 66e of conductive layer 66. The etching is performed such that the upper surface of conductive spacer 66e is recessed by an amount "R" below the portion of insulating layer 64 over conductive spacer 56. This recess amount R will result in an erase gate notch, as further explained below. A (fifth) insulating layer 82, such as oxide, is formed over conductive spacer 66e (e.g., by deposition or by thermal oxidation). Then, a (third) conductive layer, such as polysilicon, is formed over this structure. A photoresist 86 is formed over the conductive layer, and the photoresist 86 is removed, except for the block vertically positioned over conductive spacer 56 and partially over conductive spacer 66e. Then etching is used to remove portions of the conductive layer, except for the block of conductive material 88 positioned below the block of photoresist 86, as Figure 19 shown. After removing photoresist 86, implantation is performed to form a drain region 70 in substrate 40 adjacent to the conductive layer 82 over conductive spacer 66e. The structure is covered with an insulating material 72, such as ILD oxide, and a contact 74 is formed through a masking step that etches through the insulating material to form a contact hole exposing drain region 70 and fills the contact hole with a conductive material, as Figure 20 shown. In one embodiment, contacts are formed similar to each of conductive spacer 66e and conductive spacer 56 while forming contact 74.

[0034] The final memory cell structure of the alternative embodiment is shown in Figure 21 and is similar to Figure 15The memory cell structure shown, except that the conductive spacer 66e acting as a word line gate is disposed laterally and indirectly adjacent to the floating gate 44a (i.e., no portion is partially located above the floating gate 44a). Instead, the conductive material 88 block is an erase gate that extends over two floating gates 44a, over two coupling gates 56a, and at least partially over two word line gates formed by the conductive spacers 66e of the memory cell pair 76 (i.e., there is at least some vertical overlap between the erase gate formed by the conductive material 88 block and the word line gate formed by the conductive spacer 66e). The erase gate formed by the conductive material 88 block includes a notch 88a facing the sharp edge 44d of the floating gate 44a (for enhancing tunneling during erasure). This alternative embodiment is advantageous because it reduces the capacitive coupling between the floating gate 44a and the word line gate formed by the conductive spacer 66e (since the word line gate formed by the conductive spacer 66e does not have a portion that extends upward along and above the floating gate 44a), and limits the capacitive coupling between the floating gate 44a and the erase gate formed by the conductive material 88 block due to the intervening coupling gate 56a, while still providing effective erasure because the notch 88a faces the sharp edge 44d, and retains the increased capacitive coupling between the floating gate 44a and the coupling gate 56a, as described above.

[0035] Figure 22 shows the architecture of a memory array formed by memory cells 76 of an alternative embodiment, which is similar to the architecture described above with respect to Figure 16 The difference is that for each row of memory cell pairs, the erase gate formed by the conductive material 88 block is formed as a continuous line connecting all the erase gates formed by the conductive material 88 block of the entire row of memory cell pairs. Figure 23 shows exemplary non-limiting examples of the voltages and currents for read, erase, and program operations of various lines for memory cells 76 that are included (i.e., marked as "selected") or not included (i.e., marked as "not selected") for operation selection in Figure 22 One operational difference of the alternative embodiment is that the positive voltage for erasing the memory cell 76 is applied to the erase gate formed by the conductive material 88 block, rather than to the word gate line formed by the conductive spacer 66e.

[0036] It should be understood that the claims are not limited to the embodiments described above and shown herein, but cover any and all variations within the scope of any claim. For example, the references herein to embodiments and examples of the present invention are not intended to limit the scope of any claim or claim item, but only to refer to one or more features that may be covered by one or more of these claims. The examples of materials, processes, and values described above are merely examples and should not be considered as limiting the claims. Additionally, it is apparent from the claims and the specification that not all method steps need to be performed in the exact order shown or claimed, but rather in any order that allows for the proper formation of the memory device of the present invention. Finally, a single material layer may be formed as multiple such or similar material layers, and vice versa.

[0037] It should be noted that, as used herein, the terms "above" and "on" both inclusively include "directly on" (with no intervening material, element, or space therebetween) and "indirectly on" (with intervening material, element, or space therebetween). Similarly, the term "adjacent" includes "directly adjacent" (with no intervening material, element, or space therebetween) and "indirectly adjacent" (with intervening material, element, or space therebetween), "mounted to" includes "directly mounted to" (with no intervening material, element, or space therebetween) and "indirectly mounted to" (with intervening material, element, or space therebetween), and "electrically coupled to" includes "directly electrically coupled to" (with no intervening material or element electrically connecting the elements therebetween) and "indirectly electrically coupled to" (with intervening material or element electrically connecting the elements therebetween). For example, forming an element "above a substrate" may include forming the element directly on the substrate with no intervening material / element therebetween, and forming the element indirectly on the substrate with one or more intervening materials / elements therebetween.

Claims

1. A method of forming a memory device, comprising: forming a first insulating layer on an upper surface of a semiconductor substrate; forming a first conductive layer on the first insulating layer; forming a second insulating layer on the first conductive layer; forming a trench in the second insulating layer, the trench exposing an upper surface portion of the first conductive layer; performing an oxidation process and an angled etching process to re - shape the upper surface portion of the first conductive layer from a planar shape to a concave shape at a bottom of the trench; forming a third insulating layer on the re - shaped upper surface portion of the first conductive layer at the bottom of the trench; forming conductive spacers in the trench and on the third insulating layer; removing a portion of the first conductive layer, leaving a floating gate of the first conductive layer, the floating gate being located below the conductive spacers and including the upper surface portion having a concave shape that terminates at a side surface of the floating gate at a sharp edge, wherein the conductive spacers include a lower surface that: faces the upper surface portion of the floating gate, has a shape that matches the concave shape of the upper surface portion of the floating gate, and is insulated from the upper surface portion of the floating gate by a portion of the third insulating layer having a uniform thickness; forming a word - line gate that is laterally adjacent and insulated from the floating gate; and forming spaced - apart source and drain regions in the semiconductor substrate, wherein a channel region of the semiconductor substrate extends between the source and drain regions, wherein the floating gate is disposed above and insulated from a first portion of the channel region to control conductivity of the first portion of the channel region, and wherein the word - line gate is disposed above and insulated from a second portion of the channel region to control conductivity of the second portion of the channel region; wherein the word - line gate includes a portion that is at least partially disposed above the floating gate and includes a notch facing the sharp edge of the floating gate, and wherein the portion of the word - line gate that is at least partially disposed above the floating gate is also at least partially disposed above the conductive spacers.

2. The method according to claim 1, wherein performing the oxidation process and the angled etching process further includes performing the oxidation process before performing the angled etching process.

3. The method according to claim 1, wherein performing the oxidation process and the angled etching process further includes performing the oxidation process after performing the angled etching process.

4. The method according to claim 1, wherein the forming of the word - line gate comprises: forming a second conductive layer above the semiconductor substrate, the floating gate, and the conductive spacers and insulating the second conductive layer from the semiconductor substrate, the floating gate, and the conductive spacers; forming a photoresist block on the second conductive layer and above the sharp edge; and Etching is performed to remove portions of the second conductive layer, leaving a first portion of the second conductive layer that is laterally adjacent to and insulated from the floating gate, and a second portion of the second conductive layer that is at least partially located above the floating gate.

5. A method of forming a memory device, comprising: forming a first insulating layer on an upper surface of a semiconductor substrate; forming a first conductive layer on the first insulating layer; forming a second insulating layer on the first conductive layer; forming a trench in the second insulating layer, the trench exposing an upper surface portion of the first conductive layer; performing an oxidation process and an angled etching process to re-form the upper surface portion of the first conductive layer from a planar shape to a concave shape at the bottom of the trench; forming a third insulating layer on the re-formed upper surface portion of the first conductive layer at the bottom of the trench; forming conductive spacers in the trench and on the third insulating layer; removing portions of the first conductive layer, leaving a floating gate of the first conductive layer, the floating gate being located below the conductive spacers and including the upper surface portion having a concave shape that terminates at a side surface of the floating gate at a sharp edge, wherein the conductive spacers include a lower surface that: faces the upper surface portion of the floating gate, has a shape that matches the concave shape of the upper surface portion of the floating gate, and is insulated from the upper surface portion of the floating gate by a portion of the third insulating layer having a uniform thickness; forming a word line gate that is laterally adjacent to and insulated from the floating gate; forming spaced-apart source and drain regions in the semiconductor substrate, wherein a channel region of the semiconductor substrate extends between the source and drain regions, wherein the floating gate is disposed above and insulated from a first portion of the channel region for controlling conductivity of the first portion of the channel region, and wherein the word line gate is disposed above and insulated from a second portion of the channel region for controlling conductivity of the second portion of the channel region; and forming a conductive material block above the floating gate and the conductive spacers and insulating the conductive material block from the floating gate and the conductive spacers, wherein the conductive material block includes a notch facing the sharp edge of the floating gate, and wherein the conductive material block is also at least partially disposed above the word line gate.

6. A memory cell, comprising: spaced-apart source and drain regions located in a semiconductor substrate, wherein a channel region of the semiconductor substrate extends between the source and drain regions; a floating gate disposed above and insulated from a first portion of the channel region for controlling conductivity of the first portion of the channel region, wherein the floating gate includes an upper surface having a concave shape that terminates at a side surface of the floating gate at a sharp edge; a word line gate, the word line gate comprising: A first portion, the first portion being disposed over a second portion of the channel region and insulated from the second portion for controlling the conductivity of the second portion of the channel region, A second portion, the second portion being at least partially disposed over the floating gate, and A notch, the notch facing the sharp edge of the floating gate; And A coupling gate, the coupling gate being disposed over the floating gate and insulated from the floating gate, wherein the coupling gate includes a lower surface that: Faces the upper surface of the floating gate, Has a shape matching the concave shape of the upper surface of the floating gate, and Is insulated from the upper surface of the floating gate by an insulating layer of uniform thickness; Wherein the second portion of the word line gate is also at least partially disposed over the coupling gate.

7. A memory cell, Comprising: Spaced-apart source and drain regions, the spaced-apart source and drain regions being located in a semiconductor substrate, wherein a channel region of the semiconductor substrate extends between the source region and the drain region; A floating gate, the floating gate being disposed over a first portion of the channel region and insulated from the first portion for controlling the conductivity of the first portion of the channel region, wherein the floating gate includes an upper surface having a concave shape that terminates at a side surface of the floating gate at a sharp edge; A word line gate, the word line gate being disposed over a second portion of the channel region and insulated from the second portion for controlling the conductivity of the second portion of the channel region, A coupling gate, the coupling gate being disposed over the floating gate and insulated from the floating gate, wherein the coupling gate includes a lower surface that: Faces the upper surface of the floating gate, Has a shape matching the concave shape of the upper surface of the floating gate, and Is insulated from the upper surface of the floating gate by an insulating layer of uniform thickness; And An erase gate, the erase gate being disposed over the floating gate and the coupling gate and insulated from the floating gate and the coupling gate, and including a notch facing the sharp edge of the floating gate, wherein the erase gate is also at least partially disposed over the word line gate.

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