Fan-out packaging structure and method for preparing the same

Abstract

The embodiments of the present invention provide a fan-out type packaging structure and a method for preparing the fan-out type packaging structure, which relate to the field of semiconductor packaging technology. The fan-out type packaging structure includes a chip, a first plastic package, a second plastic package, a fan-out circuit layer and a solder ball. Compared with the prior art, the present invention utilizes a first buffer block to achieve stress elimination of the first plastic package, which can play a good stress release role, solve the problem of warping of the first plastic package, and at the same time achieve buffering in the drop test. When the cutter enters the rigid first plastic package during cutting, the lateral and longitudinal torsion can be reduced, the pulling of the wiring layer can be reduced, and the problem of the wiring layer and the metal layer falling off due to pulling can be avoided. In addition, by the separate arrangement of the first plastic package and the second plastic package, the layering of the plastic package structure is achieved, so that it is only necessary to groove and fill in the first plastic package to form the first buffer block, which reduces the groove depth and makes the stress release effect better.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a fan-out packaging structure and a method for preparing the fan-out packaging structure. Background Art

[0002] With the rapid development of the semiconductor industry, fan-out wafer-level packaging (FOWLP) has become widely adopted. Individual chips are typically cut from a wafer and then packaged onto a carrier wafer. Its main advantages include high-density integration, compact packaged products, superior performance, and high signal transmission frequencies. Fan-out technology primarily enables multi-pin outputs and minimizes the spacing between output pins. This often requires a larger package area to accommodate multiple chips. Furthermore, fan-out wafer chip packaging is prone to plastic warpage. Furthermore, as the thickness of fan-out wafer packaging decreases, the warpage of the plastic package increases, making it difficult to achieve structural balance. Summary of the Invention

[0003] The objects of the present invention include, for example, providing a fan-out packaging structure and a method for preparing a fan-out packaging structure, which can play a good role in releasing the stress of the plastic package, solve the problem of warping of the plastic package, and at the same time can achieve buffering during drop testing, and can reduce the pulling between the plastic package and the wiring layer during cutting, avoiding the problem of the wiring layer and the metal layer falling off due to pulling.

[0004] The embodiments of the present invention can be implemented as follows:

[0005] In a first aspect, the present invention provides a fan-out packaging structure, comprising:

[0006] chip;

[0007] a first plastic package partially covering the chip;

[0008] A second plastic package body is provided on one side of the first plastic package body and partially covers the chip;

[0009] A fan-out circuit layer provided on one side of the chip and electrically connected to the chip;

[0010] and, a solder ball disposed on a side of the fan-out circuit layer away from the chip and electrically connected to the fan-out circuit layer;

[0011] The interface between the first plastic package body and the second plastic package body extends to the side wall or surface of the chip so that the chip is embedded between the first plastic package body and the second plastic package body, and a plurality of first buffer blocks are provided in the first plastic package body. The first buffer blocks pass through the first plastic package body and contact the second plastic package body to buffer the structural stress generated in the first plastic package body.

[0012] In an optional embodiment, the fan-out circuit layer is arranged on a side of the first plastic package body away from the second plastic package body, a solder pad is provided on one side surface of the chip, the solder pad is exposed to the first plastic package body and is electrically connected to the fan-out circuit layer, and the end of the first buffer block away from the second plastic package body is in contact with the fan-out circuit layer.

[0013] In an optional embodiment, the first buffer block is in an inverted T-shape, and the width of the first buffer block at one end close to the second plastic packaging body is greater than the width of the first buffer block at one end away from the second plastic packaging body.

[0014] In an optional embodiment, a plurality of second buffer blocks are further provided in the first plastic packaging body, the second buffer blocks are spaced apart from the first buffer blocks, and the second buffer blocks pass through the first plastic packaging body and contact the second plastic packaging body.

[0015] In an optional embodiment, the second buffer block is T-shaped, and the width of the second buffer block at one end close to the second plastic packaging body is smaller than the width of the second buffer block at one end away from the second plastic packaging body.

[0016] In an optional embodiment, the interface between the first plastic package body and the second plastic package body extends to 1 / 2 of the side wall of the chip.

[0017] In an optional embodiment, the fan-out circuit layer includes a first dielectric layer, a second dielectric layer, a circuit layer and a conductive layer, the first dielectric layer is arranged on one side of the chip, the circuit layer is embedded in the first dielectric layer and is electrically connected to the chip, the second dielectric layer is arranged on a side of the first dielectric layer away from the chip, the conductive layer is embedded in the second dielectric layer and is electrically connected to the circuit layer, and the solder ball is arranged on a side of the second dielectric layer away from the first dielectric layer and is electrically connected to the conductive layer.

[0018] In an optional embodiment, a plurality of third buffer blocks are further provided in the first dielectric layer, one end of the third buffer block contacts the first plastic package body, and the other end contacts the circuit layer or the second dielectric layer, and the third buffer block is staggered with the first buffer block.

[0019] In an optional embodiment, the third buffer block is T-shaped, and the width of an end of the third buffer block close to the first plastic packaging body is smaller than the width of an end of the third buffer block away from the first plastic packaging body.

[0020] In an optional embodiment, the third buffer block is in an inverted T-shape, and the width of the end of the third buffer block close to the first plastic packaging body is greater than the width of the end of the third buffer block away from the first plastic packaging body.

[0021] In an optional embodiment, the fan-out circuit layer is arranged on a side of the second plastic package body away from the first plastic package body and is spaced apart from the first plastic package body. A solder pad is provided on the surface of the chip on a side close to the fan-out circuit layer. The fan-out circuit layer is embedded in the second plastic package body and is electrically connected to the solder pad.

[0022] In an optional embodiment, the first buffer block is T-shaped, and the width of the first buffer block at one end close to the second plastic packaging body is greater than the width of the first buffer block at one end away from the second plastic packaging body.

[0023] In an optional embodiment, a plurality of fourth buffer blocks are further provided in the first plastic packaging body. The fourth buffer blocks are in an inverted T-shape and are spaced apart from the first buffer blocks. The width of the fourth buffer block at one end close to the second plastic packaging body is smaller than the width of the fourth buffer block at one end away from the second plastic packaging body.

[0024] In an optional embodiment, the fan-out circuit layer includes a circuit layer, a conductive layer and a dielectric layer. The circuit layer is embedded in the second plastic package and electrically connected to the solder pad. The dielectric layer is arranged on a side of the second plastic package away from the first plastic package. The conductive layer is embedded in the dielectric layer and electrically connected to the circuit layer. The solder ball is arranged on a side of the dielectric layer away from the second plastic package and electrically connected to the conductive layer.

[0025] In a second aspect, the present invention provides a method for preparing a fan-out package structure, for preparing the fan-out package structure as described in any one of the aforementioned embodiments, the preparation method comprising:

[0026] providing a vehicle;

[0027] Mounting a chip on the carrier;

[0028] forming a first plastic package on the carrier, wherein the first plastic package partially covers the chip;

[0029] Cutting a groove on the first plastic package body and filling it with buffer glue to form a first buffer block;

[0030] forming a second plastic packaging body on the first plastic packaging body, wherein the second plastic packaging body partially covers the chip;

[0031] Remove the vehicle;

[0032] forming a fan-out circuit layer on one side of the chip, wherein the fan-out circuit layer is electrically connected to the chip;

[0033] forming solder balls on the fan-out circuit layer, wherein the solder balls are electrically connected to the fan-out circuit layer;

[0034] The interface between the first plastic package body and the second plastic package body extends to the side wall or surface of the chip, so that the chip is embedded between the first plastic package body and the second plastic package body. The first buffer block passes through the first plastic package body and contacts the second plastic package body to buffer the structural stress generated in the first plastic package body.

[0035] The beneficial effects of the embodiments of the present invention include, for example:

[0036] The fan-out packaging structure provided by the present invention comprises a first plastic encapsulation body that partially covers the chip, a second plastic encapsulation body that partially covers the chip is disposed on the first plastic encapsulation body, and a fan-out circuit layer and solder balls are disposed in sequence. The chip is embedded between the first plastic encapsulation body and the second plastic encapsulation body, and a plurality of first buffer blocks are disposed in the first plastic encapsulation body. The first buffer blocks penetrate the first plastic encapsulation body and contact the second plastic encapsulation body to buffer the structural stress generated in the first plastic encapsulation body. Compared with the prior art, the present invention utilizes the first buffer blocks to achieve stress relief for the first plastic encapsulation body, which can effectively relieve stress, solve the problem of warping of the first plastic encapsulation body, and provide buffering during drop tests. When cutting, the cutter can reduce lateral and longitudinal torsional forces when entering the rigid first plastic encapsulation body, reduce the pulling of the wiring layer, and avoid the problem of the wiring layer and the metal layer falling off due to pulling. Furthermore, the separate arrangement of the first and second plastic encapsulation bodies achieves a layered plastic encapsulation structure, so that only a groove needs to be opened in the first plastic encapsulation body to form the first buffer blocks, reducing the groove depth and achieving a better stress relief effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0038] Figure 1 A schematic diagram of a fan-out packaging structure provided by a first embodiment of the present invention;

[0039] Figures 2 to 8 A process flow chart of a method for preparing a fan-out packaging structure provided by the first embodiment of the present invention;

[0040] Figure 9 A schematic diagram of a fan-out packaging structure provided by a second embodiment of the present invention;

[0041] Figure 10 A schematic diagram of a fan-out packaging structure provided by a third embodiment of the present invention;

[0042] Figure 11 A schematic diagram of another fan-out packaging structure according to a third embodiment of the present invention;

[0043] Figure 12 A schematic diagram of a fan-out packaging structure provided by a fourth embodiment of the present invention;

[0044] Figure 13 A schematic diagram of another fan-out packaging structure according to a fourth embodiment of the present invention;

[0045] Figure 14 A schematic diagram of a fan-out packaging structure provided by a fifth embodiment of the present invention;

[0046] Figures 15 to 20 A process flow chart of a method for preparing a fan-out packaging structure provided in accordance with a fifth embodiment of the present invention.

[0047] Icon: 100-fan-out packaging structure; 110-chip; 111-solder pad; 130-first plastic package; 131-first buffer block; 133-second buffer block; 135-third buffer block; 137-fourth buffer block; 150-second plastic package; 170-fan-out circuit layer; 171-first dielectric layer; 173-second dielectric layer; 175-circuit layer; 177-conductive layer; 179-dielectric layer; 190-solder ball; 200-carrier. DETAILED DESCRIPTION

[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0049] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0050] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0051] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the product of the invention is usually placed when in use. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be understood as a limitation on the present invention.

[0052] In addition, the terms "first", "second", etc., if used, are merely used to distinguish and describe, and should not be understood as indicating or implying relative importance.

[0053] As disclosed in the background technology, in the prior art, for fan-out wafer packaging products, the entire chip is usually directly covered with a plastic package, and the wiring layer is completed on the plastic package. This structure is prone to the problem of plastic package warping, and the balance of the entire structure of the plastic package cannot be achieved, which affects the welding reliability of the product.

[0054] Furthermore, existing technologies have also introduced structures that incorporate a buffer layer on the chip surface. However, this structure can only balance the warpage of the chip surface, i.e., locally control the warpage, and still cannot achieve overall structural balance for the plastic package. Furthermore, the buffer layer located on the surface cannot eliminate structural stress within the chip or plastic package, and thus, it is difficult to eliminate warpage.

[0055] Moreover, if buffer columns are directly added to the entire plastic package, although some structural stress can be eliminated, a through groove needs to be opened on the plastic package, resulting in a deep groove and great difficulty in opening the groove. In addition, the buffer column runs through the entire plastic package, making it difficult to eliminate stress in a targeted manner at the stress concentration area, and thus the effect of stress release is poor.

[0056] In order to solve the above problems, the present invention provides a fan-out packaging structure and a method for preparing a fan-out packaging structure. It should be noted that the features in the embodiments of the present invention can be combined with each other without conflict.

[0057] First embodiment

[0058] See also Figure 1 This embodiment provides a fan-out packaging structure, which can effectively release the stress of the plastic package and solve the problem of warping of the plastic package. At the same time, it can achieve buffering during drop testing and reduce the pulling between the plastic package and the wiring layer during cutting, thereby avoiding the problem of the wiring layer and the metal layer falling off due to pulling.

[0059] The fan-out package structure 100 provided in this embodiment includes a chip 110, a first plastic package 130, a second plastic package 150, a fan-out circuit layer 170 and solder balls 190. The first plastic package 130 is partially wrapped around the chip 110, the second plastic package 150 is arranged on one side of the first plastic package 130 and partially wrapped around the chip 110, the fan-out circuit layer 170 is arranged on one side of the chip 110 and is electrically connected to the chip 110, and the solder balls 190 are arranged on the fan-out circuit layer 170 away from the chip. 110 and is electrically connected to the fan-out circuit layer 170, wherein the interface between the first plastic package body 130 and the second plastic package body 150 extends to the side wall or surface of the chip 110, so that the chip 110 is embedded between the first plastic package body 130 and the second plastic package body 150, and a plurality of first buffer blocks 131 are provided in the first plastic package body 130, and the first buffer blocks 131 pass through the first plastic package body 130 and contact with the second plastic package body 150, and are used to buffer the structural stress generated in the first plastic package body 130.

[0060] In this embodiment, the first buffer block 131 is made of a buffer material that can absorb the structural stress generated in the first plastic package 130 and prevent deformation. For example, the first buffer block 131 is made of a polymer composite material such as epoxy resin, polyimide, and benzocyclobutene. The material of the first buffer block 131 is different from that of the first plastic package 130, and the thermal expansion coefficient of the buffer material is smaller than that of the plastic package material, so that the first buffer block 131 deforms before the first plastic package 130, absorbs stress and prevents deformation. This embodiment uses the first buffer block 131 to eliminate stress on the first plastic package 130, which can play a good stress release role, solve the problem of warping of the first plastic package 130, and can also achieve buffering in the drop test. When the cutter enters the rigid first plastic package 130 during cutting, it can reduce the lateral and longitudinal torsional forces, reduce the pulling of the wiring layer, and avoid the problem of the wiring layer and the metal layer falling off due to pulling. Furthermore, by separately setting the first plastic package body 130 and the second plastic package body 150 , the layered plastic package structure is achieved, so that only a groove needs to be opened in the first plastic package body 130 to form the first buffer block 131 , thereby reducing the groove depth and achieving a better stress release effect.

[0061] In this embodiment, the fan-out circuit layer 170 is provided on a side of the first plastic package 130 away from the second plastic package 150. A solder pad 111 is provided on one surface of the chip 110. The solder pad 111 is exposed from the first plastic package 130 and is electrically connected to the fan-out circuit layer 170. One end of the first buffer block 131 away from the second plastic package 150 is in contact with the fan-out circuit layer 170. Specifically, the front of the chip 110 is provided with a solder pad 111. The first plastic package 130 is arranged around the chip 110 and is flush with the front of the chip 110, so that the front of the chip 110 is exposed to the first plastic package 130. When the fan-out circuit layer 170 is provided, wiring can be completed directly on the front of the first plastic package 130 and the chip 110, and the fan-out circuit layer 170 can be electrically contacted with the solder pad 111 to achieve electrical connection.

[0062] In this embodiment, the first plastic package body 130 can be formed by conventional plastic packaging technology, and can be made of materials such as silicon dioxide, or can be formed by spin spraying. The second plastic package body 150 is formed by conventional plastic packaging technology.

[0063] It should be noted that in this embodiment, the first and second plastic encapsulation bodies 130 and 150 can be made of plastic materials with different particle sizes. For example, the plastic encapsulation material in the first plastic encapsulation body 130 may have a smaller particle size, while the plastic encapsulation material in the second plastic encapsulation body 150 may have a larger particle size. This makes the second plastic encapsulation body 150 relatively less susceptible to deformation, thereby achieving a better stress relief effect. Furthermore, this can also achieve material stratification, improving the overall coherence of the second plastic encapsulation body 150 and, in turn, making the device appearance smoother. This avoids problems such as cracks, gaps, or depressions in the plastic encapsulation body caused by the first buffer block 131 penetrating the device surface.

[0064] In addition, the first plastic packaging body 130 uses a plastic packaging material with a smaller particle size, which reduces the wear of the cutter during cutting, can slow down the wear of the cutter, and increase the service life of the cutter.

[0065] In this embodiment, the first buffer block 131 is in an inverted T-shape, and the width of the first buffer block 131 at the end closest to the second plastic package 150 is greater than the width of the first buffer block 131 at the end farther from the second plastic package 150. Specifically, when preparing this structure, a carrier 200 can be used, that is, the front surface of the chip 110 is mounted on the carrier 200, and then the first plastic package 130 is prepared around the chip 110. The height of the first plastic package 130 is lower than that of the chip 110. A T-shaped groove is then opened in the first plastic package 130 and filled with buffer glue. After curing, the first buffer block 131 is formed. After the first buffer block 131 is formed, the second plastic package 150 is prepared on the first plastic package 130. The carrier 200 is then removed and the package structure is flipped over. The fan-out circuit layer 170 and solder balls 190 are prepared on the first plastic package 130, thereby making the first buffer block 131 in an inverted T-shape.

[0066] It should be noted that the first buffer block 131 here is in an inverted T-shape, and only a T-shaped slot needs to be opened when slotting. Compared with the straight slot structure, the T-shaped slot makes the slotting process more convenient and reduces the difficulty of slotting.

[0067] In other preferred embodiments of the present invention, the first buffer block 131 may also be T-shaped, so that a groove is formed in the first plastic package 130 and filled with a buffer glue before forming the fan-out circuit layer 170. In this case, the second plastic package 150 can serve as a stop layer for laser grooving, which can achieve a better grooving effect.

[0068] In this embodiment, the interface between the first plastic encapsulation body 130 and the second plastic encapsulation body 150 extends to half of the sidewall of the chip 110. Specifically, the first plastic encapsulation body 130 and the second plastic encapsulation body 150 each cover half of the sidewall of the chip 110, so that the upper half of the chip 110 is covered by the first plastic encapsulation body 130 and the lower half is covered by the second plastic encapsulation body 150. The second plastic encapsulation body 150 completely covers the back side of the chip 110, thereby providing good protection for the chip 110.

[0069] Fan-out circuit layer 170 includes a first dielectric layer 171, a second dielectric layer 173, a circuit layer 175, and a conductive layer 177. First dielectric layer 171 is disposed on one side of chip 110. Circuit layer 175 is embedded in first dielectric layer 171 and electrically connected to chip 110. Second dielectric layer 173 is disposed on a side of first dielectric layer 171 away from chip 110. Conductive layer 177 is embedded in second dielectric layer 173 and electrically connected to circuit layer 175. Solder balls 190 are disposed on a side of second dielectric layer 173 away from first dielectric layer 171 and electrically connected to conductive layer 177. Specifically, first dielectric layer 171 and second dielectric layer 173 are both made of dielectric materials, such as silicon nitride, silicon oxynitride, polyimide, or benzocyclobutene. Circuit layer 175 and conductive layer 177 are both made of conductive materials, such as at least one of copper, silver, titanium, and tungsten. During actual preparation, the first dielectric layer 171 and the second dielectric layer 173 can be formed by a physical vapor deposition process (PVD) or a chemical vapor deposition process (CVD), and the circuit layer 175 and the conductive layer 177 can be formed by electroplating, and the formed conductive layer 177 is exposed on the second dielectric layer 173, and the solder ball 190 can be formed on the conductive layer 177 by a ball planting process.

[0070] It should be noted that before forming the first dielectric layer 171, the first buffer block 131 in this embodiment is exposed from the first plastic package 130, and the material of the first buffer block 131 is different from the material of the first plastic package 130. When actually preparing the first dielectric layer 171 and the circuit layer 175, the process accuracy of the metal layer can be improved, which is more conducive to the smooth completion of the back wiring process of the chip 110.

[0071] In this embodiment, first buffer block 131 is located below circuit layer 175 and contacts first dielectric layer 171. This reduces lateral and longitudinal torsional forces when the cutter enters first plastic package body 130 during the cutting process, reduces pulling on first dielectric layer 171, and prevents separation of first dielectric layer 171 from circuit layer 175. Furthermore, it cushions the impact of drop testing on upper solder balls 190, relieves stress, and improves solder ball 190 reliability.

[0072] This embodiment further provides a method for preparing a fan-out package structure 100, which is used to prepare the fan-out package structure 100 as described above, wherein the method comprises the following steps:

[0073] S1: Mounting the chip 110 on the carrier 200 .

[0074] See also Figure 2Specifically, a substrate or carrier plate is first provided as a carrier 200. Adhesive is spin-sprayed onto the carrier 200 to form a film layer. The chip 110 is then mounted on the film layer, and the film layer is used to bond the carrier 200 to the chip 110. The film layer can be separated from the carrier 200 by irradiation with UV (ultraviolet) light and can be made of a polymer material such as epoxy resin. The carrier 200 can be made of glass, silicon nitride, or metal, serving as a support.

[0075] It should be noted that the front side of the chip 110 is mounted on the adhesive film layer, that is, the side of the chip 110 having the pad 111 is mounted on the adhesive film layer of the carrier 200 .

[0076] S2 : forming a first plastic package 130 on the carrier 200 , wherein the first plastic package 130 partially covers the chip 110 .

[0077] See also Figure 3 Specifically, after the chip 110 is mounted, the bottom of the chip 110 is again sealed using the plastic sealing process to form a first plastic sealing body 130. The height of the first plastic sealing body 130 should be lower than the surface height of the chip 110. Preferably, the height of the first plastic sealing body 130 should be half of the chip 110.

[0078] S3 : Grooving the first plastic package body 130 and filling it with buffer glue to form a first buffer block 131 .

[0079] See also Figure 4 Specifically, a T-shaped groove is formed on the first plastic package body 130 by laser grooving. During laser grooving, a large groove is first made, and then a small groove is made in the large groove, thereby forming a T-shaped groove. Then, the groove is filled with buffer glue by printing or dispensing, thereby forming a first buffer block 131. The thermal expansion coefficient of its material characteristics is smaller than the thermal expansion coefficient of the plastic package body. It needs to deform before the first plastic package body 130 to absorb the structural stress of the first plastic package body 130 to prevent deformation. The buffer glue can be a polymer composite material such as epoxy resin, polyimide, and benzocyclobutene.

[0080] S4 : forming a second plastic package 150 on the first plastic package 130 , wherein the second plastic package 150 partially covers the chip 110 .

[0081] See also Figure 5 Specifically, after the first buffer block 131 is formed, the second plastic encapsulation body 150 can be formed on the first plastic encapsulation body 130 using the molding process again to encapsulate the exposed chip 110 structure. The first buffer block 131 provided on the first plastic encapsulation body 130 can reduce the structural stress generated after the second plastic encapsulation body 150 is cured, thus preventing the first plastic encapsulation body 130 from warping due to the curing of the second plastic encapsulation body 150.

[0082] In the plastic package structure formed in this embodiment, the interface between the first plastic package body 130 and the second plastic package body 150 extends to the sidewall or surface of the chip 110, so that the chip 110 is embedded between the first plastic package body 130 and the second plastic package body 150. The first buffer block 131 passes through the first plastic package body 130 and contacts the second plastic package body 150 to buffer the structural stress generated in the first plastic package body 130.

[0083] S5: Remove the carrier 200.

[0084] See also Figure 6 Specifically, carrier 200 is peeled off using UV light, exposing the front surfaces of first plastic encapsulation body 130 and chip 110. The encapsulated package structure is then flipped over, with the front surfaces of first plastic encapsulation body 130 and chip 110 facing upward. The presence of first buffer block 131 prevents significant warping after carrier 200 is removed, effectively mitigating warping.

[0085] S6 : forming a fan-out circuit layer 170 on one side of the chip 110 , wherein the fan-out circuit layer 170 is electrically connected to the chip 110 .

[0086] See also Figure 7 Specifically, a dielectric material can be spin-coated on the front surface of the first plastic package 130 and the chip 110. Alternatively, the dielectric material can be deposited using physical vapor deposition (PVD) or chemical vapor deposition (CVD) to form a first dielectric layer 171. The first dielectric layer 171 is then patterned, exposed and developed to form patterned openings. A metal layer, such as a copper layer, is then electroplated within the openings to form a circuit layer 175. Circuit layer 175 needs to be aligned with the pads 111, thereby electrically connecting them. A second dielectric layer 173 is then formed on circuit layer 175. Slots / holes are then formed in the second dielectric layer 173, and a metal layer, such as a copper layer, is electroplated within the openings to form a conductive layer 177. A UBM layer is then formed on conductive layer 177 to improve solderability of solder balls 190. The dielectric material can be silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, or the like.

[0087] S7 : forming solder balls 190 on the fan-out circuit layer 170 , and electrically connecting the solder balls 190 to the fan-out circuit layer 170 .

[0088] See also Figure 8Specifically, after forming conductive layer 177, a ball planting process can be performed on the UBM layer of conductive layer 177 using a stencil printing method or a ball planting method to form solder balls 190. Solder balls 190 can be made of materials such as SnAg, SnAgCu, etc. After forming solder balls 190, they can be cut to form the final product. The first buffer block 131 is designed in the middle layer to reduce the pulling of circuit layer 175 during cutting.

[0089] In summary, the fan-out package structure 100 and its preparation method provided in this embodiment are as follows: a first plastic package 130 partially encapsulating a chip 110 is provided; a second plastic package 150 partially encapsulating the chip 110 is provided on the first plastic package 130; a fan-out circuit layer 170 and solder balls 190 are provided in sequence; the chip 110 is embedded between the first plastic package 130 and the second plastic package 150; and a plurality of first buffer blocks 131 are provided in the first plastic package 130. The first buffer blocks 131 pass through the first plastic package 130 and contact the second plastic package 150 to buffer the structural stress generated in the first plastic package 130. Compared with the prior art, the present invention utilizes the first buffer blocks 131 to achieve stress relief for the first plastic package 130, which can effectively relieve stress, solve the problem of warping of the first plastic package 130, and achieve buffering in drop tests. When the cutter enters the rigid first plastic encapsulation body 130 during cutting, it reduces lateral and longitudinal torsional forces, reduces pulling on the wiring layer, and prevents the wiring layer and metal layer from separating due to pulling. Furthermore, the separate configuration of the first plastic encapsulation body 130 and the second plastic encapsulation body 150 achieves a layered plastic encapsulation structure, requiring only a slot in the first plastic encapsulation body 130 to form the first buffer block 131. This reduces the slot depth and improves stress relief.

[0090] Second embodiment

[0091] See also Figure 9 This embodiment provides a fan-out packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, please refer to the corresponding content in the first embodiment.

[0092] In this embodiment, the fan-out package structure 100 includes a chip 110, a first plastic package 130, a second plastic package 150, a fan-out circuit layer 170 and solder balls 190. The first plastic package 130 is partially wrapped around the chip 110, the second plastic package 150 is arranged on one side of the first plastic package 130 and partially wrapped around the chip 110, the fan-out circuit layer 170 is arranged on one side of the chip 110 and is electrically connected to the chip 110, and the solder balls 190 are arranged on the fan-out circuit layer 170 away from the chip. 110 and is electrically connected to the fan-out circuit layer 170, wherein the interface between the first plastic package body 130 and the second plastic package body 150 extends to the side wall or surface of the chip 110, so that the chip 110 is embedded between the first plastic package body 130 and the second plastic package body 150, and a plurality of first buffer blocks 131 are provided in the first plastic package body 130, and the first buffer blocks 131 pass through the first plastic package body 130 and contact with the second plastic package body 150, and are used to buffer the structural stress generated in the first plastic package body 130.

[0093] In this embodiment, a plurality of second buffer blocks 133 are further disposed within the first plastic packaging body 130. The second buffer blocks 133 are spaced apart from the first buffer blocks 131, and the second buffer blocks 133 pass through the first plastic packaging body 130 and contact the second plastic packaging body 150. Specifically, the size of the second buffer blocks 133 can be the same as or different from that of the first buffer blocks 131.

[0094] In this embodiment, the second buffer block 133 is T-shaped, and the width of the second buffer block 133 at the end closest to the second plastic package 150 is smaller than the width of the second buffer block 133 at the end farther from the second plastic package 150. Specifically, the first buffer block 131 and the second buffer block 133 are arranged in an inverted manner. During actual preparation, the second buffer block 133 can be formed by cutting a groove in the first plastic package 130 and filling it with buffer glue before forming the fan-out circuit layer 170. The provision of the second buffer block 133 can further enhance the buffering effect of the plastic package structure. Moreover, the placement of the second buffer block 133 in the opposite direction of the first buffer block 131 can provide more directions for stress release and achieve a better buffering effect. Furthermore, the provision of the second buffer block 133 increases the contact area between the second buffer block 133 and the first dielectric layer 171, thereby resolving the stress release problem of the circuit layer 175 on the first dielectric layer 171.

[0095] Third embodiment

[0096] See also Figure 10 The fan-out packaging structure provided in this embodiment has the same basic structure, principle and technical effects as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, please refer to the corresponding content in the first embodiment.

[0097] In this embodiment, the fan-out package structure 100 includes a chip 110, a first plastic package 130, a second plastic package 150, a fan-out circuit layer 170 and a solder ball 190. The first plastic package 130 is partially wrapped around the chip 110, the second plastic package 150 is arranged on one side of the first plastic package 130 and partially wrapped around the chip 110, the fan-out circuit layer 170 is arranged on one side of the chip 110 and is electrically connected to the chip 110, and the solder ball 190 is arranged on the fan-out circuit layer 170 away from the chip 110 and is electrically connected to the fan-out circuit layer 170, wherein the interface between the first plastic package body 130 and the second plastic package body 150 extends to the side wall or surface of the chip 110, so that the chip 110 is embedded between the first plastic package body 130 and the second plastic package body 150, and a plurality of first buffer blocks 131 are provided in the first plastic package body 130, and the first buffer blocks 131 pass through the first plastic package body 130 and contact with the second plastic package body 150, and are used to buffer the structural stress generated in the first plastic package body 130.

[0098] The fan-out circuit layer 170 includes a first dielectric layer 171, a second dielectric layer 173, a circuit layer 175 and a conductive layer 177. The first dielectric layer 171 is arranged on one side of the chip 110, the circuit layer 175 is embedded in the first dielectric layer 171 and is electrically connected to the chip 110, the second dielectric layer 173 is arranged on a side of the first dielectric layer 171 away from the chip 110, the conductive layer 177 is embedded in the second dielectric layer 173 and is electrically connected to the circuit layer 175, and the solder ball 190 is arranged on a side of the second dielectric layer 173 away from the first dielectric layer 171 and is electrically connected to the conductive layer 177.

[0099] In this embodiment, a plurality of third buffer blocks 135 are further disposed in the first dielectric layer 171. One end of the third buffer block 135 contacts the first plastic package 130, and the other end contacts the circuit layer 175 or the second dielectric layer 173. The third buffer blocks 135 are staggered relative to the first buffer block 131. Specifically, the third buffer block 135 is disposed below the circuit layer 175, and the upper and lower ends of the third buffer block 135 contact the circuit layer 175 and the first plastic package 130, respectively. This further prevents the circuit layer 175 from being pulled during cutting and absorbs the structural stress generated in the fan-out circuit layer 170. This advantageously mitigates the impact stress during a drop test and reduces the impact force of the upper solder ball 190 during a drop test, thereby relieving stress, improving the reliability of the solder ball 190 connection, and ensuring device quality.

[0100] In this embodiment, the first buffer block 131 is T-shaped, meaning that the width of the first buffer block 131 at the end closest to the second plastic encapsulation body 150 is greater than the width of the first buffer block 131 at the end further away from the second plastic encapsulation body 150. In actual manufacturing, the first buffer block 131 can be formed by cutting a groove in the first plastic encapsulation body 130 after removing the carrier 200 and then filling it with a buffering glue. Furthermore, the particles of the molding compound of the second plastic encapsulation body 150 are larger than those of the first plastic encapsulation body 130, making the second plastic encapsulation body 150 less susceptible to the effects of the laser. Therefore, the second plastic encapsulation body 150 can be used as a stop layer for laser grooving, resulting in a better grooving effect.

[0101] It should be noted that in this embodiment, the third buffer block 135 can be formed by cutting a groove in the first dielectric layer 171 and filling it with buffer glue before forming the circuit layer 175. Furthermore, the third buffer block 135 is staggered with the first buffer block 131 to further expand the buffering range and effectively enhance the buffering effect of the entire structure.

[0102] In this embodiment, the third buffer block 135 is T-shaped, and the width of the end of the third buffer block 135 close to the first plastic package body 130 is smaller than the width of the end of the third buffer block 135 away from the first plastic package body 130. Therefore, the placement direction of the third buffer block 135 is the same as the placement direction of the first buffer block 131.

[0103] Of course, see Figure 11 In other preferred embodiments of the present invention, the third buffer block 135 may also be in an inverted T-shape, and the width of the end of the third buffer block 135 close to the first plastic packaging body 130 is greater than the width of the end of the third buffer block 135 away from the first plastic packaging body 130, so that the placement direction of the third buffer block 135 is opposite to the placement direction of the first buffer block 131, so as to better achieve the stress release function.

[0104] In addition, in other preferred embodiments of the present invention, the first buffer block 131 may also be in an inverted T-shape, that is, the placement of the first buffer block 131 is the same as that of the first embodiment. The specific placement of the first buffer block 131 and the third buffer block 135 is not specifically limited here and can be freely combined as needed.

[0105] The fan-out packaging structure 100 provided in this embodiment adopts a double-layer buffer block structure. A third buffer block 135 is added to the first dielectric layer 171 to reduce the pulling of the circuit layer 175 and avoid the problem of the circuit layer 175 and the conductive layer 177 falling off. It can also absorb the structural stress generated in the fan-out circuit layer 170, which is beneficial for alleviating the impact stress during the drop test and reducing the impact force of the upper solder ball 190 during the drop test, thereby relieving stress, improving the reliability of the connection of the solder ball 190, and ensuring the quality of the device.

[0106] Fourth embodiment

[0107] See also Figure 12 This embodiment provides a fan-out packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, please refer to the corresponding content in the first embodiment.

[0108] The fan-out package structure 100 includes a chip 110, a first plastic package 130, a second plastic package 150, a fan-out circuit layer 170, and solder balls 190. The first plastic package 130 is partially wrapped around the chip 110, the second plastic package 150 is arranged on one side of the first plastic package 130, and partially wrapped around the chip 110, the fan-out circuit layer 170 is arranged on one side of the chip 110 and is electrically connected to the chip 110, and the solder balls 190 are arranged on the fan-out circuit layer 170 away from the chip 110. One side, and is electrically connected to the fan-out circuit layer 170, wherein the interface between the first plastic package body 130 and the second plastic package body 150 extends to the side wall or surface of the chip 110, so that the chip 110 is embedded between the first plastic package body 130 and the second plastic package body 150, and a plurality of first buffer blocks 131 are provided in the first plastic package body 130, and the first buffer blocks 131 pass through the first plastic package body 130 and contact with the second plastic package body 150, and are used to buffer the structural stress generated in the first plastic package body 130.

[0109] In this embodiment, the fan-out circuit layer 170 is disposed on a side of the second plastic package 150 away from the first plastic package 130 and is spaced apart from the first plastic package 130. A solder pad 111 is disposed on a surface of the chip 110 on a side close to the fan-out circuit layer 170. The fan-out circuit layer 170 is embedded in the second plastic package 150 and is electrically connected to the solder pad 111. Specifically, the fan-out circuit layer 170 is disposed on a surface of the second plastic package 150, and the front surface of the chip 110 is embedded in the second plastic package 150 to achieve electrical connection with the fan-out circuit layer 170.

[0110] During actual preparation, the back side of the chip 110 can be mounted on the carrier 200 , and then the first plastic package 130 can be prepared in sequence, and then the fan-out circuit layer 170 can be prepared directly on the second plastic package 150 , and finally the carrier 200 can be removed and cut.

[0111] In this embodiment, the first buffer block 131 is T-shaped, and the width of the end of the first buffer block 131 close to the second plastic encapsulation body 150 is greater than the width of the end of the first buffer block 131 away from the second plastic encapsulation body 150. The first buffer block 131 can be formed by slotting and filling the buffer glue after the first plastic encapsulation body 130 is formed. The wider end of the first buffer block 131 contacts the second plastic encapsulation body 150, thereby improving the stress relief effect.

[0112] In this embodiment, the first plastic package body 130 is further provided with a plurality of fourth buffer blocks 137. These fourth buffer blocks 137 are in an inverted T-shape and are spaced apart from the first buffer blocks 131. The width of the fourth buffer blocks 137 at the end closest to the second plastic package body 150 is smaller than the width of the end further away from the second plastic package body 150. The inverse placement of the fourth buffer blocks 137 can mitigate stress in various directions. The first buffer blocks 131 can address external stress relief, while the second buffer blocks 133 can address internal stress relief.

[0113] In this embodiment, the fan-out circuit layer 170 includes a circuit layer 175, a conductive layer 177 and a dielectric layer 179. The circuit layer 175 is embedded in the second plastic package 150 and is electrically connected to the solder pad 111. The dielectric layer 179 is arranged on the side of the second plastic package 150 away from the first plastic package 130. The conductive layer 177 is embedded in the dielectric layer 179 and is electrically connected to the circuit layer 175. The solder ball 190 is arranged on the side of the dielectric layer 179 away from the second plastic package 150 and is electrically connected to the conductive layer 177.

[0114] It should be noted that, in this embodiment, the circuit layer 175 can be realized by electroplating a metal layer after grooving the second plastic package 150 , and the circuit layer 175 contacts the pads 111 on the chip 110 , thereby achieving electrical connection.

[0115] In this embodiment, when actually preparing the aforementioned fan-out packaging structure 100, the back side of the chip 110 is first mounted on the carrier 200, and then a first plastic package body 130 is formed. The first plastic package body 130 also covers half of the chip 110, and then grooves are cut on the first plastic package body 130 and filled with buffer glue to form a first buffer block 131. Then, a second plastic package body 150 is formed on the first plastic package body 130, and then the carrier 200 is removed. After flipping, grooves are continued to be cut on the first plastic package body 130 and buffer glue is filled to form a fourth buffer block 137. Then, it is flipped again, and the circuit layer 175, the dielectric layer 179 and the conductive layer 177 are prepared on the second plastic package body 150, and finally, ball planting and cutting are completed.

[0116] See also Figure 13 In other preferred embodiments of the present invention, the first plastic package 130 can also be coated on the back of the chip 110, so that the sidewalls and front of the chip 110 are both coated in the second plastic package 150. During actual production, the first plastic package 130 can be completed on the carrier 200 first, and then the chip 110 can be mounted on the first plastic package 130. After the first buffer block 131 is formed, the second plastic package 150 can be prepared.

[0117] The fan-out package structure 100 provided in this embodiment comprises a first plastic encapsulation body 130 partially encapsulating a chip 110, a second plastic encapsulation body 150 partially encapsulating the chip 110, and a fan-out circuit layer 170 and solder balls 190. The chip 110 is embedded between the first plastic encapsulation body 130 and the second plastic encapsulation body 150. The first plastic encapsulation body 130 is provided with a plurality of first buffer blocks 131. The first buffer blocks 131 pass through the first plastic encapsulation body 130 and contact the second plastic encapsulation body 150 to buffer the structural stress generated within the first plastic encapsulation body 130. In this embodiment, the first buffer blocks 131 are used to relieve stress in the first plastic encapsulation body 130, effectively relieving stress and resolving the warping problem of the first plastic encapsulation body 130. Furthermore, by separately setting the first plastic package body 130 and the second plastic package body 150 , the layered plastic package structure is achieved, so that only a groove needs to be opened in the first plastic package body 130 to form the first buffer block 131 , thereby reducing the groove depth and achieving a better stress release effect.

[0118] Fifth embodiment

[0119] See also Figure 14 This embodiment provides a fan-out packaging structure 100, whose basic structure, principle and technical effects are the same as those of the fourth embodiment or the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the fourth embodiment or the first embodiment.

[0120] In this embodiment, the fan-out package structure 100 includes a chip 110, a first plastic package 130, a second plastic package 150, a fan-out circuit layer 170 and a solder ball 190. The first plastic package 130 is partially wrapped around the chip 110, the second plastic package 150 is arranged on one side of the first plastic package 130 and partially wrapped around the chip 110, the fan-out circuit layer 170 is arranged on one side of the chip 110 and is electrically connected to the chip 110, and the solder ball 190 is arranged on the fan-out circuit layer 170 away from the chip 110 and is electrically connected to the fan-out circuit layer 170, wherein the interface between the first plastic package body 130 and the second plastic package body 150 extends to the side wall or surface of the chip 110, so that the chip 110 is embedded between the first plastic package body 130 and the second plastic package body 150, and a plurality of first buffer blocks 131 are provided in the first plastic package body 130, and the first buffer blocks 131 pass through the first plastic package body 130 and contact with the second plastic package body 150, and are used to buffer the structural stress generated in the first plastic package body 130.

[0121] In this embodiment, the fan-out circuit layer 170 is disposed on a side of the second plastic package 150 away from the first plastic package 130 and is spaced apart from the first plastic package 130. A solder pad 111 is disposed on a surface of the chip 110 on a side close to the fan-out circuit layer 170. The fan-out circuit layer 170 is embedded in the second plastic package 150 and is electrically connected to the solder pad 111. Specifically, the fan-out circuit layer 170 is disposed on a surface of the second plastic package 150, and the front surface of the chip 110 is embedded in the second plastic package 150 to achieve electrical connection with the fan-out circuit layer 170.

[0122] In this embodiment, the first buffer block 131 is in an inverted T-shape, and the width of the first buffer block 131 at one end close to the second plastic package body 150 is smaller than the width of the first buffer block 131 at one end away from the second plastic package body 150 .

[0123] In this embodiment, fan-out circuit layer 170 includes a first dielectric layer 171, a second dielectric layer 173, a circuit layer 175, and a conductive layer 177. First dielectric layer 171 is disposed on one side of chip 110, circuit layer 175 is embedded in first dielectric layer 171 and electrically connected to chip 110, second dielectric layer 173 is disposed on a side of first dielectric layer 171 away from chip 110, conductive layer 177 is embedded in second dielectric layer 173 and electrically connected to circuit layer 175, and solder balls 190 are disposed on a side of second dielectric layer 173 away from first dielectric layer 171 and electrically connected to conductive layer 177. Specifically, first dielectric layer 171 is disposed on second plastic package 150.

[0124] This embodiment further provides a method for preparing a fan-out package structure, which is used to prepare the aforementioned fan-out package structure. The method includes the following steps:

[0125] S1: Mounting the chip 110 on a carrier.

[0126] Please continue to see Figure 2 Specifically, the chip 110 is mounted on the carrier 200 , wherein the front side of the chip 110 is mounted facing downward, so that the front side (the side surface with the pad) of the chip 110 is attached to the carrier 200 .

[0127] S2: forming a second plastic package 150 on the carrier 200 , wherein the second plastic package 150 partially covers the chip.

[0128] See also Figure 15 Specifically, the second plastic package body 150 is prepared on the carrier 200 using a plastic packaging process. In this embodiment, the height of the second plastic package body 150 is half the height of the chip 110 .

[0129] S3 : forming the first plastic packaging body 130 on the second plastic packaging body 150 .

[0130] See also Figure 16 Specifically, after completing the second plastic package 150 , the plastic package process can be continued to be used to complete the preparation of the first plastic package 130 on the second plastic package 150 , wherein the first plastic package 130 can be wrapped around the chip 110 and cover the back of the chip 110 .

[0131] S4: Grooving the first plastic package body 130 and filling it with buffer glue.

[0132] See also Figure 17 Specifically, a T-shaped groove is opened on the first plastic package body 130 and filled with buffer material. When laser grooving, a large groove is opened first, and then a small groove is opened in the large groove to form a T-shaped groove. Then, the groove is filled with buffer glue by printing or dispensing.

[0133] S5: Grinding the first plastic package 130 to expose the back side of the chip 110 .

[0134] See also Figure 18 Specifically, the back side of the chip 110 is used as a grinding stop layer, and part of the T-groove is removed. After the buffer glue in the remaining T-groove is cured, the first buffer block 131 is formed. The back side of the chip 110 is exposed, thereby increasing the heat dissipation effect.

[0135] Moreover, since a first buffer block 131 formed of a buffer glue is provided in the first plastic package body 130, it can buffer the structural stress during the grinding process, thereby avoiding cracking of the first plastic package body 130 during the grinding process, and avoiding the material delamination phenomenon caused by the influence of stress on the first plastic package body 130.

[0136] In other preferred embodiments of the present invention, the first plastic package body 130 may not be ground, so that the first plastic package body 130 is directly covered on the back side of the chip 110 to play a protective role.

[0137] S6: Remove the carrier 200.

[0138] See also Figure 19 Specifically, the carrier 200 is peeled off by UV light irradiation, so that the second plastic package 150 and the front surface of the chip 110 are exposed to the outside.

[0139] S7 : forming a fan-out circuit layer 170 on one side of the chip 110 , wherein the fan-out circuit layer 170 is electrically connected to the chip 110 .

[0140] See also Figure 20Specifically, a dielectric material can be spin-coated on the front surface of the second plastic package 150 and the chip 110. Alternatively, the dielectric material can be deposited using physical vapor deposition (PVD) or chemical vapor deposition (CVD) to form a first dielectric layer 171. The first dielectric layer 171 is then patterned, exposed and developed to form patterned openings. A metal layer, such as a copper layer, is then electroplated within the openings to form a circuit layer 175. Circuit layer 175 needs to be aligned with the pads 111, thereby electrically connecting circuit layer 175 to pads 111. A second dielectric layer 173 is then formed on circuit layer 175. Slots / holes are then formed in second dielectric layer 173, and a metal layer, such as a copper layer, is electroplated within the openings to form a conductive layer 177. A UBM layer is then formed on conductive layer 177 to improve solderability of solder balls 190. The dielectric material can be silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, or the like.

[0141] S8 : forming solder balls 190 on the fan-out circuit layer 170 , where the solder balls 190 are electrically connected to the fan-out circuit layer 170 .

[0142] Specifically, after forming conductive layer 177, a ball planting process can be performed on the UBM layer of conductive layer 177 using a stencil printing method or a ball planting method to form solder balls 190. Solder balls 190 can be made of materials such as SnAg, SnAgCu, etc. After forming solder balls 190, they can be cut to form the final product. The first buffer block 131 is designed in the middle layer to reduce the pulling of circuit layer 175 during cutting.

[0143] In summary, in this embodiment, the first plastic package 130 exposes the chip 110 by adopting the grinding process, thereby enhancing the heat dissipation effect of the chip 110 .

[0144] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A fan-out packaging structure, characterized in that: include: chip; a first plastic package partially covering the chip; A second plastic package body is provided on one side of the first plastic package body and partially covers the chip; A fan-out circuit layer provided on one side of the chip and electrically connected to the chip; and, a solder ball disposed on a side of the fan-out circuit layer away from the chip and electrically connected to the fan-out circuit layer; The interface between the first plastic package and the second plastic package extends to the side wall of the chip, so that the chip is embedded between the first plastic package and the second plastic package. The first plastic package surrounds the chip and is flush with the front surface of the chip. The first plastic package is provided with a plurality of first buffer blocks, which pass through the first plastic package and contact the second plastic package to buffer the structural stress generated in the first plastic package. The first buffer block is made of a buffer material, the thermal expansion coefficient of the buffer material is smaller than the thermal expansion coefficient of the plastic packaging material, and the particle size of the plastic packaging material in the first plastic packaging body is smaller than the particle size of the plastic packaging material in the second plastic packaging body; The first buffer block is in an inverted T-shape, and the width of the first buffer block at one end close to the second plastic sealing body is greater than the width of the first buffer block at one end away from the second plastic sealing body; a plurality of second buffer blocks are further provided in the first plastic sealing body, the second buffer blocks are spaced apart from the first buffer blocks, and the second buffer blocks pass through the first plastic sealing body and contact the second plastic sealing body; the second buffer block is in a T-shape, and the width of the second buffer block at one end close to the second plastic sealing body is less than the width of the second buffer block at one end away from the second plastic sealing body; The first buffer block and the second buffer block are arranged in opposite directions.

2. The fan-out packaging structure according to claim 1, wherein: The fan-out circuit layer is arranged on a side of the first plastic package away from the second plastic package, a solder pad is provided on one side surface of the chip, the solder pad is exposed from the first plastic package and is electrically connected to the fan-out circuit layer, and one end of the first buffer block away from the second plastic package is in contact with the fan-out circuit layer.

3. The fan-out packaging structure according to claim 1, wherein: The interface between the first plastic package body and the second plastic package body extends to half of the side wall of the chip.

4. The fan-out packaging structure according to any one of claims 1 to 3, wherein: The fan-out circuit layer includes a first dielectric layer, a second dielectric layer, a circuit layer, and a conductive layer. The first dielectric layer is arranged on one side of the chip, the circuit layer is embedded in the first dielectric layer and is electrically connected to the chip, the second dielectric layer is arranged on a side of the first dielectric layer away from the chip, the conductive layer is embedded in the second dielectric layer and is electrically connected to the circuit layer, and the solder balls are arranged on a side of the second dielectric layer away from the first dielectric layer and are electrically connected to the conductive layer.

5. The fan-out packaging structure according to claim 4, wherein: A plurality of third buffer blocks are further provided in the first dielectric layer, one end of the third buffer block contacts the first plastic package body, and the other end contacts the circuit layer or the second dielectric layer, and the third buffer block is staggered with the first buffer block.

6. The fan-out packaging structure according to claim 5, wherein: The third buffer block is T-shaped, and a width of an end of the third buffer block close to the first plastic packaging body is smaller than a width of an end of the third buffer block away from the first plastic packaging body.

7. The fan-out packaging structure according to claim 5, wherein: The third buffer block is in an inverted T-shape, and a width of an end of the third buffer block close to the first plastic packaging body is greater than a width of an end of the third buffer block away from the first plastic packaging body.

8. The fan-out packaging structure according to claim 1, wherein: The fan-out circuit layer is arranged on a side of the second plastic package body away from the first plastic package body and is spaced apart from the first plastic package body. A solder pad is provided on the surface of the chip on a side close to the fan-out circuit layer. The fan-out circuit layer is embedded in the second plastic package body and is electrically connected to the solder pad.

9. The fan-out packaging structure according to claim 8, wherein: The first plastic packaging body is further provided with a plurality of fourth buffer blocks, which are in an inverted T-shape and are spaced apart from the first buffer block. The width of the fourth buffer block at one end close to the second plastic packaging body is smaller than the width of the fourth buffer block at one end away from the second plastic packaging body.

10. The fan-out packaging structure according to claim 8, wherein: The fan-out circuit layer includes a circuit layer, a conductive layer and a dielectric layer. The circuit layer is embedded in the second plastic package and electrically connected to the solder pad. The dielectric layer is arranged on a side of the second plastic package away from the first plastic package. The conductive layer is embedded in the dielectric layer and electrically connected to the circuit layer. The solder ball is arranged on a side of the dielectric layer away from the second plastic package and electrically connected to the conductive layer.

11. A method for preparing a fan-out packaging structure, characterized in that: For preparing the fan-out packaging structure according to any one of claims 1 to 10, the preparation method comprises: providing a vehicle; Mounting a chip on the carrier; forming a first plastic package on the carrier, wherein the first plastic package partially covers the chip; Cutting a groove on the first plastic package body and filling it with buffer glue to form a first buffer block; forming a second plastic packaging body on the first plastic packaging body, wherein the second plastic packaging body partially covers the chip; Remove the vehicle; forming a fan-out circuit layer on one side of the chip, wherein the fan-out circuit layer is electrically connected to the chip; forming solder balls on the fan-out circuit layer, wherein the solder balls are electrically connected to the fan-out circuit layer; The interface between the first plastic package body and the second plastic package body extends to the side wall of the chip so that the chip is embedded between the first plastic package body and the second plastic package body. The first buffer block passes through the first plastic package body and contacts the second plastic package body to buffer the structural stress generated in the first plastic package body.

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