Integrated assembly and semiconductor memory device

Abstract

This application is directed to integrated assemblies and semiconductor memory devices. Some embodiments include an integrated assembly having a CMOS region with fins extending along a first direction and having a gate structure extending across the fins. A circuit arrangement is associated with the CMOS region and includes a pair of the gate structures separated by an intervening region having a missing gate structure. The circuit arrangement has a first dimension along the first direction. A second region is proximate to the CMOS region. Conductive structures are associated with the second region. Some of the conductive structures are electrically coupled with the circuit arrangement. A second dimension is a distance along the first direction across the some of the conductive structures. The conductive structures and the circuit arrangement are aligned such that the second dimension is substantially the same as the first dimension. Some embodiments include methods of forming integrated assemblies.

Description

TECHNICAL FIELD

[0001] Integrated assembly. Integrated memory. Multi-stack assembly. FinFET, CMOS, FinFET integration, CMOS integration, etc. BACKGROUND

[0002] Memory is one type of integrated circuit, and is used in computer systems for storing data. Memory can be fabricated in one or more arrays of individual memory cells. Memory cells can be written to or read from using digit lines (which can also be referred to as bit lines, data lines, sense lines, or data / sense lines) and access lines (which can also be referred to as word lines). The digit lines can extend along columns of the array, and the access lines can extend along rows of the array. Each memory cell can be uniquely addressed by a combination of a digit line and an access line.

[0003] Memory cells can be volatile or non-volatile. Non-volatile memory cells can store data for a long period of time, including when the computer is off. Volatile memory dissipates, and thus is quickly refreshed / re-written, in many cases multiple times per second. Regardless, memory cells are configured to retain or store memory in at least two different optional states. In binary, the states are considered a “0” or a “1”. In other systems, at least some individual memory cells can be configured to store more than two levels or states of information.

[0004] Some memory cells can include a transistor in combination with a capacitor (or other suitable charge storage device). The transistor is used to selectively access the capacitor, and can be referred to as an access device. The capacitor can store energy electrostatically as an electric field within a capacitor dielectric between two capacitor electrodes. The electrical state of the capacitor can be used to represent a memory state.

[0005] Word lines can be coupled with word line driver circuitry, and digit lines can be coupled with sense amplifier circuitry. The word line driver circuitry and the sense amplifier circuitry can be within a CMOS region of the integrated assembly.

[0006] Memory is one example of integrated circuitry, and many other types of integrated circuitry are known (e.g., sensor circuitry, logic circuitry, etc.). In some applications, these other types of integrated circuitry can be used in combination with integrated memory.

[0007] A continuing goal of integrated assembly fabrication is to increase the level of integration, or in other words, to pack more memory into ever decreasing space. New architectures for integrated assemblies need to be developed, and such new architectures need to be suitable for highly integrated applications. SUMMARY

[0008] In one aspect, the application is directed to an integrated assembly including: a CMOS region; the CMOS region including fins extending along a first direction and including gate structures extending across the fins and located on a first pitch; a circuit arrangement associated with the CMOS region and including a pair of gate structures separated by an intervening region that includes a missing gate structure; the pair of gate structures thus being located on an extended pitch that is greater than the first pitch; the circuit arrangement having a first dimension along the first direction; a second region proximate the CMOS region; and conductive structures associated with the second region and extending along a second direction that is substantially orthogonal to the first direction; some of the conductive structures being electrically coupled with the circuit arrangement; the conductive structures being located on a second pitch that is different than the first pitch; a second dimension being a distance along the first direction across some of the conductive structures; the conductive structures and the circuit arrangement being aligned such that the second dimension is substantially the same as the first dimension.

[0009] In another aspect, the application is directed to an integrated assembly including: a first memory array region laterally offset from a second memory array region; a CMOS region laterally between the first memory array region and the second memory array region; fins extending across the CMOS region along a first direction; gate structures extending across the fins and located on a first pitch; a sense amplifier circuit associated with the CMOS region and including a pair of gate structures separated by an intervening region that includes a missing gate structure; the pair of gate structures thus being located on an extended pitch that is greater than the first pitch; the sense amplifier circuit having a first dimension along the first direction; first digit lines associated with the first memory array region and extending along a second direction that is different than the first direction; some of the first digit lines being electrically coupled with the sense amplifier circuit; a second dimension being a distance along the first direction across the some of the first digit lines; the first digit lines and the sense amplifier circuit being aligned such that the second dimension is substantially the same as the first dimension; and second digit lines associated with the second memory array region; some of the second digit lines being electrically coupled with the sense amplifier circuit; a second dimension being a distance along the first direction across the some of the second digit lines.

[0010] In another aspect, the application is directed to a method of forming an integrated assembly, comprising: forming a construction including a CMOS region; the CMOS region including semiconductor material configured to include a fin projecting upward from a base region; the fin extending along a first direction; the CMOS region including linear structures above the fin, wherein the linear structures extend along a second direction, the linear structures including a main material, a cap material above the main material, and a sidewall spacer along a side edge of the main material; one of the linear structures being a center linear structure and laterally between two other of the linear structures, the two other of the linear structures being outer linear structures; removing at least a section of the main material and the cap material of the center linear structure to form an opening extending downward between sidewall spacers of the center linear structure; filling the opening with one or more insulating materials to form an insulating structure; forming a circuit arrangement to include a pair of gating structures at locations of the outer linear structures, wherein the pair of gating structures are laterally spaced apart from each other by an intervening region including the insulating structure; the circuit arrangement having a first dimension along the first direction; forming a memory array offset from the CMOS region and having conductive structures extending along the second direction; and electrically coupling some of the conductive structures with the circuit arrangement; a second dimension being a distance along the first direction across the some of the conductive structures; the conductive structures and the circuit arrangement being aligned such that the second dimension is substantially the same as the first dimension. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 Schematic diagram of an example region of an example integrated memory array.

[0012] Figure 2 Diagrammatic top view of an example region of an example CMOS- containing semiconductor substrate.

[0013] Figure 3 Diagrammatic top view of an example region of an example CMOS- containing semiconductor substrate and one or more example regions of an integrated memory array proximate the substrate.

[0014] Figure 4 , 4A and 4B are diagrammatic cross-sectional side views, diagrammatic top views, and diagrammatic cross-sectional side views, respectively, of an example region of an example CMOS- containing semiconductor substrate at example processing stages of an example method. Figure 4B the cross-sectional side view of Figure 4 is along a cross-section orthogonal to

[0015] Figure 5 , 5A and 5B are diagrammatic cross-sectional side views, diagrammatic top views, and diagrammatic cross-sectional side views, respectively, of an example region of an example CMOS- containing semiconductor substrate of Figure 4 , 4A and 4B at Figure 4 , 4Adiagrammatic cross-sectional side view, diagrammatic top view, and diagrammatic cross-sectional side view of example processing stages following the example processing stages of FIGS. 4A and 4B. Figure 5B diagrammatic cross-sectional side view of an example CMOS-containing semiconductor substrate region of FIGS. 4A and 4B along a cross-section orthogonal to the cross-section of Figure 5

[0016] Figure 6 6A diagrammatic cross-sectional side view of example processing stages following the example processing stages of FIGS. 4A and 4B. Figure 4 4A diagrammatic cross-sectional side view of example processing stages following the example processing stages of FIGS. 4A and 4B. Figure 5 5A diagrammatic cross-sectional side view of example processing stages following the example processing stages of FIGS. 4A and 4B. Figure 6 6A diagrammatic cross-sectional side view of example processing stages following the example processing stages of FIGS. 4A and 4B.

[0017] Figure 7 diagrammatic cross-sectional side view of example processing stages following the example processing stages of FIGS. 4A and 4B. Figure 4 4A diagrammatic cross-sectional side view of example processing stages following the example processing stages of FIGS. 4A and 4B. Figure 6

[0018] diagrammatic cross-sectional side view of example processing stages following the example processing stages of FIGS. 4A and 4B. Figure 8 Figure 4 diagrammatic cross-sectional side view of example processing stages following the example processing stages of FIGS. 4A and 4B. 4A Figure 7 diagrammatic cross-sectional side view of example processing stages following the example processing stages of FIGS. 4A and 4B. Figure 8A diagrammatic cross-sectional side view of an example CMOS-containing semiconductor substrate region of FIGS. 4A and 4B along a cross-section orthogonal to the cross-section of 8B diagrammatic cross-sectional side view of an example CMOS-containing semiconductor substrate region of FIGS. 4A and 4B along a cross-section orthogonal to the cross-section of Figure 8 diagrammatic cross-sectional side view of an example CMOS-containing semiconductor substrate region of FIGS. 4A and 4B along a cross-section orthogonal to the cross-section of Figure 8 diagrammatic cross-sectional side view of an example CMOS-containing semiconductor substrate region of FIGS. 4A and 4B along a cross-section orthogonal to the cross-section of Figure 8A diagrammatic cross-sectional side view of an example CMOS-containing semiconductor substrate region of FIGS. 4A and 4B along a cross-section orthogonal to the cross-section of 8B diagrammatic cross-sectional side view of an example CMOS-containing semiconductor substrate region of FIGS. 4A and 4B along a cross-section orthogonal to the cross-section of Figure 8C diagrammatic cross-sectional side view of example processing stages following the example processing stages of FIGS. 4A and 4B. Figure 4 diagrammatic cross-sectional side view of example processing stages following the example processing stages of FIGS. 4A and 4B. 4A diagrammatic cross-sectional side view of example processing stages following the example processing stages of FIGS. 4A and 4B. Figure 7 diagrammatic cross-sectional side view of example processing stages following the example processing stages of FIGS. 4A and 4B. Figure 8 diagrammatic cross-sectional side view of example processing stages following the example processing stages of FIGS. 4A and 4B.

[0019] Figure 9 diagrammatic cross-sectional side view of example processing stages following the example processing stages of FIGS. 4A and 4B. Figure 4 diagrammatic cross-sectional side view of example processing stages following the example processing stages of FIGS. 4A and 4B. 4A diagrammatic cross-sectional side view of example processing stages following the example processing stages of FIGS. 4A and 4B. Figure 8 diagrammatic cross-sectional side view of example processing stages following the example processing stages of FIGS. 4A and 4B.

[0020] Figure 10 diagrammatic cross-sectional side view of example processing stages following the example processing stages of FIGS. 4A and 4B. Figure 4 diagrammatic cross-sectional side view of example processing stages following the example processing stages of FIGS. 4A and 4B.​​​​​​​​4A Example regions of an example CMOS-containing semiconductor substrate of Figure 9 diagrammatic cross-sectional side view at an example processing stage following the example processing stages of

[0021] Figure 11 Figure 4 4A Example regions of an example CMOS-containing semiconductor substrate of Figure 9 diagrammatic cross-sectional side view at an example processing stage following the example processing stages of Figure 10 diagrammatic cross-sectional side view at an example processing stage following the alternative example processing stages of

[0022] Figures 12 to 16 Figure 4 4A Example regions of an example CMOS-containing semiconductor substrate of Figure 11 diagrammatic cross-sectional side view at an example processing stage following the example processing stages of

[0023] Figure 17 Figure 4 4A Example regions of an example CMOS-containing semiconductor substrate of Figure 15 diagrammatic cross-sectional side view at an example processing stage following the example processing stages of Figure 16 diagrammatic cross-sectional side view at an example processing stage following the alternative example processing stages of

[0024] Figure 18 diagrammatic side view of an example region of an example multi-stack assembly. DETAILED DESCRIPTION

[0025] Some embodiments include an architecture (integrated assembly) having a CMOS region with fins (i.e., a FinFET arrangement) and having conductive lines (e.g., word lines, digit lines, etc.) aligned with circuit arrangements (e.g., word line drivers, sense amplifiers, etc.) associated with the CMOS region. Reference is made to Figures 1 to 18 Example embodiments are described.

[0026] Reference is made to Figure 1 The integrated assembly 200 is shown as including memory cells (MCs) 204 arranged within a memory array 202. The memory cells can be any suitable memory cell now known or yet to be developed. In some embodiments, the memory cells can be configured for dynamic random access memory (DRAM). In such embodiments, the memory cells can each include an access device (e.g., a transistor) in combination with a storage element (e.g., a capacitor).

[0027] ​​​​​​Word lines (access lines) 206 extend along a first direction (the illustrated x-axis direction) and across the memory array 202. The illustrated word lines are labeled WL1 through WL4. The word lines are coupled with word line driver circuitry 208 (e.g., word line drivers).

[0028] Digit lines (bit lines, sense lines) 210 extend along a second direction (the illustrated y-axis direction) and across the memory array 202. The illustrated digit lines are labeled DL1 through DL4. The digit lines are coupled with sense circuitry (e.g., sense amplifiers) 212.

[0029] The term "sense / access line" can be used generically to refer to both word lines and digit lines.

[0030] Each of the memory cells 204 can be considered to be uniquely addressed by a combination of one of the word lines 206 and one of the digit lines 210.

[0031] In the illustrated embodiment, the second direction (the y-axis direction) is orthogonal to the first direction (the x-axis direction). In general, the digit lines 210 extend orthogonally or at least substantially orthogonally with respect to the word lines 206; where the term "substantially orthogonal" means orthogonal within reasonable manufacturing and measurement tolerances.

[0032] In some embodiments, the word lines 206 can be considered a first set of conductive lines, and the digit lines 210 can be considered a second set of conductive lines. The first and second sets of conductive lines cross each other, and in the illustrated embodiment are shown as being orthogonal to each other (or at least substantially orthogonal to each other).

[0033] The word lines 206 are shown as being spaced apart from each other by a word line pitch 214 (WL pitch), and the digit lines 210 are shown as being spaced apart from each other by a digit line pitch 216 (DL pitch). The word line pitch can be the same as (or at least substantially the same as) the digit line pitch, or can be different from the digit line pitch. Note that a pitch is not simply the space between features, but rather refers to a measure of the pattern repetition. Thus, a pitch includes, for example, the width of a feature and the width of the space between adjacent features (or sometimes, half the width of the space and half the width of the feature). In the case of word lines and digit lines (where "WL / DL" is generic to both word lines and digit lines), the pitch can include the width of a WL / DL along with the width of the space between adjacent WL / DLs.

[0034] In practice, a semiconductor assembly can include one or more regions containing CMOS circuitry, and the drive circuitry 208 and sense circuitry 212 can comprise devices associated with the CMOS circuitry. One or more memory arrays can be formed within a region of the semiconductor assembly proximate the CMOS circuitry, and the word lines 206 and digit lines 210 of the arrays can be coupled with devices associated with the CMOS circuitry.

[0035] Aligning word lines 206 and digit lines 210 with devices associated with CMOS circuitry can be challenging, and such challenges can be addressed with embodiments described below. Word lines and digit lines are examples of conductive structures that can be aligned with CMOS circuitry devices. Embodiments described below are presented primarily with respect to alignment of digit lines with CMOS circuitry devices (e.g., sense amplifier circuitry), but one of skill in the art will appreciate that the embodiments can be used to align other conductive structures (e.g., word lines) with CMOS circuitry devices (e.g., word line driver circuitry).

[0036] Figure 2 A portion of a CMOS region 100 is shown. The CMOS region can be formed in a semiconductor base 12. The base 12 may, for example, include, consist essentially of, or consist of monocrystalline silicon. The base 12 can be referred to as a semiconductor substrate. The term “semiconductor substrate” means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductor substrates described above.

[0037] A fin 10 extends across the CMOS region 100. The fin can be a raised region of semiconductor material (e.g., monocrystalline silicon) of the base 12. The fin can extend across the entire CMOS region 100, and is incorporated into a fin field effect transistor (FinFET). The fin 10 is located on a fin pitch (FP) 11, where this fin pitch is established by the manufacturing process used to form the fin.

[0038] A gate structure 14 extends across the fin 10. The gate structure can include any suitable material, and in some embodiments can include silicon (e.g., polysilicon, amorphous silicon, a mixture of polysilicon and amorphous silicon, etc.), metal, metal-containing material (e.g., metal nitride, metal silicide, etc.), etc. The gate structure 14 is located on a gate pitch 15.

[0039] The fin 10 is shown as extending along a first direction (the direction of the illustrated A1 axis), and the gate structure 14 is shown as extending along a second direction (the direction of the illustrated A2 axis); where the second direction is orthogonal to (or at least substantially orthogonal to) the first direction.

[0040] The gating structures 14 and fins 10 can be incorporated into circuit arrangements associated with the CMOS 100 (e.g., word line drivers, sense amplifiers, etc.). The circuit arrangements associated with the CMOS can be coupled with conductive structures associated with a memory array (e.g., word lines, bit lines). Problems can be encountered in achieving a desired alignment between the circuit arrangements associated with the CMOS and the conductive structures associated with the memory array. Such problems are addressed in subsequent discussion.

[0041] Referring to Figure 3 , portions of memory array regions 202a (array- 1) and 202b (array-2) are shown proximate to a portion of the CMOS region 100. One of the array regions 202a and 202b can be referred to as a second region disposed proximate to a first region corresponding to the CMOS region 100, and the other of the array regions 202a and 202b can be referred to as a third region. In some embodiments, the regions 202a and 202b can be referred to as a first memory array region and a second memory array region, respectively, that are offset relative to one another; and the CMOS region 100 can be viewed as being located between the first and second memory array regions.

[0042] The array regions 202a and 202b are shown laterally offset from one another and from the illustrated portion of the CMOS region 100. However, it should be understood that the array regions can be in any suitable location relative to one another and relative to the CMOS region. For example, at least portions of the array regions 202a and 202b can be vertically offset from the illustrated portion of the CMOS region, instead of or in addition to being laterally offset from the illustrated portion of the CMOS region (i.e., in a CMOS-under-array configuration, the array region 202a and the array region 202b can be over the CMOS region 100).

[0043] The CMOS region 100 includes the fins 10 arranged at a fin pitch 11, and includes the gating structures 14 arranged on a gate pitch 15. A sense amplifier circuit 16 is associated with the CMOS region 100. The sense amplifier circuit includes a pair of gating regions 14a and 14b, and such gating regions are spaced apart from one another by an intervening region 18. The gating structures should be within the intervening region 18, but instead such gating structures are removed and replaced with a region 20 corresponding to the missing gating structures. The region 20 can include an insulating material 22. The insulating material 22 is shown in stipple to emphasize to the reader that the region 20 is different from the gating regions 14.

[0044] The missing region 20 of the gate 20 effectively increases the spacing between the remaining gates 14 of the sense amplifier circuit 16, and in the illustrated embodiment, such remaining gates 14a and 14b can be considered to be located on an extended spacing 17 that is greater than the gate spacing 15. In some embodiments, the spacings 15 and 17 can be referred to as first and second spacings, respectively.

[0045] The circuit arrangement 16 is shown as including a section of six fins 10, two gates 14, and a region 20 of a missing gate. In other embodiments, the circuit arrangement can include more than six fins or fewer than six fins, more than two gates, and more than one region 20 of a missing gate.

[0046] The fins 10 can be considered to extend along a first direction corresponding to the illustrated x-axis direction of Figure 3 The sense amplifier circuit has a dimension D1 along this first direction.

[0047] The array region 202a includes first digit lines 210a arranged on a spacing P1, and the array region 202b includes second digit lines 210b also arranged on the spacing P1. The digit lines extend along a second direction that is transverse to the first direction of the fins 10, and in the illustrated embodiment, along the illustrated y-axis direction of Figure 3 The illustrated direction of the digit lines is orthogonal (or at least substantially orthogonal) to the illustrated direction of the fins 10, and in the illustrated embodiment, parallel (or at least substantially parallel) to the direction of the gates 14. Further, in the illustrated embodiment, the digit lines 210a of the first array 202a are parallel (or at least substantially parallel) to the digit lines 210b of the second array 202b. The spacing P1 of the digit lines 210a / 210b can be substantially different from the fin spacing 11 and the gate spacing 15, and in some embodiments, can be substantially less than the spacings 11 and 15.

[0048] The illustrated digit lines 210a / 210b can represent only a small subset of the total number of digit lines of the memory arrays 202a and 202b. For example, in some embodiments, the arrays can include hundreds, thousands, hundreds of thousands, millions, etc. of digit lines 210a / 210b.

[0049] In the illustrated application, four of the digit lines 210a from the first array 202a are coupled with the circuit arrangement 16 (readout amplifier circuit), and four of the digit lines 210b from the second array 202b are also coupled with the circuit arrangement 16. The digit lines 210a that are coupled with the readout amplifier circuit are labeled 1 through 4, and the digit lines 210b that are coupled with the readout amplifier circuit are labeled 1* through 4*. The digit lines labeled with a simple number (e.g., the digit line labeled 1) can be considered a true digit line, and the digit lines labeled with a number and an asterisk (e.g., the digit line labeled 1*) can be considered a complementary digit line. The true and complementary digit lines can be coupled with respect to each other by the readout amplifier circuit 16. For purposes of understanding the present disclosure and the appended claims, a first digit line is "coupled with respect to" a second digit line by the readout amplifier circuitry if the readout amplifier circuitry is configured to compare an electrical characteristic (e.g., voltage) of the first digit line and the second digit line to each other. It should be noted that the terms "true" and "complementary" are arbitrary when used to label digit lines, and are simply used to distinguish between digit lines that are compared to each other by the readout amplifier circuitry.

[0050] The four digit lines 1 through 4 of the array 202a are a subset of the eight digit lines that are aligned with the readout amplifier circuit 16, with this 8 digit lines being identified with the standoff 24a. Similarly, the four digit lines 1* through 4* of the array 202b are a subset of the eight digit lines that are aligned with the readout amplifier circuit 16, with this 8 digit lines being identified with the standoff 24b. The second dimension D2 extends across the 8 digit lines within the standoff 24a and across the 8 digit lines within the standoff 24b.

[0051] The circuit arrangement 16 has a conductive pad 26 configured for coupling with a digit line 210. For purposes of illustration, the conductive pad 26 is shown as a single pad within the circuit arrangement 16. In other embodiments, there can be two or more than two pads 26. The pad 26 can be in any suitable location within the circuit arrangement 16. The illustrated circuit arrangement 16 is also shown as having a conductive structure (e.g., a rod-shaped conductor) 28 coupled with a first voltage supply (e.g., VDD), and a conductive structure (e.g., a rod-shaped conductor) 30 coupled with a second voltage supply (e.g., VSS), as would be suitable for a readout amplifier circuit.

[0052] One of the dimensions Dl and D2 can be referred to as a first dimension, and the other as a second dimension. It is desirable that the first dimension Dl and the second dimension D2 be the same as each other (or at least substantially the same as each other, where the term "substantially the same" means the same within reasonable manufacturing and measurement tolerances). This enables the circuit arrangement 16 to be matched to the conductive lines 210a and 210b with which it is coupled, and thus can save valuable semiconductor real estate as compared to configurations in which the dimensions Dl and D2 are not substantially the same as each other.

[0053] By forming the missing pass-gate region 20 to thereby adjust the size Dl of the CMOS circuit arrangement 16, the sizes Dl and D2 can be matched (or at least substantially matched) to one another.

[0054] Figure 3 The configuration of FIG. 1 corresponds to an open memory architecture in which each of the regions 24a and 24b of the memory arrays 202a and 202b has four digit lines coupled with the sense amplifier circuit 16 and has four digit lines that are not coupled with the sense amplifier circuit 16 (but which can be coupled with other sense amplifier circuits of a display region of the assembly 300). In the illustrated embodiment, the digit lines that are not coupled with the illustrated sense amplifier circuit 16 alternate with the digit lines that are coupled with the illustrated sense amplifier circuit 16, and more specifically, alternate along the direction of the x-axis.

[0055] The illustrated circuit arrangement 16 can represent a large number of substantially identical circuit arrangements formed within the CMOS region 100 and coupled with the digit lines of the memory arrays 202a and 202b.

[0056] The circuit arrangement 16 can be formed by any suitable process. Reference is made to Figures 4 to 17 An example process is described.

[0057] Reference is made to Figures 4 to 4B to illustrate the CMOS region 100 in a diagrammatic cross-sectional side view along the direction of the x-axis Figure 4 ), a diagrammatic top view Figure 4A ), and a diagrammatic cross-sectional side view along the direction of the y-axis Figure 4B Figure 4B The views of FIG. 1 illustrate the general layout of the CMOS region 100. Figure 4 The views of FIG. 1 illustrate the general layout of the CMOS region 100. Figure 4A The top view of FIG. 1 illustrates the main features and does not correspond to particular cross-sections of the construction in Figure 4 and 4B . In particular, the views of FIG. 1 are provided to orient the reader to the general direction of the main features associated with the region 100. Figure 4A

[0058] In Figures 4 to 4B ​​The CMOS region 100 at the processing stage of FIG. 1 can be considered to correspond to a construction. The construction includes a semiconductor material 32 configured as a base 12. The semiconductor material 32 of the base 12 is configured to include a fin 10 that protrudes upward from a base region (base region) 34. The semiconductor material 32 can include any suitable composition; and in some embodiments can include, consist essentially of, or consist of one or more of: silicon, germanium, a III / V semiconductor material (e.g., gallium phosphide), a semiconductor oxide, etc.; where the term III / V semiconductor material refers to a semiconductor material that includes an element selected from Groups III and V of the periodic table (where Groups III and V are the old nomenclature, and are now referred to as Groups 13 and 15). For example, in some example embodiments, the semiconductor material 32 can include, consist essentially of, or consist of monocrystalline silicon.

[0059] The fin 10 extends along a first direction corresponding to the illustrated x-axis direction.

[0060] An insulating material 36 extends over the base region 34 and partially over the fin, as Figure 4B shown. The material 36 can include any suitable composition, and in some embodiments can include, consist essentially of, or consist of silicon dioxide.

[0061] An insulating material 38 extends over an upper surface of the fin 10 and along a sidewall surface of an upper region of the fin. The insulating material 38 can be compositionally different from the insulating material 36, and can include any suitable composition. For example, the insulating material 38 can include, consist essentially of, or consist of one or more of: aluminum oxide, hafnium dioxide, zirconium oxide, silicon oxide, silicon nitride, tantalum oxide, etc.

[0062] Linear structures (features) 40 are over the fin, and in the illustrated embodiment extend along the illustrated y-axis direction. In some embodiments, the fin 10 can be considered to extend along a first direction, and the linear structures 40 can be considered to extend along a second direction that intersects the first direction of the fin. In the illustrated embodiment, the second direction of the linear structures 40 is substantially orthogonal to the first direction of the fin 10.

[0063] The linear structures 40 include a main material 42 and a capping material 44 (the capping material is not shown in the diagrammatic top view of Figure 4A FIG. 1, as it is not one of the principle features of interest of the view of Figure 4A FIG. 1). The main material 42 can include any suitable composition. In some embodiments, the main material 42 is a sacrificial material, and is removed at a subsequent processing stage described below with reference to Figure 15 FIG. 2. Thus, the material 42 can include, in some embodiments, a material that is removed by a process that is selective to the capping material 44.Figure 15 compositions selectively removed at the processing stage of the line structure 40, including, for example: insulative materials (silicon dioxide, silicon nitride, tantalum oxide, aluminum oxide, etc.), conductive materials (metals, metal nitrides, etc.; including, for example, titanium, titanium nitride, tungsten, tungsten nitride, etc.), and semiconductive materials (e.g., silicon, germanium, etc.). In some embodiments, the main material is a conductive material of the gate structure, and accordingly can include any suitable conductive composition; such as one or more of: various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). If the main material 42 includes conductively-doped silicon, the silicon can be in any suitable crystalline morphology, including, for example, one or more of: poly crystalline, amorphous, etc.

[0064] The capping material 44 can include any suitable composition, and in some embodiments, can include, consist essentially of, or consist of silicon nitride.

[0065] The sidewall spacers 46 extend along the sidewall surfaces (lateral edges) of the line structures 40, as shown in Figure 4 of the figures (the sidewall spacers are not shown in the diagrammatic top views of Figure 4A because they are not among the principle features of interest in the views). Figure 4A

[0066] The sidewall spacers 46 can extend along the lateral edges of both the main material 42 and the capping material 44 (as shown). The sidewall spacers 46 include a spacer material 48. The spacer material 48 can include any suitable composition; and in some embodiments, can include, consist essentially of, or consist of one or more of: silicon dioxide, aluminum oxide, tantalum oxide, hafnium dioxide, zirconium oxide, etc.

[0067] The source / drain regions 50 are between the line structures 40, as shown in Figure 4 of the figures (the source / drain regions are not shown in the diagrammatic top views of because they are not among the principle features of interest in the views).

[0068] Figure 4 The insulative material 52 is over the source / drain regions and between the line structures 40, as shown in Figure 4A of the figures (the insulative material 52 is not shown in the diagrammatic top views of Figure 4A ​The insulating material 52 can include any suitable composition, and in some embodiments can include, consist essentially of, or consist of silicon dioxide. It is noted that both the spacer material 48 and the insulating material 52 can include silicon dioxide. It can be desirable for the materials 48 and 52 to differ in composition from one another. If both materials include silicon dioxide, it can be desirable for one of the materials to be a low-k material (e.g., including porous silicon dioxide, boron-doped silicon dioxide, carbon-doped silicon dioxide, etc.) and the other not to be a low-k material. In some embodiments, the materials 48 and 52 can both include silicon dioxide, but can have different densities relative to one another.

[0069] Three of the illustrated linear structures 40 can be within a region 54 that will eventually become an arrangement of circuitry associated with the CMOS region 100. Such an arrangement of circuitry can correspond, for example, with the readout amplifier circuit 16 of the type described above with reference to Figure 3 One of the three linear structures can be considered a central linear structure 40a, and the other two of the three linear structures can be considered outer linear structures 40b and 40c.

[0070] The planarized upper surface 47 is shown as extending across the materials 44, 48, and 52. Such a planarized surface can be formed with any suitable process, such as chemical mechanical polishing (CMP).

[0071] Reference is made to Figures 5 to 5B , which shows the CMOS region 100 at a processing stage after the processing stage of Figures 4 to 4B . Figure 5 and 5B are respectively diagrammatic cross-sectional side views along the x-axis and y-axis directions; wherein Figure 5B is shown in a view that exhibits a deeper portion of the region than Figure 5 . Figure 5A The top view of Figure 5 and 5B do not correspond to particular cross-sections in the construction of

[0072] Figures 5 to 5BA stack 58 of materials 60, 62, 64, 66, and 68 is formed above the upper surface 47. Materials 60, 62, 64, 66, and 68 may comprise any suitable composition. In some embodiments, material 60 may comprise silicon dioxide, be primarily composed of silicon dioxide, or be composed of silicon dioxide; material 62 may comprise silicon nitride, be primarily composed of silicon nitride, or be composed of silicon nitride; material 64 may comprise carbon (e.g., amorphous carbon), be primarily composed of carbon, or be composed of carbon; material 66 may comprise an antireflective coating (e.g., may comprise silicon oxynitride, be primarily composed of silicon oxynitride, or be composed of silicon oxynitride); and material 68 may comprise a patterned resist (e.g., patterned photoresist).

[0073] The patterned resist 68 is configured to have an opening 70 extending therethrough, wherein this opening is located directly above at least a portion of the central linear structure 40a. In the illustrated embodiment, the opening 70 exposes the entire central linear structure 40a.

[0074] Figure 5A The top view indicates the location of opening 70. Resist 68 is present. Figure 5A The images are illustrated using cross-hatching and are semi-transparent to allow features 40 and 10 to be observed through the patterned photoresist. Materials 60, 62, 64, and 66 are not shown. Figure 5A The opening is within 70 degrees to simplify the diagram.

[0075] refer to Figure 6 The opening is made by one or more suitable etch extensions 70 through the materials 60, 62, 64 and 66 of the stack 58, and then by a suitable etch extension through the capping material 44 of the central linear structure 40a.

[0076] Figure 6A The display is similar to Figure 6 The processing stage is a stage where the opening 70 can be modified by spacer 72 to narrow the opening before it is extended. Therefore, the overall size of the opening 70 can be reduced beyond the photolithography limit, which can be advantageous in applications with high integration density. Spacer 72 can contain any suitable composition, including, for example, silicon dioxide, alumina, hafnium dioxide, etc.

[0077] Figure 6 and 6A The processing demonstrates etching conditions that are highly selective to the capping material 44 relative to adjacent materials 48 and 52, extending the opening 70 through the capping material 44. In other embodiments, the etching conditions may be less selective. For example, Figure 6B The display is similar to Figure 6A The processing stage is in the processing stage, but it shows that the etching conditions have penetrated into the insulating material 52.

[0078] Referring to Figure 7 , a cross-section along the y-axis direction is shown at a processing stage of Figure 6 . Specifically, material 64, 66 and 68 have been removed. In some embodiments, upper material 62 of Figure 7 may be thinned during processing to remove material 64, 66 and 68.

[0079] Referring to Figure 8 , opening 70 extends through main material 42 of center linear structure 40a Figure 7 , through dielectric material 38 and into semiconductor material 32 of fin 10. Accordingly, opening 70 is formed to extend downward between sidewall spacers 46 of center linear structure 40a Figure 7 and into fin 10.

[0080] Figure 8A A cross-section along the y-axis direction is shown at a processing stage of Figure 8 (i.e., a view along the same cross-section as the view of Figure 5B ), and shows that opening 70 can extend into all fins 10 that overlap center linear structure 40a Figure 5B . In contrast, Figure 8B shows an embodiment in which opening 70 is formed to extend across only some of the fins that overlap center linear structure 40a. In some embodiments, center linear structure 40a can be considered to extend across multiple fins 10 (where in the illustrated embodiment, this multiple includes six fins 10, as shown in the top view of Figure 4A ). Figure 8A may be considered to illustrate an embodiment in which opening 70 is large enough such that the segment of linear structure 40a removed by the opening extends across all of the multiple fins that overlap linear structure 40a, and Figure 8B may be considered to illustrate an embodiment in which opening 70 is of a suitable size such that the segment of linear structure 40a removed by the opening extends across only some of the multiple fins that overlap linear structure 40a.

[0081] Figure 8 An embodiment is shown in which opening 70 is extended with an etch that is highly selective for semiconductor material 32, dielectric material 38 and main material 42 relative to insulating materials 48 and 52. In other embodiments, the etch can be less selective, as shown by example embodiments of Figure 8C .

[0082] Referring to Figure 9 , a cross-section along the y-axis direction is shown at a processing stage of Figure 8The insulative material 74 is formed within the openings 70 to fill the openings. The insulative material 74 can include any suitable composition, and in some embodiments can include, consist essentially of, or consist of silicon dioxide. Although only a single, homogeneous material is shown to fill the openings 70, in other embodiments two or more insulative materials can be used to fill the openings 70.

[0083] Referring to Figure 10 The integrated assembly 100 is subjected to polishing (e.g., CMP) to remove excess material 74 from above the upper surface of the material 62, and to form a planarized surface 75 extending across the materials 74 and 62. Figure 10 The assembly 100 can be considered to include a configuration of the circuit arrangement 16 described above with reference to Figure 3 In particular, the host materials 44 of the outer linear structures 40a and 40b can correspond to the gate structures 14a and 14b, with such gate structures being laterally spaced apart from one another by the intervening regions 18, which include the insulative structures 76 corresponding to the insulative material 74. In some embodiments, the insulative material 74 of the assembly 100 can be considered to be the same as the insulative material 22 described above with reference to Figure 10 Figure 3 and the structures 76 can be considered to correspond to insulative structures formed within regions of the assembly 100 where gate structures would otherwise exist (i.e., in the locations of the gate structures of the central linear structure 40a of the assembly 100). Figure 4 4A In particular, the host materials 44 of the outer linear structures 40a and 40b can correspond to the gate structures 14a and 14b, with such gate structures being laterally spaced apart from one another by the intervening regions 18, which include the insulative structures 76 corresponding to the insulative material 74. In some embodiments, the insulative material 74 of the assembly 100 can be considered to be the same as the insulative material 22 described above with reference to

[0084] Figure 10 The circuit arrangement 16 can be incorporated into the assembly 300 of Figure 3 and thus can have a dimension D1 along the illustrated x-axis direction. Incorporation of the circuit arrangement 16 into the assembly 300 of Figure 3 may include forming the memory arrays 202a and 202b to be offset from the circuit arrangement 16, and then forming electrical connections from digit lines of the memory arrays to the conductive posts 26 associated with the circuit arrangement 16 (shown in Figure 3 but not in Figure 10 ).

[0085] The insulative structures 76 can optionally be modified to include two or more different insulative materials. This can enable customization of the medium and / or stress properties associated with this insulative structure for particular applications. Examples of such optional modifications are described with reference to Figures 11 to 13 .

[0086] Referring to Figure 11 , the insulative material 74 is recessed within the openings 70.

[0087] Referring to Figure 12 ​​Additional insulating materials 78 and 80 are formed within the openings 70 and over the recessed material 74. The materials 78 and 80 can include any suitable compositions. In some embodiments, the material 78 can include, consist essentially of, or consist of silicon nitride; and the material 80 can include, consist essentially of, or consist of silicon dioxide.

[0088] Reference is made to Figure 13 The integrated assembly 100 is subjected to polishing (e.g., CMP) to remove the excess materials 78 and 80 from above the upper surface of the material 62, and to form a planarized surface 81 extending across the materials 78, 80, and 62. Figure 13 The assembly 100 can be considered to include a configuration of the circuit arrangement 16 described above with reference to Figure 3 Specifically, the main materials of the outer linear structures 40a and 40b can correspond to the gate structures 14a and 14b, with such gate structures being laterally spaced apart from one another by the intervening region 18, which includes the insulating structure 76 modified to include the insulating materials 78 and 80 in addition to the material 74. In some embodiments, Figure 13 The insulating materials 74, 78, and 80 of the assembly 100 can together be considered to be the same as the insulating material 22 described above with reference to Figure 3

[0089] Figure 13 The insulating structure 76 includes three vertically-stacked materials 74, 78, and 80. Although the structure 76 is shown to include three vertically-stacked materials, in other embodiments, the structure 76 can include a different number of vertically-stacked materials than the three materials illustrated, and can generally be considered to include two or more than two vertically-stacked materials. In the illustrated embodiment, the insulating material 78 can be considered to be vertically sandwiched between an upper region and a lower region including the materials 74 and 80. In some embodiments, the materials 74 and 80 can include the same composition as one another (which can be referred to as a first insulating material composition), and the material 78 can include a composition that is different from the composition of the materials 74 and 80 (which can be referred to as a second insulating material composition). In some embodiments, the materials 74 and 80 can each include, consist essentially of, or consist of silicon dioxide, and the material 78 can include, consist essentially of, or consist of silicon nitride.

[0090] Figure 10 and 13 Example embodiments of the assembly 100 illustrate the gate structures 14a and 14b including the main materials 42 of the linear structures 40a and 40b. In other embodiments, the main materials 42 can be sacrificial materials that are removed and replaced with conductive materials. Example of such other embodiments are described with reference to Figures 14 to 16

[0091] Reference is made to Figure 14 ​​The assembly 100 is subjected to planarization (e.g., CMP) to remove materials 60 and 62, and a planarized surface 83 extending across materials 44, 48, 52, 78 and 80 is formed.

[0092] refer to Figure 15 From linear structure 40 ( Figure 14 Material is removed from locations 38, 42, and 44 to form opening 88.

[0093] refer to Figure 16 The gate dielectric material 84 is in the opening 88 ( Figure 15 The bottom of the assembly 100 is formed along material 32, and conductive material 86 is formed above gate dielectric material 84. A planarization surface 89 is formed across material 86 at the upper surface of the assembly 100. The planarization surface 89 can be formed using any suitable processing, including, for example, CMP.

[0094] The gate dielectric material 84 may comprise any suitable composition, and in some embodiments may comprise one or more of the following, consist primarily of one or more of the following, or consist of one or more of the following: silicon dioxide, hafnium dioxide, zirconium oxide, aluminum oxide, tantalum oxide, etc.

[0095] Material 86 may comprise any suitable conductive composition; for example, one or more of the following: various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). In some embodiments, material 86 may comprise one or more metal-containing materials, such as one or more of tungsten, titanium, tungsten nitride, titanium nitride, etc.

[0096] Figure 16 Assembly 100 can be considered as including the above reference. Figure 3 The circuit arrangement 16 described herein. Specifically, conductive material 86 can be considered as replacing the main material 42 of the external linear structures 40a and 40b, and can be considered as corresponding to the gate structures 14a and 14b. The gate structures 14a and 14b are laterally spaced from each other by an intermediate region 18 including an insulating structure 76.

[0097] Figure 16 The embodiment shows that the dielectric material 84 is only in the opening 88 ( Figure 15 The bottom of the dielectric material 84 is formed along the semiconductor material 32. In other embodiments, the dielectric material 84 may line the opening 88 (e.g., Figure 17 (as shown in the figure), and then conductive material 86 can be formed in the opening of the liner. Figure 17 Assembly 100 can be considered as including the above reference. Figure 3 Another example configuration of the described circuit arrangement 16.

[0098] In some embodiments, Figure 3 The CMOS region 100 can be under the memory arrays 202a and 202b in a multi-stack configuration. For example, Figure 18 An example multi-stack configuration 400 is shown that includes a substrate 12 and includes several memory stacks 402-405 over the substrate. Although the illustrated configuration includes four memory stacks, it should be understood that other configurations can have more than four memory stacks or less than four memory stacks. For example, some configurations can include only a single memory stack. In some embodiments, the substrate 12 can be referred to as a stack disposed under the memory stacks 402-405.

[0099] The illustrated board 12 and 402-405 can be considered examples of a hierarchy of layers stacked on one another. The hierarchy can be located within different semiconductor dies, or at least two of the hierarchy can be located within the same semiconductor die. The memory stacks 402-405 can include memory arrays, or at least portions of memory arrays. The memory arrays within the various stacks can be the same as one another (e.g., can all be DRAM arrays, ferroelectric memory arrays, NAND memory arrays, etc.), or can be different from one another (e.g., some can be DRAM arrays while others are NAND memory arrays, ferroelectric memory arrays, etc.). Further, one or more of the upper stacks can include control circuitry, sensor circuitry, etc.

[0100] The memory within the stack 402 is diagrammatically indicated as containing memory arrays 202a and 202b of the type described above with reference to Figure 3 Thus, word lines and digit lines (similar to the word lines 206 and digit lines 210 of FIG. 1) can be associated with the memory stack 402. Figure 1

[0101] The substrate 12 can include CMOS, and can include a circuit arrangement 16. The region 16 is diagrammatically illustrated as being coupled with the memory arrays 202a and 202b within the stack 402. In some embodiments, the region 16 includes sense amplifier circuitry coupled with digit lines of the memory arrays 202a and 202b.

[0102] In the illustrated embodiment, electrical coupling from the memory circuitry within the stacks 402-405 to the CMOS circuitry within the substrate 12 is shown as extending through the stacks. This can be accomplished with sockets or other suitable regions as conduits for conductive lines through the various stacks. Alternatively, at least some of the electrical coupling from the stacks to the substrate can extend laterally around the stacks.

[0103] ​In the illustrated embodiment, CMOS circuitry within the base 12 is directly beneath the memory arrays of the stacks 402-405. In other embodiments, at least some of the CMOS circuitry can be laterally offset relative to the memory circuitry within the upper stacks 402-405, and vertically offset relative to the memory circuitry within such stacks.

[0104] The assemblies and structures discussed above can be used within integrated circuits (where the term "integrated circuit" means an electronic circuit that is supported by a semiconductor substrate); and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and business machines, and can include multilayer, multichip modules. The electronic systems can be any that include a memory module in accordance with the present disclosure, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0105] Unless otherwise specified, the various materials, substances, compositions, etc. described herein can be formed in any suitable method now known or to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0106] The terms "dielectric" and "insulative" can be used to describe materials having insulative electrical properties. The terms are considered synonymous in the present disclosure. The term "dielectric" in some instances and the term "insulative" (or "electrically insulative") in other instances can be used within the present disclosure to provide a linguistic variation to simplify the premise within the accompanying claims, and not to indicate any significant chemical or electrical difference.

[0107] The terms "electrically connected" and "electrically coupled" can both be used within the present disclosure. The terms are considered synonymous. The use of one term in some instances and the other term in other instances can provide a linguistic variation within the present disclosure to simplify the premise within the accompanying claims.

[0108] The particular orientations of the various embodiments in the figures are for purposes of illustration only and in some applications, embodiments can be rotated relative to the orientation shown. The description provided herein and the appended claims relate to any structure that has the described relationship between the various features, regardless of the orientation of the structure in the figures.

[0109] Unless otherwise specified, the cross-sectional views of the accompanying drawings merely illustrate features within the cross-sectional plane; material not within the cross-sectional view is omitted so as to simplify the drawings.

[0110] When a structure is referred to above as being "on", "adjacent", or "residing against" another structure, the structure can be directly on the other structure or there can also be intervening structures present. In contrast, when a structure is referred to as being "directly on", "directly adjacent", or "directly residing against" another structure, there are no intervening structures present. The terms "directly below", "directly above", and the like do not necessarily indicate direct physical contact (unless otherwise explicitly stated), but instead indicate upright alignment.

[0111] A structure (e.g., a layer, material, etc.) can be referred to as "vertically extending" to indicate that the structure generally extends upward from a bottom base (e.g., a substrate). A vertically extending structure can generally extend perpendicular relative to an upper surface of the base, or can not extend perpendicular relative to the upper surface of the base.

[0112] Some embodiments include an integrated assembly having a CMOS region including fins extending along a first direction and including gate structures extending across the fins and located on a first pitch. A circuit arrangement is associated with the CMOS region and includes a pair of gate structures separated by an intervening region having a missing gate structure. The pair of gate structures are thus located on an extended pitch that is greater than the first pitch. The circuit arrangement has a first dimension along the first direction. A second region is proximate to the CMOS region. Conductive structures are associated with the second region and extend along a second direction that is generally orthogonal to the first direction. Some of the conductive structures are electrically coupled with the circuit arrangement. The conductive structures are located on a second pitch that is different than the first pitch. A second dimension is a distance along the first direction across the some of the conductive structures. The conductive structures and the circuit arrangement are aligned such that the second dimension is generally the same as the first dimension.

[0113] Some embodiments include an integrated assembly including a first memory array region laterally offset from a second memory array region. A CMOS region is laterally between the first memory array region and the second memory array region. Fins extend across the CMOS region along a first direction. Gate structures extend across the fins and are located on a first pitch. Sense amplifier circuitry is associated with the CMOS region and includes a pair of gate structures separated by an intervening region having a missing gate structure. The pair of gate structures are thus located on an extended pitch that is greater than the first pitch. The sense amplifier circuitry has a first dimension along the first direction. First digit lines are associated with the first memory array region and extend along a second direction that is different than the first direction. Some of the first digit lines are electrically coupled with the sense amplifier circuitry. A second dimension is a distance along the first direction across the some of the first digit lines. The first digit lines and the sense amplifier circuitry are aligned such that the second dimension is generally the same as the first dimension. Second digit lines are associated with the second memory array region. Some of the second digit lines are electrically coupled with the sense amplifier circuitry. The second dimension is a distance along the first direction across the some of the second digit lines.

[0114] Some embodiments include a method of forming an integrated assembly. A CMOS region is formed. The CMOS region includes semiconductor material configured to include a fin that protrudes upward from a base region. The fin extends along a first direction. The CMOS region includes linear structures above the fin, where the linear structures extend along a second direction. The linear structures include a main material, a cap material above the main material, and a sidewall spacer along a lateral edge of the main material. One of the linear structures is a center linear structure and is laterally between two other ones of the linear structures. The two other ones of the linear structures are outer linear structures. The main material and the cap material of at least a section of the center linear structure are removed to form an opening extending downward between sidewall spacers of the center linear structure. The opening is filled with one or more insulating materials to form an insulating structure. A circuit arrangement is formed to include a pair of gating structures at locations of the outer linear structures, where the pair of gating structures are laterally spaced apart from each other by an intervening region that includes the insulating structure. The circuit arrangement has a first dimension along the first direction. A memory array is formed offset from the CMOS region and has conductive structures extending along the second direction. Some of the conductive structures are electrically coupled with the circuit arrangement. A second dimension is a distance along the first direction across the some of the conductive structures. The conductive structures and the circuit arrangement are aligned such that the second dimension is substantially the same as the first dimension.

[0115] In compliance with the statute, the subject matter disclosed herein has been described in language specific to structural features and / or methodological acts. It is to be understood, however, that the claims are not limited to the specific features or acts described because the means herein disclosed comprise examples of implementations. Therefore, the scope of the claims should be construed more broadly in accordance with the entire scope of the disclosure, including examples where more or less specific language is used.

Claims

1. An integrated assembly comprising: a CMOS region; the CMOS region including fins extending along a first direction, and including gate structures extending across the fins and located on a first pitch; a circuit arrangement associated with the CMOS region and including a pair of the gate structures separated by an intervening region including a missing gate structure; the pair of the gate structures thus being located on an extended pitch greater than the first pitch; the circuit arrangement having a first dimension along the first direction; a second region proximate the CMOS region; and conductive structures associated with the second region and extending along a second direction substantially orthogonal to the first direction; ones of the conductive structures being electrically coupled with the circuit arrangement; the conductive structures being located on a second pitch different from the first pitch; a second dimension being a distance across the ones of the conductive structures along the first direction; the conductive structures and the circuit arrangement being aligned such that the second dimension is substantially the same as the first dimension.

2. The integrated assembly of claim 1, wherein the intervening region includes only a single insulative material within a location of the missing gate structure.

3. The integrated assembly of claim 1, wherein the intervening region includes two or more vertically-stacked insulative materials within a location of the missing gate structure.

4. The integrated assembly of claim 3, wherein the two or more vertically-stacked insulative materials include a second insulative material vertically sandwiched between an upper region and a lower region including a first insulative material.

5. The integrated assembly of claim 4, wherein the first insulative material includes silicon dioxide, and the second insulative material includes silicon nitride.

6. The integrated assembly of claim 1, wherein the conductive structures are digit lines.

7. The integrated assembly of claim 6, wherein the circuit arrangement includes a sense amplifier.

8. The integrated assembly of claim 1, wherein the second region is laterally offset relative to the CMOS region.

9. The integrated assembly of claim 1, wherein the second region is vertically offset relative to the CMOS region.

10. The integrated assembly of claim 1, wherein another of the conductive structures is within the second dimension in addition to the ones of the conductive structures electrically coupled with the circuit arrangement.

11. An integrated assembly comprising: a first memory array region laterally offset from a second memory array region; a CMOS region laterally between the first memory array region and the second memory array region; a fin extending along a first direction across the CMOS region; gate structures extending across the fins and located on a first pitch; a sense amplifier circuit associated with the CMOS region and including a pair of the gate structures separated by an intervening region including a missing gate structure; the pair of the gate structures thus being located on an extended pitch greater than the first pitch; the sense amplifier circuit having a first dimension along the first direction; a first digit line associated with the first memory array region and extending along a second direction different from the first direction; ones of the first digit lines are electrically coupled with the sense amplifier circuit; a second dimension is a distance along the first direction across the ones of the first digit lines; the first digit lines and the sense amplifier circuit are aligned such that the second dimension is substantially the same as the first dimension; and a second digit line associated with the second memory array region; ones of the second digit lines are electrically coupled with the sense amplifier circuit; the second dimension is a distance along the first direction across the ones of the second digit lines.

12. The integrated assembly of claim 11 wherein the second direction is substantially orthogonal to the first direction.

13. The integrated assembly of claim 11 wherein the second digit line extends along the second direction.

14. The integrated assembly of claim 11 wherein the ones of the first digit lines are coupled opposite the ones of the second digit lines by the sense amplifier circuit.

15. The integrated assembly of claim 11 wherein the intervening region includes only a single insulative material within locations of the missing pass gates.

16. The integrated assembly of claim 11 wherein the intervening region includes two or more vertically-stacked insulative materials within locations of the missing pass gates.

17. The integrated assembly of claim 11 wherein the first memory array region and the second memory array region are vertically offset relative to the CMOS region.

18. A method of forming an integrated assembly, comprising: forming a construction including a CMOS region; the CMOS region including semiconductor material configured to include a fin protruding upward from a base region; the fin extending along a first direction; the CMOS region including linear structures above the fin, wherein the linear structures extend along a second direction; the linear structures including a main material, a cap material above the main material, and a sidewall spacer along a side edge of the main material; one of the linear structures being a center linear structure and laterally between two others of the linear structures, the two others of the linear structures being outer linear structures; removing the main material and the cap material of at least a section of the center linear structure to form an opening extending downward between the sidewall spacer of the center linear structure; filling the opening with one or more insulative materials to form an insulative structure; forming a circuit arrangement to include a pair of pass gates at locations of the outer linear structures, wherein the pair of the pass gates are laterally spaced apart from one another by an intervening region including the insulative structure; the circuit arrangement having a first dimension along the first direction; forming a memory array offset from the CMOS region and having conductive structures extending along the second direction; and electrically coupling ones of the conductive structures with the circuit arrangement; A second dimension is a distance across the ones of the conductive structures along the first direction; the conductive structures and the circuit arrangement are aligned so that the second dimension is substantially the same as the first dimension.

19. The method of claim 18, wherein the opening extends into at least one fin overlapped by the center linear structure.

20. The method of claim 18, wherein the center linear structure overlaps a plurality of the fins, and wherein the segment of the center linear structure extends across all of the plurality of the fins.

21. The method of claim 18, wherein the center linear structure overlaps a plurality of the fins, and wherein the segment of the center linear structure extends across only some of the plurality of the fins.

22. The method of claim 18, wherein the gate structure comprises the host material.

23. The method of claim 18, wherein the gate structure does not comprise the host material.

24. The method of claim 18, wherein the host material comprises silicon, and wherein the gate structure comprises the silicon.

25. The method of claim 18, wherein the gate structure comprises a metal-containing material.

26. The method of claim 18, wherein a dielectric material is between the host material and the semiconductor material.

27. The method of claim 26, wherein the semiconductor material is a first semiconductor material, and wherein the host material comprises a second semiconductor material.

28. The method of claim 27, wherein the first semiconductor material comprises single crystalline silicon, and wherein the second semiconductor material comprises one or both of amorphous silicon and polycrystalline silicon.

29. The method of claim 18, wherein the one or more insulating materials comprises only a single insulating material.

30. The method of claim 29, wherein the single insulating material comprises silicon dioxide.

31. The method of claim 18, wherein the one or more insulating materials comprises two or more vertically-stacked insulating materials.

32. The method of claim 31, wherein the two or more vertically-stacked insulating materials comprise a second insulating material vertically sandwiched between an upper region and a lower region comprising a first insulating material.

33. The method of claim 32, wherein the first insulating material comprises silicon dioxide and the second insulating material comprises silicon nitride.

34. The method of claim 18, wherein the conductive structures are digit lines.

35. The method of claim 34, wherein the circuit arrangement comprises a sense amplifier.

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