Array Substrate and Display Panel

Abstract

The present application provides an array substrate and a display panel. In the array substrate, the dielectric constant of the second insulating layer is greater than that of the first insulating layer. By providing the first insulating layer and the second insulating layer between the active layer and the first metal layer and the second metal layer, and making the dielectric constant of the second insulating layer greater than that of the first insulating layer, since the second insulating layer is disposed on the side of the first insulating layer close to the first metal layer and the second metal layer, the mobility of the array substrate can be improved through the second insulating layer, while the reliability of the array substrate can be improved through the first insulating layer, so that the mobility and reliability of the thin film transistor can be taken into account.

Description

Technical Field

[0001] This application relates to the field of display technologies, and in particular, to an array substrate and a display panel. Background Art

[0002] OLED (Organic Light-Emitting Diode) display devices are widely used due to advantages such as self-luminescence, wide color gamut, low power consumption, and flexible display capabilities. Existing OLED display devices adopt top-gate indium gallium zinc oxide thin-film transistor technology. To improve device reliability, silicon dioxide is used as the insulating layer, but this results in a low mobility of the thin-film transistors. Using other materials as the insulating layer leads to low reliability of the thin-film transistors.

[0003] Therefore, existing OLED display devices have the technical problem of being unable to balance the mobility and reliability of thin-film transistors. Summary of the Invention

[0004] Embodiments of this application provide an array substrate and a display panel to alleviate the technical problem that existing OLED display devices are unable to balance the mobility and reliability of thin-film transistors.

[0005] Embodiments of this application provide an array substrate, which includes:

[0006] A substrate;

[0007] An active layer disposed on one side of the substrate;

[0008] A first insulating layer disposed on the side of the active layer away from the substrate;

[0009] A second insulating layer disposed on the side of the first insulating layer away from the active layer;

[0010] A first metal layer disposed on the side of the second insulating layer away from the first insulating layer;

[0011] A second metal layer disposed on the side of the second insulating layer away from the first insulating layer. The second metal layer includes a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively in contact with the active layer;

[0012] Wherein, the dielectric constant of the second insulating layer is greater than the dielectric constant of the first insulating layer.

[0013] In some embodiments, the first insulating layer includes a first part, a second part, and a third part. The second part is disposed between the first part and the third part, and there is a gap between the second part and the first part, and there is a gap between the second part and the third part.

[0014] In some embodiments, the second insulating layer includes a fourth portion, a fifth portion, and a sixth portion. The fourth portion is located on a side of the first portion away from the active layer. The fifth portion is disposed on a side of the second portion away from the active layer. The sixth portion is disposed on a side of the third portion away from the active layer. And there is a spacing between any part of the fifth portion and the active layer.

[0015] In some embodiments, the second metal layer further includes a gate. The gate is disposed on a side of the fifth portion away from the second portion. And the gate is insulated from the source electrode and insulated from the drain electrode.

[0016] In some embodiments, the first metal layer includes a gate. The gate is disposed on a side of the fifth portion away from the second portion. And the gate is insulated from the source electrode and insulated from the drain electrode.

[0017] In some embodiments, the drain electrode is connected to the active layer along a side surface of the first portion and a side surface of the fifth portion. The source electrode is connected to the active layer along a side surface of the third portion and a side surface of the sixth portion.

[0018] In some embodiments, the array substrate further includes a light-shielding layer and a buffer layer. The light-shielding layer is disposed between the buffer layer and the active layer. The source electrode passes through the first insulating layer and the second insulating layer to be connected to the light-shielding layer.

[0019] In some embodiments, the second insulating layer is disposed between the source electrode and the active layer. And one side of the second insulating layer is in contact with the source electrode, and the other side of the second insulating layer is in contact with the active layer.

[0020] In some embodiments, the second insulating layer is disposed between the drain electrode and the active layer. And one side of the second insulating layer is in contact with the drain electrode, and the other side of the second insulating layer is in contact with the active layer.

[0021] Meanwhile, an embodiment of the present application provides a display panel, which includes:

[0022] An array substrate includes a substrate, an active layer, a first insulating layer, a second insulating layer, a first metal layer, and a second metal layer. The active layer is disposed on one side of the substrate. The first insulating layer is disposed on the side of the active layer away from the substrate. The second insulating layer is disposed on the side of the first insulating layer away from the active layer. The first metal layer is disposed on the side of the second insulating layer away from the first insulating layer. The second metal layer is disposed on the side of the second insulating layer away from the first insulating layer. The second metal layer includes a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively in contact with the active layer. Wherein, the dielectric constant of the second insulating layer is greater than that of the first insulating layer;

[0023] A light-emitting layer is disposed on the side of the second metal layer away from the first metal layer.

[0024] Advantageous effects: The present application provides an array substrate and a display panel. The array substrate includes a substrate, an active layer, a first insulating layer, a second insulating layer, a first metal layer, and a second metal layer. The active layer is disposed on one side of the substrate. The first insulating layer is disposed on the side of the active layer away from the substrate. The second insulating layer is disposed on the side of the first insulating layer away from the active layer. The first metal layer is disposed on the side of the second insulating layer away from the first insulating layer. The second metal layer is disposed on the side of the second insulating layer away from the first insulating layer. The second metal layer includes a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively in contact with the active layer. Wherein, the dielectric constant of the second insulating layer is greater than that of the first insulating layer. By providing the first insulating layer and the second insulating layer between the active layer and the first metal layer and the second metal layer, and making the dielectric constant of the second insulating layer greater than that of the first insulating layer, since the second insulating layer is disposed on the side of the first insulating layer close to the first metal layer and the second metal layer, the mobility of the array substrate can be improved through the second insulating layer, and the reliability of the array substrate can be improved through the first insulating layer, so that the mobility and reliability of the thin-film transistor can be taken into account. Description of the Drawings

[0025] The following will make the technical solutions and other advantageous effects of the present application obvious by describing the specific embodiments of the present application in detail with reference to the drawings.

[0026] Figure 1 It is a schematic diagram of the array substrate provided by the embodiment of the present application.

[0027] Figure 2 It is a schematic diagram of the display panel provided by the embodiment of the present application. Detailed Embodiments

[0028] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0029] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more, unless otherwise specifically defined.

[0030] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "mounted", "connected" and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection or an integral connection; it may be a mechanical connection, an electrical connection or a connection capable of mutual communication; it may be directly connected, or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0031] In the present application, unless otherwise clearly specified and limited, the first feature being "on" or "under" the second feature may include the direct contact between the first and second features, or may include the situation where the first and second features are not in direct contact but in contact through other features therebetween. Moreover, the first feature being "above", "over" and "on top of" the second feature includes that the first feature is directly above and obliquely above the second feature, or merely means that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "beneath" and "underneath" the second feature includes that the first feature is directly below and obliquely below the second feature, or merely means that the horizontal height of the first feature is lower than that of the second feature.

[0032] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. To simplify the disclosure of the present application, components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present application. In addition, the present application may repeat reference numerals and / or reference letters in different examples. Such repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0033] An embodiment of the present application aims at the technical problem that the existing OLED display device cannot balance the mobility and reliability of thin film transistors, and provides an array substrate and a display panel to alleviate the above technical problem.

[0034] As Figure 1 shown, an embodiment of the present application provides an array substrate, and the array substrate 1 includes:

[0035] A substrate 11;

[0036] An active layer 14, disposed on one side of the substrate 11;

[0037] A first insulating layer 15, disposed on the side of the active layer 14 away from the substrate 11;

[0038] A second insulating layer 16, disposed on the side of the first insulating layer 15 away from the active layer 14;

[0039] A first metal layer 17, disposed on the side of the second insulating layer 16 away from the first insulating layer 15;

[0040] A second metal layer 18, disposed on the side of the second insulating layer 16 away from the first insulating layer 15. The second metal layer 18 includes a source electrode 182 and a drain electrode 181, and the source electrode 182 and the drain electrode 181 are respectively in contact with the active layer 14;

[0041] Wherein, the dielectric constant of the second insulating layer 16 is greater than the dielectric constant of the first insulating layer 15.

[0042] An embodiment of the present application provides an array substrate. By disposing a first insulating layer and a second insulating layer between the active layer and the first metal layer and the second metal layer, and making the dielectric constant of the second insulating layer greater than the dielectric constant of the first insulating layer. Since the second insulating layer is disposed on the side of the first insulating layer close to the first metal layer and the second metal layer, the mobility of the array substrate can be improved through the second insulating layer, while the first insulating layer can improve the reliability of the array substrate, so that the mobility and reliability of the thin film transistor can be balanced.

[0043] In one embodiment, as Figure 1 shown, the first insulating layer 15 includes a first portion 151, a second portion 152, and a third portion 153. The second portion 152 is disposed between the first portion 151 and the third portion 153, and there is a gap between the second portion 152 and the first portion 151, and there is a gap between the second portion 152 and the third portion 153. By forming the first insulating layer from the first portion, the second portion, and the third portion, when the source and drain are provided, the source and drain can be connected to the active layer through the gaps between the first portion and the second portion and between the second portion and the third portion; and by separating the first portion, the second portion, and the third portion, when the second insulating layer is provided, the second insulating layer can be separated, avoiding electrical connection between the source, drain, and gate.

[0044] Regarding the problem that the second insulating layer being connected together may cause electrical connection between the gate and the source / drain. In one embodiment, as Figure 1 shown, the second insulating layer 16 includes a fourth portion 161, a fifth portion 162, and a sixth portion 163. The fourth portion 161 is located on the side of the first portion 151 away from the active layer 14, the fifth portion 162 is disposed on the side of the second portion 152 away from the active layer 14, the sixth portion 163 is disposed on the side of the third portion 153 away from the active layer 14, and there is a gap between any part of the fifth portion 153 and the active layer 14. By forming the second insulating layer from the fourth portion, the fifth portion, and the sixth portion, electrical connection between the gate, source, and drain is avoided, and the source and drain can be connected to the active layer through the gaps between the fourth portion and the fifth portion and between the fifth portion and the sixth portion, enabling the thin film transistor to operate normally. And the second insulating layer is in contact with the source, drain, and gate, and the dielectric constant of the second insulating layer is greater than that of the first insulating layer, improving the mobility of the array substrate.

[0045] Specifically, there is a gap between any part of the fourth portion and the active layer, and there is a gap between any part of the sixth portion and the active layer. By ensuring that each part of the second insulating layer does not contact the active layer, it is avoided that the small gap between the second insulating layers causes electrical connection between the source, drain, and gate, affecting the normal operation of the thin film transistor.

[0046] In one embodiment, the second metal layer further includes a gate, the gate is disposed on a side of the fifth portion away from the second portion, and the gate is insulated from the source electrode and the drain electrode. By forming the gate with the second metal layer, the source electrode, the drain electrode, and the gate can be all disposed on the first insulating layer and the second insulating layer and formed synchronously. The second insulating layer is in direct contact with the source electrode, the drain electrode, and the gate, improving the mobility of the array substrate. Moreover, the first insulating layer can improve the reliability of the array substrate, thus taking into account both the mobility and reliability of the thin film transistor.

[0047] In one embodiment, the first metal layer includes a gate, the gate is disposed on a side of the fifth portion away from the second portion, and the gate is insulated from the source electrode and the drain electrode. By forming the gate with the first metal layer and disposing the gate on a side of the fifth portion away from the second portion, the mobility of the thin film transistor in the array substrate can be improved through the second insulating layer. Since the first portion, the second portion, and the third portion in the first insulating layer are separated from each other, and the fourth portion, the fifth portion, and the sixth portion in the second insulating layer are separated from each other, disposing the gate on a side of the fifth portion away from the second portion can insulate the gate from the source electrode and the drain electrode, preventing the thin film transistor from malfunctioning. Moreover, the first insulating layer is located between the second insulating layer and the active layer, improving the reliability of the thin film transistor, thus taking into account both the mobility and reliability of the thin film transistor.

[0048] In one embodiment, as Figure 1 shown, the drain electrode 181 is connected to the active layer 14 along the side surfaces of the first portion 151 and the fifth portion 162, and the source electrode 182 is connected to the active layer 14 along the side surfaces of the third portion 153 and the sixth portion 163. By connecting the drain electrode to the active layer along the side surfaces of the first portion and the fifth portion, and connecting the source electrode to the active layer along the side surfaces of the third portion and the sixth portion, the connection between the source electrode and the drain electrode and the active layer can be achieved. Since there are intervals between the first portion, the second portion, and the third portion, and between the fourth portion, the fifth portion, and the sixth portion, the occurrence of electrical connection between the source electrode, the drain electrode, and the gate is avoided, thus preventing interference between the electrodes.

[0049] Regarding the problem that excessive impedance of the source electrode may cause signal distortion. In one embodiment, as Figure 1As shown, the array substrate 1 further includes a light-shielding layer 12 and a buffer layer 13. The light-shielding layer 12 is disposed between the buffer layer 13 and the active layer 14, and the source electrode 182 passes through the first insulating layer 15 and the second insulating layer 16 to be connected to the light-shielding layer 12. By connecting the source electrode to the light-shielding layer through the first insulating layer and the second insulating layer, the electrical property of the source electrode can be improved through the light-shielding layer, the loss during the transmission of the electrical signal can be reduced, and the display effect can be improved.

[0050] Aiming at the technical problem that the current display device cannot balance the mobility and reliability of the thin-film transistor. In one embodiment, the second insulating layer is disposed between the source electrode and the active layer, and one side of the second insulating layer is in contact with the source electrode, and the other side of the second insulating layer is in contact with the active layer. By directly connecting the second insulating layer to the active layer and the source electrode, the second insulating layer can improve the mobility of the thin-film transistor, and the first insulating layer is disposed between the gate electrode and the active layer, which can improve the reliability of the thin-film transistor, thereby balancing the mobility and reliability of the thin-film transistor.

[0051] In one embodiment, the second insulating layer is disposed between the drain electrode and the active layer, and one side of the second insulating layer is in contact with the drain electrode, and the other side of the second insulating layer is in contact with the active layer. By directly connecting the second insulating layer to the active layer and the drain electrode, the second insulating layer can improve the mobility of the thin-film transistor, and the first insulating layer is disposed between the gate electrode and the active layer, which can improve the reliability of the thin-film transistor, thereby balancing the mobility and reliability of the thin-film transistor.

[0052] In one embodiment, as Figure 1 shown, the array substrate 1 further includes a passivation layer 19 and a planarization layer 20.

[0053] In one embodiment, the material of the second insulating layer is zirconia.

[0054] Meanwhile, as Figure 2 shown, an embodiment of the present application provides a display panel. The display panel 2 includes:

[0055] An array substrate includes a substrate 11, an active layer 14, a first insulating layer 15, a second insulating layer 16, a first metal layer 17, and a second metal layer 18. The active layer 14 is disposed on one side of the substrate 11. The first insulating layer 15 is disposed on the side of the active layer 14 away from the substrate 11. The second insulating layer 16 is disposed on the side of the first insulating layer 15 away from the active layer 14. The first metal layer 17 is disposed on the side of the second insulating layer 16 away from the first insulating layer 15. The second metal layer 18 is disposed on the side of the second insulating layer 16 away from the first insulating layer 15. The second metal layer 18 includes a source electrode 182 and a drain electrode 181, and the source electrode 182 and the drain electrode 181 are respectively in contact with the active layer 14. Wherein, the dielectric constant of the second insulating layer 16 is greater than the dielectric constant of the first insulating layer 15;

[0056] A light-emitting layer 21 is disposed on the side of the second metal layer 18 away from the first metal layer 17.

[0057] An embodiment of the present application provides a display panel. The display panel includes an array substrate and a light-emitting layer. By disposing a first insulating layer and a second insulating layer between the active layer and the first metal layer and the second metal layer, and making the dielectric constant of the second insulating layer greater than the dielectric constant of the first insulating layer, since the second insulating layer is disposed on the side of the first insulating layer close to the first metal layer and the second metal layer, the mobility of the array substrate can be improved through the second insulating layer, while the first insulating layer can improve the reliability of the array substrate, so that the mobility and reliability of the thin-film transistor can be taken into account.

[0058] Specifically, as Figure 2 shown, the light-emitting layer 21 includes a pixel electrode layer 211, a pixel defining layer 213, a light-emitting material layer 212, and a common electrode layer 214.

[0059] In one embodiment, the display panel further includes a packaging layer, and the packaging layer is disposed on the side of the common electrode layer away from the pixel electrode layer.

[0060] The above embodiments are described in detail by taking an OLED display panel as an example, but the embodiments of the present application are not limited thereto, and this structure can also be applied to a liquid crystal display panel.

[0061] Meanwhile, an embodiment of the present application provides a method for manufacturing a display panel. The method for manufacturing a display panel includes:

[0062] Providing a substrate and depositing a light-shielding layer on the substrate; specifically, the material of the light-shielding layer includes molybdenum, aluminum, copper, and titanium, and the thickness range of the light-shielding layer is 1000 Å to 8000 Å.

[0063] Then, silicon oxide is deposited on the light-shielding layer to form a buffer layer; specifically, the thickness range of the buffer layer is from 1000 angstroms to 5000 angstroms.

[0064] Then, indium gallium zinc oxide is deposited on the buffer layer by physical vapor deposition, and a pattern is defined by a yellow light process and an etching process to form an active layer; specifically, the thickness range of the active layer is from 400 angstroms to 1000 angstroms.

[0065] Then, silicon oxide is deposited on the active layer as the first insulating layer; specifically, the thickness range of the first insulating layer is from 500 angstroms to 1000 angstroms.

[0066] Then, zirconium oxide is deposited on the first insulating layer by atomic layer deposition to form a second insulating layer; specifically, the thickness range of the second insulating layer is from 500 angstroms to 1000 angstroms.

[0067] Specifically, the second insulating layer is formed by atomic layer deposition to improve the density of the second insulating layer.

[0068] Then, a yellow light process is used to define the opening patterns of the first insulating layer and the second insulating layer, and the first insulating layer and the second insulating layer are dried and made conductive.

[0069] Then, a first metal layer is deposited on the second insulating layer. First, the pattern of the gate is etched by a yellow light process, and then the first insulating layer and the second insulating layer are etched using metal pattern self-alignment; specifically, the first metal layer includes a molybdenum titanium / copper / molybdenum titanium stack, and the thickness range of the first metal layer is from 2000 angstroms to 8000 angstroms.

[0070] Then, a full-surface plasma treatment is performed so that the oxides not protected by the first insulating layer, the second insulating layer, and the gate metal are treated to have a reduced resistance to form a conductor, while the oxides below the first insulating layer and the second insulating layer are not treated and maintain semiconductor characteristics as the channel layer;

[0071] Then, a first interlayer insulating layer is deposited on the first metal layer; specifically, the material of the first interlayer insulating layer includes silicon oxide, and the thickness range of the first interlayer insulating layer is from 2000 angstroms to 5000 angstroms.

[0072] Then, a second interlayer insulating layer is deposited on the first interlayer insulating layer, and source contact regions and drain contact regions are defined; specifically, the material of the second interlayer insulating layer includes silicon nitride.

[0073] Then, a second metal layer is deposited on the second interlayer insulating layer, and the pattern of the second metal layer is defined; the material of the second metal layer includes molybdenum, aluminum, copper, and titanium, and the thickness range of the second metal layer is from 2000 angstroms to 8000 angstroms.

[0074] Then, a passivation layer is deposited on the second metal layer, and openings are formed in the passivation layer; specifically, the material of the passivation layer includes silicon nitride and silicon oxide, and the thickness range of the passivation layer is from 1000 angstroms to 5000 angstroms.

[0075] Then, a planarization layer is deposited on the passivation layer, and openings are formed in the passivation layer; specifically, the thickness range of the planarization layer is from 10000 angstroms to 30000 angstroms;

[0076] Then, indium tin oxide / silver / indium tin oxide is deposited on the planarization layer, and a pattern is defined by a yellow light process to form a pixel definition layer;

[0077] Then, a pixel definition layer, a light-emitting material layer, and a common electrode layer are formed on the pixel definition layer to obtain a display panel.

[0078] According to the above embodiments, it can be known that:

[0079] The embodiment of the present application provides an array substrate and a display panel; the array substrate includes a substrate, an active layer, a first insulating layer, a second insulating layer, a first metal layer, and a second metal layer. The active layer is disposed on one side of the substrate, the first insulating layer is disposed on the side of the active layer away from the substrate, the second insulating layer is disposed on the side of the first insulating layer away from the active layer, the first metal layer is disposed on the side of the second insulating layer away from the first insulating layer, the second metal layer is disposed on the side of the second insulating layer away from the first insulating layer, the second metal layer includes a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively in contact with the active layer. Among them, the dielectric constant of the second insulating layer is greater than that of the first insulating layer. By providing the first insulating layer and the second insulating layer between the active layer and the first metal layer and the second metal layer, and making the dielectric constant of the second insulating layer greater than that of the first insulating layer, since the second insulating layer is disposed on the side of the first insulating layer close to the first metal layer and the second metal layer, the mobility of the array substrate can be improved through the second insulating layer, while the first insulating layer can improve the reliability of the array substrate, so that the mobility and reliability of the thin film transistor can be taken into account.

[0080] In the above embodiments, the descriptions of the respective embodiments have their own focuses. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0081] The above has introduced in detail an array substrate and a display panel provided by the embodiments of the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the technical solution and its core idea of the present application; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized in that, Comprising: A substrate; An active layer disposed on one side of the substrate; A first insulating layer disposed on the side of the active layer away from the substrate; A second insulating layer disposed on the side of the first insulating layer away from the active layer; A first metal layer disposed on the side of the second insulating layer away from the first insulating layer; A second metal layer disposed on the side of the second insulating layer away from the first insulating layer, the second metal layer includes a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively in contact with the active layer; Wherein, the dielectric constant of the second insulating layer is greater than the dielectric constant of the first insulating layer; The first insulating layer includes a first part, a second part and a third part, the second part is disposed between the first part and the third part, and there is a spacing between the second part and the first part, and there is a spacing between the second part and the third part. The second insulating layer includes a fourth part, a fifth part and a sixth part. The fourth part is located on the side of the first part away from the active layer. The fifth part is disposed on the side of the second part away from the active layer. The sixth part is disposed on the side of the third part away from the active layer. And any part of the fifth part has a spacing from the active layer. The first metal layer or the second metal layer further includes a gate electrode, the gate electrode is disposed on the side of the fifth part away from the second part, and the gate electrode is insulated from the source electrode and the gate electrode is insulated from the drain electrode.

2. The array substrate according to claim 1, wherein The drain electrode is connected to the active layer along the side surface of the first part and the side surface of the fifth part, and the source electrode is connected to the active layer along the side surface of the third part and the side surface of the sixth part.

3. The array substrate according to claim 1, wherein The array substrate further includes a light-shielding layer and a buffer layer, the light-shielding layer is disposed between the buffer layer and the active layer, and the source electrode passes through the first insulating layer and the second insulating layer to be connected to the light-shielding layer.

4. The array substrate according to claim 1, wherein The second insulating layer is disposed between the source electrode and the active layer, and one side of the second insulating layer is in contact with the source electrode, and the other side of the second insulating layer is in contact with the active layer.

5. The array substrate according to claim 4, wherein The second insulating layer is disposed between the drain electrode and the active layer, and one side of the second insulating layer is in contact with the drain electrode, and the other side of the second insulating layer is in contact with the active layer.

6. A display panel, characterized in that, Comprising the array substrate according to any one of claims 1 to 5 and a light-emitting layer, the light-emitting layer is disposed on the side of the second metal layer away from the first metal layer.

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