Circuit, method and laser radar for multiplexing of photodetector array

Abstract

The present invention provides a circuit for multiplexing a photodetector array, comprising: a photodetector array including multiple detection units, each including a power input, a signal output, and a photodetector that converts an optical signal into an electrical signal; a power switch circuit coupled to the power input of each detection unit, capable of determining a first group of detection units and simultaneously providing power input to the first group of detection units; and a multiplexer coupled to the signal output of each detection unit, capable of selectively enabling the signal output of a second group of detection units for signal output, wherein the first and second groups of detection units share only one detection unit. The present invention achieves the same functionality using fewer multiplexer and power switch circuit channels, thus reducing circuit cost and complexity in PCB and IC designs and pin count in photodetector array packaging designs.

Description

Technical Field

[0001] The present invention relates to the field of photoelectric detection, and in particular to a circuit for multiplexing a photoelectric detector array, a laser radar, and a method for multiplexing a photoelectric detector array. Background Art

[0002] LiDAR can be used to obtain three-dimensional information about the environment by measuring the distance to objects. A LiDAR system may include at least a light source configured to emit light pulses and a detector configured to receive returned light pulses. The returned light pulse or light beam may be referred to as an echo beam. The distance can be obtained based on the time between the emission of the light pulse and the detection of the returned light pulse (i.e., the time of flight). The light pulses may be generated by a laser emitter and then focused by a lens or lens assembly. The returned light pulses may be received by a photodetector located near the laser emitter. In order to save cost and space, the readout circuitry of the photodetector typically needs to be multiplexed, especially for high-line-count LiDARs.

[0003] In a lidar, only some (usually 1 or 2) photodetectors are in operation at the same time. Therefore, a multiplexing circuit can be used to enable the output ends of multiple photodetectors to share a set of subsequent circuits. Figure 1 A schematic diagram of an 8-to-1 multiplexing circuit is shown. The output ends of multiple photodetectors are respectively connected to the input ends of the multiplexer. Due to the limitations of the lidar volume and PCB (Printed Circuit Board) area, it is difficult for a circuit based on the multiplexer to achieve a very large number of lines, such as 128 lines or 256 lines.

[0004] Figure 2 A schematic diagram of an existing 32-channel common-anode SiPM array device is shown. The circuit includes a power switch circuit, a SiPM (Silicon Photomultiplier) array, and a multiplexer. A channel refers to a photodetector, such as a SiPM, and the number of channels refers to the number of photodetectors. The complexity of the multiplexer and power switch circuits is proportional to the number of channels. Therefore, as the number of channels increases, the area and cost of these circuits also increase exponentially, which greatly restricts LiDAR system and circuit design.

[0005] On the other hand, in LiDAR, SiPM is typically used as a component, soldered to the PCB via SMT (Surface Mount Technology). As the number of SiPMs increases, the pixel pitch decreases, and the number of pins within the same package area increases, the requirements for packaging technology are becoming increasingly stringent.

[0006] The contents of the background technology section are merely the technologies known to the inventors and do not necessarily represent the existing technologies in this field. Summary of the Invention

[0007] In view of one or more deficiencies in the prior art, the present invention provides a circuit and method for multiplexing a photodetector array. This circuit and method achieve the same functionality using a multiplexer with fewer channels and a power switch circuit. This approach is suitable for reducing circuit cost and complexity in PCB and IC design, as well as pin count in photodetector array packaging. Furthermore, power is supplied only to the selected channels, while other channels are disabled to conserve power.

[0008] The present invention provides a circuit for multiplexing a photodetector array, the circuit comprising:

[0009] a photodetector array comprising a plurality of detection units, each detection unit comprising a power input terminal, a signal output terminal, and a photodetector, wherein the photodetector is configured to detect an optical signal and convert the optical signal into an electrical signal;

[0010] a power switch circuit coupled to a power input terminal of each detection unit of the photodetector array, configured to determine a first group of detection units among the plurality of detection units and to simultaneously provide power input to the first group of detection units;

[0011] A multiplexer is coupled to the signal output end of each detection unit of the photodetector array and is configured to selectively enable the signal output end of the second group of detection units among the multiple detection units to output signals, wherein the first group of detection units and the second group of detection units have only one detection unit in common.

[0012] According to one aspect of the present invention, the number of detection units in the first group of detection units and the second group of detection units are both multiple; or the number of detection units in one of the first group of detection units and the second group of detection units is multiple, and the number of detection units in the other group is 1.

[0013] According to one aspect of the present invention, the power switch circuit includes a voltage input terminal, an address input terminal and a voltage output terminal, wherein the voltage input terminal is configured to receive a bias voltage, each voltage output terminal is respectively coupled to the power input terminal of one of the first group of detection units, the address input terminal is configured to receive an address bit to determine the first group of detection units, and output the bias voltage from one of the voltage output terminals corresponding to the address bit.

[0014] According to one aspect of the present invention, the multiplexer includes a signal input terminal, an address input terminal and a signal output terminal, wherein each signal input terminal of the multiplexer is respectively coupled to the signal output terminal of one of the second group of detection units, the address input terminal is configured to receive an address bit to determine the second group of detection units, and the signal output terminal of the multiplexer is configured to select the signal output terminal of the second group of detection units for signal output.

[0015] According to one aspect of the present invention, the power switch circuit and the multiplexer share some address bits.

[0016] According to one aspect of the present invention, the photodetector array includes N detection units, the power switch circuit includes M voltage output terminals, and the multiplexing circuit includes P signal input terminals, where N, M and P are all positive integers, and P*M≥N.

[0017] According to one aspect of the present invention, M=N or M=1.

[0018] According to one aspect of the present invention, the photodetector array further includes a common power supply terminal coupled to a fixed voltage, and the photodetectors of the plurality of detection units are all coupled to the common power supply terminal.

[0019] According to one aspect of the present invention, the photodetector comprises a silicon photomultiplier tube.

[0020] According to one aspect of the present invention, the circuit also includes a controller, which is coupled to the power switch circuit and the multiplexer and is configured to sequentially select each of the first group of photodetection units and / or the second group of photodetection units until the detection and signal output of each photodetection unit are completed.

[0021] According to one aspect of the present invention, the controller is coupled to the address input terminal of the power switch circuit, thereby selecting one of the first group detection units among the multiple first group detection units by providing the address bit provided to the address input terminal of the power switch circuit; the multiplexer has an address input terminal, and the controller is coupled to the address input terminal of the multiplexer, thereby selecting the output terminal of one of the second group detection units among the multiple second group detection units by providing the same address bit as the address input terminal of the power switch circuit to the address input terminal of the multiplexer.

[0022] The present invention also provides a laser radar, comprising:

[0023] a transmitting unit configured to emit a laser beam for detecting a target object; and

[0024] The receiving unit comprises the circuit as described above, wherein the photodetector array in the circuit is configured to receive the echo of the laser beam on the target object and convert it into an electrical signal.

[0025] The present invention further provides a method for multiplexing a photodetector array, wherein the photodetector array includes a plurality of detection units, each detection unit including a power input terminal, a signal output terminal, and a photodetector, wherein the signal output terminal of each detection unit is coupled to one of the input terminals of a multiplexing circuit, the method comprising:

[0026] S101: simultaneously providing power input to a first group of detection units among the plurality of detection units; and

[0027] S102: enabling the output end of the second group of detection units among the plurality of detection units through the multiplexing circuit for output, wherein the first group of detection units and the second group of detection units have only one detection unit in common.

[0028] According to one aspect of the present invention, the number of detection units in the first group of detection units and the second group of detection units are both multiple; or the number of detection units in one of the first group of detection units and the second group of detection units is multiple, and the number of detection units in the other group is 1.

[0029] According to one aspect of the present invention, step S101 includes: determining the first group of detection units through a power switching circuit and providing power input to the first group of detection units, wherein the power switching circuit includes a voltage input terminal, an address input terminal and a voltage output terminal, wherein the voltage input terminal is configured to receive a bias voltage, each voltage output terminal is respectively coupled to the power input terminal of one of the first group of detection units, the address input terminal is configured to receive an address bit to determine the first group of detection units, and outputs the bias voltage from one of the voltage output terminals corresponding to the address bit.

[0030] According to one aspect of the present invention, step S101 also includes: determining the second group of detection units through a multiplexer, and selecting the second group of detection units for signal output, wherein the multiplexer includes a signal input terminal, an address input terminal and a signal output terminal, wherein each signal input terminal of the multiplexer is respectively coupled to the signal output terminal of one of the second group of detection units, the address input terminal is configured to receive an address bit to determine the second group of detection units, and the signal output terminal of the multiplexer is configured to select the signal output terminal of the second group of detection units for signal output.

[0031] According to one aspect of the present invention, the power switch circuit and the multiplexer share some address bits.

[0032] According to one aspect of the present invention, the photodetector array includes N detection units, the power switch circuit includes M voltage output terminals, and the multiplexing circuit includes P input terminals, where N, M, and P are all positive integers, and P*M≥N.

[0033] According to one aspect of the present invention, M=N or M=1.

[0034] According to one aspect of the present invention, the photodetector array further includes a common power supply terminal coupled to a fixed voltage, and the photodetectors of the plurality of detection units are all coupled to the common power supply terminal.

[0035] According to one aspect of the present invention, the photodetector comprises a silicon photomultiplier tube.

[0036] According to one aspect of the present invention, the method further comprises:

[0037] S103: changing the first group of detection units and / or the second group of detection units, and repeating steps S101 and S102 until the detection and output of each detection unit are completed.

[0038] The present invention provides a circuit and method for multiplexing photodetector arrays. Through the circuit connection method of the present invention, a multiplexer with the same number of input channels can support a greater number of photodetector channels (e.g., double the number of channels), reducing packaging complexity and accommodating a greater number of channels (e.g., doubling the number of channels) within the same PCB area. Alternatively, for a photodetector array with the same number of channels, the package size can be reduced, while the power switching circuit only supplies power to the selected photodetector channels, thus saving power. The circuit and method designed by the present invention are suitable for reducing circuit cost and complexity in PCB and IC design, as well as reducing the number of pins in SiPM array packaging design. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0040] Figure 1 Shows a schematic diagram of an existing 8-to-1 multiplexing circuit;

[0041] Figure 2 Shows a schematic diagram of an existing 32-channel common anode SiPM array device;

[0042] Figure 3 A schematic diagram of a circuit for photodetector array multiplexing according to an embodiment of the present invention is shown;

[0043] Figure 4 shows a schematic diagram of the SiPM structure;

[0044] Figure 5 A schematic diagram of a 32-channel common anode SiPM array device according to an embodiment of the present invention is shown;

[0045] Figure 6 Schematic diagram of pin multiplexing of a 32-channel common anode SiPM array according to the first embodiment of the present invention is shown;

[0046] Figure 7 A schematic diagram of pin multiplexing of a 32-channel common anode SiPM array according to a second embodiment of the present invention is shown;

[0047] Figure 8 FIG2 shows a schematic diagram of the pins of a 16-channel SiPM array according to a third embodiment of the present invention;

[0048] Figure 9 A schematic diagram of a laser radar module according to an embodiment of the present invention is shown; and

[0049] Figure 10 A flow chart of a method for photodetector array multiplexing according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0050] Hereinafter, only certain exemplary embodiments are briefly described. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways without departing from the spirit or scope of the present invention. Therefore, the drawings and description are to be considered as illustrative in nature and not restrictive.

[0051] In the description of the present invention, it should be understood that terms such as "center," "longitudinal," "transverse," "length," "width," "thickness," "up," "down," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inside," "outside," "clockwise," and "counterclockwise" are used to indicate positions or relationships based on those shown in the accompanying drawings. These terms are intended solely to facilitate description and simplify the description of the present invention and are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed to indicate or imply relative importance or to implicitly specify the number of the technical features referred to. Thus, features designated "first" or "second" may explicitly or implicitly include one or more of the designated features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0052] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they may refer to fixed, removable, or integral connections; mechanical, electrical, or intercommunication connections; direct or indirect connections through an intermediary; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of these terms in the present invention based on specific circumstances.

[0053] In the present invention, unless otherwise expressly specified or limited, "above" or "below" a first feature may include direct contact between the first and second features, or may include contact between the first and second features not in direct contact but via another feature between them. Furthermore, "above," "above," and "above" a first feature may include both directly above and diagonally above the second feature, or simply indicate that the first feature is at a higher level than the second feature. "Below," "below," and "below" a first feature may include both directly above and diagonally above the second feature, or simply indicate that the first feature is at a lower level than the second feature.

[0054] The disclosure below provides many different embodiments or examples for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. In addition, the present invention may repeat reference numerals and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides examples of various specific processes and materials, but those skilled in the art will appreciate the application of other processes and / or the use of other materials.

[0055] The present invention provides a circuit and method for multiplexing a photodetector array. Through the circuit connection method of the present invention, a multiplexer with the same number of channels can support a greater number of channels (e.g., double the number of channels), reducing packaging difficulty and enabling the same PCB area to accommodate a greater number of channels (e.g., double the number of channels). Alternatively, for a photodetector array with the same number of channels, the package size is reduced, and the power switch circuit only powers the selected photodetectors, thereby saving power. In the context of the present invention, a channel refers to a photodetector, and the number of channels refers to the number of photodetectors. The photodetectors can be SiPMs. The circuit and method designed by the present invention are suitable for reducing circuit cost and complexity in PCB and IC design, as well as reducing the number of pins in SiPM array packaging design.

[0056] The preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0057] The present invention relates to a circuit 10 for multiplexing a photodetector array, such as Figure 3 As shown, it includes a photodetector array 11 , a power switch circuit 12 and a multiplexer 13 .

[0058] The photodetector array 11 includes a plurality of detection units 111 (also referred to as a plurality of detection channels). Figure 3 111-1, 111-2, and 111-n. Each detection unit 111 includes a power input terminal, a signal output terminal, and a photodetector. The photodetector is configured to detect light signals and convert the light signals into electrical signals. In each detection unit 111, the power input terminal is used to provide a driving voltage or driving current to the photodetector, so that the photodetector is in an operating state capable of detecting light signals. The electrical signal generated by the photodetector is output through the signal output terminal.

[0059] The photodetector may be a silicon photomultiplier (SiPM), which is a commonly used high-sensitivity photodetection device. Figure 4 The schematic diagram of the SiPM structure is shown. The SiPM is a three-port device with an anode, a cathode and a signal output terminal. It includes multiple single photon avalanche diodes (SPADs), multiple quenching resistors R and multiple fast output capacitors C. The connection method is as follows: Figure 4 As shown, each SPAD is connected in series with a quenching resistor R between the cathode and anode. Multiple SPADs and quenching resistors R are connected in parallel. For each SPAD, the position between it and the quenching resistor R is coupled to the output terminal of the SiPM through a fast output capacitor C. Multiple SiPMs form a detection unit 111, which is part of the photodetector array 11 in a common cathode or common anode circuit form. When multiple SiPMs share a common anode, the anode is connected to a fixed voltage (such as ground), and each cathode is connected to the power switch circuit 12 through the power input terminal of the detection unit 111; when multiple SiPMs share a common cathode, the cathode is connected to a fixed voltage (such as ground), and each anode is connected to the power switch circuit through the power input terminal of the detection unit 111. Its working process is as follows: when a single photon is incident on a SPAD, if the photon is detected by the SPAD, it will cause the SPAD to undergo a Geiger avalanche. The charge accumulated in the junction capacitance of the SPAD will flow from the P pole to the N pole through the avalanche effect, causing the bias voltage at both ends of the SPAD to drop. The SPAD Geiger avalanche stops, and the voltage change ΔV at both ends of the SPAD is output through the fast output capacitor C. After that, it is charged to both ends of the SPAD's junction capacitance through the quenching resistor R, restoring it to the Geiger mode. Only when the SPAD returns to the Geiger mode can it continue to respond to the next photon. The time it takes for the quenching resistor R to charge the junction capacitance of the SPAD is the recovery time of the device. Figure 4 In the SiPM device model schematic diagram, the anode and / or cathode of the SiPM is electrically connected to the power input terminal of the above-mentioned detection unit 111, which is used to establish an operating voltage for the SiPM, and the signal output terminal of the SiPM is electrically connected to the signal output terminal of the above-mentioned detection unit 111.

[0060] When multiple photons strike different SPADs, they cause Geiger avalanches in multiple SPADs. The multiple fast output capacitors C connected to these avalanching SPADs then accumulate the voltage changes ΔV across each SPAD and output them. The magnitude of this accumulated voltage output is positively correlated with the number of SPADs experiencing Geiger avalanches. The more SPADs experiencing Geiger avalanches, the more charge is applied to the junction capacitance via the quenching resistor R, resulting in a greater charging current.

[0061] The photodetector array 11 composed of SiPM is generally a one-dimensional or two-dimensional array, wherein the two-dimensional array can be two or more columns. According to a preferred embodiment of the present invention, a 32-channel common anode SiPM array device is taken as an example. Figure 5 As shown, pins C1-C32 are connected to the cathodes of 32 SiPMs in the SiPM array, and pins F1-F32 are connected to the signal output terminals of 32 SiPMs in the SiPM array (refer to Figure 4 ), the other 32 SiPMs have a common anode (Anode), so Figure 5 The chip of the photodetector array 11 shown has a total of 65 pins, of which 32 cathodes are connected to the power switch circuit 12, and the anodes are connected to a fixed voltage (such as ground). The voltage difference between the cathodes and the anodes is the bias voltage VB applied to the SiPM. Figure 5 In a common-anode SiPM array device, pins C1-C32 constitute the voltage input terminals of each detection unit 111. Those skilled in the art will readily appreciate that, in addition to a common-anode connection, multiple detection units 111 can also be connected using a common-cathode connection, all of which fall within the scope of the present invention. An embodiment including a 32-channel common-anode SiPM array will be described in detail below. Furthermore, while the above description of photodetectors uses SiPMs as an example, the present invention is not limited thereto; other types of photodetectors capable of converting optical signals into electrical signals may also be used.

[0062] The power switch circuit 12 has a power input terminal and multiple voltage output terminals, wherein the voltage output terminal is coupled to the voltage input terminal of each detection unit 111 of the photodetector array 11, and the multiple detection units 111 are divided into multiple first-group detection units. The power switch circuit 12 is configured to select one of the multiple first-group detection units and provide power input to the first-group detection unit. Specifically, the power switch circuit 12 includes a voltage input terminal VBIAS, address input terminals A0-A3 and voltage output terminals V1-V16. The voltage input terminal VBIAS is configured to receive a bias voltage VB. Each voltage output terminal is respectively coupled to the power input terminal of one of the first group detection units. The power input terminal of each first group detection unit is different, and the power input terminals of all first group detection units correspond to all detection units. The address input terminals A0-A3 are configured to receive an address bit to select one of the multiple first group detection units, and output the bias voltage VB from one of the voltage output terminals corresponding to the address bit. Therefore, all photodetectors 111 in a first group detection unit corresponding to the voltage output terminal can be affected by the bias voltage VB and be in a working state.

[0063] The multiplexer 13 has multiple signal input terminals and signal output terminals, which are coupled to the signal output terminals of each detection unit 111 of the photodetector array 11. The multiple detection units 111 are divided into multiple second-group detection units. The multiplexer 13 is configured to select one of the multiple second-group detection units and select the signal output terminal of the second-group detection unit for signal output. Each signal input terminal is respectively coupled to the signal output terminal of one of the second-group detection units. The signal output terminal of each second-group detection unit is different, and the signal output terminals of all second-group detection units correspond to all detection units. Specifically, the multiplexer 13 includes signal input terminals S1-S16, address input terminals A0'-A3', and a signal output terminal FOUT. The signal input terminals S1-S16 of the multiplexer 13 are coupled to the signal output terminal of each detection unit 111 of the photodetector array 11. The address input terminals A0'-A3' are configured to receive address bits to select one of the plurality of second-group detection units. The signal output terminal FOUT of the multiplexer 13 is configured to select the signal output terminal of one of the second-group detection units for signal output. The multiplexer can be an analog multiplexer (MUX), an application-specific integrated circuit (ASIC), or other types, all of which are within the scope of protection of the present invention.

[0064] In summary, there is only one detection unit 111 in common between one of the first group of detection units selected by the power switch circuit 12 and one of the second group of detection units selected by the multiplexer 13, thereby ensuring that even if multiple detection units 111 are in working state, they can detect echoes and actually generate electrical signals, but through the multiplexer 13, only the detection signal output of one of the detection units 111 is realized, thereby realizing that the photodetector array 11 shares a group of post-stage circuits.

[0065] Regarding the division of the plurality of detection units 111 into a plurality of first group detection units and a plurality of second group detection units, and how to select one of the first group detection units and one of the second group detection units, reference will be made below. Figure 6 Detailed description.

[0066] According to a preferred embodiment of the present invention, if the photodetector array 11 includes N channels (i.e., N detection units 111), the power switch circuit 12 includes M channels (i.e., M voltage output terminals), and the multiplexing circuit 13 includes P channels (i.e., P signal input terminals), where N, M, and P are all positive integers, as long as P*M≥N is satisfied, the pin multiplexing of the photodetector array can be implemented according to the preferred embodiment.

[0067] Figure 6 In the circuit 10 of the embodiment, the number of channels N of the photodetector array 11 is 32, the number of channels M of the power switch circuit 12 is 16, and the number of channels P of the multiplexing circuit 13 is 16, so M*P>N, satisfying the above-mentioned multiplexing condition; Figure 7 In the circuit 10 of the embodiment, the number of channels N of the photodetector array 11 is 32, the number of channels M of the power switch circuit 12 is 4, and the number of channels P of the multiplexing circuit 13 is 8. Thus, M*P=N, satisfying the aforementioned multiplexing condition. For another example, in another circuit, N=32, M=3, and P=11, also satisfying the multiplexing condition M*P>N.

[0068] Figure 6 FIG. 1 shows a circuit 10 for multiplexing a photodetector array according to a preferred embodiment of the present invention, which includes a 16-channel power switch circuit 12, a 32-channel photodetector array 11, and a 16-channel multiplexing circuit 13. Figure 6 As shown, the photodetector array 11 includes 32 detection units 111 (which can also be represented by C1-F1, C2-F2, ..., C32-F32), including signal input pins C1-C32 corresponding to the cathodes of the 32 detection units and 32 signal output pins F1-F32. The anodes of the 32 detection units are shared and connected to the pin ANODE. The power switch circuit 12 includes a voltage input terminal VBIAS, an address input port A0-A3, and a voltage output terminal V1-V16. The voltage input terminal VBIAS is used to receive a bias voltage VB. The power switch circuit 12 selects one of the voltage output terminals C1-C16 and outputs the bias voltage VB according to the address bit received by the address input port A0-A3. The bias voltage VB can be set to different bias voltages according to the type of detection unit in the photodetector array 11, which will not be described in detail here.

[0069] like Figure 6As shown, the multiple detection units 111 in the photodetector array 11 are divided into multiple first groups of detection units. Specifically, the two detection units corresponding to pins C1 and C4 form one first group of detection units, the two detection units corresponding to pins C2 and C3 form another first group of detection units, and so on. Each of the voltage output terminals V1-V16 of the power switch circuit 12 is electrically connected to the two power input terminals of one of the first group of detection units. Specifically, the first group of detection units formed by pins C1 and C4 of the photodetector array 11 is connected to the voltage output terminal V1 of the power switch circuit 12; the first group of detection units formed by pins C2 and C3 of the photodetector array 11 is connected to the voltage output terminal V2 of the power switch circuit 12, and so on; the multiple detection units 111 in the photodetector array 11 are further divided into multiple second groups of detection units. Specifically, the two detection units corresponding to pins F1 and F2 form one of the second groups of detection units, and the two detection units corresponding to pins F3 and F4 form another second group of detection units, and so on; the second group of detection units formed by pins F1 and F2 is connected to the signal input terminal S1 of the multiplexing circuit 13; the second group of detection units formed by pins F3 and F4 is connected to the signal input terminal S2 of the multiplexing circuit, and so on.

[0070] The division of the first group of detection units into the second group of detection units is not limited to the above situation. For example, the two detection units corresponding to pins C1 and C3 may form one of the first group of detection units, the two detection units corresponding to pins F1 and F3 may form one of the second group of detection units, and so on. The division of the first group of detection units into the second group of detection units is typically achieved by soldering the pins of the SiPM array together on a PCB using traces, but is not limited to this. For example, a multiplexing circuit may be coupled between the power switch circuit 12 and the photodetector array 11 to achieve dynamic division of the first group of detection units, and a multiplexing circuit may be coupled between the photodetector array 11 and the multiplexing circuit 13 to achieve dynamic division of the second group of detection units. All of these are within the scope of protection of the present invention.

[0071] In the working state, if the power switch circuit 12 is controlled by the address input terminals A0-A3 to select the voltage output terminal V1, and the voltage output terminal V1 outputs the bias voltage VB, then two detection units (C1-F1 and C4-F4) in the first group of detection units are applied with the bias voltage VB. At the same time, the signal input terminal S1 is selected by the multiplexing circuit 13, then two detection units (C1-F1 and C2-F2) in the second group of detection units output signals. At this time, only the detection unit C1-F1 is both applied with the bias voltage VB and selected for output, and although the detection unit C4-F4 is applied with the bias voltage, it is not selected for output. At the next moment, if the address input terminals A0-A3 are used to control the voltage output terminal V2 of the power switch circuit 12 to supply power, two detection units (C2-F2 and C3-F3) in the first group of detection units are applied with a bias voltage VB. At the same time, the signal input terminal S1 is selected through the multiplexing circuit 13, and two detection units (C1-F1 and C2-F2) in the second group of detection units output signals. At this time, only the detection unit C2-F2 works normally, and is both applied with voltage and selected for output. Although the detection unit C1-F1 is applied with a bias voltage, it is not selected for output. By analogy, the single-channel gating function of the photodetector array is finally realized.

[0072] Furthermore, to achieve the above functions, the power switch circuit 12 and the multiplexing circuit 13 share some address bits. Figure 6 As shown, the address bits of the two are not exactly the same. Specifically, the power switch circuit 12 includes four address input ports A0-A3 for receiving externally provided address bits a0, a2, a3 and a4; the multiplexing circuit 13 also includes four address input terminals A0'-A3' for receiving externally provided address bits a1, a2, a3 and a4. When the externally provided address bits a0-a4 are 00000, the power switch circuit 12 selects the first detection unit C1-F1 and the fourth detection unit C4-F4 in the first group of detection units, and supplies power to the first detection unit C1-F1 and the fourth detection unit C4-F4 through the voltage input terminal VB. Simultaneously, the multiplexing circuit 13 selects the first detection unit C1-F1 and the second detection unit C2-F2 in the second group of detection units according to the address 00000, and causes the signal input terminals F1 and F2 of the selected multiplexing circuit 13 to collect the output signals of the corresponding detection units. In summary, only the first detection unit is both applied with voltage and selected for output, and the collected signal is ultimately output through the signal output terminal of the multiplexing circuit 13. As for the fourth detection unit, although voltage is applied to it, its signal output terminal is not selected to output a signal. As for the second detection unit, although its signal output terminal is selected to output a signal, voltage is not applied to it, and therefore no output signal is generated.

[0073] The table below shows Figure 6 The channel selection logic truth table of the embodiment is as follows: the external 5-bit address bits a0-a4 are provided, wherein the power switch circuit 12 receives the address bits a0, a2, a3 and a4, and the multiplexing circuit 13 receives the address bits a1, a2, a3 and a4, as shown in the following table. When the address bit is 00000, the power switch circuit 12 receives 0000, the multiplexing circuit 13 receives 0000, and the actual output channel is channel 1, that is, the detection unit C1-F1; when the address bit is 00001, the power switch circuit 12 receives 0001, the multiplexing circuit 13 receives 0000, and the actual output channel is channel 1, that is, the detection unit C1-F1; when the address bit is 00001, the power switch circuit 12 receives 0001, the multiplexing circuit 13 receives 0000 When receiving 0001, the actual output channel is channel 2, that is, detection units C2-F2. Similarly, when the address bit is 11110, the power switch circuit 12 receives 1110, and the multiplexing circuit 13 receives 1110, and the actual output channel is 32, that is, detection units C32-F32. When the address bit is 11111, the power switch circuit 12 receives 1111, and the multiplexing circuit 13 receives 1111, and the actual output channel is channel 31, that is, detection units C31-F31. In this way, the 32-channel photodetector array is multiplexed with the 16-channel power switch circuit and the 16-channel multiplexer.

[0074] Address lines a[0:4] Powered Cx Selected Fx Actual output channel 0(00000) C1+C4 F1+F2 Channel 1 1(00001) C2+C3 F1+F2 Channel 2 2(00010) C1+C4 F3+F4 Channel 4 3(00011) C2+C3 F3+F4 Channel 3 …… …… …… 31(11111) C30+C31 F31+F32 Channel 31

[0075] The present invention has no particular requirements for the number of detection units included in the first and second groups of detection units, as long as the first and second groups of detection units share only one detection unit. According to a preferred embodiment of the present invention, both groups have multiple detection units, such as the photodetector array in the above embodiment, whose input and output are both multiplexed; or one of the first and second groups of detection units has multiple detection units, while the other group has only one detection unit, i.e., only the input or output is multiplexed.

[0076] Figure 7A schematic diagram of multiplexing a 32-channel common anode photodetector array according to another embodiment of the present invention is shown. Circuit 10 includes a 4-channel power switch circuit 12, a 32-channel photodetector array 11, and an 8-channel multiplexing circuit 13. The photodetector array 11 includes 32 detection units 111, which are divided into four first-group detection units. Signal input terminals C1-C32, including C1, C5, C9, C13, C17, C21, C25, and C29, form one of the first-group detection units and are connected to the voltage output terminal V1 of the power switch circuit. Signal input terminals C2, C6, C10, C14, C18, C22, C26, and C30 of the photodetector array 11 form one of the first-group detection units and are connected to the voltage output terminal V2 of the power switch circuit, and so on. Similarly, the photodetector array 11 is further divided into eight second-group detection units. Specifically, Four adjacent ones of the signal output terminals F1-F32 are connected respectively, and the signal output terminals F1-F4 form one of the second group of detection units, which are connected to the signal input terminal S1 of the multiplexing circuit 13; the signal output terminals F5-F8 form one of the second group of detection units, which are connected to the signal input terminal S2 of the multiplexing circuit 13, and so on; when the address bits a0-a4 are 00000, the address bits received by the power switch circuit 12 are 0000, and the corresponding voltage output terminal V1 selects a first group of detection units in the photodetector array 11, namely, the detection units C1-F1, C5-F5, C9-F9, C13-F13, C17-F17, C21-F21, C25-F25, and C29-F29. The first group of detection units is powered by the bias voltage VB; at the same time, the address bit 0000 received by the multiplexing circuit 13 is used to select a second group of detection units in the photodetector array 11, namely, including detection units C1-F1, C2-F2, C3-F3, and C4-F4, and the signal input terminal S1 of the selected multiplexing circuit receives the output signal of the second group of detection units. In summary, only the photodetectors C1-F1 are both applied with voltage and selected for output, and the final collected signal is output through the signal output terminal of the multiplexing circuit 13.

[0077] As described above, if the photodetector array 11 includes N channels (i.e., N detection units 111), the power switch circuit 12 includes M channels (i.e., M voltage output terminals), and the multiplexing circuit 13 includes P channels (i.e., P signal input terminals), where N, M, and P are all positive integers, pin multiplexing of the photodetector array can be achieved according to the preferred embodiment as long as P*M≥N is satisfied. However, the values ​​of M and P in actual circuits are limited by circuit performance and parameters. Specifically, the number of channels M of the power switch circuit 12 determines the power consumption of the circuit 10. When M=N, it is the most power-saving configuration, and only one channel of the photodetector array 11 is powered. When M=1, all channels are powered, and the power consumption of the power switch circuit 12 is the highest. The number of channels P in multiplexing circuit 13 determines the signal quality of circuit 10. For photodetector array 11, parallel connection of channels increases load impedance, reduces output signal amplitude, and consequently reduces the signal-to-noise ratio of photodetector array 11. For example, if signal output terminals F1-F4 are connected in parallel, when signal output terminal F1 outputs a signal, signal output terminals F2-F4 act as a load on F1, reducing the signal amplitude at F1. Furthermore, too many parallel channels can lead to longer PCB traces. The parasitic capacitance and inductance of these traces can reduce signal bandwidth, impacting output signal quality. When designing circuits, trade-offs can be made based on factors such as power consumption, bandwidth, and signal quality.

[0078] According to a preferred embodiment of the present invention, the photodetector array 11 further includes a common power supply terminal coupled to a fixed voltage, to which the photodetectors of the plurality of detection units 111 are all coupled. This preferred embodiment uses a common anode SiPM array as an example; however, common cathode SiPM arrays or photodetector arrays of other circuit forms or types are also within the scope of protection of the present invention.

[0079] like Figure 3 As shown, according to a preferred embodiment of the present invention, the circuit 10 further includes a controller 14, which is coupled to the power switch circuit 12 and the multiplexer 13 to provide a common address bit, for example, to generate and output Figure 6 and 7 The address bits a0-a4 shown are configured to sequentially select each of the first group of photoelectric detection units and / or the second group of photoelectric detection units until detection and signal output of each photoelectric detection unit are completed.

[0080] Specifically, the controller 14 is coupled to the address input of the power switch circuit 12, thereby selecting the first group of detection units by providing an address bit to the address input of the power switch circuit 12. The multiplexer 13 also has an address input, and the controller 14 is coupled to the address input of the multiplexer 13, thereby selecting the output of the second group of detection units by providing an address bit to the address input of the multiplexer 13. The power switch circuit 12 and the multiplexer 13 share some address bits. Based on the logical truth table of the address bits provided by the controller 14, the first group of detection units includes different detection units 111, and the second group of detection units also includes different detection units 111. Only one detection unit 111 is shared between the two groups of detection units 111. By selecting the address bits, all detection units 111 of the photodetector array 11 can be traversed.

[0081] In addition to reducing the number of channels in the multiplexing circuit 13 and the power switch circuit 12, embodiments of the present invention can also reduce the pin count of the photodetector array. Reducing the pin count significantly helps reduce both package size and packaging costs. For SiPM arrays, by connecting the signal input terminals Cn and the signal output terminals Fn in parallel according to a specific pattern, where n is a positive integer greater than zero, the number of required pins can be reduced exponentially without introducing additional processing or costs.

[0082] Figure 8 The pin diagram of the 16-channel photodetector array of the embodiment of the present invention is shown. According to a preferred embodiment of the present invention, in addition to being used on a PCB board, it can also be used for a customized ASIC (Application Specific Integrated Circuit). For a 16-channel SiPM array, a total of 33 pins are usually required, including the power input terminal C[16:1] + the signal output terminal F[16:1] + the common power terminal (cathode ANODE). If the multiplexing method of the present invention is used, with P=8 and M=8, the package can be simplified to Figure 8As shown, only 17 pins are required. Specifically, at the power input end, pin M1 is the multiplexed pin of signal input terminals C1 and C2, pin M2 is the multiplexed pin of signal input terminals C3 and C4, pin M3 corresponds to the multiplexed pin of signal input terminals C5 and C6, pin M4 is the multiplexed pin of signal input terminals C7 and C8, pin M5 is the multiplexed pin of signal input terminals C9 and C10, pin M6 is the multiplexed pin of signal input terminals C11 and C12, and pin M7 is the multiplexed pin of signal input terminals C13 and C14. Pin M8 is the multiplexed pin of signal input terminals C15 and C16; at the signal output end, pin N1 is the multiplexed pin of signal output terminals F1 and F4, pin N2 is the multiplexed pin of signal output terminals F2 and F3, pin N3 is the multiplexed pin of signal output terminals F5 and F8, pin N4 is the multiplexed pin of signal output terminals F6 and F7, pin N5 is the multiplexed pin of signal output terminals F9 and F12, pin N6 is the multiplexed pin of signal output terminals F10 and F11, pin N7 is the multiplexed pin of signal output terminals F13 and F16, and pin N8 is the multiplexed pin of signal output terminals F14 and F15. In the working state, for example, based on the address bit, pin M1 is selected through the power switch circuit 12, and pin N1 is selected through the multiplexer 13. At this time, only channel 1 (having a signal input terminal C1 and a signal output terminal F1) is both applied with voltage and selected for output, and so on, ultimately realizing the single-channel selection function of the photodetector array 11 customized into an ASIC.

[0083] The present invention also provides a laser radar 20, such as Figure 9 Shown, including:

[0084] a transmitting unit 21 configured to transmit a laser beam for detecting a target object; and

[0085] The receiving unit 22 includes the circuit 10 as described above, wherein the photodetector array 11 in the circuit 10 is configured to receive the echo of the laser beam on the target object and convert it into an electrical signal.

[0086] The present invention also provides a method 30 for multiplexing a photodetector array, such as Figure 10 As shown, the photodetector array 11 includes a plurality of detection units 111, each detection unit 111 includes a power input terminal, a signal output terminal, and a photodetector, and the signal output terminal of each detection unit 111 is coupled to one of the input terminals of the multiplexing circuit 13. The method includes:

[0087] In step S101 : simultaneously providing power input to a first group of detection units among the plurality of detection units 111 ; and

[0088] In step S102 : the multiplexing circuit 13 is used to select the output ends of the second group of detection units in the plurality of detection units 111 for output, wherein the first group of detection units and the second group of detection units have only one detection unit 111 in common.

[0089] The method 100 may be executed, for example, by the circuit 10 as described above.

[0090] According to a preferred embodiment of the present invention, the number of detection units in the first group of detection units and the second group of detection units are both multiple; or the number of detection units in one of the first group of detection units and the second group of detection units is multiple, and the number of detection units in the other group is 1. Figure 6 and Figure 7 The diagram shows a case where both the first group of detection units and the second group of detection units have multiple detection units.

[0091] According to a preferred embodiment of the present invention, step S101 includes: determining the first group of detection units through the power switching circuit 12, and providing power input to the first group of detection units, wherein the power switching circuit 12 includes a voltage input terminal, an address input terminal and a voltage output terminal, wherein the voltage input terminal is configured to receive a bias voltage, each voltage output terminal is respectively coupled to the power input terminal of one of the first group of detection units 111, the address input terminal is configured to receive an address bit to determine the first group of detection units, and output the bias voltage from one of the voltage output terminals corresponding to the address bit.

[0092] According to a preferred embodiment of the present invention, step S101 further includes: determining the second group of detection units through a multiplexer 13, and selecting the second group of detection units for signal output, wherein the multiplexer 13 includes a signal input terminal, an address input terminal and a signal output terminal, wherein each signal input terminal of the multiplexer 13 is respectively coupled to the signal output terminal of one of the second group of detection units 111, the address input terminal is configured to receive an address bit to determine the second group of detection units, and the signal output terminal of the multiplexer 13 is configured to select the signal output terminal of the second group of detection units for signal output.

[0093] According to a preferred embodiment of the present invention, the power switch circuit and the multiplexer share some address bits.

[0094] According to a preferred embodiment of the present invention, the photodetector array 11 includes N detection units, the power switch circuit 12 includes M voltage output terminals, and the multiplexing circuit 13 includes P input terminals, where N, M and P are all positive integers, and P*M≥N.

[0095] According to a preferred embodiment of the present invention, M=N or M=1.

[0096] According to a preferred embodiment of the present invention, the photodetector array further includes a common power supply terminal, the common power supply terminal is coupled to a fixed voltage, and the photodetectors of the plurality of detection units are all coupled to the common power supply terminal.

[0097] According to a preferred embodiment of the present invention, the photodetector comprises a silicon photomultiplier tube.

[0098] According to a preferred embodiment of the present invention, the method 30 further includes:

[0099] S103: changing the first group of detection units and / or the second group of detection units, and repeating steps S101 and S102 until the detection and output of each detection unit are completed.

[0100] The present invention provides a multiplexing method for photodetector arrays 11, achieving the same functionality as the prior art with a reduced number of channels in multiplexing circuits 13 and power switch circuits 12. This method is suitable for reducing circuit cost and complexity in PCB and IC design, as well as reducing the number of pins in SiPM array packaging design.

[0101] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art will be able to modify the technical solutions described in the aforementioned embodiments or substitute equivalents for some of the technical features. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A circuit for multiplexing a photodetector array, the circuit comprising: A photodetector array comprising a plurality of detection units, each detection unit comprising a power input terminal, a signal output terminal and a photodetector, wherein the photodetector is configured to detect an optical signal and convert the optical signal into an electrical signal; a power switch circuit coupled to a power input terminal of each detection unit of the photodetector array, configured to determine a first group of detection units among the plurality of detection units and to simultaneously provide power input to the first group of detection units; a multiplexer coupled to a signal output terminal of each detection unit of the photodetector array, configured to selectively enable a signal output terminal of a second group of detection units among the plurality of detection units to output a signal, wherein the first group of detection units and the second group of detection units have only one detection unit in common; The number of detection units in both the first group of detection units and the second group of detection units is multiple; or the number of detection units in one of the first group of detection units and the second group of detection units is multiple, and the number of detection units in the other group is one.

2. The circuit of claim 1 , wherein the power switch circuit comprises a voltage input terminal, an address input terminal, and a voltage output terminal, wherein the voltage input terminal is configured to receive a bias voltage, each voltage output terminal is respectively coupled to a power input terminal of one of the first group of detection units, and the address input terminal is configured to receive an address bit to determine the first group of detection units and output the bias voltage from one of the voltage output terminals corresponding to the address bit.

3. The circuit of claim 2 , wherein the multiplexer comprises a signal input terminal, an address input terminal, and a signal output terminal, wherein each signal input terminal of the multiplexer is respectively coupled to a signal output terminal of one of the second group of detection units, the address input terminal is configured to receive an address bit to determine the second group of detection units, and the signal output terminal of the multiplexer is configured to select the signal output terminal of the second group of detection units for signal output.

4. The circuit of claim 3, wherein the power switch circuit and the multiplexer share some address bits.

5. The circuit of claim 1 , wherein the photodetector array comprises N detection units, the power switch circuit comprises M voltage output terminals, and the multiplexing circuit comprises P signal input terminals, where N, M, and P are all positive integers, and P*M≥N. The circuit of claim 5 , wherein M=N or M=1. 7 . The circuit of claim 1 , wherein the photodetector array further comprises a common power supply terminal coupled to a fixed voltage, and the photodetectors of the plurality of detection units are all coupled to the common power supply terminal.

8. The circuit of any one of claims 1 to 7, wherein the photodetector comprises a silicon photomultiplier tube.

9. The circuit according to any one of claims 1 to 7 further comprises a controller, wherein the controller is coupled to the power switch circuit and the multiplexer and is configured to sequentially select each of the first group of photodetection units and / or the second group of photodetection units until detection and signal output of each photodetection unit are completed.

10. A circuit as claimed in claim 9, wherein the controller is coupled to the address input terminal of the power switch circuit, thereby selecting one of the first group detection units in the plurality of first group detection units by providing the address bit provided to the address input terminal of the power switch circuit; the multiplexer has an address input terminal, and the controller is coupled to the address input terminal of the multiplexer, thereby selecting the output terminal of one of the second group detection units in the plurality of second group detection units by providing the same address bit as the address input terminal of the power switch circuit to the address input terminal of the multiplexer.

11. A laser radar comprising: a transmitting unit configured to transmit a laser beam for detecting a target object; and A receiving unit comprising the circuit according to any one of claims 1 to 10, wherein the photodetector array in the circuit is configured to receive the echo of the laser beam on the target object and convert it into an electrical signal.

12. A method for multiplexing a photodetector array, the photodetector array comprising a plurality of detection units, each detection unit comprising a power input terminal, a signal output terminal, and a photodetector, the signal output terminal of each detection unit being coupled to one of the input terminals of a multiplexing circuit, the method comprising: S101: simultaneously providing power input to a first group of detection units among the plurality of detection units; and S102: enabling the output end of the second group of detection units among the plurality of detection units to output by the multiplexing circuit, wherein the first group of detection units and the second group of detection units have only one detection unit in common. The number of detection units in both the first group of detection units and the second group of detection units is multiple; or the number of detection units in one of the first group of detection units and the second group of detection units is multiple, and the number of detection units in the other group is one.

13. The method according to claim 12, wherein the step S101 comprises: The first group of detection units is determined by a power switching circuit, and a power input is provided to the first group of detection units, wherein the power switching circuit includes a voltage input terminal, an address input terminal and a voltage output terminal, wherein the voltage input terminal is configured to receive a bias voltage, and each voltage output terminal is respectively coupled to the power input terminal of one of the first group of detection units, and the address input terminal is configured to receive an address bit to determine the first group of detection units, and output the bias voltage from one of the voltage output terminals corresponding to the address bit.

14. The method according to claim 13, wherein the step S101 further comprises: The second group of detection units is determined by a multiplexer, and the second group of detection units is selected for signal output, wherein the multiplexer includes a signal input terminal, an address input terminal and a signal output terminal, wherein each signal input terminal of the multiplexer is respectively coupled to the signal output terminal of one of the second group of detection units, the address input terminal is configured to receive an address bit to determine the second group of detection units, and the signal output terminal of the multiplexer is configured to select the signal output terminal of the second group of detection units for signal output.

15. The method of claim 14, wherein the power switch circuit and the multiplexer share some address bits.

16. The method of claim 12, wherein the photodetector array comprises N detection units, the power switch circuit comprises M voltage output terminals, and the multiplexing circuit comprises P input terminals, N, M, and P are all positive integers, where P*M≥N. The method of claim 16 , wherein M=N or M=1.

18. The method according to claim 12, wherein the photodetector array further comprises a common power supply terminal coupled to a fixed voltage, and the photodetectors of the plurality of detection units are all coupled to the common power supply terminal.

19. The method of claim 12, wherein the photodetector comprises a silicon photomultiplier tube.

20. The method of claim 12, further comprising: S103: changing the first group of detection units and / or the second group of detection units, and repeating steps S101 and S102 until the detection and output of each detection unit are completed.

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