Four-level pulse amplitude modulation IO circuit

Abstract

The application relates to the technical field of integrated circuits, in particular to a four-level pulse amplitude modulation IO circuit. The four-level pulse amplitude modulation IO circuit comprises a level amplitude providing circuit, the level amplitude providing circuit comprises a first level providing circuit for providing a first level, a second level providing circuit for providing a second level, a third level providing circuit for providing a third level, and a fourth level providing circuit for providing a fourth level; the level amplitudes of the first level, the second level, the third level to the fourth level decrease in turn; a gating circuit is used for gating the output end of the corresponding level providing circuit according to transmission data; an output circuit is used for outputting the corresponding level output by the level providing circuit gated by the gating circuit; a load capacitor is arranged in the output circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a four-level pulse amplitude modulation IO circuit. BACKGROUND

[0002] A common single-ended signal digital IO drive circuit realizes the transmission of signal "1" and "0" by charging the interconnection line load capacitor to the power supply potential and discharging it to the ground potential. Generally, the load capacitor of the IO circuit is generally large, so the charging and discharging power consumption of the load capacitor constitutes the main part of the power consumption of the IO circuit, resulting in large power consumption of the IO circuit. SUMMARY

[0003] The present application provides a four-level pulse amplitude modulation IO circuit, which can solve the problem of large power consumption of the IO circuit in the related art.

[0004] In order to solve the technical problems described in the background art, the present application provides a four-level pulse amplitude modulation IO circuit, which comprises:

[0005] A level amplitude providing circuit, the level amplitude providing circuit comprises a first level providing circuit for providing a first level, a second level providing circuit for providing a second level, a third level providing circuit for providing a third level, and a fourth level providing circuit for providing a fourth level; the level amplitudes of the first level, the second level, the third level to the fourth level decrease in turn;

[0006] A gating circuit, the gating circuit is used for gating the output end of the corresponding level providing circuit according to the transmission data;

[0007] An output circuit, the output circuit is used for outputting the corresponding level output by the level providing circuit gated by the gating circuit; the output circuit is provided with a load capacitor.

[0008] Optionally, the second level providing circuit generates a second level having a first proportional relationship with the first level based on the first level and the fourth level.

[0009] Optionally, the third level providing circuit generates a third level having a second proportional relationship with the first level based on the first level and the fourth level.

[0010] Optionally, the second level providing circuit or / and the third level providing circuit comprises a PMOS tube and an NMOS tube.

[0011] The source of the PMOS transistor is configured to receive the first level, the drain of the PMOS transistor is connected to the source of the NMOS transistor as a level output terminal, the drain of the NMOS transistor is configured to receive the fourth level, and the drain of the NMOS transistor is connected to the level output terminal and connected to a multiplexing capacitor;

[0012] The gate of the PMOS transistor is connected to a first comparator, the non-inverting input terminal of the first comparator is connected to the level output terminal, and the inverting input terminal of the first comparator is connected to a first reference voltage;

[0013] The gate of the NMOS transistor is connected to a second comparator, the non-inverting input terminal of the second comparator is connected to the level output terminal, and the inverting input terminal of the second comparator is connected to a second reference voltage;

[0014] The second reference voltage is greater than the first reference voltage.

[0015] Optionally, the second reference voltage and the first reference voltage are pre-set according to the first level, a proportional relationship between a voltage output by the level output terminal and the first level, and an error range.

[0016] Optionally, the circuit further comprises first, second, third, fourth and fifth voltage dividing resistors R1, R2, R3, R4 and R5 connected in series from a ground terminal to a power supply terminal.

[0017] The voltage of the power supply terminal is the first level VDDH, and a node connected between the first voltage dividing resistor R1 and the second voltage dividing resistor R2 is configured to provide a first reference voltage VIL1 required by the third level providing circuit.

[0018] A node connected between the second voltage dividing resistor R2 and the third voltage dividing resistor R3 is configured to provide a second reference voltage VIH1 required by the third level providing circuit.

[0019] A node connected between the third voltage dividing resistor R3 and the fourth voltage dividing resistor R4 is configured to provide a first reference voltage VIL2 required by the second level providing circuit.

[0020] A node connected between the fourth voltage dividing resistor R4 and the fifth voltage dividing resistor R5 is configured to provide a second reference voltage VIH2 required by the second level providing circuit.

[0021] Optionally, the resistance ratios of the first, second, third, fourth and fifth voltage dividing resistors R1, R2, R3, R4 and R5 are as follows:

[0022] R1:R2:R3:R4:R5=VIL1:(VIH1-VIL1):(VIL2-VIH1):(VIH2-VIL1):(VDDH-VIH2).

[0023] The technical scheme of the present application has at least the following advantages: the strobe circuit can realize the transmission of signals with four levels of amplitude, can improve the data transmission rate of the four-level pulse amplitude modulation IO circuit at the same signal frequency, and can improve the efficiency and reduce the power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical scheme in the specific embodiments of the present application or the prior art, the drawings needed in the description of the specific embodiments or the prior art will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0025] Figure 1 A four-level pulse amplitude modulation IO circuit provided by an embodiment of the present application is shown in the schematic diagram.

[0026] Figure 2 The circuit schematic diagram of the level amplitude providing circuit provided by an embodiment is shown.

[0027] Figure 3 The circuit schematic diagram of the second level providing circuit or the third level providing circuit is shown.

[0028] Figure 4 The circuit for obtaining the second reference voltage VIH and the first reference voltage VIL is shown.

[0029] Figure 5 The signal switching schematic diagram of the four-level pulse amplitude modulation IO circuit is shown taking the first strobe circuit in the circuit as an example. Figure 1 The signal switching schematic diagram of the four-level pulse amplitude modulation IO circuit is shown taking the first strobe circuit in the circuit as an example. DETAILED DESCRIPTION

[0030] The technical scheme in the present application will be described in detail below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of the present application.

[0031] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0032] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements, it can be wireless connection, or it can be wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0033] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as there is no conflict.

[0034] Figure 1 The schematic diagram of the four-level pulse amplitude modulation IO circuit provided by an embodiment of the present application is shown, from Figure 1 It can be seen that the four-level pulse amplitude modulation IO circuit comprises a level amplitude providing circuit 110, a gating circuit and an output circuit.

[0035] The level amplitude providing circuit 110 comprises a first level providing circuit 111 for providing a first level VDDH, a second level providing circuit 112 for providing a second level, a third level providing circuit 113 for providing a third level, and a fourth level providing circuit 114 for providing a fourth level VSSH.

[0036] The level amplitudes of the first level VDDH, the second level, the third level to the fourth level VSSH decrease in turn.

[0037] Referring to Figure 2 , which shows the circuit schematic diagram of the level amplitude providing circuit provided by an embodiment, from Figure 2 It can be seen that:

[0038] The second level providing circuit 112 generates a second level having a first proportional relationship with the first level VDDH based on the first level VDDH and the fourth level VSSH. Optionally, the first proportional relationship between the second level and the first level VDDH is that the second level is two-thirds of the first level VDDH.

[0039] The third level providing circuit 113 generates a third level having a second proportional relationship with the first level VDDH based on the first level VDDH and the fourth level VSSH. Optionally, the second proportional relationship between the third level and the first level VDDH is that the third level is one-third of the first level VDDH.

[0040] The gating circuit is configured to gate the output of the corresponding level providing circuit according to the transmission data.

[0041] The output circuit is configured to output the corresponding level gated by the gating circuit.

[0042] With reference to the four-level pulse amplitude modulation IO circuit shown in Figure 1 , Figure 1 The four-level pulse amplitude modulation IO circuit includes first gating circuit 121, second gating circuit 122, …, and nth gating circuit 123, and further includes first output circuit 131, second output circuit 132, …, and nth output circuit 133.

[0043] The first output circuit 131 is connected to the gating output of the first gating circuit 121, and the output I / OA of the first output circuit 131 is configured to output the corresponding level gated by the first gating circuit 121. The first output circuit 131 is provided with a first load capacitor Cload A.

[0044] The second output circuit 132 is connected to the gating output of the second gating circuit 122, and the output I / OB of the second output circuit 132 is configured to output the corresponding level gated by the second gating circuit 122. The second output circuit 132 is provided with a second load capacitor Cload B.

[0045] The nth output circuit 133 is connected to the gating output of the nth gating circuit 123, and the output I / ON of the nth output circuit 131 is configured to output the corresponding level gated by the nth gating circuit 123. The nth output circuit 133 is provided with an nth load capacitor Cload N.

[0046] The gating input of the first gating circuit 121, the second gating circuit 122, …, and the nth gating circuit 123 are respectively connected to the output of each level providing circuit in the level amplitude providing circuit 110.

[0047] Taking the first gating circuit 121 as an example, the gating input end of the first gating circuit 121 is connected with the output end of the first level providing circuit 111, the output end of the second level providing circuit 112, the output end of the third level providing circuit 113 and the output end of the fourth level providing circuit 114; the gating output end of the first gating circuit 121 is connected with the first output circuit 131.

[0048] The first gating circuit 121 can also receive the first transmission data A1A0, and switch the gating of the output end of the corresponding level providing circuit according to the value of the first transmission data A1A0.

[0049] The first transmission data A1A0 includes two data bits A1 and A0, and can transmit 2bit data information at the same time. When the first transmission data A1A0 = 11, the first gating circuit 121 gates the first level providing circuit 111, and the output end I / OA of the first output circuit 131 outputs the first level VDDH; when the first transmission data A1A0 = 10, the first gating circuit 121 gates the second level providing circuit 112, and the output end I / OA of the first output circuit 131 outputs the second level; when the first transmission data A1A0 = 01, the first gating circuit 121 gates the third level providing circuit 113, and the output end I / OA of the first output circuit 131 outputs the third level; when the first transmission data A1A0 = 00, the first gating circuit 121 gates the fourth level providing circuit 114, and the output end I / OA of the first output circuit 131 outputs the fourth level VSSH.

[0050] The gating principles of the second gating circuit 122 to the nth gating circuit 123 are the same as those of the first gating circuit 121, and will not be repeated here.

[0051] The embodiment can realize the transmission of signals of four levels of amplitudes through the gating circuit, can improve the data transmission rate of the four-level pulse amplitude modulation IO circuit under the same signal frequency, improve the efficiency and reduce the power consumption.

[0052] For the second level providing circuit and the third level providing circuit in Figure 1 and Figure 2 , the circuit principle shown in Figure 3 can be used to realize them.

[0053] Referring to Figure 3 , the circuit principle diagram of the second level providing circuit or the third level providing circuit is shown, and the circuit principle diagram of the second level providing circuit or the third level providing circuit is shown in Figure 3As can be seen, the second level providing circuit or the third level providing circuit comprises a PMOS transistor MP0 and an NMOS transistor MN0, a source of the PMOS transistor MP0 is used to receive the first level VDDH, a drain of the PMOS transistor MP0 is connected with a source of the NMOS transistor MN0 as a level output end, the level output end is used to output the second level generated by the second level providing circuit or the third level generated by the third level providing circuit.

[0054] A drain of the NMOS transistor MN0 is used to receive a fourth level VSSH, the drain of the NMOS transistor MN0 is connected with the level output end with a multiplexing capacitor C therebetween. A gate of the PMOS transistor MP0 is connected with a first comparator, a non-inverting input end of the first comparator is connected with the level output end, and an inverting input end of the first comparator is connected with a first reference voltage VIL. A gate of the NMOS transistor MN0 is connected with a second comparator, a non-inverting input end of the second comparator is connected with the level output end, and an inverting input end of the second comparator is connected with a second reference voltage VIH, wherein the second reference voltage VIH is greater than the first reference voltage VIL.

[0055] By Figure 3 the circuit shown, the second level output by the second level providing circuit and the third level output by the third level providing circuit can be stabilized between the first reference voltage VIL and the second reference voltage VIH. That is, when Figure 3 the voltage output by the level output end is greater than the second reference voltage VIH, the first comparator and the second comparator both output high level, so that the PMOS transistor MP0 is turned off and the NMOS transistor MN0 is turned on, so that the multiplexing capacitor C is discharged through the NMOS transistor MN0 until the voltage output by the level output end is less than the second reference voltage VIH; that is, when Figure 3 the voltage output by the level output end is less than the first reference voltage VIL, the first comparator and the second comparator both output low level, so that the PMOS transistor MP0 is turned on and the NMOS transistor MN0 is turned off, so that the multiplexing capacitor C is charged through the PMOS transistor MP0 until the voltage output by the level output end is greater than the first reference voltage VIL; that is, when Figure 3 the voltage output by the level output end is between the first reference voltage VIL and the second reference voltage VIH, so that the PMOS transistor MP0 and the NMOS transistor MN0 are both turned off, so that the charge in the multiplexing capacitor C is stabilized, thereby maintaining the voltage output by the level output end stable.

[0056] It should be noted that the second reference voltage VIH and the first reference voltage VIL are pre-set according to the first level VDDH, the proportional relationship between the voltage output by the level output end and the first level VDDH, and an error range.

[0057] When using Figure 3The circuit shown as the second level providing circuit 112 to output the second level, the second reference voltage VIH and the first reference voltage VIL need to be set in advance according to the first level VDDH, the first proportional relationship between the second level and the first level VDDH, and the error range.

[0058] Exemplarily, when the first proportional relationship is determined to be two-thirds and the error range is ±1 / 20VDDH, the first reference voltage VIL is set in advance to be 2 / 3VDDH-1 / 20VDDH, and the second reference voltage VIH is set in advance to be 2 / 3VDDH+1 / 20VDDH, and then the second level is obtained through the circuit shown in the figure. Figure 3 The circuit shown as the second level providing circuit 112 to output the second level, the second reference voltage VIH and the first reference voltage VIL need to be set in advance according to the first level VDDH, the first proportional relationship between the second level and the first level VDDH, and the error range.

[0059] Similarly, when the circuit shown in the figure is used as the third level providing circuit 113 to output the third level, the second reference voltage VIH and the first reference voltage VIL need to be set in advance according to the first level VDDH, the second proportional relationship between the third level and the first level VDDH, and the error range. Figure 3 The circuit shown as the second level providing circuit 112 to output the second level, the second reference voltage VIH and the first reference voltage VIL need to be set in advance according to the first level VDDH, the first proportional relationship between the second level and the first level VDDH, and the error range.

[0060] Exemplarily, when the second proportional relationship is determined to be one-third and the error range is ±1 / 20VDDH, the first reference voltage VIL is set in advance to be 1 / 3VDDH-1 / 20VDDH, and the second reference voltage VIH is set in advance to be 1 / 3VDDH+1 / 20VDDH, and then the third level is obtained through the circuit shown in the figure. Figure 4 The circuit shown as the second level providing circuit 112 to output the second level, the second reference voltage VIH and the first reference voltage VIL need to be set in advance according to the first level VDDH, the first proportional relationship between the second level and the first level VDDH, and the error range.

[0061] Alternatively, the second reference voltage VIH and the first reference voltage VIL can be obtained through the voltage dividing circuit shown in the figure. Referring to the voltage dividing circuit shown in the figure, Figure 4 The circuit shown as the second level providing circuit 112 to output the second level, the second reference voltage VIH and the first reference voltage VIL need to be set in advance according to the first level VDDH, the first proportional relationship between the second level and the first level VDDH, and the error range. Figure 5The voltage divider circuit comprises first voltage dividing resistor R1, second voltage dividing resistor R2, third voltage dividing resistor R3, fourth voltage dividing resistor R4 and fifth voltage dividing resistor R5 connected in series from ground terminal to power terminal. The voltage of the power terminal is first level VDDH. The node connected with the first voltage dividing resistor R1 and the second voltage dividing resistor R2 is used to provide the first reference voltage VIL1 required by the third level providing circuit 113. The node connected with the second voltage dividing resistor R2 and the third voltage dividing resistor R3 is used to provide the second reference voltage VIH1 required by the third level providing circuit 113. The node connected with the third voltage dividing resistor R3 and the fourth voltage dividing resistor R4 is used to provide the first reference voltage VIL2 required by the second level providing circuit 112. The node connected with the fourth voltage dividing resistor R4 and the fifth voltage dividing resistor R5 is used to provide the second reference voltage VIH2 required by the second level providing circuit 112.

[0062] The resistance ratio of the first voltage dividing resistor R1, the second voltage dividing resistor R2, the third voltage dividing resistor R3, the fourth voltage dividing resistor R4 and the fifth voltage dividing resistor R5 is:

[0063] R1:R2:R3:R4:R5=VIL1:(VIH1-VIL1):(VIL2-VIH1):(VIH2-VIL1):(VDDH-VIH2).

[0064] Figure 1 The signal switching schematic diagram of the four-level pulse amplitude modulation IO circuit is illustrated by taking the first gating circuit in Figure 5 as an example.

[0065] As can be seen from Figure 3 , the signal switching of the four-level pulse amplitude modulation IO circuit has 16 possibilities.

[0066] The process of generating the third level can include the following P1, P2 and P3 states: state P1 is that the first transmission data A1A0 is switched from 11 to 01, state P2 is that the first transmission data A1A0 is switched from 10 to 01, and state P3 is that the first transmission data A1A0 is switched from 00 to 01. Among the above P1, P2 and P3 states, state P1 and state P2 are Figure 3 the states in which the charge of the multiplexing capacitor C is obtained, and state P3 is the state in which the multiplexing capacitor C loses charge, so that the statistical expectation of the process of generating the third level is determined to be charge excess from the perspective of probability statistics, and the NMOS transistor MN0 in the circuit Figure 3 is required to release the excess charge in the multiplexing capacitor C.

[0067] The process of generating the second level can include the following three states: P4, P5, and P6. State P4 is when the first transmitted data A1A0 changes from 11 to 10; state P5 is when the first transmitted data A1A0 changes from 00 to 10; and state P6 is when the first transmitted data A1A0 changes from 01 to 10. Among these three states, states P5 and P6 are... Figure 3 The diagram shows the states where the reused capacitor C loses charge, and state P4 shows the states where the reused capacitor C gains charge. Therefore, from a probabilistic statistical perspective, the expected process for generating the second level is that the charge is insufficient, requiring... Figure 1 In the circuit shown, the PMOS transistor MP0 replenishes the insufficient charge of the multiplexed capacitor C.

[0068] by Figures 2 to 4 Taking the first gating circuit in the example, combined with Figure 3 It can be seen that during the process of the output level amplitude of the first output circuit 131 I / OA switching from high to low, the first load capacitor Cload A needs to release charge, and during the process of the output level amplitude of the first output circuit 131 I / OA switching from low to high, the first load capacitor Cload A needs to replenish charge.

[0069] When the first transmitted data A1A0 switches from 11 to 01, or from 10 to 01, the output level of the first output circuit 131 at terminal I / OA switches from high to low to the third level. During this process, the charge released by the first load capacitor Cload A is stored in... Figure 3 The multiplexed capacitor C shown is used.

[0070] When the first transmitted data A1A0 switches from 00 to 01, the output level of the first output circuit 131 at terminal I / OA switches from low to high to the third level. During this process, the voltage level of the output terminal I / OA switches from low to high. Figure 3 The multiplexed capacitor C shown needs to release charge to provide to the first load capacitor Cload A.

[0071] When the first transmitted data A1A0 switches from 11 to 10, the output level of the first output circuit 131 at terminal I / OA switches from high to low to the second level. During this process, the charge released by the first load capacitor Cload A is stored in... Figure 3 The multiplexed capacitor C shown is used.

[0072] When the first transmitted data A1A0 switches from 00 to 10, or from 01 to 10, the output level of the first output circuit 131 at terminal I / OA switches from low to high to the second level. During this process, the voltage level of the output terminal I / OA of the first output circuit 131 changes from low to high. ​The multiplexing capacitor C needs to release the charge to provide the first load capacitor Cload A.

[0073] Therefore, it can be seen that the charging and discharging of the first load capacitor Cload A and the charging and discharging of the multiplexing capacitor C can only achieve charge multiplexing, so that in the process of switching the amplitude of the level output by the output end of the output circuit from low to high, the part of the charge directly provided by the power supply can be reduced, thereby reducing power consumption.

[0074] Obviously, the above embodiments are only examples for the purpose of clarity, and are not limiting on the embodiments. Based on the above description, other different forms of changes or variations can also be made by those of ordinary skill in the art. Here, it is not necessary and impossible to exhaust all the embodiments. The obvious changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. A four-level pulse amplitude modulation (IO) circuit, characterized in that, The four-level pulse amplitude modulation IO circuit comprises: a level amplitude providing circuit, which comprises a first level providing circuit for providing a first level, a second level providing circuit for providing a second level, a third level providing circuit for providing a third level, and a fourth level providing circuit for providing a fourth level; the level amplitudes of the first level, the second level, the third level to the fourth level decrease in turn; a gating circuit, which is used for gating the output end of the corresponding level providing circuit according to the transmission data; an output circuit, which is used for outputting the corresponding level outputted by the level providing circuit gated by the gating circuit; the output circuit is provided with a load capacitor; wherein the second level providing circuit or / and the third level providing circuit comprises a PMOS tube and an NMOS tube; the source of the PMOS tube is used for receiving the first level, the drain of the PMOS tube is connected with the source of the NMOS tube as a level output end, the drain of the NMOS tube is used for receiving the fourth level, and the drain of the NMOS tube is connected with the level output end through a multiplexing capacitor; the gate of the PMOS tube is connected with a first comparator, the non-inverting input end of the first comparator is connected with the level output end, and the inverting input end of the first comparator is connected with a first reference voltage; the gate of the NMOS tube is connected with a second comparator, the non-inverting input end of the second comparator is connected with the level output end, and the inverting input end of the second comparator is connected with a second reference voltage; wherein the second reference voltage is greater than the first reference voltage.

2. The four-level pulse amplitude modulation IO circuit of claim 1, wherein, The second level providing circuit generates the second level having a first proportional relationship with the first level based on the first level and the fourth level.

3. The four-level pulse amplitude modulation IO circuit of claim 1, wherein, The third level providing circuit generates the third level having a second proportional relationship with the first level based on the first level and the fourth level.

4. The four-level pulse amplitude modulation IO circuit of claim 1, wherein, The second reference voltage and the first reference voltage are preset according to the proportional relationship between the first level and the voltage outputted by the level output end, and an error range.

5. The four-level pulse amplitude modulation IO circuit of claim 1, wherein, It also comprises a first voltage dividing resistor R1, a second voltage dividing resistor R2, a third voltage dividing resistor R3, a fourth voltage dividing resistor R4 and a fifth voltage dividing resistor R5 connected in series from a ground end to a power supply end; the voltage of the power supply end is the first level VDDH, the connected node of the first voltage dividing resistor R1 and the second voltage dividing resistor R2 is used for providing the first reference voltage VIL1 required by the third level providing circuit; the connected node of the second voltage dividing resistor R2 and the third voltage dividing resistor R3 is used for providing the second reference voltage VIH1 required by the third level providing circuit; the connected node of the third voltage dividing resistor R3 and the fourth voltage dividing resistor R4 is used for providing the first reference voltage VIL2 required by the second level providing circuit; and the connected node of the fourth voltage dividing resistor R4 and the fifth voltage dividing resistor R5 is used for providing the second reference voltage VIH2 required by the second level providing circuit.

6. The four-level pulse amplitude modulation IO circuit of claim 5, wherein, The resistance ratio of the first voltage division resistor R1, the second voltage division resistor R2, the third voltage division resistor R3, the fourth voltage division resistor R4 and the fifth voltage division resistor R5 is: R1:R2:R3:R4:R5=VIL1:(VIH1-VIL1):(VIL2-VIH1):(VIH2-VIL1):(VDDH-VIH2).

Images