Multiple patterning with selective mandrel formation

Abstract

A method of forming a device includes forming a patterned resist layer over a substrate using an extreme ultraviolet (EUV) lithography process. The method includes forming a mandrel in a plasma processing chamber by selectively depositing a mandrel material over the patterned resist layer, the mandrel comprising the patterned resist layer and the mandrel material.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to U.S. Provisional Patent Application No. 62 / 960,958, filed on January 14, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention generally relates to semiconductor manufacturing, and in certain embodiments to multiple patterning with selective mandrel formation. Background Technology

[0004] Semiconductor devices, such as integrated circuits (ICs), are typically fabricated by sequentially depositing and patterning dielectric, conductive, and semiconductor layers over a semiconductor substrate, using photolithography and etching to form the structures of circuit components and interconnects (e.g., transistors, resistors, capacitors, metal wires, contacts, and vias). At each successive technology node, feature sizes shrink to approximately twice the component density. A straightforward approach to printing higher resolution patterns is to reduce the wavelength of the light source. The 248nm deep ultraviolet (DUV) radiation source (KrF laser) used to expose critical patterns at the 250nm and 130nm nodes was replaced by a 193nm ArF laser starting at the 90nm node. Using 193nm photolithography with resolution enhancement techniques (such as immersion lithography), features as low as 35nm can be printed. 193nm optics have been further extended to 14nm and even 10nm nodes using multiple patterning techniques, but this comes at the cost and process complexity associated with additional masks. In sub-10nm node solutions, DUV can be replaced by even shorter wavelengths like 13.5nm extreme ultraviolet (EUV). While EUV promises high resolution with fewer masks, it requires integrating all components of the lithography system (radiation source, scanner, mask, and resist) to overcome engineering hurdles for each component. A major problem is that resists exposed by EUV radiation are sensitive to stochastic effects, leading to random failures when printing extremely small areas and fine lines. These effects are amplified at smaller features, such as in sub-10nm node designs. Further innovation is needed in this field to successfully deploy EUV lithography in high-volume semiconductor IC manufacturing. Summary of the Invention

[0005] According to an embodiment of the present invention, a method of forming a device includes forming a patterned resist layer over a substrate using an extreme ultraviolet (EUV) lithography process. The method includes forming a mandrel in a plasma processing chamber by selectively depositing a mandrel material over the patterned resist layer, the mandrel comprising the patterned resist layer and the mandrel material.

[0006] According to an embodiment of the present invention, a self-aligned multiple patterning process includes placing a layer to be patterned over a substrate. The method includes: forming a patterned resist layer over the layer to be patterned using extreme ultraviolet (EUV) lithography; and selectively depositing a mandrel material over the patterned resist layer in a plasma processing chamber to form a mandrel. The method includes: forming spacers along the mandrel in the plasma processing chamber; and removing the mandrel after forming the spacers in the plasma processing chamber, wherein depositing the mandrel material, forming the spacers, and removing the mandrel are performed in a single process step. The method includes using these spacers as a hard mask to pattern the layer to be patterned to form features.

[0007] According to an embodiment of the present invention, a self-aligned multiple patterning process includes placing a layer to be patterned over a substrate. The method includes: forming a patterned resist layer over the layer to be patterned using a photolithography process; performing a cyclic process in a plasma processing chamber to form a mandrel including the patterned resist layer, the cyclic process including depositing a mandrel material layer over the patterned resist layer and the layer to be patterned; and performing a trimming process to selectively remove portions of the mandrel material layer that contact the layer to be patterned. The method includes: forming spacers along the mandrel in the plasma processing chamber; and removing the mandrel in the plasma processing chamber after forming the spacers. The method includes using the spacers as an etching mask to pattern the layer to be patterned to form features. Attached Figure Description

[0008] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0009] Figures 1A to 1C A cross-sectional view of a semiconductor device according to a conventional process flow is shown;

[0010] Figure 2A and Figure 2B A semiconductor device is shown during manufacturing after a patterned resist layer 203 has been formed over a patterned layer 202, according to an embodiment of the present invention, wherein... Figure 2A Showing cross-sectional views and Figure 2B A top view is shown;

[0011] Figure 3A and Figure 3B A semiconductor device is shown during fabrication following the deposition of a mandrel material layer 205 onto a patterned resist layer 203, according to an embodiment of the present invention. Figure 3A Showing cross-sectional views and Figure 3B A top view is shown;

[0012] Figure 4A and Figure 4B A semiconductor device is illustrated during manufacturing after the trimming of the mandrel material layer, according to an embodiment of the present invention, wherein, Figure 4A Showing cross-sectional views and Figure 4B A top view is shown;

[0013] Figure 5A and Figure 5B A semiconductor device is shown during manufacturing after the desired CD (i.e., height and width) of the mandrel has been achieved, according to an embodiment of the invention. Figure 5A Showing cross-sectional views and Figure 5B A top view is shown;

[0014] Figure 6A and Figure 6B This illustrates a semiconductor device during manufacturing following the deposition of spacer material 211 over a mandrel 207, according to an embodiment of the present invention. Figure 6A Showing cross-sectional views and Figure 6B A top view is shown;

[0015] Figure 7A and Figure 7B A semiconductor device is illustrated during manufacturing following a multiple patterning process according to an embodiment of the present invention, wherein, Figure 7A Showing cross-sectional views and Figure 7B A top view is shown;

[0016] Figure 8 A flowchart illustrating a method for forming a semiconductor device according to an embodiment of the present invention is shown;

[0017] Figure 9 A flowchart illustrating a method for forming a semiconductor device according to another embodiment of the present invention is shown; and

[0018] Figure 10 A flowchart illustrating a method for forming a semiconductor device according to another embodiment of the present invention is shown.

[0019] The accompanying drawings are not necessarily drawn to scale. The drawings are merely illustrative and not intended to depict specific parameters of the invention. The drawings are intended to depict only specific embodiments of the invention and should therefore not be considered as limiting the scope. In the drawings, the same numbers denote the same elements. Detailed Implementation

[0020] The structure, methods, and uses of various embodiments of the electronic device are discussed in detail below. However, it should be noted that the various embodiments described in detail herein are applicable to a wide range of disciplines. The specific embodiments described herein are merely illustrative of specific ways of making and using the various embodiments and should not be interpreted in a limited manner.

[0021] In a self-aligned multiple patterning process, a mandrel is used to form sidewall spacers aligned with the mandrel. These sidewall spacers are then used as etching masks to pattern the underlayer. This allows for the formation of features in the underlayer that are thinner than the critical dimension of the mandrel, which might be limited by the lithographic limits of that particular system. However, as further explained, the height of the mandrel determines the quality of the sidewall spacers. If the mandrel height is too small, reliable sidewall spacers cannot be formed.

[0022] The embodiments of the invention described further below use a selective deposition process to increase the height of the mandrel. (The following text will use...) Figures 2A to 7B as well as Figures 8 to 10 The flowcharts are used to discuss embodiments of the present invention.

[0023] Figures 1A to 1C A cross-sectional view of a semiconductor device according to a conventional process flow is shown.

[0024] refer to Figure 1A In this processing stage, a patterned EUV photoresist layer 106 is formed over a substrate 101, the substrate having a stack of layers including an underlayer 102, a core material layer 103, an optical planarization layer (OPL) 104, and an anti-reflective coating (ARC) mask layer 105.

[0025] The shorter 13.5 nm wavelength used in EUV lithography provides high-resolution single-patterning capabilities, for example, printing a dense array of 13 nm resist lines and spacing (26 nm pitch) using only a single mask. In contrast, two to four masks can be used to achieve the same resolution as 193 nm DUV lithography using multiple patterning techniques. It is estimated that fabricating a typical IC design at the 7 nm node would be an unacceptably lengthy and expensive process, requiring more than 80 DUV 193 nm masks, while EUV could potentially reduce the mask count to a more manageable range of approximately 60 masks. However, as is known to those skilled in the art, EUV technology presents numerous engineering challenges due to the high energy of photons at the short 13.5 nm wavelength. This disclosure describes embodiments of methods for mitigating some of these problems.

[0026] One problem with EUV photons having 14.3 times the energy (92 eV vs. 6.4 eV) is that the number of photons available to define the edges of the exposure area is correspondingly reduced under fixed exposure conditions. For example, for 15 mJ / cm 2 The exposure of 1nm 2 On average, EUV photoresist is exposed to only 10 photons per area, while 193nm DUV resist is exposed to 143 photons. As explained further below, this reduces the thickness of the resulting EUV photoresist layer 106 and other issues such as increased shot noise.

[0027] Smaller doses can result in greater noise, leading to poorer resist pattern quality. This is because some areas may randomly receive more photons than average, while others may receive fewer. Furthermore, the same area on each die of a wafer may receive randomly different exposures as the scanner moves from one die to another. This random variation in photon count (also known as shot noise) follows a Poisson process, resulting in a percentage variation in exposure variability (the ratio of the root mean square value to the mean value (σ / μ)) of √(14.3) or approximately 3.8 times greater for EUV lithography relative to DUV at the same exposure level. The effect of exposure variability on the exposure pattern worsens as the feature size decreases. The randomness of where photons interact with the resist to induce chemical reactions translates into corresponding blurring at the edges of the exposure lines. This loss of resolution is more severe for EUV (relative to DUV) because the average distance between the locations of photon-resist interactions increases with decreasing photon density.

[0028] Another problem associated with high photon energies is that photon absorption events (within the resist or the layer beneath it) are accompanied by the generation of high-energy photoelectrons, which rapidly cascade into secondary emissions of lower-energy electrons. As these electrons scatter along random trajectories (often referred to as random walks) in a random process, some electrons may induce chemical reactions in the resist quite far from where the original photon was absorbed. As a result, random secondary exposures may exist above the region defined by the original pattern. This secondary exposure is yet another random process that produces random patterns superimposed on an image generated solely through photon-resist interactions.

[0029] While forming a thick EUV photoresist layer 106 is advantageous, trade-offs exist due to the relatively thin EUV resist film, as explained herein. For example, increasing the resist thickness can lead to undesirable vertical non-uniform exposure. During exposure to DUV radiation, the radiation intensity gradually decreases with depth of penetration as photons are absorbed by the resist material. Once the resist is developed, the gradually decreasing exposure dose towards the bottom can result in an undesirable sloping resist profile. Furthermore, a thicker resist means fewer photons reach the bottom region, thus leading to undesirable amplified shot noise. The degree of vertical non-uniformity also depends on the photon absorbance of the resist material; higher absorbance leads to increased non-uniformity. However, due to the relatively small number of EUV photons, the absorbance of the EUV resist can remain sufficiently high to provide adequate sensitivity at a reasonable exposure dose. Excessive exposure dose can cause various problems such as overheating and outgassing. Thickness can also be limited by resist collapse and resist stripping considerations at high aspect ratios.

[0030] The use of a thin EUV photoresist layer 106 limits the thickness of the mandrel that can be formed. This is because some of the EUV photoresist layer 106 will be etched during subsequent etching processes to pattern the mandrel.

[0031] As follows Figure 1B The mandrel 11 is shown to be formed after a series of anisotropic etching processes.

[0032] Next reference Figure 1C Spacer material 12 is formed along and above the mandrel 11, followed by an etching process to form sidewall spacers. The mandrel is removed and can be used to pattern the underlayer 102. The sidewall thickness defines the critical dimensions of the underlayer features formed during subsequent patterning steps in the multi-patterning process. However, the mandrel must be high enough to allow the spacer material 12 to form sidewalls of uniform thickness, such as... Figure 1C The hypothetical scenario is illustrated in the text. Otherwise, the thickness of the spacer material 12 varies in the vertical direction, and the spacer material will be transferred to the pattern to be formed in the underlayer 102.

[0033] However, in practice, the short wavelength of extreme ultraviolet radiation used to form the extremely small scaling features limits the height of the mandrel 11. Therefore, it is impossible to form sidewall spacers with a uniform thickness (thickness not varying along the sidewalls of the mandrel 11). Furthermore, etching selectivity during mandrel removal can also become a problem.

[0034] Furthermore, the mandrel deposition and spacer deposition are separated by a series of process steps, including top-layer deposition for photolithography, photolithography, and subsequent etching. Therefore, these steps must be fabricated in different tools, or at least in different equipment rooms.

[0035] Embodiments of the present invention facilitate the reshaping of the incoming resist after EUV by using a selective deposition process with an improved mandrel aspect ratio. Embodiments further facilitate the formation of the mandrel directly from the photoresist instead of... Figures 1A to 1B These improvements are achieved using conventional processes that involve etching through a series of layers.

[0036] Figures 2A to 7B Semiconductor devices are shown during various manufacturing stages according to embodiments of the present invention, wherein, Figures 2A to 7A Showing cross-sectional views and Figures 2B to 7B A top-down view is shown.

[0037] Figure 2A and Figure 2B A semiconductor device is shown during manufacturing after a patterned resist layer 203 has been formed over a patterned layer 202, according to an embodiment of the present invention, wherein... Figure 2A Showing cross-sectional views and Figure 2B A top-down view is shown.

[0038] refer to Figure 2A In this processing stage, the semiconductor device includes a semiconductor substrate 201, wherein a patterned layer 202 has been deposited on the semiconductor substrate 201, followed by a patterned resist layer 203 formed on the patterned layer 202. Since the mandrel is formed directly through selective deposition rather than etching, the use of additional layers, such as etch stop layers, can be avoided. Figure 1A What is shown.

[0039] In embodiments of the invention, forming a patterned resist layer 203 is a preliminary step in forming the mandrel, as the patterned photoresist provides the base structure on which the mandrel grows and takes shape. Details regarding this mandrel formation process, relevant to embodiments of the invention, will be described herein.

[0040] In embodiments of the present invention, the semiconductor substrate 201 may include silicon, silicon germanium, silicon carbide, and compound semiconductors such as gallium nitride, gallium arsenide, indium arsenide, indium phosphide, etc. The semiconductor substrate 201 may include a semiconductor wafer, which may include a semiconductor epitaxial layer comprising a heteroepitaxial layer. For example, in one or more embodiments, one or more heteroepitaxial layers comprising a compound semiconductor may be formed over the semiconductor substrate. In various embodiments, a portion or all of the semiconductor substrate 201 may be amorphous, polycrystalline, or monocrystalline. In various embodiments, the semiconductor substrate 201 may be doped, undoped, or contain both doped and undoped regions. In some embodiments, the semiconductor substrate 201 may already include a dielectric stack of a previously patterned layer and a layer 202 to be patterned.

[0041] The layer 202 to be patterned may be a stack of films and may include one or more hard mask layers. In various embodiments, the layer 202 to be patterned may include films of dielectric and / or conductive materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, titanium nitride, tantalum nitride, alloys thereof, and combinations thereof. In some embodiments, the layer 202 to be patterned may be a sacrificial layer that is removed after being used as a hard mask in a subsequent etching step. In one embodiment, the layer 202 to be patterned may also include, for example, an intermetallic dielectric (IMD) comprising a low-k dielectric material, and the semiconductor substrate 201 may include a plurality of interconnect layers comprising dielectric films having embedded conductive interconnect elements formed over a single-crystal semiconductor or semiconductor-on-insulator (SOI) wafer in which various active devices can be fabricated.

[0042] In embodiments of the present invention, any technique suitable for the material to be deposited can be used to deposit the patterned layer 202. These techniques may include, but are not limited to, atomic layer deposition (ALD), chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmospheric CVD (SACVD), high-density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UH-VCVD), finite reaction processing CVD (LRPCVD), metal-organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser-assisted deposition, thermal oxidation, thermal nitriding, spin coating, physical vapor deposition (PVD), chemical oxidation, molecular beam epitaxy (MBE), electroplating, and / or evaporation.

[0043] In various embodiments, EUV lithography or electron beam lithography can be used to form the patterned resist layer 203.

[0044] According to one or more embodiments of the present invention, the patterned resist layer 203 can be achieved by depositing a thick layer of EUV-sensitive photoresist film onto a certain layer (e.g., Figure 2A The patterned layer 202 is formed on the substrate. In one embodiment, the EUV-sensitive photoresist film may be an organic photoresist film or a metal oxide photoresist film that is sensitive to EUV radiation with a wavelength range of 10 nm to about 14 nm, typically 13.5 nm.

[0045] In one or more embodiments, an EUV-sensitive photoresist film may be deposited or coated over the layer 202 to be patterned. This thick layer of EUV-sensitive photoresist film may be deposited to a desired height / thickness H203. In various embodiments, the height H203 of the EUV-sensitive photoresist film may be from about 10 nm to about 30 nm, and in one embodiment, it is about 25 nm. As previously discussed, the height H203 of the EUV-sensitive photoresist film is limited by the nature of the radiation used for development and its interaction with the EUV-sensitive photoresist film.

[0046] Then, the thick EUV-sensitive photoresist film is patterned using standard EUV lithography patterning techniques to form a structure including, for example, Figure 2A The patterned resist layer 203 exhibits multiple features. For example... Figure 2A As shown, the multiple features patterned in the EUV-sensitive photoresist film can have the desired critical size or width W203 of that layer. In various embodiments, the width W203 can be from about 5 nm to about 30 nm, and in one embodiment it is about 20 nm. In another embodiment, the width W203 can be from about 5 nm to about 15 nm, and in one embodiment it is about 10 nm. For example, the width W203 can be a critical size of the EUV-sensitive photoresist film that the photolithography system can achieve after development.

[0047] In various embodiments, the ratio of height H203 to width W203 is approximately 1:1 to approximately 1:10. There are many reasons why the sidewall spacers may not deposit uniformly when the height decreases or the aspect ratio increases. Many of these reasons relate to the etching process, such as selectivity, pattern collapse, and pattern wobbling.

[0048] These multiple features of the patterned resist layer 203 can provide an initial or structural basis for the subsequent growth / formation of the mandrel. Unlike conventional processes, in various embodiments, the mandrel formation process includes a photolithography process followed by a selective deposition process or a cyclic deposition / trimming process, as will be described further.

[0049] In the above example, the patterned resist layer 203 is described as being formed in a photolithography step of a multiple patterning technique. In other examples, the patterned resist layer 203 may be formed as a subsequent intermediate feature, for example, as a result of pitch doubling. However, in various embodiments, the patterned resist layer 203 is a feature with a critical dimension having a minimum feature size that can only be obtained by photolithography processes using extreme ultraviolet (EUV) lithography or electron beam lithography (EBL).

[0050] Figure 3A and Figure 3BA semiconductor device is shown during fabrication following the deposition of a mandrel material layer 205 onto a patterned resist layer 203, according to an embodiment of the present invention. Figure 3A Showing cross-sectional views and Figure 3B A top-down view is shown.

[0051] refer to Figure 3A In one embodiment, mandrel material 205 is deposited over a patterned resist layer 203. In one embodiment, the deposition process may involve thick-layer deposition of mandrel material 205 across a semiconductor substrate 201.

[0052] In various embodiments, the mandrel material 205 may include a hard mask material, a soft mask material, or a photoresist material. In one embodiment, the mandrel material 205 comprises porous silicon or any other type of sacrificial material known in the art. The mandrel material 205 may also comprise a plasma-polymerized organic film or a dielectric film.

[0053] In various embodiments, plasma deposition processes can be used to perform thick-layer deposition. In one embodiment, atomic layer deposition processes can be used to deposit the mandrel material 205.

[0054] Due to the thick deposition process, for a fully conformal process, the width W206 of the multiple features increases the thickness of the mandrel material 205 layer formed on the sidewalls of the patterned resist layer 203 by approximately twice. The height H206 of the multiple features increases the thickness of the mandrel material 205 layer above the patterned resist layer 203.

[0055] In one or more embodiments, a partially selective deposition process or a highly selective deposition process may be used to deposit the mandrel material 205, wherein more mandrel material 205 is deposited on the patterned resist layer 203 than on the exposed patterned layer 202. For example, in one embodiment, the mandrel material 205 has greater selectivity for deposition on the patterned resist layer 203, and therefore has a higher affinity for depositing more mandrel material 205 along the top surface of the patterned resist layer 203 compared to the top surface of the patterned layer 202.

[0056] Figure 4A and Figure 4B A semiconductor device is illustrated during manufacturing after the trimming of the mandrel material layer, according to an embodiment of the present invention, wherein, Figure 4A Showing cross-sectional views and Figure 4B A top-down view is shown.

[0057] In embodiments of the invention, the selective deposition process may optionally include a trimming stage. The trimming stage is optional and may be used when depositing the mandrel material 205 using a partially selective deposition process or even a conformal deposition process. Therefore, some embodiments of the invention may include a deposition stage followed by a trimming stage. The deposition and trimming stages may be cycled to achieve the desired height and critical dimension (CD).

[0058] After the trimming stage, the mandrel material 205 is removed, exposing the sidewalls of the patterned resist layer 203 and the top surface of the layer 202 to be patterned. Therefore, advantageously, the critical dimension can be adjusted to, or be smaller than / greater than, the critical dimension of the mandrel being formed. For example, in one illustration, the critical dimension of the mandrel being formed is not increased and the process maintains the critical dimension of the previous step. However, in some alternative embodiments, some of the mandrel material 205 (e.g., a thin layer of a fraction of a nanometer) on the sidewalls of the patterned resist layer 203 can be retained after the trimming stage. By removing a portion of the sidewalls, embodiments of this process can help smooth the sidewalls and reduce line edge roughness and line width roughness.

[0059] When partially selective deposition is used to form the mandrel material 205, the thickness of the mandrel material 205 on the sidewalls of the patterned resist layer 203 and above the layer 202 to be patterned is thinner than the thickness of the mandrel material 205 above the patterned resist layer 203. Therefore, in one embodiment, a timed isotropic etching process can be used to remove the mandrel material 205 from above the sidewalls of the patterned resist layer 203 and above the layer 202 to be patterned.

[0060] Alternatively, the trimming stage may include a combination of anisotropic and isotropic etching. For example, the trimming stage may optionally begin with an isotropic etching stage before switching to anisotropic etching.

[0061] Alternatively, in another embodiment, the trimming stage may consist solely of an anisotropic etching process to remove the mandrel material 205. In various embodiments of the invention, the trimming stage may include anisotropic etching processes, such as reactive ion etching (RIE), or any other removal process known in the art.

[0062] In various embodiments of the invention, a trimming phase may be performed after an iteration of the deposition phase. In embodiments of the invention, the deposition phase, followed by the trimming phase, may occur cyclically. For example, a cycle may include a single deposition phase up to a specified height H206, followed by a trimming phase up to a specified width W208. Due to optional over-etching during the trimming phase, the height of the mandrel being formed may be reduced to H208. According to embodiments, when one cycle has been completed, another cycle may begin until the desired final height and CD of the mandrel being formed have been reached.

[0063] According to embodiments of the invention, the trimming stage may also involve smoothing elements, such that each iterative step involves reshaping the mandrel to eliminate roughness along the surface and edges. In embodiments of the invention, during the mandrel formation process on the patterned resist layer 203, the critical dimension (CD), line edge roughness (LER), and line width roughness (LWR) of the progressively formed mandrel can be controlled simultaneously. As previously mentioned, this can occur within a plasma processing chamber. In various embodiments of the invention, the CD can be additionally trimmed to achieve the correct dimensions (e.g., to compensate for pitch drift). Advantageously, this trimming can be performed while increasing the mandrel aspect ratio. Therefore, the process enables simultaneous CD control and roughness improvement of the mandrel.

[0064] Figure 5A and Figure 5B A semiconductor device is shown during manufacturing after the desired CD (i.e., height and width) of the mandrel has been achieved, according to an embodiment of the invention. Figure 5A Showing cross-sectional views and Figure 5B A top-down view is shown.

[0065] like Figure 5A As shown, mandrel 207 is formed after multiple cycles of repeated deposition and finishing stages. Figure 5A In the diagram, each layer from the iterative cycle (i.e., the deposition and trimming stages) is depicted by a black line on the segmented mandrel 207.

[0066] After repeated cycles, the final CD of the mandrel 207 reaches the desired height and desired width W209, represented by H209. In various embodiments of the invention, the ratio of the height H209 to the width W209 of the mandrel 207 is between 10:1 and 20:1. In various embodiments of the invention, the mandrel 207 can therefore be grown to a final height of about 30 nm to 60 nm, and in one embodiment, it can be grown to about 40 nm to about 50 nm.

[0067] As will become clear from the manufacturing process described further, the mandrel 207 is an intermediate structure used to form the etch mask / hard mask. Additionally, the mandrel 207 can be used to define the distance between adjacent features (such as etch masks / hard masks or other mandrels 207).

[0068] In various embodiments, the mandrel 207 can be used for self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), or any other multipatterning technique.

[0069] Furthermore, embodiments of the present invention allow for execution within the same plasma processing chamber. Figures 3A to 6B The demonstrated device fabrication process steps advantageously improve the complexity of semiconductor device integration. Thus, as shown, the formation of the mandrel 207, the deposition of spacer material 211, the etching of the spacer material 211, and the removal of the mandrel 207 are all performed in a single plasma processing chamber. In addition to improved process integration, improvements are also made in throughput time, cost, and pattern transfer performance. While many advantages are mentioned herein, the selective deposition and trimming process described using embodiments of the invention enables the use of self-aligned multiple patterning (SAMP) on EUV lithography.

[0070] As previously described, the mandrel formation process (i.e., growth and trimming) and spacer deposition can be performed in a single plasma deposition process. Alternatively, in some embodiments, the spacer deposition process can be performed using methods described above (such as chemical vapor deposition, atomic layer deposition, etc.). Therefore, in embodiments of the invention, different gases can be introduced during deposition to modify the deposition conditions. Alternatively, the process chemistry can be modified more dynamically by controlling or altering the bias / bias scheme applied in the plasma processing chamber. Therefore, in some embodiments, a compositional gradient can be established between layers of the mandrel material based on the properties of the etching chemistry.

[0071] In various embodiments, Figures 3A to 3B and Figures 4A to 4B The process described in the text can be cyclical to produce Figures 5A to 5B The features shown.

[0072] While the above discussion focuses on a cyclic process including deposition and trimming, in alternative embodiments, a single-step selective deposition process can be used to directly grow the mandrel material 205 layer. A trimming stage is used because there is deposition above the layer 202 to be patterned. In the case of partially selective deposition, a smaller number of trimming cycles can be used.

[0073] Figure 6A and Figure 6BThis illustrates a semiconductor device during manufacturing following the deposition of spacer material 211 over a mandrel 207, according to an embodiment of the present invention. Figure 6A Showing cross-sectional views and Figure 6B A top-down view is shown.

[0074] In various embodiments, the spacer material 211 may be deposited using conformal deposition processes such as atomic layer deposition (ALD) or any other conformal deposition technique used in semiconductor device fabrication. The spacer material 211 may include silicon oxide (SiOx), silicon nitride, titanium nitride, titanium oxide, or any other type of oxide or insulating material known in the art.

[0075] In various embodiments, the ALD fabrication step for depositing spacer material 211 can be a process of deposition using a less corrosive oxidant (e.g., O3, H2O, H2O2, thermal O2, etc.) that does not damage adjacent photoresist or mandrel 207.

[0076] Figure 7A and Figure 7B A semiconductor device is illustrated during manufacturing following a multiple patterning process according to an embodiment of the present invention, wherein, Figure 7A Showing cross-sectional views and Figure 7B A top-down view is shown.

[0077] refer to Figure 7A An anisotropic etching process is used to etch the spacer material 211 and then remove the mandrel 207 to expose the underlying now-patterned layer 202 to be patterned. In various embodiments, a wet etching process can be used to remove the mandrel 207. Alternatively, anisotropic plasma etching processes such as reactive ion etching (RIE) can be used to remove the mandrel 207, allowing all etching processes to be performed in a single plasma etching chamber. The anisotropic etching process can be timed or stopped at the underlying (optional) etch stop layer. After etching, any remaining portion of the spacer etching / hard mask can be removed.

[0078] In various embodiments of the invention, the remaining spacer material 211 can therefore be used as an etching mask to pattern the layer 202 to be patterned into a plurality of features 212. With the mandrel 207 now removed, individual spacers are left as etching masks / hard masks to etch the layer 202 to be patterned below the spacers. Any exposed areas of the layer 202 to be patterned that were not exposed by the spacers are removed during etching, leaving a plurality of features 212.

[0079] In various embodiments, the plurality of features 212 may be formed as part of a multi-patterning process, such as self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), or any other multi-patterning technique known in the art. In various embodiments, the plurality of features 212 formed by this multi-patterning technique may be contact holes, metal lines, gate lines, isolation regions, and other such features formed using a self-aligned multi-patterning lithography process.

[0080] Subsequent processing can be carried out as in a conventional process flow, forming subsequent features and ultimately forming a semiconductor device that includes all active and passive devices containing metallization layers to interconnect these devices.

[0081] Advantageously, using embodiments of the invention, a subset of the above steps can be performed in a single process formulation. This is because the change from deposition to etching can be rapidly accomplished by simply altering the plasma chemistry. For example, in one embodiment, as... Figures 3A to 5B The selective deposition of mandrel materials shown, such as Figures 6A to 6B and Figures 7A to 7B The formation of multiple spacers shown and / or as Figures 7A to 7B The removal of the mandrel shown can be performed in a single process step. In a further embodiment, such as Figures 7A to 7B The patterning of the layer 202 shown can also be part of the same process formulation and performed in the same processing chamber.

[0082] As shown in the figure, in various embodiments, the deposition of mandrel material 205 can be performed using a CxHy / N2 / Ar / He / SiCl4 precursor, wherein the trimming step includes CO2 / CO / CH4 / O2 / N2 / H2 / fluorocarbon / HBr / Cl, etc. In various embodiments, the above processes (such as mandrel deposition including deposition and trimming, spacer deposition, spacer etching, mandrel removal) can be selected to be substantially similar to improve yield. For example, embodiments of the invention include switching from deposition to etching by removing a gas and / or (simultaneously) rapidly switching the bias scheme. In one illustrative embodiment, the mandrel can be an organic material, for example, using C x H y Type precursors and dilution gases (such as Ar, N2, He, H2) and the use of C x H y The mandrel is formed by trimming chemicals such as CO, CO2, Ar, He, N2, H2, and O2, so mandrel removal can be accomplished by ash chemicals (such as N2, H2, CO2, CO, O2, Ar, and He type chemicals) or alternative wet chemicals.

[0083] Figure 8A flowchart illustrating a method for forming a semiconductor device according to an embodiment of the present invention is shown. Method 300 includes depositing a photoresist layer over a substrate (box 310) and patterning the photoresist layer using an EUV lithography process (box 320), such as using, for example... Figures 2A to 2B As described. Next, a mandrel (frame 330) is formed over the patterned photoresist layer, such as using, for example... Figures 3A to 5B As described. Multiple spacers (frame 340) are formed on the sidewalls of the mandrel, such as using, for example... Figures 6A to 6B As described. The mandrel is then removed, leaving multiple spacers (frame 350), as if using, for example... Figures 7A to 7B As described. Next, multiple spacers are used as etching masks to pattern the substrate layer (box 360), such as using, for example... Figures 7A to 7B As described. In one or more embodiments, selectively depositing mandrel material, forming multiple spacers, etching back the spacers, and removing the mandrel are performed in a single process step.

[0084] Figure 9 A flowchart illustrating a method for forming a semiconductor device according to another embodiment of the present invention is shown. Method 400 includes placing a layer to be patterned over a substrate (box 410). A patterned resist layer is then formed over the layer to be patterned using an EUV lithography process (box 420), such as using, for example... Figures 2A to 2B As described. Next, a core material is deposited over the patterned photoresist layer to form the core (frame 430), such as using, for example... Figures 3A to 5B As described. Next, spacers (frame 440) are formed along the mandrel, such as using, for example... Figures 6A to 6B As described. Then remove the mandrel (frame 450), as if using, for example Figures 7A to 7B As described. Next, the spacers can be used as hard masks to pattern the layer to be patterned in order to form features (boxes 460), such as using, for example... Figures 7A to 7B As described.

[0085] Figure 10 A flowchart illustrating a method for forming a semiconductor device according to another embodiment of the present invention is shown. Method 500 includes placing a layer to be patterned over a substrate (box 510). Next, a patterned resist layer is formed over the layer to be patterned using a photolithography process (box 520), such as using, for example... Figures 2A to 2B As described. Next, a cyclic process is performed to form a mandrel (box 530), which includes depositing a mandrel material layer (box 531) and performing a trimming process (box 532), such as using, for example... Figures 3A to 4BThe described cyclic process may include repeated deposition and execution, wherein repetition may be stopped when the ratio of mandrel height to mandrel width is between 2:1 and 20:1. Spacers (box 540) may be formed along the mandrel, as will be used below, for example. Figures 6A to 6B As described. After the spacers are formed, the mandrel (frame 550) can be removed, for example, using... Figures 7A to 7B As described. Next, the spacers can be used as an etching mask to pattern the layer to be patterned to form the feature (box 560), such as using, for example... Figures 7A to 7B As described.

[0086] Therefore, as described above, in conventional techniques, photoresist is used as the sole mandrel material because the resist cannot form to a sufficient height. However, this technique is insufficient to form depth-scaled features using extreme ultraviolet (EUV) lithography or electron beam lithography. To achieve spacer deposition (typically a subsequent semiconductor processing step after mandrel formation), the patterned resist must reach a sufficient height. As previously described, resist budgets (i.e., allowable margins / limits) do not allow for this height, thus limiting or excluding the possibility of using EUV patterned photoresist as the sole material for the mandrel. This is because the typical achievable height of EUV photoresist is approximately 10 nm to approximately 30 nm, which is insufficient for current semiconductor manufacturing requirements. To achieve sufficient spacer deposition on the mandrel, embodiments of the present invention employ a selective mandrel growth and trimming process using an introduced resist profile as the base feature for mandrel formation. According to various embodiments of the invention, as the mandrel material is deposited onto the introduced resist profile, the mandrel material can be simultaneously reshaped and smoothed, all within the same plasma processing chamber and optionally as part of the same process.

[0087] Exemplary embodiments of the invention are summarized herein. Other embodiments may also be understood from the entire specification and the claims set forth herein.

[0088] Example 1. A method of forming a device, the method comprising forming a patterned resist layer over a substrate using an extreme ultraviolet (EUV) lithography process; and forming a mandrel in a plasma processing chamber by selectively depositing a mandrel material over the patterned resist layer, the mandrel comprising the patterned resist layer and the mandrel material.

[0089] Example 2. The method of Example 1 further includes: forming a plurality of spacers on the sidewall of the mandrel in the plasma processing chamber; removing the mandrel in the plasma processing chamber, leaving the plurality of spacers; and using the plurality of spacers as an etching mask to pattern layers of the substrate to form features of the device.

[0090] Example 3. The method as described in either Example 1 or 2, wherein selectively depositing the mandrel material, forming the plurality of spacers, and removing the mandrel are performed in a single process step.

[0091] Example 4. The method as described in any one of Examples 1 to 3, wherein the ratio of the height of the mandrel to the width of the mandrel is between 2:1 and 20:1.

[0092] Example 5. The method as described in any one of Examples 1 to 4, wherein selectively depositing the mandrel material comprises: depositing a mandrel material layer over the substrate; and performing a trimming process to selectively remove portions of the mandrel material layer that are in contact with the substrate.

[0093] Example 6. The method as described in any one of Examples 1 to 5 further includes repeating the deposition of the layer and performing the trimming process.

[0094] Example 7. The method as described in any one of Examples 1 to 6, wherein the mandrel material comprises a resist material, silicon, an organic material, or a dielectric material.

[0095] Example 8. The method of any one of Examples 1 to 7 further comprises: forming a plurality of spacers on the sidewall of the mandrel in the plasma processing chamber by depositing a spacer material layer and anisotropically etching the spacer material layer or by using an atomic layer deposition process in situ in the plasma processing chamber.

[0096] Example 9. The method as described in any one of Examples 1 to 8, wherein selectively depositing the mandrel material comprises: depositing the mandrel material over the patterned resist layer in a single process step.

[0097] Example 10. A self-aligned multiple patterning process includes: placing a layer to be patterned over a substrate; forming a patterned resist layer over the layer to be patterned using extreme ultraviolet (EUV) lithography; selectively depositing a mandrel material over the patterned resist layer to form a mandrel in a plasma processing chamber; forming spacers along the mandrel in the plasma processing chamber; removing the mandrel in the plasma processing chamber after forming the spacers, wherein depositing the mandrel material, forming the spacers, and removing the mandrel are performed in a single process step; and using the spacers as a hard mask to pattern the layer to be patterned to form features.

[0098] Example 11. The process as described in Example 10, wherein selectively depositing the mandrel material comprises: depositing a mandrel material layer over the patterned resist layer and the layer to be patterned; and performing a trimming process to selectively remove portions of the mandrel material layer that are in contact with the layer to be patterned.

[0099] Example 12. The process as described in one of Examples 10 or 11 further includes repeating the deposition of the layer and performing the trimming process.

[0100] Example 13. The process described in any one of Examples 10 to 12, wherein the mandrel material comprises a resist material.

[0101] Example 14. A process as described in any one of Examples 10 to 13, wherein the mandrel material comprises silicon, an organic material, or a dielectric material.

[0102] Example 15. A process as described in any one of Examples 10 to 14, wherein forming these spacers includes: depositing a spacer material layer and anisotropically etching the spacer material layer.

[0103] Example 16. A process as described in any one of Examples 10 to 15, wherein forming these spacers includes using a fusion-type process.

[0104] Example 17. A self-aligned multiple patterning process includes: placing a layer to be patterned over a substrate; forming a patterned resist layer over the layer to be patterned using a photolithography process; performing a cyclic process in a plasma processing chamber to form a mandrel including the patterned resist layer, the cyclic process including depositing a mandrel material layer over the patterned resist layer and the layer to be patterned, and performing a trimming process to selectively remove portions of the mandrel material layer that are in contact with the layer to be patterned; forming spacers along the mandrel in the plasma processing chamber; removing the mandrel after forming the spacers in the plasma processing chamber; and using the spacers as etching masks to pattern the layer to be patterned to form features.

[0105] Example 18. The process as described in Example 17, wherein the cyclic process includes repeating the deposition and the execution, wherein the repetition is stopped when the ratio of the height of the mandrel to the width of the mandrel is between 2:1 and 20:1.

[0106] Example 19. A process as described in one of Examples 17 or 18, wherein the cyclic process includes repeating the deposition of the layer and performing the trimming process.

[0107] Example 20. A process as described in any one of Examples 17 to 19, wherein the mandrel material comprises silicon, a photoresist material, an organic material, or a dielectric material.

[0108] Example 21. A process as described in any one of Examples 17 to 20, wherein forming these spacers includes: depositing a spacer material layer and anisotropically etching the spacer material layer; or using an atomic layer deposition process in situ in the plasma processing chamber.

[0109] Although the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations thereof will be apparent to those skilled in the art from the description, illustrative embodiments, and other embodiments of the invention. Therefore, it is intended that the appended claims cover any such modifications or embodiments.

Claims

1. A method of forming a semiconductor device, the method comprising: forming a metal oxide photoresist film as a patterned resist layer over a substrate using an extreme ultraviolet lithography process; and executing a single process recipe in-situ in a plasma processing chamber, wherein the single process recipe is executed by changing plasma chemistry, the single process recipe comprising: forming a mandrel comprising the patterned resist layer and the mandrel material on the patterned resist layer in the plasma processing chamber by selectively depositing porous silicon as a mandrel material over the patterned resist layer, and the formed mandrel's patterned resist layer's sidewalls are free of the mandrel material, wherein selectively depositing the porous silicon as a mandrel material comprises: depositing a mandrel material layer composed of the mandrel material over the substrate, the mandrel material having a greater selectivity to deposit on a top surface of the metal oxide photoresist film than on a top surface of a material on which the metal oxide photoresist film is formed; and executing a trim process to selectively remove portions of the mandrel material layer in contact with the substrate, the trim process comprising a combination of anisotropic and isotropic etching; forming a plurality of spacers on the mandrel's sidewalls in the plasma processing chamber; and removing the mandrel in the plasma processing chamber, leaving the plurality of spacers.

2. The method of claim 1, further comprising: using the plurality of spacers as an etch mask, patterning a layer of the substrate to form features of the device.

3. The method of claim 2, wherein, The selective deposition of the mandrel material, the forming of the plurality of spacers, and the removing of the mandrel are executed in a single process step.

4. The method of claim 1, wherein, The ratio of the height of the mandrel to the width of the mandrel is between 2: 1 and 20:

1.

5. The method of claim 1, further comprising repeating the deposition of the layer and the execution of the trim process.

6. The method of claim 2, wherein, The plurality of spacers comprises silicon oxide, silicon nitride, titanium nitride, or titanium oxide.

7. A self-aligned multiple patterning process, comprising: having a layer to be patterned over a substrate; forming a metal oxide photoresist film as a patterned resist layer over the layer to be patterned using an extreme ultraviolet lithography process; selectively depositing porous silicon as a mandrel material over the patterned resist layer to form a mandrel comprising the patterned resist layer and the mandrel material on the patterned resist layer in a plasma processing chamber, and the formed mandrel's patterned resist layer's sidewalls are free of the mandrel material, wherein selectively depositing the porous silicon as a mandrel material comprises: depositing a mandrel material layer composed of the mandrel material over the patterned resist layer and the layer to be patterned, the mandrel material having a greater selectivity to deposit on a top surface of the metal oxide photoresist film than on a top surface of a material on which the metal oxide photoresist film is formed; and executing a trim process to selectively remove portions of the mandrel material layer in contact with the layer to be patterned, the trim process comprising a combination of anisotropic and isotropic etching; forming a spacer along the mandrel in the plasma processing chamber; In the plasma processing chamber, after the spacers are formed, the mandrel is removed, wherein depositing the mandrel material, forming the spacers, removing the mandrel are performed in a single process step by changing plasma chemistry; and Using the spacers as a hard mask, the layer to be patterned is patterned to form features.

8. The process of claim 7, further comprising repeating the depositing of the layer and the performing of the trimming process.

9. The process of claim 7, wherein, The mandrel is removed using an anisotropic plasma etch process.

10. The process of claim 7, wherein, The spacers comprise silicon oxide, silicon nitride, titanium nitride, or titanium oxide.

11. The process of claim 7, wherein, Forming the spacers comprises: depositing a layer of spacer material and anisotropically etching the layer of spacer material.

12. The process of claim 7, wherein, Forming the spacers comprises using a fusion-type process.

13. A self-aligned multiple patterning process, comprising: having a layer to be patterned over a substrate; using a photolithography process to form a metal oxide photoresist film as a patterned resist layer over the layer to be patterned; in a plasma processing chamber, performing a cyclic process to form a mandrel comprising the patterned resist layer and a plurality of mandrel material layers of a mandrel material on the patterned resist layer, and a sidewall of the patterned resist layer of the formed mandrel is free of the mandrel material, the cyclic process comprising: depositing a porous silicon as the mandrel material layers over the patterned resist layer and the layer to be patterned, the mandrel material being more selective to deposition on a top surface of the patterned resist layer than on a top surface of a material on which the metal oxide photoresist film is formed, and performing a trimming process to selectively remove portions of the mandrel material layers that are in contact with the layer to be patterned and portions of the mandrel material layers that are at sidewalls of the patterned resist layer, the trimming process comprising a combination of anisotropic and isotropic etching; wherein the cyclic process comprises repeating the steps of depositing the mandrel material layers and performing the trimming process, a composition gradient is established between the mandrel material layers based on etch chemistry properties; in the plasma processing chamber, forming spacers along the mandrel; in the plasma processing chamber, after the spacers are formed, the mandrel is removed; and Using the spacers as an etch mask, the layer to be patterned is patterned to form features.

14. The process of claim 13, wherein, The repeating is stopped when a ratio of a height of the mandrel to a width of the mandrel is between 2: 1 and 20:

1.

15. The process of claim 13, wherein, The spacers comprise silicon oxide, silicon nitride, titanium nitride, or titanium oxide.

16. The process of claim 13, wherein, Forming the spacers comprises: depositing a layer of spacer material and anisotropically etching the layer of spacer material; or using an atomic layer deposition type process in situ in the plasma processing chamber.

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