Inductive Superjunction Transistor

Abstract

A device comprises: a first drain / source region (116) and a second drain / source region (126) located on a substrate (102); a first gate (134) adjacent to the first drain / source region (116) and comprising a plurality of first fingers forming a first comb-like structure; and a second gate (136) adjacent to the second drain / source region (126) and comprising a plurality of second fingers forming a second comb-like structure, wherein the plurality of first fingers and the plurality of second fingers are arranged in an alternating manner, and the first drain / source region (116), the second drain / source region (126), the first gate (134) and the second gate (136) form two transistors connected back to back.

Description

[0001] This application claims priority to U.S. Provisional Application No. 63 / 131,658, filed on December 29, 2020, entitled “Inductive Superjunction Transistor,” the contents of which are incorporated herein by reference. Technical Field

[0002] The present invention relates to reverse current protection devices (eg, load switches), and more particularly, in some embodiments, to load switches including a pair of transistors connected back-to-back. Background Art

[0003] With the development of semiconductor technology, metal oxide semiconductor field effect transistor (MOSFET) has been widely used in integrated circuits. MOSFET is a device controlled by voltage. When a control voltage is applied to the gate of the MOSFET and the control voltage is greater than the threshold voltage of the MOSFET, a conductive channel is established between the drain and source of the MOSFET. After the conductive channel is established, current flows between the drain and source of the MOSFET. On the other hand, when the control voltage applied to the gate is less than the threshold voltage of the MOSFET, the MOSFET will be turned off accordingly.

[0004] MOSFET can include two major categories: N-channel MOSFET and P-channel MOSFET. According to the different structures, MOSFET can be divided into three subcategories: planar MOSFET, lateral double-diffused metal oxide semiconductor (LDMOS) device and vertical double-diffused MOSFET. Compared with other types of MOSFET, LDMOS device can provide a larger current per unit area, which is due to the asymmetric structure of LDMOS device, which provides a short channel between the drain and source of LDMOS device. In order to further improve the performance of LDMOS device, reduced surface field (RESURF) diffusion technology is used in the drift region to increase the breakdown voltage of the LDMOS device under the condition of the specific on-resistance (Rsp) of the given LDMOS device.

[0005] With the further development of semiconductor technology, super junction MOSFETs have emerged to further improve key performance, such as reducing on-resistance and improving power conversion efficiency. In planar MOSFETs, the rated voltage of planar MOSFETs is increased by increasing the length of the drift layer and / or reducing the doping concentration of the drift layer. As the drift layer length increases and the doping concentration decreases, the on-resistance increases exponentially. In contrast, super junction MOSFETs have multiple P-type deep pillar structures in a lightly doped N-type epitaxial layer. These multiple P-type deep pillar structures form multiple vertical PN junctions with the N-type epitaxial layer. These multiple vertical PN junctions help to limit the electric field in the lightly doped N-type epitaxial layer. Compared with planar MOSFETs, super junction MOSFETs have lower N-type epitaxial layer resistance due to multiple P-type deep pillar structures while maintaining the same breakdown voltage. Multiple vertical PN junctions also achieve unique nonlinear parasitic capacitance characteristics, which helps to reduce switching power losses.

[0006] The load switch is used to connect the load to the power supply or disconnect the load from the power supply. The load switch can be controlled by an external signal. During operation, when the load switch is turned off, the load switch is able to block the flow of current in both directions. On the other hand, when the load switch is turned on, a conductive path is established between the load and the power supply. Current flows from the power supply to the load via the conductive path. The load switch can be implemented by an isolation switch, wherein the isolation switch has two transistors connected back to back. In high voltage (e.g., 24V) applications, each transistor can be implemented by an LDMOS device respectively. LDMOS devices connected back to back can achieve bidirectional current blocking.

[0007] The existing high-voltage load switch has the following disadvantages: Since the device area and on-resistance are doubled at the same time, the structure of LDMOS devices connected back to back will effectively increase the characteristic on-resistance Rsp of the load switch by four times. With the further development of the semiconductor industry, the load switch can be implemented on an integrated circuit. It is hoped that the area occupied by the load switch can be reduced to improve the efficiency and cost of the integrated circuit. Summary of the invention

[0008] The present disclosure provides a load switch including a pair of transistors connected back to back. In some preferred embodiments of the present disclosure, the above-mentioned problems and other problems can generally be solved or circumvented, and technical advantages can be achieved.

[0009] According to one embodiment, the present disclosure provides a device comprising: a first drain / source region and a second drain / source region located on a substrate; a first gate adjacent to the first drain / source region, the first gate comprising a plurality of first fingers forming a first comb-like structure; and a second gate adjacent to the second drain / source region, the second gate comprising a plurality of second fingers forming a second comb-like structure, wherein the plurality of first fingers and the plurality of second fingers are arranged alternately, and the first drain / source region, the second drain / source region, the first gate and the second gate form two transistors connected back to back.

[0010] According to another embodiment, the present disclosure provides a method, comprising: growing an epitaxial layer of a first conductive type on a substrate of a first conductive type; forming a drift layer of a second conductive type on the epitaxial layer; forming a first body region and a second body region of the first conductive type in the drift layer; injecting ions of the second conductive type to form a first source region in the first body region and a second source region in the second body region; forming a first gate adjacent to the first source region, the first gate having a first comb structure including a plurality of first finger-shaped portions; and forming a second gate adjacent to the second source region, the second gate having a second comb structure including a plurality of second finger-shaped portions.

[0011] According to another embodiment, a load switch is provided, comprising: a first transistor and a second transistor, the second transistor being connected back-to-back to the first transistor, a source of the first transistor and a source of the second transistor being formed above a substrate, a gate of the first transistor being adjacent to the source of the first transistor, the gate of the first transistor having a first comb structure including a plurality of first fingers, the gate of the second transistor being adjacent to the source of the second transistor, the gate of the second transistor having a second comb structure including a plurality of second fingers.

[0012] The above description broadly summarizes the features and technical advantages of the present disclosure so that the following detailed description of the present disclosure can be better understood. Additional features and advantages of the present disclosure will be described below, and these additional features and advantages constitute the subject matter protected by the claims of the present disclosure. It should be understood by those skilled in the art that, based on the concepts and specific embodiments of the present disclosure, it is easy to modify or design other structures or processes that have the same purpose as the present disclosure. It should also be recognized by those skilled in the art that these equivalent structures do not deviate from the spirit and scope of the present disclosure as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more fully understand the present disclosure and its advantages, the following description is now provided for reference in conjunction with the accompanying drawings, in which:

[0014] Figure 1 A schematic diagram of a common drain transistor according to various embodiments of the present disclosure is shown;

[0015] Figure 2 A schematic top view of a load switch formed by a common drain LDMOS transistor according to various embodiments of the present disclosure is shown;

[0016] Figure 3 The following are shown according to various embodiments of the present disclosure. Figure 2 A first cross-sectional schematic diagram of a load switch shown;

[0017] Figure 4 The following are shown according to various embodiments of the present disclosure. Figure 2 A second cross-sectional schematic diagram of the load switch shown;

[0018] Figure 5 The following are shown according to various embodiments of the present disclosure. Figure 2 A third cross-sectional schematic diagram of the load switch shown;

[0019] Figure 6 The following are shown according to various embodiments of the present disclosure. Figure 2 A schematic top view of a first implementation of a gate structure shown;

[0020] Figure 7 The following are shown according to various embodiments of the present disclosure. Figure 2 A schematic top view of a second implementation of the gate structure shown;

[0021] Figure 8 FIG. 2 shows a structure after forming an accumulation layer in a drift layer according to various embodiments of the present disclosure. Figure 2 A cross-sectional schematic diagram of a load switch shown in;

[0022] Fig. 9 FIG. 2 shows a diagram of a depletion region after forming a depletion region in a drift layer according to various embodiments of the present disclosure. Figure 2 A cross-sectional schematic diagram of a load switch shown in ; and

[0023] Fig.10 The invention is shown in accordance with various embodiments of the present disclosure for manufacturing Figure 1 A flow chart of a method for a load switch is shown.

[0024] In the different drawings, corresponding numerals and symbols are generally used to indicate corresponding parts unless otherwise indicated. These drawings are for the purpose of clearly illustrating the relevant aspects of the various embodiments and are not necessarily and not necessarily drawn to scale. DETAILED DESCRIPTION

[0025] The implementation and use of the preferred embodiments of the present disclosure will be discussed in detail below. However, it should be understood that the present disclosure provides many applicable inventive concepts, which can be embodied in a variety of specific contextual descriptions. The specific embodiments discussed are merely illustrations of some specific ways to implement and apply the present disclosure, and are not intended to limit the scope of the present disclosure.

[0026] The present disclosure will describe some embodiments in a specific context, namely a load switch, which includes a pair of lateral double-diffused metal oxide semiconductor (LDMOS) devices connected back to back. However, the embodiments of the present disclosure can also be applied to various reverse current protection devices formed by metal oxide semiconductor field effect transistors (MOSFET).

[0027] Figure 1 Schematic diagram of a common drain transistor according to various embodiments of the present disclosure is shown. The load switch can be implemented by two LDMOS devices connected back to back. The two LDMOS devices share a drain. In the description of the present disclosure, the load switch may also be referred to as a common drain transistor. It should be noted that Figure 1 The load switch shown in is only an example, which should not be used to overly limit the scope of the claims. A person skilled in the art may recognize many variations, substitutions, and modifications. For example, various embodiments of the present disclosure may be applied to various reverse current protection devices.

[0028] like Figure 1 As shown, the common drain transistor 100 includes two N-type transistors connected back to back. The first transistor includes a first drain D1, a first gate G1 and a first source S1. The second transistor includes a second drain D2, a second gate G2 and a second source S2. The drains of the two N-type transistors are directly connected together, as shown in FIG. Figure 1 shown. Figure 1 The back-to-back connected N-type transistors shown can be used as load switches. Load switches are capable of bidirectional current blocking. Therefore, load switches are also called isolation switches.

[0029] During operation, the source of the second transistor can be connected to a high voltage potential, such as a bias voltage. The source of the first transistor can be connected to a low voltage potential. In this configuration, the second switch can be turned on when the second gate is driven by a voltage higher than the high voltage potential. A charge pump can be used to provide a gate drive voltage higher than the high voltage potential.

[0030] In some embodiments, Figure 1Each transistor shown may be implemented by a lateral double diffused MOS (LDMOS) device. The common drain transistor 100 may have only four terminals, namely a first gate terminal, a first source terminal, a second gate terminal, and a second source terminal. Figure 1 As shown, the drains of the two N-type transistors connected back to back are connected to each other. That is, the drain is shared by the first transistor and the second transistor. The shared drain is floating, as shown in FIG. Figure 1 As shown. Therefore, the common drain transistor 100 does not include a drain terminal. By removing unnecessary drain regions (such as drain diffusion regions, drain contact holes, drain metal regions, etc.), the layout of the common drain transistor 100 is improved. Under the premise of ensuring that the spacing between the two gates (G1 and G2) meets the minimum spacing specified by the design rules, by removing unnecessary drain regions, Figure 1 The two transistors shown can be placed as close to each other as possible. Figures 2 to 5 Detailed layout of the common-drain transistor 100 is described below.

[0031] Figure 2 A schematic top view of a load switch formed by a common drain LDMOS transistor according to various embodiments of the present disclosure is shown. Two U-shaped N+ regions are arranged adjacent to each other. On the left side, the end of the first U-shaped N+ region and the end of the second U-shaped N+ region form a first source region 114. The first source region 114 is formed in the first body region 112. Similarly, on the right side, the end of the first U-shaped N+ region and the end of the second U-shaped N+ region form a second source region 124. The second source region 124 is formed in the second body region 122.

[0032] The first P+ region 115 is formed in the first body region 112 and is located between the two N+ regions of the first source region 114. The first P+ region 115 may contact the P-type first body region. A plurality of first source contact holes 116 are formed on the first P+ region 115 and the adjacent N+ region. At least one source contact hole 116 couples the first P+ region 115 to the adjacent N+ region.

[0033] It should be noted that, although one P+ region 115 is shown on the left, the semiconductor device may include multiple P+ regions 115. More specifically, multiple N+ regions and multiple P+ regions may be alternately arranged according to design requirements (e.g., more P+ regions may need to be provided based on an increase in channel width).

[0034] The second P+ region 125 is formed in the second body region 122 and is located between the two N+ regions of the second source region 124. The second P+ region 125 can contact the P-type second body region. A plurality of second source contact holes 126 are formed on the second P+ region 125 and the adjacent N+ region. At least one source contact hole 126 couples the second P+ region 125 to the adjacent N+ region.

[0035] It should be noted that, although one P+ region 125 is shown on the right side, the semiconductor device may include a plurality of P+ regions 125. More specifically, a plurality of N+ regions and a plurality of P+ regions may be alternately arranged.

[0036] The high voltage oxidation region 132 is located between the first body region 112 and the second body region 122. Figure 2 As shown, the active region 120 of the common drain LDMOS transistor is vertically disposed to the high voltage oxide region 132 .

[0037] The first gate 134 is arranged adjacent to the first source region 114. The first gate 134 has a first comb-like structure, which includes a first shaft and a plurality of first fingers. A plurality of first gate contact holes 137 are formed on the first gate 134. The second gate 136 is arranged adjacent to the second source region 124. The second gate 136 is a second comb-like structure, which includes a second shaft and a plurality of second fingers. A plurality of second gate contact holes 139 are formed on the second gate 136. Figure 3 As shown, the first gate 134 and the second gate 136 are separated from each other. The first fingers of the first gate 134 and the second fingers of the second gate 136 are arranged alternately.

[0038] Figure 2 The cross-sectional reference lines used in the subsequent figures are further shown. The cross-sectional reference line AA′ extends along the second finger of the second gate 136. The cross-sectional reference line BB′ extends along the space between two adjacent fingers. The cross-sectional reference line CC′ extends along the first finger of the first gate 134. For clarity, the cross-sectional schematic diagrams shown in the subsequent figures refer to these cross-sectional reference lines.

[0039] Figure 3 The following are shown according to various embodiments of the present disclosure. Figure 2 The first cross-sectional schematic diagram of the load switch is shown. The first cross-sectional schematic diagram is along Figure 2 The cross section shown is taken along reference line AA′. The common drain LDMOS transistor 200 includes a substrate 102 , a first layer 104 , a first body region 112 , a second body region 122 , and a drift layer 106 formed on the first layer 104 .

[0040] The common drain LDMOS transistor 200 further includes: a first source region 114 formed in the first body region 112; a second source region 124 formed in the second body region 122; a first gate dielectric layer 133, a high voltage oxidation region 132, a second gate dielectric layer 135, a first source contact hole 116, a first gate 134, a second gate 136, and a second source contact hole 126. In the description of the present disclosure, the first source region 114 may also be referred to as a first drain / source region. The second source region 114 may also be referred to as a second drain / source region.

[0041] In some embodiments, the substrate 102, the first layer 104, the first body region 112, and the second body region 122 have a first conductivity type. The drift layer 106, the first source region 114, and the second source region 124 have a second conductivity type. In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type. The common drain LDMOS transistor 200 is formed by two N-type transistors. In other embodiments, the first conductivity type is N-type and the second conductivity type is P-type. The common drain LDMOS transistor 200 is formed by two P-type transistors.

[0042] The substrate 102 may be formed of a suitable semiconductor material such as silicon, silicon germanium, silicon carbide, etc. Depending on different applications and design requirements, the substrate 102 may be N-type or P-type. In some embodiments, the substrate 102 is a P-type substrate. The substrate 102 is doped with a suitable P-type dopant, such as boron. In other embodiments, the substrate 102 is an N-type substrate. The substrate 102 is doped with a suitable N-type dopant, such as phosphorus.

[0043] The first layer 104 may be used as a P-type epitaxial layer. In the description of the present disclosure, the first layer 104 may also be referred to as the P-type epitaxial layer 104. The P-type epitaxial layer 104 is grown based on the substrate 102. The epitaxial growth of the P-type epitaxial layer 104 may be achieved by using any suitable semiconductor manufacturing process such as chemical vapor deposition (CVD). In some embodiments, the doping concentration of the P-type epitaxial layer 104 is about 10 14 / cm 3 Up to 10 16 / cm 3 within the range.

[0044] The drift layer 106 is an N-type layer formed on the first layer 104. In some embodiments, the drift layer 106 may be doped with an N-type dopant such as phosphorus at a doping concentration of about 10 15 / cm 3 Up to 10 17 / cm 3It should be noted that other N-type dopants, such as arsenic, antimony, etc., may also be used alternatively. It should also be noted that the drift layer 106 may also be referred to as an extended drain region.

[0045] The first body region 112 and the second body region 122 are P-type body regions. The P-type body region can be formed by implanting a P-type doping material (such as boron). Alternatively, the P-type body region can be formed by a diffusion process. In some embodiments, the P-type material (such as boron) can be formed at a rate of about 10 16 / cm 3 Up to 10 18 / cm 3 The first body region 112 may also be referred to as a first channel region. The second body region 122 may also be referred to as a second channel region.

[0046] The first source region 114 is a first N+ region formed in the first body region 112. The first source region 114 may also be referred to as the first N+ region 114. The first source region 114 may be formed by implanting N-type dopants (eg, phosphorus and arsenic) at a doping concentration of about 10 19 / cm 3 Up to 10 20 / cm 3 In addition, a source contact hole 116 is formed on the first N+ region 114 .

[0047] It should be noted that the P+ region (not shown) Figure 2 ) is adjacent to the first N+ region 114 in the first body region 112. The P+ region may be formed by implanting a P-type dopant (such as boron) with a doping concentration of about 10 19 / cm 3 Up to 10 20 / cm 3 The P+ region may be in contact with the P-type body region. To eliminate the body effect, the P+ region may be directly connected to the first source region (first N+ region 114) through the first source contact hole 116.

[0048] The second source region 124 is a second N+ region 124 formed in the second body region 122. The second source region 124 may also be referred to as a second N+ region 124. The second source region 124 may be formed by implanting N-type dopants (such as phosphorus and arsenic) at a doping concentration of about 10 19 / cm 3 Up to 10 20 / cm 3 In addition, a second source contact hole 126 is formed on the second N+ region 124 .

[0049] It should be noted that the P+ region (not shown) Figure 2) is adjacent to the second N+ region 124 in the second body region 122. The P+ region may be formed by implanting a P-type dopant (eg, boron, etc.) with a doping concentration of approximately 10 19 / cm 3 Up to 10 20 / cm 3 The P+ region may be in contact with the P-type body region. In order to eliminate the body effect, the P+ region may be directly connected to the second source region (second N+ region 124) through the second source contact hole 126.

[0050] The first gate dielectric layer 133, the high voltage oxidation region 132 and the second gate dielectric layer 135 are formed on the drift layer 106. Figure 3 As shown, the first gate dielectric layer 133 includes a portion located on the first body region 112 and a portion located on the drift layer 106. Similarly, the second gate dielectric layer 135 includes a portion located on the second body region 122 and a portion located on the drift layer 106. The high voltage oxidation region 132 is formed between the first gate dielectric layer 133 and the second gate dielectric layer 135.

[0051] like Figure 3 As shown, the thickness of the high-voltage oxidation region 132 is much greater than the thickness of the first gate dielectric layer 133 and the second gate dielectric layer 135. In some embodiments, the thickness of the first gate dielectric layer 133 and the second gate dielectric layer 135 is between about 100 angstroms and 200 angstroms. The thickness of the high-voltage oxidation region 132 is about 5000 angstroms. In some embodiments, the first gate dielectric layer 133, the high-voltage oxidation region 132 and the second gate dielectric layer 135 can be made of a suitable oxide material, such as silicon oxide, silicon oxynitride, hafnium oxide, zirconium oxide, etc.

[0052] The first gate 134 is formed on the first gate dielectric layer 133 and the high voltage oxidation region 132. The second gate 136 is formed on the second gate dielectric layer 135 and the high voltage oxidation region 132. The first gate 134 and the second gate 136 may be made of polysilicon, polysilicon germanium, nickel silicide or other metal or metal alloy materials.

[0053] like Figure 3 As shown, the first gate 134 extends upward to above the high voltage oxide region 132. The combination of the first gate 134 and the high voltage oxide region 132 serves as a first field plate. The first field plate helps maintain the breakdown voltage of the first transistor in the common drain LDMOS transistor 200. Similarly, the second gate 136 extends upward to above the high voltage oxide region 132. The combination of the second gate 136 and the high voltage oxide region 132 serves as a second field plate. The second field plate helps maintain the breakdown voltage of the second transistor in the common drain LDMOS transistor 200.

[0054] Refer to Figure 2 The cross-sectional reference line AA′ extends through the shaft of the comb-shaped structure of the first gate 134 and the finger-shaped structure of the second gate 136 . Therefore, most of the upper surface of the high voltage oxidation region 132 is covered by the second gate 136 .

[0055] The first gate 134 and the second gate 136 can be formed by the following steps: depositing a polysilicon layer with a thickness of about 4000 angstroms above the gate dielectric layer and the high voltage oxidation region, depositing a photoresist layer on the polysilicon layer, developing the photoresist layer to define the regions of the first gate 134 and the second gate 136, and etching the polysilicon layer to form the first gate 134 and the second gate 136. Figure 3 As shown, the first source region 114 and the second source region 124 are symmetrically arranged relative to a center line 101 , and the center line 101 passes through the high voltage oxidation region 132 .

[0056] In a conventional common drain LDMOS transistor, two LDMOS transistors are arranged in a symmetrical manner relative to the common drain. Each LDMOS transistor has its own high voltage oxidation region. The two high voltage oxidation regions are separated by a drain contact hole. Based on the design rules of a 24V LDMOS device, the size of a single LDMOS transistor is approximately 2.2um. The size of two LDMOS transistors is approximately 4.4um. It should be noted that the sizes selected in the foregoing examples are merely examples and are not meant to limit the embodiments of the present invention to any particular size. Those skilled in the art will appreciate that the size of the LDMOS device may vary depending on the different manufacturing processes.

[0057] like Figure 3 As shown, the embodiment of the present disclosure uses a single high-voltage oxide region 132 to replace the two high-voltage oxide regions used in the conventional common-drain LDMOS transistor. In addition, the drain region and the drain contact hole are removed. Since the two high-voltage oxide regions are merged into one high-voltage oxide region, and the drain region and the drain contact hole are removed, the two LDMOS transistors can be close to each other. In addition, see Figure 2 The plurality of first fingers and the plurality of second fingers are arranged in an alternating manner. Such an arrangement of the fingers of the first gate 134 and the fingers of the second gate 136 helps to further reduce the distance between the first source contact hole 116 and the second source contact hole 126.

[0058] like Figure 3 As shown, the size of the common drain LDMOS transistor 200 is represented by D. Specifically, D refers to the distance between the first source contact hole 116 and the second source contact hole 126. According to the design rules of the 24V LDMOS device, D is about 2.6um. The size of the common drain LDMOS transistor 200 is much smaller than the size of the conventional common drain LDMOS transistor (4.4um).

[0059] For a common drain LDMOS transistor formed by a 24V LDMOS device, such as Figure 3 The area of ​​the common drain LDMOS transistor shown is about 1.18 times the area of ​​a single transistor. The characteristic on-resistance Rsp is equal to the area of ​​the semiconductor device multiplied by the on-resistance of the semiconductor device. The effective characteristic on-resistance Rsp can be obtained by a normalization process. Based on the normalization process, the effective characteristic on-resistance Rsp of a single 24V LDMOS device is equal to 1. Figure 2 The comb-like structure of the gate helps to reduce the on-resistance of the common drain LDMOS transistor 200, because the comb-like structure of the gate forms a super-junction like transistor device. The equivalent on-resistance of this super-junction like transistor device is much less than twice the on-resistance of a single 24V LDMOS device. Based on the same normalization process, Figure 3 The effective characteristic on-resistance Rsp of the common drain LDMOS transistor shown is much less than 2.36 (2 times 1.18). In conventional devices, the effective characteristic on-resistance Rsp is equal to 4. Therefore, Figure 3 The common drain LDMOS transistor shown has a characteristic on-resistance Rsp reduced by more than 50% relative to conventional devices.

[0060] During operation, when the first gate voltage and the second gate voltage are applied to the first gate 134 and the second gate 136, respectively, and each gate voltage is greater than the threshold voltage of the corresponding transistor, a first inversion layer is formed in the first body region 112. The first inversion layer couples the first N+ region 114 to the drift layer 106. The second inversion layer is formed in the second body region 122. The second inversion layer couples the second N+ region 124 to the drift layer 106. Due to the presence of the first inversion layer and the second inversion layer, a conductive channel is established between the first source region and the second source region. Current flows between the first source region and the second source region of the common drain LDMOS transistor. On the other hand, when each gate voltage is less than the threshold voltage of the corresponding transistor, the common drain LDMOS transistor is turned off accordingly.

[0061] Figure 4 The following are shown according to various embodiments of the present disclosure. Figure 2 The second cross-sectional schematic diagram of the load switch is shown. The second cross-sectional schematic diagram is along Figure 2 The cross-section shown is taken along reference line BB′. Figure 4 The second cross-sectional schematic diagram shown in Figure 3 The first cross-sectional schematic diagram shown in FIG. 1 is similar to that shown in FIG. 1 , except that the cross-sectional reference line BB′ does not extend through the finger-shaped portions of the first gate 134 and the second gate 136. Figure 4As shown, the first gate 134 and the second gate 136 only cover the edge portion of the upper surface of the high voltage oxidation region 132 .

[0062] Figure 5 The following are shown according to various embodiments of the present disclosure. Figure 2 A third cross-sectional schematic diagram of the load switch is shown. Figure 5 The third cross-sectional diagram shown is Figure 3 The first cross-sectional schematic diagram shown is similar, except that the cross-sectional reference line CC′ extends through the finger portion of the first gate 134 and the shaft portion of the second gate 136. Figure 5 As shown, the first gate 134 covers most of the upper surface of the high voltage oxidation region 132 .

[0063] Figure 6 The following are shown according to various embodiments of the present disclosure. Figure 2 1 is a top view of a first embodiment of the gate structure shown in FIG. The first gate 134 includes a first shaft portion and a plurality of first finger portions. The second gate 136 includes a second shaft portion and a plurality of second finger portions. The first shaft portion of the first gate 134 is parallel to the second shaft portion of the second gate 136. Figure 6 As shown, the plurality of first fingers and the plurality of second fingers are arranged in an alternating manner.

[0064] Figures 3 to 5 The LDMOS transistor shown is designed using a two-dimensional (2D) RESURF principle, which forms a vertical PN structure between an N-type drift layer and a P-type epitaxial layer. Figure 6 The gate structure shown is conducive to achieving a three-dimensional (3D) RESURF effect. The 3D RESURF effect helps to achieve a three-dimensional (3D) RESURF effect in the vertical source-drain direction ( Figure 6 A uniform electric field is formed in the x direction as shown, and the lateral ( Figure 6 The electric field changes periodically in the y direction (shown in the figure). It should be noted that the z direction described below is perpendicular to the plane formed by the x and y directions. The electric field satisfies Poisson's equation:

[0065]

[0066] In formula (1), E x ,E y and E z represents the components of the electric field in the x, y, and z directions; q represents the charge; ∈ si Represents the dielectric constant of silicon; N d represents the doping concentration of the floating drift region; n represents the electron concentration.

[0067] The periodically changing lateral electric field can be generated by the comb-like structure of the first gate 134 and the second gate 136. The first gate 134 and the second gate 136 act as gates of the load switch, coupled between a high voltage (HV for short) and ground (0V). When both transistors are turned off, the first gate voltage (acting on the first gate 134) and the first source voltage (acting on the source 114) are equal to 0V. The second gate voltage (acting on the second gate 136) and the second source voltage (acting on the source 124) are equal to the high voltage HV. The voltage of the floating drift layer swings between 0V and the high voltage HV, as shown in FIG. Figure 6 As shown. The fingers of the comb-like structure of the first gate 134 are configured to generate multiple depletion regions in the drift layer. The fingers of the comb-like structure of the second gate 136 are configured to generate multiple accumulation layers in the drift layer. The multiple depletion regions and the multiple accumulation layers form alternating columns with opposite charges in the drift layer. Such alternating columns with opposite charges establish a superjunction-like structure, which makes the equation (1) Items can be maximized. The term can further enhance the RESURF effect in the x-direction.

[0068] Due to the three-dimensional RESURF structure, the electric field E in the x direction x It is basically uniform. The breakdown voltage can be calculated according to the following formula:

[0069]

[0070] In formula (2), BV represents the breakdown voltage; Ecr represents the critical electric field at the breakdown point; and p represents the device spacing (i.e., the distance between the two source regions of the load switch). The three-dimensional RESURF structure can improve the breakdown voltage. More specifically, when the common-drain LDMOS transistor is in the off state, the three-dimensional RESURF structure helps to improve the breakdown voltage of the common-drain LDMOS transistor. In some embodiments, the common-drain LDMOS transistor is formed by a 24V LDMOS device. In the absence of a comb structure, the breakdown voltage is approximately 37V. In a case having Figure 6 In the case of the comb structure shown, the breakdown voltage is about 56V.

[0071] Figure 7 The following are shown according to various embodiments of the present disclosure. Figure 2 The diagram is a top view of a second implementation of the gate structure shown. Figure 7 The second embodiment shown is similar to Figure 6 The embodiment shown is different in that the finger-shaped portions located on the outermost side are the finger-shaped portions of the second gate 136 .

[0072] Figure 8 FIG. 2 shows a structure of a drift layer after an accumulation layer is formed in the drift layer according to various embodiments of the present disclosure. Figure 2 Schematic cross-sectional view of a load switch shown in FIG. Figure 8 The cross-sectional diagram is similar to Figure 3 The cross-sectional schematic diagram shown in FIG. 1 is different in that a high gate drive voltage is applied to the second gate 136. In some embodiments, the high gate drive voltage is about 20V. In response to the high gate drive voltage, positive charges are generated on the second gate 136. The positive charges on the second gate 136 attract electrons to form an accumulation layer 802, such as Figure 8 shown.

[0073] Fig. 9 FIG. 2 shows a diagram of a depletion region after forming a depletion region in a drift layer according to various embodiments of the present disclosure. Figure 2 Schematic cross-sectional view of a load switch shown in FIG. Fig. 9 The cross-sectional diagram is similar to Figure 5 1, except that a low gate drive voltage is applied to the first gate 134. In some embodiments, the low gate drive voltage is about 0 V. In addition, a high gate drive voltage is applied to the second gate 136. In response to the low gate drive voltage applied to the first gate 134 and the high gate drive voltage applied to the second gate 136, electrons are depleted, and ionized donors form a positively charged depletion region 902 below the first gate 134.

[0074] Figure 8 The accumulation layer 802 shown serves as an N-type pillar. Fig. 9 The depletion region 902 shown is used as a P-type pillar. Figure 7 As shown, the fingers of the comb-like structure of the first gate 134 are configured to generate a plurality of depletion regions (eg, Fig. 9 The fingers of the comb-like structure of the second gate 136 are configured to generate a plurality of accumulation layers in the drift layer (eg, Figure 8 The plurality of depletion regions and the plurality of accumulation layers form columns (P-type columns and N-type columns) arranged alternately and having opposite charges in the drift layer. Such columns arranged alternately and having opposite charges form an inductive super junction transistor structure.

[0075] Fig.10 The invention is shown in accordance with various embodiments of the present disclosure for manufacturing Figure 1 A flow chart of the method for a load switch is shown. Fig.10 The flowchart shown is only an example and should not be used to unduly limit the scope of the claims. A person of ordinary skill in the art may recognize many variations, substitutions, and modifications. For example, Fig.10The steps shown in the drawings may be added, deleted, replaced, rearranged and repeated.

[0076] Refer to Figure 1 and Figure 2 The load switch includes a first transistor and a second transistor. The second transistor is connected back to back to the first transistor. The source of the first transistor and the source of the second transistor are formed on a substrate. The gate of the first transistor is adjacent to the source of the first transistor. The gate of the first transistor has a first comb structure, which includes a plurality of first fingers. The gate of the second transistor is adjacent to the source of the second transistor. The gate of the second transistor has a second comb structure, which includes a plurality of second fingers.

[0077] The load switch further comprises an epitaxial layer on the substrate, a drift layer on the epitaxial layer, a first body region and a second body region in the drift layer, and a high voltage oxidation region on the drift layer. A plurality of first fingers and a plurality of second fingers are arranged in an alternating manner on the high voltage oxidation region.

[0078] In step 1002 , an epitaxial layer of a first conductivity type is grown on a substrate of a first conductivity type.

[0079] In step 1004, a drift layer of a second conductivity type is formed on the epitaxial layer. In some embodiments, the first conductivity type is P type and the second conductivity type is N type.

[0080] At step 1006 , a first body region and a second body region of a first conductivity type are formed in the drift layer.

[0081] At step 1008, ions of the second conductivity type are implanted into the first body region and the second body region to form a first source region and a second source region, respectively.

[0082] In step 1010, a first gate is formed adjacent to a first source region. The first gate has a first comb structure including a plurality of first fingers.

[0083] In step 1012, a second gate is formed adjacent to the second source region. The second gate has a second comb structure including a plurality of second fingers.

[0084] refer to Figure 2 The method further includes: configuring the first gate and the second gate so that the plurality of first finger-shaped portions and the plurality of second finger-shaped portions are arranged in an alternating manner.

[0085] refer to Figure 2The method further includes: forming a high voltage oxidation region on the drift layer; forming a gate dielectric layer, the gate dielectric layer extending from the edge of the first source region to the edge of the second source region; forming a first gate along the edge of the first source region, the first gate covering the first side wall and the first edge portion of the high voltage oxidation region; and forming a second gate along the edge of the second source region, the second gate covering the second side wall and the second edge portion of the high voltage oxidation region.

[0086] refer to Figure 8 and Fig. 9 The method further includes: applying a high gate drive voltage to the plurality of second fingers of the second gate to form a plurality of accumulation layers in the drift layer; and applying a low gate drive voltage to the plurality of first fingers of the first gate to form a plurality of depletion regions in the drift layer. The plurality of depletion regions and the plurality of accumulation layers form alternatingly arranged columns with opposite charges in the drift layer, wherein the alternatingly arranged columns with opposite charges form an inductive superjunction transistor structure.

[0087] Although the embodiments of the present disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure as defined by the appended claims.

[0088] In addition, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, material compositions, devices, methods, and steps described in the specification. As can be easily understood by those of ordinary skill in the art from this disclosure, processes, machines, manufactures, material compositions, devices, methods, or steps having substantially the same functions or achieving substantially the same results as the corresponding embodiments described herein can be adopted according to the present disclosure, and these processes, machines, manufactures, material compositions, devices, methods, or steps may be currently existing or developed in the future. Based on this, the attached claims are intended to include such processes, machines, manufactures, material compositions, devices, methods, or steps within their scope.

Claims

1. A device comprising: A first drain / source region and a second drain / source region located on the substrate; a first gate adjacent to the first drain / source region, the first gate comprising a plurality of first fingers forming a first comb-like structure; as well as a second gate adjacent to the second drain / source region, the second gate comprising a plurality of second fingers forming a second comb-like structure, The plurality of first fingers and the plurality of second fingers are arranged in an alternating manner, and the first drain / source region, the second drain / source region, the first gate and the second gate form two transistors connected back to back.

2. The device according to claim 1, wherein: The first drain / source region is a first source of the two transistors connected back to back, and the second drain / source region is a second source of the two transistors connected back to back.

3. The device according to claim 1, wherein: Also includes: An epitaxial layer of the first conductivity type, located on the substrate of the first conductivity type; A drift layer of a second conductivity type, located on the epitaxial layer; A first body region of a first conductivity type is formed in the drift layer, and the first drain / source region of a second conductivity type is formed in the first body region; A second body region of a first conductivity type is formed in the drift layer, and the second drain / source region of a second conductivity type is formed in the second body region; A high-voltage oxidation region, located above the drift layer; a first gate dielectric layer formed between the high voltage oxidation region and the first drain / source region; and A second gate dielectric layer is formed between the high voltage oxidation region and the second drain / source region.

4. The device according to claim 3, wherein: The first conductivity type is P type, and the second conductivity type is N type.

5. The apparatus according to claim 3, further comprising: a first body contact region formed in the first body region; as well as a second body contact region formed in the second body region, The first body contact region is coupled to the first drain / source region via a first source contact hole, and the second body contact region is coupled to the second drain / source region via a second source contact hole.

6. The device according to claim 3, wherein: The first drain / source region and the second drain / source region are symmetrically arranged relative to a center line, and the center line passes through the high-voltage oxidation region.

7. The device according to claim 1, wherein: After the two transistors connected back-to-back are turned off, the plurality of first fingers are configured to generate a plurality of depletion regions, and the plurality of second fingers are configured to generate a plurality of accumulation layers.

8. The device according to claim 7, wherein: The plurality of depletion regions and the plurality of accumulation layers are formed in an alternating manner.

9. The device according to claim 1, wherein: After the two transistors connected back-to-back are turned off, the plurality of first fingers have a first voltage potential, and the plurality of second fingers have a second voltage potential, which is higher than the first voltage potential.

10. The device according to claim 9, wherein: The plurality of first fingers and the plurality of second fingers are alternately arranged and have opposite charges, and the first fingers and the second fingers alternately arranged and having opposite charges form a super junction structure.

11. A method, wherein: include: growing an epitaxial layer of a first conductivity type on a substrate of the first conductivity type; forming a drift layer of a second conductivity type on the epitaxial layer; forming a first body region and a second body region of a first conductivity type in the drift layer; implanting ions of a second conductivity type to form a first source region in the first body region and a second source region in the second body region; forming a first gate adjacent to the first source region, the first gate having a first comb-shaped structure including a plurality of first fingers; and A second gate is formed adjacent to the second source region, the second gate having a second comb structure including a plurality of second fingers, the plurality of first fingers and the plurality of second fingers being arranged in an alternating manner.

12. The method according to claim 11, wherein: Also includes: forming a high voltage oxidation region on the drift layer; forming a gate dielectric layer, wherein the gate dielectric layer extends from an edge of the first source region to an edge of the second source region; forming the first gate along an edge of the first source region, the first gate covering a first sidewall and a first edge portion of the high voltage oxidation region; and The second gate is formed along the edge of the second source region, and the second gate covers the second side wall and the second edge portion of the high voltage oxidation region.

13. The method according to claim 11, wherein: The first source region, the second source region, the first gate, and the second gate form two transistors connected back to back.

14. The method according to claim 11, wherein: Also includes: applying a high gate drive voltage to the plurality of second fingers of the second gate to form a plurality of accumulation layers in the drift layer; as well as A low gate drive voltage is applied to the plurality of first fingers of the first gate to form a plurality of depletion regions in the drift layer.

15. The method according to claim 14, wherein: The plurality of depletion regions and the plurality of accumulation layers form alternately arranged columns with opposite charges in the drift layer, and the alternately arranged columns with opposite charges form an inductive super junction transistor structure.

16. A load switch, comprising: a first transistor; as well as a second transistor connected back-to-back with the first transistor, in: A source of the first transistor and a source of the second transistor are formed on a substrate; The gate of the first transistor is adjacent to the source of the first transistor, and the gate of the first transistor has a first comb structure including a plurality of first fingers; The gate of the second transistor is adjacent to the source of the second transistor, and the gate of the second transistor has a second comb structure including a plurality of second fingers, and the plurality of first fingers and the plurality of second fingers are arranged in an alternating manner.

17. The load switch according to claim 16, wherein: Also includes: an epitaxial layer located on the substrate; a drift layer located on the epitaxial layer; a first body region and a second body region located in the drift layer; as well as a high voltage oxidation region located above the drift layer, The plurality of first finger-shaped portions and the plurality of second finger-shaped portions are arranged above the high-voltage oxidation region in an alternating manner.

18. The load switch according to claim 17, wherein: Also includes: a plurality of accumulation layers in the drift layer, the plurality of accumulation layers being formed by applying a high gate drive voltage to the plurality of second fingers of the gate of the second transistor; as well as A plurality of depletion regions are located in the drift layer, the plurality of depletion regions being formed by applying a low gate drive voltage to the plurality of first fingers of the gate of the first transistor.

19. The load switch according to claim 18, wherein: Also includes: The plurality of depletion regions and the plurality of accumulation layers form an inductive super junction transistor structure.

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