Calibration methods for memory and its internal detection circuits, and memory systems

Abstract

This application provides a calibration method and storage system for a memory and its internal detection circuit, belonging to the field of storage technology. In the solution provided by this application, the control circuit in the calibration circuit can control the word line driving circuit to charge or discharge the charging circuit, and can form a current path between the charging circuit and the ground terminal through a resistor configuration circuit to simulate the voltage change process on the word lines in the memory. During the simulation of voltage change, the control circuit can also acquire the detection result obtained by the internal detection circuit detecting the voltage of the detection node. Since this detection result reflects the detection sensitivity of the internal detection circuit to the voltage of the detection node, the detection parameters of the internal detection circuit when performing leakage current detection on the word lines in the memory can be calibrated based on this detection result. Therefore, the problem of inaccurate leakage current detection results due to differences in the detection sensitivity of the internal detection circuit itself can be effectively avoided.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a calibration method and storage system for a memory and its internal detection circuit. Background Technology

[0002] Memory typically integrates internal detection circuitry that can detect leakage current in each word line of the memory. The magnitude of this leakage current can be used to determine whether the memory meets factory standards.

[0003] When detecting the leakage current of a target word line in the memory, the internal detection circuit first charges the target word line to a preset voltage. Then, the internal detection circuit sets the target word line to a floating state. After the target word line has been in the floating state for a preset period, the internal detection circuit detects the voltage on the target word line and determines whether the leakage current of the target word line is within the allowable range based on the detected voltage.

[0004] However, due to limitations in manufacturing precision, the detection sensitivity of the internal detection circuits in different memory chips can vary. Therefore, for word lines with the same leakage current, the leakage current detection results from the internal detection circuits in different memory chips may differ. In other words, the difference in the detection sensitivity of the internal detection circuits themselves can affect the accuracy of the leakage current detection results. Summary of the Invention

[0005] This application provides a calibration method and storage system for a memory and its internal detection circuit, which can solve the technical problem that the difference in the detection performance of the internal detection circuit itself affects the accuracy of leakage current detection results. The technical solution is as follows:

[0006] In a first aspect, a memory is provided, the memory including: a word line driving circuit, an internal detection circuit and a calibration circuit, the calibration circuit including: a resistor configuration circuit, a charging circuit and a control circuit;

[0007] The resistor configuration circuit is connected to the detection node and the ground terminal in the calibration circuit respectively. The resistor configuration circuit is used to form a current path between the detection node and the ground terminal, and the resistance value of the current path is the target resistance value. The charging circuit is connected to the detection node.

[0008] The control circuit is connected to the word line driving circuit, the detection node, and the internal detection circuit, respectively. The control circuit is used to: control the word line driving circuit to charge or discharge the charging circuit; set the detection node to a floating state and control the internal detection circuit to detect the voltage of the detection node; and obtain the detection result output by the internal detection circuit.

[0009] Optionally, the resistor configuration circuit includes: one resistor or multiple resistors; the multiple resistors are connected in series or in parallel between the detection node and the ground terminal.

[0010] Optionally, the resistor configuration circuit further includes at least one first switch connected to at least one of the plurality of resistors; the control circuit is further configured to control the on / off state of the at least one first switch to adjust the number of resistors used to form the current path, such that the resistance value of the current path is the target resistance value.

[0011] Optionally, if the plurality of resistors are connected in series between the detection node and the grounding terminal, then the two ends of each first switch are connected in parallel with at least one of the plurality of resistors;

[0012] If the plurality of resistors are connected in parallel between the detection node and the grounding terminal, then one end of each first switch is connected to one end of a resistor, and the other end of each first switch is connected to the detection node or the grounding terminal.

[0013] Optionally, the calibration circuit further includes: a current detection circuit; the current detection circuit is connected to the detection node, and the current detection circuit is used to apply the target voltage to the detection node and detect the current in the current path;

[0014] The control circuit is also connected to the current detection circuit, and the control circuit is used to adjust the resistance value of the resistor configuration circuit according to the current detected by the current detection circuit.

[0015] Optionally, the calibration circuit further includes a switching circuit, which is connected to the current detection circuit, the resistor configuration circuit, and the detection node, respectively; the switching circuit is used to adjust the on / off state of the current detection circuit and the resistor configuration circuit, and the on / off state of the resistor configuration circuit and the detection node, under the control of the control circuit.

[0016] Optionally, the switching circuit includes: a second switch and a third switch; the control terminal of the second switch is connected to the control circuit, the first terminal of the second switch is connected to the current detection circuit, and the second terminal of the second switch is connected to the resistor configuration circuit.

[0017] The control terminal of the third switch is connected to the control circuit, the first terminal of the third switch is connected to the resistor configuration circuit, and the second terminal of the third switch is connected to the detection node.

[0018] Optionally, the charging circuit includes a capacitor, one end of which is connected to the detection node, and the other end of which is connected to the ground terminal.

[0019] Optionally, the control circuit includes: a switching sub-circuit and a control sub-circuit;

[0020] The switching sub-circuit is connected to the word line driving circuit, the detection node, the input terminal of the internal detection circuit, and the control sub-circuit, respectively; the control sub-circuit is also connected to the output terminal of the internal detection circuit, and the control sub-circuit is used for:

[0021] Control the on / off state of the switch sub-circuit so that the switch sub-circuit adjusts the on / off state of the word line driving circuit and the detection node, and adjusts the on / off state of the detection node and the input terminal of the internal detection circuit;

[0022] In addition, the detection result output from the output terminal of the internal detection circuit is obtained.

[0023] Optionally, the switch sub-circuit includes: a fourth switch and a fifth switch; the control terminal of the fourth switch is connected to the control sub-circuit, the first terminal of the fourth switch is connected to the word line driving circuit, and the second terminal of the fourth switch is connected to the detection node;

[0024] The control terminal of the fifth switch is connected to the control sub-circuit, the first terminal of the fifth switch is connected to the detection node, and the second terminal of the fifth switch is connected to the input terminal of the internal detection circuit.

[0025] Optionally, the switch sub-circuit further includes: a sixth switch; the control terminal of the sixth switch is connected to the control sub-circuit, the first terminal of the sixth switch is connected to the word line driving circuit, and the second terminal of the sixth switch is connected to the input terminal of the internal detection circuit.

[0026] Secondly, a calibration method for an internal detection circuit is provided for calibrating the internal detection circuit in the memory provided in the first aspect, the method comprising:

[0027] The charging circuit in the calibration circuit is charged so that the voltage of the detection node in the calibration circuit is the target voltage;

[0028] The detection node is set to a floating state, and the internal detection circuit is controlled to detect the current value of the current path in the calibration circuit, wherein the resistance value of the current path is the target resistance value.

[0029] The internal detection circuit obtains the target time required for the current value to reach the target current, where the target current is the ratio of the target voltage to the target resistance.

[0030] Optionally, the method further includes: when the internal detection circuit performs leakage current detection on the word lines in the memory, controlling the floating duration of the word lines to the target duration.

[0031] Optionally, before charging the charging circuit in the calibration circuit, the method further includes:

[0032] Adjust the resistance value of the current path to the target resistance value.

[0033] Optionally, adjusting the resistance value of the current path to the target resistance value includes:

[0034] After applying the target voltage to the detection node, the resistance value of the current path is adjusted according to the detected current value of the current path until the current value of the current path is the target current.

[0035] Thirdly, another calibration method for an internal detection circuit is provided for calibrating the internal detection circuit in the memory provided in the first aspect above, the method comprising:

[0036] Perform multiple charge-discharge operations;

[0037] The target duration is determined based on the resistance value of the current path in the calibration circuit detected by the internal detection circuit after each charge / discharge operation; wherein each charge / discharge operation includes:

[0038] Charge the charging circuit in the calibration circuit;

[0039] During the discharge duration after the charging circuit has completed charging, the charging circuit is controlled to discharge; wherein the discharge duration is different in the multiple charge and discharge operations.

[0040] The detection node is set to a floating state, and the internal detection circuit is controlled to detect the resistance value of the current path.

[0041] The determination of the target duration based on the detection results of the internal detection circuit on the resistance value of the current path in the calibration circuit after each charge and discharge operation includes: determining the discharge duration of the charge and discharge operation that causes the detection result output by the internal detection circuit to change during the multiple charge and discharge operations as the target duration.

[0042] Optionally, the method further includes: when the internal detection circuit performs resistance detection on the word lines in the memory, controlling the discharge duration of the word lines to the target duration.

[0043] Fourthly, a storage system is provided, the storage system comprising: a memory controller, and at least one memory as provided in the above aspects.

[0044] The technical solution provided in this application may include the following beneficial effects:

[0045] This application provides a calibration method and storage system for a memory and its internal detection circuit. The memory provided includes an internal detection circuit and a calibration circuit. The control circuit in the calibration circuit can control the word line driving circuit to charge or discharge the charging circuit, and can form a current path between the charging circuit and the ground terminal through a resistor configuration circuit to simulate the voltage change process on the word lines in the memory. During the simulation of voltage change, the control circuit can also acquire the detection result obtained by detecting the voltage of the detection node output by the internal detection circuit. Since this detection result reflects the detection sensitivity of the internal detection circuit to the voltage of the detection node, the detection parameters of the internal detection circuit when performing leakage current detection on the word lines in the memory can be calibrated based on this detection result. Therefore, the problem of inaccurate leakage current detection results due to differences in the detection sensitivity of the internal detection circuit itself can be effectively avoided. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a schematic diagram of the structure of a storage system provided in an embodiment of this application;

[0048] Figure 2 This is a schematic diagram of the structure of a memory provided in an embodiment of this application;

[0049] Figure 3 This is a schematic diagram of the structure of a storage array provided in an embodiment of this application;

[0050] Figure 4 This is a schematic diagram of the structure of an internal detection circuit provided in an embodiment of this application;

[0051] Figure 5 This is a timing diagram of a leakage current detection process provided in an embodiment of this application;

[0052] Figure 6 This is a timing diagram of a resistance detection process provided in an embodiment of this application;

[0053] Figure 7 This is a schematic diagram illustrating the detection sensitivity of an internal detection circuit in a different die provided in an embodiment of this application;

[0054] Figure 8 This is a schematic diagram of the structure of a calibration circuit provided in an embodiment of this application;

[0055] Figure 9 This is a schematic diagram of another calibration circuit provided in an embodiment of this application;

[0056] Figure 10 This is a schematic diagram of another calibration circuit provided in the embodiments of this application;

[0057] Figure 11 This is a schematic diagram of a resistor configuration circuit provided in an embodiment of this application;

[0058] Figure 12 This is a schematic diagram of another resistor configuration circuit provided in an embodiment of this application;

[0059] Figure 13 This is a schematic diagram of another calibration circuit provided in an embodiment of this application;

[0060] Figure 14 This is a flowchart of a calibration method for an internal detection circuit provided in an embodiment of this application;

[0061] Figure 15 This is a flowchart of another calibration method for an internal detection circuit provided in an embodiment of this application. Detailed Implementation

[0062] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0063] The solutions provided in this application can be applied to electronic devices. These electronic devices can be mobile terminals, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality devices, augmented reality devices, or any other suitable electronic device having memory.

[0064] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, such as... Figure 1 As shown, the electronic device includes a storage system 10 and a host 20. The host 20 can be a central processing unit (CPU) or a system-on-chip (SOC) of the electronic device. The host 20 is used to send data to the storage system 10 for storage or to read data from the storage system 10.

[0065] refer to Figure 1 The storage system 10 includes a memory controller 101 and at least one memory 100 for storing data, for example... Figure 1 Multiple memories 100 are shown. Each memory 100 can be a three-dimensional (3D) memory, such as a 3D NAND flash memory. A memory controller 101 is connected to both the memory 100 and the host 20. The memory controller 101 manages the data stored in the memory 100 and communicates with the host 20.

[0066] In this embodiment, the memory controller 101 and at least one memory 100 can be integrated, meaning the storage system 10 can be integrated into a single storage device. As a possible example, the memory controller 101 and a single memory 100 can be integrated into a memory card. This memory card may include PCMCIA cards, compact flash (CF) cards, smart media (SM) cards, memory sticks, multi-media cards (MMC), secure digital (SD) cards, and universal flash storage (UFS), etc. As another possible example, the memory controller 101 and multiple memories 100 can be integrated into a solid-state disk (SSD).

[0067] Figure 2 This is a schematic diagram of the structure of a memory provided in an embodiment of this application. For example... Figure 2 As shown, the memory 100 includes peripheral circuitry 110 and memory array 120. The peripheral circuitry 110 is used to write data into the memory array 120 and to read data from the memory array 120. Figure 3 This is a schematic diagram of a storage array structure provided in an embodiment of this application, with reference to... Figure 3 The memory array 120 may include a plurality of memory strings 121, which are arranged along a bearing surface parallel to the substrate (i.e., Figure 3 The memory cells are arranged in the XY plane of the substrate. Each memory string 121 includes multiple memory cells connected in series, which are arranged in a direction perpendicular to the bearing surface of the substrate (i.e., the XY plane of the substrate). Figure 3 The memory cells are arranged in the Z-direction. Each memory cell can be a floating-gate field-effect transistor or a charge-trap field-effect transistor.

[0068] like Figure 3As shown, each memory string 121 also includes at least one upper select transistor connected to the first pole of the first memory cell, and at least one lower select transistor connected to the second pole of the last memory cell. The upper select transistor is also called a top select gate (TSG) or drain select transistor, and the lower select transistor is also called a bottom select gate (BSG) or source select transistor.

[0069] Each TSG's gate is connected to the drain select line (DSL), and the second terminal of each TSG is connected to the first terminal of the first memory cell in its memory string. The first terminal of each TSG is also connected to the bit line (BL). Each BSG's gate is connected to the source select line (SSL), and the first terminal of each BSG is connected to the second terminal of the last memory cell in its memory string. The second terminal of each BSG is also connected to the source line (SL). It is understood that the first terminal mentioned above can refer to either the source or the drain, and the second terminal can refer to the other. For example, the first terminal could refer to the drain, and the second terminal could refer to the source.

[0070] from Figure 3 As can be seen, the memory array 120 includes n BLs (BL1 to BLn) arranged along the X direction, x DSLs (DSL1 to DSLx) arranged along the Y direction, and x SSLs (SSL1 to SSLx) arranged along the Y direction. Here, n and x are both integers greater than 1. Each DSL is connected to the gate of the n TSGs arranged along the X direction, each BL is connected to the first electrode of the x TSGs arranged along the Y direction, and each SSL is connected to the gate of the n BSGs arranged along the X direction. Furthermore, the second electrode of each BSG is connected to the same SL.

[0071] Continue to refer to Figure 3 Each memory cell in a memory string 121 shares a set of word lines (WLs) with memory cells in other memory strings 121. Assuming each memory string 121 includes m memory cells, the memory array 120 can include m WLs arranged along the Z direction: WL1 to WLm, where m is an integer greater than 1. Each WL is connected to each memory cell located on the same layer (i.e., having the same height relative to the substrate's bearing surface). Alternatively, it can be understood that the control gates of each memory cell on the same layer, and the gate connection lines between the control gates, constitute a WL.

[0072] Peripheral circuitry 110 can be connected to storage array 120 via BL, WL, DSL, SSL, and SL. For example... Figure 2As shown, the peripheral circuit 110 may include a voltage generator 111, a page buffer (also known as a sense amplifier) ​​112, a column decoder (also known as a bit line driver) 113, a word line driver circuit (also known as a word line driver or row decoder) 114, and a control logic circuit 115.

[0073] The voltage generator 111 is connected to the control logic circuit 115 and is used to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, and verification voltage), bit line voltages, and source line voltages for loading onto the memory array 120 under the control of the control logic circuit 115.

[0074] Data buffer (also called page buffer) 112 is used to read data from memory array 120 under the control of control logic circuitry 115. In one example, page buffer 112 may store data to be programmed into memory array 120. In another example, page buffer 112 may perform a programming verification operation to ensure that data has been correctly programmed into the memory cell connected to the selected word line. In yet another example, page buffer 112 may also sense voltage signals from bit lines representing data bits stored in the memory cell and amplify the sensed voltage signals to a recognizable logic level.

[0075] The column decoder 113 is connected to each bit line of the memory array 120 and is used to apply bit line voltages from the voltage generator 111 to each bit line of the memory array 120 under the control of the control logic circuit 115.

[0076] Word line driver circuit 114 is connected to each row line of memory array 120 and, under the control of control logic circuit 115, applies row line voltage from voltage generator 111 to each row line of memory array 120. Each row line of memory array 120 includes a word line, a drain select line, a source select line, and a source line. For example, during the programming phase, word line driver circuit 114, under the control of control logic circuit 115, can apply a programming voltage to selected word lines and a pass voltage to non-selected word lines.

[0077] Continue to refer to Figure 2 The peripheral circuitry 110 of the memory 100 also includes an internal detection circuit 116. This internal detection circuit 116 is connected to both the control logic circuit 115 and the current loops (WL) in the memory 100, and is used to detect the leakage current of each WL in the memory 100 under the drive of the control logic circuit 115. This internal detection circuit 116 can also be referred to as an internal current sensing (ICS) circuit.

[0078] In this embodiment, the internal detection circuit 116 can detect not only the leakage current of WL, but also the RC state of the resistors and capacitors in the path (also known as XPATH) where WL is located. Since the probability of capacitor abnormalities in the path where WL is located is relatively low, while the probability of resistor abnormalities is relatively high, the internal detection circuit 116 can primarily detect whether the resistance of the path where WL is located is too high or too low. That is, the internal detection circuit 116 can detect whether the resistance of the path where WL is located is high (HR) or low (LR).

[0079] Optionally, the peripheral circuit 110 may include a plurality of internal detection circuits 116. The plurality of WLs in the memory 100 may be divided into multiple groups, and each of the plurality of internal detection circuits 116 may be connected to a group of WLs through a word line driving circuit 114 and used to detect the leakage current or resistance of a group of WLs.

[0080] Compared to external detection circuits such as precision measurement units (PMUs), this ICS circuit can effectively shorten the detection time and improve the efficiency of leakage current detection or resistance detection while ensuring detection accuracy. For example, the time required for an external detection circuit to perform a leakage current detection on all WLs in memory 100 is approximately 15 hours, while the internal detection circuit 116 can complete the leakage current detection on all WLs in only about 5 minutes.

[0081] In this embodiment, the peripheral circuit 110 of the memory 100 further includes a calibration circuit 117, which is connected to the internal detection circuit 116 and the word line driving circuit 114, and is used to calibrate the detection parameters of the internal detection circuit 116. These detection parameters may include: the floating duration of WL during leakage current detection, or the discharge duration of WL during resistance detection.

[0082] Figure 4 This is a schematic diagram of an internal detection circuit 116 provided in an embodiment of this application. The following will refer to... Figure 4 The working principle of the internal detection circuit 116 will be introduced using an example. Figure 4 As shown, the internal detection circuit 116 may include switches SW01, SW02, SW03 and SW044, capacitors C01 and C02, transistor M0 and comparator A0.

[0083] In this circuit, the first input terminal of comparator A0 is connected to the reference power supply terminal Vref. The second input terminal of comparator A0 is connected to one end of switch SW03, one end of capacitor C02, and the first terminal (e.g., the source) of transistor M0. The other end of switch SW03 is connected to the drive power supply terminal V1, the other end of capacitor C02 is connected to the ground terminal GND, the second terminal (e.g., the drain) of transistor M0 is connected to one end of switch SW02 and one end of capacitor C01, and the gate of transistor M0 is connected to the control power supply terminal V2. The other end of switch SW02 is connected to the drive power supply terminal V1, the other end of capacitor C01 is connected to one end of switch SW01, and the other end of switch SW01 is connected to WL. Switch SW02 and capacitor C01 are connected in parallel.

[0084] Furthermore, the aforementioned switches SW01 to SW04, as well as the control power supply terminal V2, are also connected to the control logic circuit 115. This control logic circuit 115 can control the on / off states of switches SW01 to SW04 and transistor M0.

[0085] Optionally, all of the aforementioned switches SW01 to SW04 can be transistors. For example, switches SW01 to SW04, as well as transistor M0, can all be metal-oxide-semiconductor field-effect transistors (MOSFETs). Furthermore, the type of the MOSFET can be either N-type or P-type, and this embodiment of the application does not limit this.

[0086] It is understandable that the first input terminal of the comparator A0 mentioned above can be either a non-inverting input terminal or an inverting input terminal, and the second input terminal of the comparator A0 can be either a non-inverting input terminal or an inverting input terminal.

[0087] As a possible example, see reference Figure 4 The internal detection circuit 116 can be connected to each WL via the word line driving circuit 114. The word line driving circuit 114 can connect the target WL to be detected (i.e., sel_WL) to the internal detection circuit 116 so that the internal detection circuit 116 can detect the voltage on the sel_WL.

[0088] As another possible example, the internal detection circuit 116 can be directly connected to sel_WL and can directly detect the voltage on sel_WL. For example, the peripheral circuitry 110 of the memory 100 includes a plurality of internal detection circuits 116, each internal detection circuit 116 being connected to a WL.

[0089] Figure 5 This is a timing diagram of a leakage current detection process provided in an embodiment of this application. (Reference) Figure 5 The leakage current detection process can include a pre-charging phase and a floating phase. During the pre-charging phase, the word line driver circuit 114 pre-charges the target WL (i.e., sel_WL) to be detected in the memory 100 to charge its voltage to the target voltage VPE. Furthermore, for other WLs in the memory 100 besides sel_WL (i.e., unsel_WL), the word line driver circuit 114 sets their voltage to a low voltage VSS. For example, unsel_WLs can all be grounded.

[0090] During this pre-charging phase, the control logic circuit 115 can also turn on (i.e., close) switches SW01, SW02, and SW03, and also turn on transistor M0. At this time, the word line driving circuit 114 can charge the first plate of capacitor C01 to the target voltage VPE, and the driving power supply terminal V1 can charge the second plate of capacitor C01 to the starting voltage. The target voltage VPE is higher than the starting voltage provided by the driving power supply terminal V1, and the starting voltage is higher than the reference voltage provided by the reference power supply terminal Vref. For example, the target voltage VPE can be 12 volts (V), the starting voltage can be 3.3V, and the reference voltage can be approximately 2.2V. For example, the range of the reference voltage can be from 1.6V to 2.3V.

[0091] Example, reference Figure 5 During the pre-charge phase, from t0 to t1, the voltage of sel_WL can be charged from a low voltage VSS to the target voltage VPE. From t1 to t2, the voltage of sel_WL can stabilize at the target voltage VPE. Combined with... Figure 4 and Figure 5 It can be seen that during the pre-charge phase, the voltage at the second input terminal of comparator A0 is the starting voltage provided by the drive power supply terminal V1. Since this starting voltage is greater than the reference voltage provided by the reference power supply terminal Vref, the sensing flag (S flag) output by comparator A0 can be the first flag.

[0092] Understandably, if the first input of comparator A0 is a non-inverting input and the second input is an inverting input, then the first flag can be 0. If the first input of comparator A0 is an inverting input and the second input is a non-inverting input, then the first flag can be 1.

[0093] It is also understandable that the switches and comparator A0 in the internal detection circuit 116 are generally low-voltage devices, while the charging voltage (i.e., target voltage VPE) of the word line drive circuit 114 for sel_WL is usually higher. If the voltage on sel_WL is directly detected through the second input terminal of comparator A0, the aforementioned low-voltage devices may be burned out. Therefore, a capacitor C01 can be set in the internal detection circuit 116, and the two plates of the capacitor C01 are charged to different voltages during the pre-charging phase. When there is leakage in sel_WL, the voltage of the first plate of capacitor C01 will drop, and the voltage of the second plate will also drop accordingly. Thus, the second input terminal of comparator A0 can detect the change in voltage on sel_WL. Based on the above analysis, it can be seen that the capacitor C01 can isolate the word line drive circuit 114 and the low-voltage devices, and therefore can also be called a high-voltage isolation capacitor.

[0094] Understandably, if the target voltage VPE is low, high-voltage isolation via capacitor C01 is not necessary. Accordingly, control logic circuit 115 can turn on switch SW04, and the second input of comparator A0 can directly detect the voltage of sel_WL.

[0095] Continue to refer to Figure 5 Once the voltage of sel_WL stabilizes at the target voltage VPE, the leakage current detection process can enter the floating stage. Figure 5 The duration of the floating phase is defined by the high level of the floating flag bit in sel_WL, which can be controlled by the control logic circuit 115. During this floating phase, the control logic circuit 115 can control the word line drive circuit 114 to stop supplying the target voltage VPE to sel_WL, thus keeping sel_WL in a floating state. Furthermore, the control logic circuit 115 can turn off switches SW02 and SW03, while keeping switch SW01 and transistor M0 on. At this time, voltage changes in sel_WL can be transmitted to the second input terminal of comparator A0 through capacitor C01.

[0096] Understandably, after floating sel_WL, if sel_WL has no leakage current or a small leakage current, then... Figure 5 As shown by curve s1, the voltage of sel_WL remains essentially constant or decreases only slightly. Consequently, the voltage across the two plates of capacitor C01 remains constant or decreases only slightly, and correspondingly, the voltage at the second input terminal of comparator A0 also remains constant or decreases only slightly. If, during this floating phase, the voltage at the second input terminal of comparator A0 is still greater than the reference voltage at the reference power supply terminal Vref, the detection flag output by comparator A0 will remain at the first flag. This first flag indicates that the leakage current of sel_WL is within the allowable range, meaning the leakage current detection result of sel_WL is passable.

[0097] After floating sel_WL, if the leakage current of sel_WL is large, then as follows: Figure 5 As shown by curve s2, the voltage of sel_WL will drop significantly. Consequently, the voltage across the two plates of capacitor C01 will also drop. Correspondingly, the voltage at the second input terminal of comparator A0 will also drop synchronously. If, during this floating phase, the voltage drop at the second input terminal of comparator A0 is too large, resulting in a voltage lower than the reference voltage at the reference power supply terminal Vref, the detection flag output by comparator A0 will change from the first flag to the second flag. This second flag indicates that the leakage current of sel_WL exceeds the allowable range, meaning the leakage current detection result of sel_WL is unacceptable (fail). For example, assuming the first input terminal of comparator A0 is a non-inverting input terminal and the second input terminal is an inverting input terminal, then the second flag can be 1.

[0098] refer to Figure 5 Assuming that during the pre-charging and floating phases, from t2 to t3, the voltage at the second input terminal of comparator A0 is higher than the reference voltage at the reference power supply terminal Vref, then the detection flag output by comparator A0 remains at the first flag 0. If comparator A0 detects at time t3 that the voltage at its second input terminal is lower than the reference voltage at the reference power supply terminal Vref, then it can change the detection flag output to the second flag 1.

[0099] Based on the above analysis, if the detection flag output by comparator A0 does not change during the floating phase, it indicates that the leakage current detection result of sel_WL is qualified. If the detection flag output by comparator A0 changes during the floating phase, it indicates that the leakage current detection result of sel_WL is unqualified.

[0100] Figure 6 This is a timing diagram of a resistance detection process provided in an embodiment of this application, and Figure 6 The following example illustrates how to check if the resistance of the path containing sel_WL is HR. (Reference) Figure 6 The resistance detection process can include a pre-charging phase, a discharging phase, and a detection phase. The implementation process of the pre-charging phase can be referred to the relevant description in the leakage current detection process described above. In the discharging phase, the control logic circuit 115 can control the word line drive circuit 114 to apply a low voltage VSS to sel_WL. That is, the word line drive circuit 114 can switch the voltage applied to sel_WL from the target voltage VPE to the low voltage VSS, so that sel_WL discharges. Figure 6The duration for which the WL discharge flag is at a high level is the duration of the discharge phase, and the duration for which the WL discharge flag is at a high level is pre-configured by the control logic circuit 115. That is to say, the duration of this discharge phase can be controlled by the control logic circuit 115.

[0101] In the detection phase after the end of the discharge phase, the control logic circuit 115 can disconnect the connection between the word line driving circuit 114 and sel_WL, so that sel_WL is in a floating state. Moreover, the control logic circuit 115 can turn off the switch SW02 and the switch SW03, and keep the switch SW01 and the transistor M0 in a conducting state. At this time, the voltage of sel_WL can be transmitted to the second input terminal of the comparator A0 through the capacitor C01.

[0102] It can be understood that if the resistance of the path where sel_WL is located is too high, then as Figure 6 shown by the curve s3 in, the voltage of this sel_WL drops relatively slowly during the discharge phase. Thus, the voltage drop amplitude of the two plates of the capacitor C01 is small, and correspondingly, the voltage drop amplitude of the second input terminal of the comparator A0 is also small. If during the detection phase, the voltage of the second input terminal of the comparator A0 is still greater than the reference voltage of the reference power supply terminal Vref, the detection flag output by the comparator A0 remains the first flag. This first flag can indicate that the resistance of the path where sel_WL is located is too high, that is, the resistance detection result of this sel_WL is unqualified.

[0103] If the resistance of the path where sel_WL is located is within the normal range, then as Figure 6 shown by the curve s4 in, the voltage of this sel_WL drops relatively fast during the discharge phase. Thus, the voltage drop amplitude of the two plates of the capacitor C01 is large, and correspondingly, the voltage drop amplitude of the second input terminal of the comparator A0 is also large. If during the detection phase, the voltage of the second input terminal of the comparator A0 is less than the reference voltage of the reference power supply terminal Vref, the detection flag output by the comparator A0 will become the second flag. This second flag can indicate that the resistance of the path where sel_WL is located is within the normal range, that is, the resistance detection result of this sel_WL is qualified.

[0104] In the embodiment of the present application, the control logic circuit 115 can also adjust the reference voltage of the reference power supply terminal Vref, and / or adjust the duration of the discharge phase, so that the internal detection circuit 116 detects whether the resistance of the path where sel_WL is located is LR.

[0105] During the LR detection process, if the resistance of the path containing sel_WL is within the normal range, the voltage of sel_WL will decrease relatively slowly during the discharge phase. Therefore, during the detection phase, the voltage at the second input terminal of comparator A0 will be greater than the reference voltage at the reference power supply terminal Vref. Accordingly, the detection flag output by comparator A0 will remain at the first flag. This first flag indicates that the resistance of the path containing sel_WL is within the normal range, meaning that the resistance detection result of sel_WL is qualified.

[0106] When the resistance of the path containing sel_WL is too low, the voltage of sel_WL will drop faster during the discharge phase. Therefore, during the detection phase, the voltage at the second input terminal of comparator A0 will be lower than the reference voltage at the reference power supply terminal Vref. Accordingly, the detection flag output by comparator A0 will change to the second flag. This second flag indicates that the resistance of the path containing sel_WL is too low, meaning the resistance detection result is unqualified.

[0107] It is understood that the internal detection circuit 116 in this embodiment is used to perform leakage current detection or resistance detection before the memory 100 leaves the factory. Since the memory 100 is obtained by packaging a die in a wafer, the leakage current detection or resistance detection performed by the internal detection circuit 116 can also be understood as being performed on the die.

[0108] Since the internal detection circuit 116 is integrated inside the memory 100, due to limitations in manufacturing process precision, the detection sensitivity of the internal detection circuit 116 in different dies on the same wafer will vary, and the detection sensitivity of the internal detection circuit 116 in dies on different wafers will also vary. The detection sensitivity of the internal detection circuit 116 refers to its sensitivity to voltage changes on sel_WL.

[0109] For the internal detection circuit 116 with high detection sensitivity, when the voltage on sel_WL drops only slightly, the comparator A0 in the internal detection circuit 116 can detect that the voltage at the second input terminal is less than the reference voltage at the reference power supply terminal Vref, and output the second mark. However, for the internal detection circuit 116 with low detection sensitivity, when the voltage on sel_WL drops significantly, the comparator A0 in the internal detection circuit 116 will detect that the voltage at the second input terminal is less than the reference voltage and output the second mark.

[0110] It is also understandable that during leakage current detection, the longer the floating time of sel_WL, the greater the voltage drop on sel_WL will be. Correspondingly, for the same sel_WL, after setting sel_WL to a floating state, the internal detection circuit 116 with higher detection sensitivity only needs a short time to output the second mark. However, the internal detection circuit 116 with lower detection sensitivity requires a longer time to output the second mark.

[0111] During resistance detection, the longer the discharge time of sel_WL, the greater the voltage drop across sel_WL. Correspondingly, for the same sel_WL, the internal detection circuit 116 with higher sensitivity can output the second mark after a shorter discharge time. However, the internal detection circuit 116 with lower sensitivity can only output the second mark after a longer discharge time.

[0112] Figure 7 This is a schematic diagram illustrating the detection sensitivity of an internal detection circuit in a different die provided in an embodiment of this application. Figure 7 The vertical axis represents the reference voltage at the reference power supply terminal Vref, in volts (V). The horizontal axis T represents the duration (hereinafter referred to as the detection duration) required for the internal detection circuit to output the second flag after sel_WL is set to the floating state, in microseconds (µs). For example, the reference... Figure 5 Assuming that sel_WL is set to a floating state at time t2, and the detection flag output by the comparator in the internal detection circuit changes from the first flag 0 to the second flag 1 at time t3, then the detection time T of the internal detection circuit is: T = t3 - t2.

[0113] Figure 7 This shows the detection sensitivity of the internal detection circuits in the six dies (D1 to D6) at different reference voltages when the leakage current of sel_WL is 0 nanoamps (nA), i.e., when there is no leakage current in sel_WL. Figure 7 It can be seen that when the reference voltage is 2.2V, the detection time T1 required for the internal detection circuit in die D1 to output the second mark is approximately 70µs, the detection time T2 required for the internal detection circuit in die D2 to output the second mark is approximately 330µs, and the detection time T3 required for the internal detection circuit in die D3 to output the second mark is approximately 750µs. Based on Figure 7 It can be seen that the detection sensitivity of the internal detection circuit in die D2 is relatively normal, while the detection sensitivity of the internal detection circuit in die D1 is too high (i.e., oversensitive), and the detection sensitivity of the internal detection circuit in die D3 is too low (i.e., undersensitive).

[0114] As the above analysis shows, due to limitations in manufacturing process precision, the detection sensitivity of the internal detection circuits in different dies can vary significantly. If the die's compliance with factory standards is determined directly based on the detection results of these internal circuits, die-level misjudgments can occur. For example, during leakage current detection, if the internal detection circuit is oversensitive, the die may be overkilled; if it is undersensitive, the die may be underkilled. Overkill refers to misjudging a die that meets factory standards as one that does not. Underkill refers to misjudging a die that does not meet factory standards as one that does.

[0115] The calibration circuit in the memory provided in this application embodiment is described below. This calibration circuit can detect the detection sensitivity of the internal detection circuit, thereby calibrating the detection parameters of the internal detection circuit. These detection parameters may include: the floating duration of the memory's storage space (WL) when performing leakage current detection, or the discharge duration of the memory's storage space (WL) when performing resistance detection on the path containing the WL. Figure 8 As shown, the calibration circuit 117 includes: a resistor configuration circuit 01, a charging circuit 02, and a control circuit 03.

[0116] The resistor configuration circuit 01 is connected to the detection node P0 and the ground terminal GND in the calibration circuit 117. The resistor configuration circuit 01 forms a current path between the detection node P0 and the ground terminal GND, and the resistance value of this current path is a target resistance value. This target resistance value can be predetermined according to the requirements of the application scenario. If the resistance value of the resistor configuration circuit 01 is adjustable, the target resistance value is the resistance value achieved by adjusting the resistance value of the resistor configuration circuit 01 before calibrating the internal detection circuit. If the resistance value of the resistor configuration circuit 01 is fixed and cannot be adjusted, the target resistance value is the fixed resistance value of the resistor configuration circuit 01.

[0117] The charging circuit 02 is connected to the detection node P0. The charging circuit 02 is used to store electrical energy. In this embodiment, the capacitance value of the charging circuit 02 can be designed based on the capacitance value between two adjacent WLs in the memory 100. That is, the charging circuit 02 can be used to simulate the situation where electrical energy is stored in the WLs of the memory 100.

[0118] The control circuit 03 is connected to the word line driving circuit 114, the detection node P0, and the internal detection circuit 116, respectively. The control circuit 03 is used for:

[0119] The control word line drive circuit 114 charges or discharges the charging circuit 02;

[0120] Set the detection node P0 to a floating state and control the internal detection circuit 116 to detect the voltage of the detection node P0;

[0121] And to obtain the detection results output by the internal detection circuit 116.

[0122] The following explanation uses the floating time of WL during leakage current detection calibration as an example. The control circuit 03 first controls the word line drive circuit 114 to charge the charging circuit 02, so that the voltage of the detection node P0 reaches the target voltage. After the voltage of the detection node P0 reaches the target voltage, the control circuit 03 sets the detection node P0 to a floating state and controls the internal detection circuit 116 to detect the current value of the current path. Then, the control circuit 03 can obtain the target time taken for the internal detection circuit 116 to detect that the current value reaches the target current.

[0123] Understandably, the internal detection circuit 116 can detect the current value of the current path by detecting the voltage change of the detection node P0. The target current is the ratio of the target voltage to the target resistance. When the internal detection circuit 116 performs leakage current detection on WL in the memory 100, this target duration can be used to calibrate the floating duration of WL.

[0124] For example, when using the internal detection circuit 116 to detect whether the leakage current of WL in memory 100 reaches the target current, the floating duration of WL (i.e., the duration of the floating phase) can be set to the target duration. That is, the target duration is a trim value for the duration of the floating phase during the leakage current detection process.

[0125] In this embodiment, the target voltage can be equal to the voltage at which the WL is charged when the leakage current of the WL is detected (i.e., VPE as mentioned above). For example, the target voltage can be equal to 12V. The target current can be the maximum allowable leakage current of the WL in the memory. Furthermore, the magnitude of the target current can be flexibly configured according to different application scenarios. For example, the target current can be 200nA, 500nA, 1000nA, or 2000nA, etc. The target resistance value can be determined based on the target voltage and the target current, i.e., target resistance value = target voltage / target current.

[0126] Based on the above analysis, it can be seen that the calibration circuit 117 provided in this embodiment can simulate the situation when WL in the memory 100 is charged to the target voltage and then leaks current according to the target current. Correspondingly, the target time taken for the internal detection circuit 116 to detect the current value reaching the target current reflects the detection sensitivity of the internal detection circuit 116 to the leakage current. Using this target time to calibrate the floating time of WL when the internal detection circuit 116 performs leakage current detection on WL can effectively avoid the problem of inaccurate leakage current detection results due to differences in the detection sensitivity of the internal detection circuit itself.

[0127] It is understandable that, such as Figure 9 As shown, the memory 100 can integrate multiple internal detection circuits 116. The control circuit 03 in the calibration circuit 117 provided in this embodiment can be connected to each of the multiple internal detection circuits 116, and the calibration circuit 117 can calibrate the multiple internal detection circuits 116 sequentially. The calibration process of the calibration circuit 117 calibrating any one of the internal detection circuits 116 can be referred to the description above, and will not be repeated here.

[0128] Since the solution provided in this application embodiment can calibrate the multiple internal detection circuits 116 integrated in the memory 100 through a calibration circuit 117, it can effectively avoid increasing the size and structural complexity of the memory 100 and reduce the manufacturing cost of the memory 100.

[0129] As a first optional implementation, after setting the detection node P0 to a floating state, the control circuit 03 can control the internal detection circuit 116 to continuously detect the current value of the current path and monitor the detection flag output by the internal detection circuit 116 in real time. When the control circuit 03 detects that the detection flag changes from the first flag to the second flag, it can determine that the internal detection circuit 116 has detected that the current value of the current path has reached the target current. Furthermore, the control circuit 03 can determine the duration between the transition time of the detection flag and the start time of the detection node P0 being in the floating state as the target duration.

[0130] As a second optional implementation, the control circuit 03 can perform multiple charging-float operations, and can determine the target duration based on the detection flag output by the internal detection circuit 116 after each charging-float operation. Each charging-float operation includes a charging phase and a floating phase, and the duration of the floating phase in the multiple charging-float operations can be increased or decreased sequentially.

[0131] During the charging phase, control circuit 03 can control word line drive circuit 114 to charge charging circuit 02 so that the voltage of detection node P0 is the target voltage. During the floating phase, control circuit 03 can set detection node P0 to a floating state. After the floating phase ends, control circuit 03 can control internal detection circuit 116 to detect the current value of the current path once and obtain the detection mark output by internal detection circuit 116.

[0132] In this second implementation, the target duration obtained by the control circuit 03 can be the charging float operation that causes the internal detection circuit 116 to output the second mark and has the shortest float phase duration among the multiple charging float operations.

[0133] For example, control circuit 03 can initially perform the charging float operation with a shorter float phase. Then, as the number of charging float operations increases, control circuit 03 can gradually increase the duration of this float phase. Furthermore, control circuit 03 can determine the target duration as the float phase corresponding to the first output of the second mark by internal detection circuit 116 (i.e., when the output detection mark changes from the first mark to the second mark). This method of obtaining the target duration by adjusting the float phase duration can also be called the Shmoo test method.

[0134] Figure 10 This is a schematic diagram of another calibration circuit provided in an embodiment of this application. For example... Figure 10 As shown, the resistor configuration circuit 01 may include one or more resistors connected in parallel or series between the detection node P0 and the ground terminal GND. For example, Figure 10 The diagram shows three resistors, R1, R2, and R3, which are connected in series between the detection node P0 and the ground terminal GND.

[0135] It is understood that if the resistor configuration circuit 01 includes one resistor, the resistance value of that resistor can be equal to the target resistance value. If the resistor configuration circuit 01 includes multiple resistors, the resistance value of the multiple resistors connected in parallel or in series can be equal to the target resistance value. Furthermore, the resistance values ​​of the multiple resistors in the resistor configuration circuit 01 can be equal or unequal, and this application embodiment does not limit this.

[0136] Optionally, continue to refer to Figure 10 The resistor configuration circuit 01 may further include at least one first switch connected to at least one of the plurality of resistors. For example, Figure 10 The diagram shows three first switches: M1, M2, and M3.

[0137] The control circuit 03 ( Figure 10(Not shown) is connected to the control terminal of each first switch and is used to control the on / off state of the at least one first switch. Thus, the number of resistors among the plurality of resistors used to form a current path can be adjusted, thereby making the resistance value of the current path a target resistance value.

[0138] Since the resistor configuration circuit 01 has at least one first switch, the control circuit 03 can flexibly adjust the resistance value of the current path by controlling the on / off state of the at least one first switch. Furthermore, since adjusting the resistance value of the current path can flexibly adjust the leakage current flowing through the current path under the premise of a fixed target voltage, in this embodiment, for each target current, the calibration circuit 117 can obtain the target time taken for the internal detection circuit 116 to detect the leakage current reaching the target current. That is, the calibration circuit 117 can detect and calibrate the detection sensitivity of the internal detection circuit 116 to target currents of different magnitudes to meet the needs of different application scenarios.

[0139] For example, assuming the target voltage is 12V and the target currents to be detected are 500nA, 1000nA and 2000nA, the control circuit 03 in the calibration circuit 117 can set the target resistance values ​​of the current path between the detection node P0 and the ground terminal GND to 24 megohms (MΩ), 10MΩ and 6MΩ, respectively, by controlling the on / off state of the at least one first switch.

[0140] As shown in Table 1, when the target resistance in die D1 is 6MΩ, the calibration circuit 117 in die D1 can obtain the target time of 100µs for the internal detection circuit 116 to detect the target current of 2000nA. When the target resistance in die D1 is 10MΩ, the calibration circuit 117 in die D1 can obtain the target time of 120µs for the internal detection circuit 116 to detect the target current of 1000nA. When the target resistance in die D1 is 24MΩ, the calibration circuit 117 in die D1 can obtain the target time of 140µs for the internal detection circuit 116 to detect the target current of 500nA.

[0141] Table 1

[0142] nude film 2000nA 1000nA 500nA D1 (Oversensitive) 100us 120us 140us D2 (Normal) 160us 200us 240us D3 (Unstable) 240us 260us 280us

[0143] Table 1 also shows the detection sensitivity of the internal detection circuit 116 in dies D2 and D3 for different target currents. For example, the target time for the internal detection circuit 116 in die D2 to detect a target current of 2000nA is 160µs, while the target time for the internal detection circuit 116 in die D3 to detect a target current of 2000nA is 240µs. Based on Table 1, it can be seen that when the leakage current of the WL or current path in different dies is the same, the target time for the internal detection circuit 116 in different dies to detect this leakage current will have a significant difference, that is, the detection sensitivity of the internal detection circuit 116 in different dies will have a significant difference. For example, in Table 1, the detection sensitivity of the internal detection circuit 116 in die D1 is too high, the detection sensitivity of the internal detection circuit 116 in die D2 is normal, while the detection sensitivity of the internal detection circuit 116 in die D3 is too low.

[0144] In this embodiment, the calibration circuit 117 can obtain the target duration used by the internal detection circuit 116 to detect target currents of different magnitudes, and use this target duration to calibrate the floating phase duration when performing leakage current detection on WL. This effectively avoids the influence of the internal detection circuit's own detection sensitivity on the leakage current detection results, ensuring the reliability of the leakage current detection.

[0145] As an optional implementation method, such as Figure 10 As shown, multiple resistors in the resistor configuration circuit 01 can be connected in series between the detection node P0 and the ground terminal GND. In this implementation, the first and second terminals of each first switch can be connected in parallel with at least one of the multiple resistors, and are used to bypass the at least one resistor connected in parallel under the control of the control circuit 03. Accordingly, the resistors among the multiple resistors that are not bypassed can form a current path.

[0146] Example, reference Figure 10 The resistor configuration circuit 01 includes a number of first switches that can be the same as the number of resistors. The first terminal of each first switch is connected to one end of a resistor, and the second terminal of each first switch is connected to ground (GND). For example... Figure 10 In the circuit, the two ends of the first switch M1 are connected in parallel with resistors R1, R2 and R3, the two ends of the first switch M2 are connected in parallel with resistors R2 and R3, and the two ends of the first switch M3 are connected in parallel with resistor R3.

[0147] When control circuit 03 controls the first switch M1 to be on and controls the first switches M2 and M3 to be off, resistors R1, R2, and R3 are all bypassed, and the current path is formed by the on-state first switch M1. When control circuit 03 controls the first switch M2 to be on and controls the first switches M1 and M3 to be off, resistors R2 and R3 are bypassed, and the current path is formed by resistor R1. When control circuit 03 controls the first switch M3 to be on and controls the first switches M1 and M2 to be off, resistor R3 is bypassed, and the current path is formed by resistors R1 and R2 connected in series.

[0148] It is understood that in this implementation, the number of first switches included in the resistor configuration circuit 01 can be less than the number of resistors, and the number of resistors connected in parallel across different first switches can be the same or different. For example, refer to... Figure 11 The resistor configuration circuit 01 may include two first switches, M2 and M3, and each first switch is connected in parallel with a resistor across its two ends.

[0149] As another alternative implementation, such as Figure 12 As shown, the multiple resistors in the resistor configuration circuit 01 can be connected in parallel between the detection node P0 and the ground terminal GND. In this implementation, the first terminal of each first switch is connected to one end of one of the multiple resistors, and the second terminal is connected to either the detection node P0 or the ground terminal GND. Each first switch is used to disconnect one of the resistors it is connected to under the control of the control circuit 03. Accordingly, the resistors that are not disconnected can form a current path.

[0150] Example, reference Figure 12 The resistor configuration circuit 01 includes a number of first switches that can be the same as the number of resistors. The first terminal of each first switch is connected to one end of a resistor, and the second terminal of each first switch is connected to ground (GND). For example... Figure 12 The resistor configuration circuit 01 shown includes three first switches, M1 to M3. The first end of the first switch M1 is connected to one end of the resistor R1, the first end of the first switch M2 is connected to one end of the resistor R2, and the first end of the first switch M3 is connected to one end of the resistor R3.

[0151] When control circuit 03 controls the first switch M1 to be closed and controls the first switches M2 and M3 to be open, resistor R1 is disconnected, and a current path is formed by the parallel resistors R2 and R3. When control circuit 03 controls the first switches M1 and M2 to be closed and controls the first switch M3 to be open, resistors R1 and R2 are disconnected, and a current path is formed by resistor R3.

[0152] It is understood that in this implementation, the number of first switches included in the resistor configuration circuit 01 may also be less than the number of resistors, and this application embodiment does not limit this.

[0153] Optionally, each first switch included in the resistor configuration circuit 01 can be a transistor, such as a MOSFET. Furthermore, the transistor can be either N-type or P-type. Correspondingly, the control terminal of the first switch can be the gate of the transistor, the first terminal of the first switch can be one of the source and drain of the transistor, and the second terminal of the first switch can be the other of the source and drain. For example, the first terminal of the first switch can be the drain of the transistor, and the second terminal can be the source of the transistor.

[0154] Optionally, refer to Figure 9 and Figure 10 The calibration circuit 117 may further include a current detection circuit 04. The current detection circuit 04 is connected to the detection node P0 and the control circuit 03 respectively. The current detection circuit 04 is used to apply a target voltage to the detection node P0 and detect the current in the current path.

[0155] The control circuit 03 can also be used to adjust the resistance value of the resistor configuration circuit 01 based on the current detected by the current detection circuit 04. For example, the control circuit 03 can adjust the on / off state of at least one first switch in the resistor configuration circuit 01 so that the resistance value of the current path is a target resistance value.

[0156] Since the control circuit 03 can accurately adjust the on / off state of the at least one first switch based on the current detected by the current detection circuit 04, the resistance value of the current path can be accurately calibrated.

[0157] Continue to refer to Figure 9 and Figure 10 The calibration circuit 117 may further include a switching circuit 05. The switching circuit 05 is connected to the current detection circuit 04, the detection node P0, and the resistor configuration circuit 01, respectively. The switching circuit 05 can be used to adjust the on / off state of the current detection circuit 04 and the resistor configuration circuit 01, and to adjust the on / off state of the resistor configuration circuit 01 and the detection node P0, under the control of the control circuit 03.

[0158] In this embodiment, the control circuit 03 can be used to: control the switching circuit 05 to connect the current detection circuit 04 to the resistor configuration circuit 01 and disconnect the resistor configuration circuit 01 from the detection node P0 before the current detection circuit 04 applies the target voltage to the detection node P0.

[0159] After the switching circuit 05 turns on the current detection circuit 04 and the resistor configuration circuit 01, the current detection circuit 04 can apply the target voltage to the resistor configuration circuit 01 and detect the current in the current path formed by the resistor configuration circuit 05. Since the connection between the resistor configuration circuit 01 and the detection node P0 is broken at this time, the charging circuit 02 can be prevented from affecting the current detection result of the current detection circuit 04.

[0160] The control circuit 03 can also be used to: control the switch circuit 05 to disconnect the current detection circuit 04 from the resistor configuration circuit 01 and connect the resistor configuration circuit 01 to the detection node P0 before the word line drive circuit 114 charges the charging circuit 02.

[0161] By connecting the resistor configuration circuit 01 to the detection node P0 and disconnecting it from the current detection circuit 04, the switching circuit 05 prevents the current detection circuit 04 from affecting the charging effect of the word line drive circuit 114 on the charging circuit 02. This ensures that the charging circuit 02 and the resistor configuration circuit 01 can simulate the actual charging state of WL in the memory 100, thereby ensuring the reliability of the subsequently obtained target duration.

[0162] Optionally, such as Figure 10 As shown, the switching circuit 05 may include: a second switch SW12 and a third switch SW13. The control terminal of the second switch SW12 ( Figure 10 (Not shown in the diagram) is connected to the control circuit 03. The first end of the second switch SW12 is connected to the current detection circuit 04. The second end of the second switch SW12 is connected to one end of the resistor configuration circuit 01 used to connect to the detection node P0.

[0163] The control terminal of the third switch SW13 ( Figure 10 (Not shown in the diagram) is connected to the control circuit 03. The first end of the third switch SW13 is connected to one end of the resistor configuration circuit 01 used to connect to the detection node P0. The second end of the third switch SW13 is connected to the detection node P0.

[0164] When calibrating the resistance value of the current path formed by the resistor configuration circuit 01, the control circuit 03 can control the two ends of the second switch SW12 to be turned on and the two ends of the third switch SW13 to be turned off. This prevents the charging circuit 03 from affecting the calibration accuracy of the resistance value. During the charging of the charging circuit 02 and the detection of leakage current in the current path, the control circuit 03 can control the two ends of the second switch SW12 to be turned off and the two ends of the third switch SW13 to be turned on. This prevents the current detection circuit 04 from affecting the charging and leakage detection processes.

[0165] Optionally, the charging circuit 02 may include a capacitor bank, which may include one or more capacitors. For example, such as Figure 10 As shown, the capacitor bank includes capacitor C10, one end of which is connected to the detection node P0, and the other end of which is connected to the ground terminal GND.

[0166] In this embodiment, the capacitance value of the capacitor bank (e.g., capacitor C10) can be designed based on the capacitance values ​​between adjacent WLs in the memory 100 to ensure accurate simulation of the actual energy storage state of the WLs in the memory 100. For example, assuming the capacitor bank includes capacitor C10, this capacitor C10 can be formed by two adjacent, non-leaking WLs in the memory 100. For instance, two WLs in the memory 100 can be led out from the storage array 120 to the area where the calibration circuit 117 is located to form capacitor C10. Alternatively, the capacitors in the capacitor bank can be capacitors set independently of each WL.

[0167] Optionally, such as Figure 9 As shown, the control circuit 03 may include a switch sub-circuit 031 and a control sub-circuit 032. The switch sub-circuit 031 is connected to the word line driving circuit 114, the detection node P0, the input terminal of the internal detection circuit 116, and the control sub-circuit 032, respectively. Under the control of the control sub-circuit 032, the switch sub-circuit 031 can control the on / off state between the word line driving circuit 114 and the detection node P0, as well as the on / off state between the detection node P0 and the input terminal of the internal detection circuit 116.

[0168] The control sub-circuit 032 is also connected to the output terminal of the internal detection circuit 116 and can acquire the detection result output by the internal detection circuit 116. For example, the control sub-circuit 032 can be used for:

[0169] The control switch sub-circuit 031 connects the word line driving circuit 114 to the detection node P0, so that the word line driving circuit 114 charges the charging circuit 02.

[0170] After the voltage of the detection node P0 reaches the target voltage, the control switch sub-circuit 031 disconnects the word line drive circuit 114 from the detection node P0 so that the detection node P0 is in a floating state, and the control switch sub-circuit 031 connects the detection node P0 to the input terminal of the internal detection circuit 116 so that the internal detection circuit 116 detects the current value of the current path.

[0171] In addition, the internal detection circuit 116 obtains the target time for the current value to reach the target current.

[0172] It is understood that the control sub-circuit 032 can also be connected to the control terminals of each switch in the switch circuit 05 and the resistor configuration circuit 01, and used to control the on / off state of each switch. Furthermore, the control sub-circuit 032 can reuse a circuit module from the control logic circuit 115, meaning the control sub-circuit 032 can be integrated into the control logic circuit 115. Alternatively, the control sub-circuit 032 can be set independently of the control logic circuit 115; for example, the control sub-circuit 032 can be a separate integrated circuit (IC).

[0173] Optionally, such as Figure 10 As shown, the switch sub-circuit 031 may include: a fourth switch SW14 and a fifth switch SW15. The control terminal of the fourth switch SW14 ( Figure 10 (Not shown in the diagram) is connected to the control sub-circuit 032. The first end of the fourth switch SW14 is connected to the word line drive circuit 114, and the second end of the fourth switch SW14 is connected to the detection node P0.

[0174] The control terminal of the fifth switch SW15 ( Figure 10 (Not shown in the diagram) is connected to the control sub-circuit 032. The first end of the fifth switch SW15 is connected to the detection node P0, and the second end of the fifth switch SW15 is connected to the input end of the internal detection circuit 116.

[0175] When the word line driving circuit 114 charges the charging circuit 02, the control sub-circuit 032 can control the two ends of the fourth switch SW14 to be turned on and the two ends of the fifth switch SW15 to be turned off to ensure the reliability of charging. After the charging circuit 02 has finished charging, the control sub-circuit 032 can control the two ends of the fourth switch SW14 to be turned off and the two ends of the fifth switch SW15 to be turned on, so that the internal detection circuit 116 can detect the leakage current in the current path.

[0176] Optionally, such as Figure 10 As shown, the switch sub-circuit 031 may further include: a sixth switch SW16. The control terminal of the sixth switch SW16 ( Figure 10 (Not shown in the diagram) is connected to the control sub-circuit 032. The first end of the sixth switch SW16 is connected to the word line drive circuit 114, and the second end of the sixth switch SW16 is connected to the input end of the internal detection circuit 116.

[0177] The control sub-circuit 032 can also be used to: control the sixth switch SW16 to be turned off when the fourth switch SW14 or the fifth switch SW15 is turned on, and control the sixth switch SW16 to be turned on and the fourth switch SW14 and the fifth switch SW15 to be turned off after the target duration is obtained.

[0178] It is understandable that the stage when control subcircuit 032 controls the fourth switch SW14 to conduct is the stage when word line drive circuit 114 charges charging circuit 02. The stage when control subcircuit 032 controls the fifth switch SW15 to conduct is the stage when internal detection circuit 116 detects leakage current in the current path. Disconnecting the sixth switch SW16 during the above two stages can avoid interference with charging and leakage current detection.

[0179] After acquiring the target duration, the control sub-circuit 032 can control the sixth switch SW16 to be turned on, so that the internal detection circuit 116 can detect the leakage current status of WL in the memory 100 based on the target duration. During this detection process, the control sub-circuit 032 needs to control the fourth switch SW14 and the fifth switch SW15 to be turned off to avoid interfering with the leakage current detection process of WL.

[0180] Optionally, continue to refer to Figure 10 The switch sub-circuit 031 may further include a seventh switch SW17. The first terminal of the seventh switch SW17 is connected to the second terminal of the fourth switch SW14 and the first terminal of the fifth switch SW15, respectively, and the second terminal of the seventh switch SW17 is connected to the detection node P0. Correspondingly, the second terminal of the fourth switch SW14 and the first terminal of the fifth switch SW15 are both connected to the detection node P0 through the seventh switch SW17.

[0181] The control terminal of the seventh switch SW17 is connected to the control sub-circuit 032. Figure 10 (Not shown) The control sub-circuit 032 can also be used to: control the two ends of the seventh switch SW17 to be turned on during the charging process of the charging circuit 02 and during the process of the internal detection circuit 116 detecting the current value of the current path, and control the two ends of the seventh switch SW17 to be turned off during the process of calibrating the resistance value of the current path.

[0182] It is understood that the second switch SW12 to the seventh switch SW17 can all be transistors, such as MOSFETs. The transistor can be N-type or P-type. Furthermore, the control terminal of each switch can be the gate of the transistor, the first terminal can be one of the source and drain terminals of the transistor, and the second terminal can be the other of the source and drain terminals.

[0183] It is also understood that each of the aforementioned second switches SW12 to seventh switches SW17 can be a single switch or can include multiple switches, such as multiple transistors. This application embodiment does not limit the implementation method of each switch.

[0184] The above description uses the internal detection circuit 116 to detect the leakage current of WL and the calibration circuit 117 to calibrate the floating time of WL as an example. It can be understood that the internal detection circuit 116 can also be used to detect the resistance value of the path where WL is located. Correspondingly, the calibration circuit 117 provided in this application embodiment can also be used to calibrate the discharge time of WL when the internal detection circuit 116 detects the resistance of the path where WL is located.

[0185] In the scenario of calibrating the discharge duration of WL, the control circuit 03 in the calibration circuit 117 can be used to: perform multiple charge-discharge operations, and determine the target duration based on the detection result of the resistance value of the current path by the internal detection circuit 116 after each charge-discharge operation. Each charge-discharge operation includes:

[0186] The control word line drive circuit 114 charges the charging circuit 02 to charge the voltage of the detection node P0 to the target voltage.

[0187] During the discharge period after the charging circuit 02 has finished charging, the word line driving circuit 114 is controlled to discharge the charging circuit 02.

[0188] Set the detection node P0 to a floating state and control the internal detection circuit 116 to detect the resistance value of the current path.

[0189] The internal detection circuit 116 can detect the resistance value of the current path by detecting the voltage of the detection node P0. The discharge duration in the multiple charge-discharge operations increases or decreases sequentially, and the target duration obtained by the control circuit 03 can refer to the discharge duration of a single charge-discharge operation that causes a jump in the detection result output by the internal detection circuit 116 (e.g., from the first mark to the second mark). This target duration is used to calibrate the discharge duration of WL when the internal detection circuit 116 performs resistance detection on the path containing WL in the memory 100. For example, when using the internal detection circuit 116 for resistance detection, the discharge duration of WL can be set to this target duration. That is, the target duration is a correction value for the duration of the discharge phase during the resistance detection process.

[0190] In this embodiment, if the internal detection circuit 116 is used to detect HR, the target resistance value can be the maximum resistance value allowed in the path where WL is located. Furthermore, when the detection result output by the internal detection circuit 116 is a first marker, it indicates that it has detected a resistance value in the current path that is greater than the target resistance value. The target duration can also be understood as the discharge duration in the longest charge-discharge operation that enables the internal detection circuit 116 to output the first marker.

[0191] If the internal detection circuit 116 is used to detect LR, the target resistance value can be the minimum resistance value allowed by the path where WL is located in the memory. Furthermore, when the internal detection circuit 116 outputs the second mark, it indicates that it has detected a resistance value in the current path that is less than the target resistance value. The target duration can also be understood as the discharge duration in a single charge-discharge operation that enables the internal detection circuit 116 to output the second mark and has the shortest discharge duration.

[0192] It is understood that the charging circuit 02 and the resistor configuration circuit 01 can form an RC oscillation circuit, which can simulate the RC delay of the path containing WL after WL is charged to the target voltage. Furthermore, the discharge rate of this RC oscillation circuit is related to the resistance value of the resistor configuration circuit 01. Therefore, the target duration obtained by the control circuit 03 reflects the detection sensitivity of the internal detection circuit 116 to the resistance of the path containing WL. Using this target duration to calibrate the internal detection circuit 116's resistance detection of the path containing WL effectively avoids inaccurate resistance detection results due to differences in the detection sensitivity of the internal detection circuit itself.

[0193] The following text is incomplete and cannot be translated. Figure 9 and Figure 10 Taking the calibration circuit shown as an example, each charge / discharge operation performed by the control circuit 03 will be explained. First, the control sub-circuit 032 in the control circuit 03 can control the switch sub-circuit 031 to turn on the word line drive circuit 114 and the detection stage P0, so that the word line drive circuit 114 charges the charging circuit 02. For example, the word line drive circuit 114 can apply a target voltage to the charging circuit 02 so that the voltage of the detection node P0 reaches the target voltage.

[0194] Subsequently, the control sub-circuit 032 can control the word line drive circuit 114 to apply a low voltage VSS to the charging circuit 02. For example, the word line drive circuit 114 can switch the voltage source used to apply voltage to the charging circuit 02 from VPE to VSS, so that the charging circuit 02 discharges. During the discharge of the charging circuit 02, the voltage of the detection node P0 gradually decreases, and the rate of decrease of the voltage of the detection node P0 is related to the discharge rate of the charging circuit 02. The discharge rate of the charging circuit 02 is related not only to its own capacitance value but also to the resistance value of the resistor configuration circuit 01.

[0195] After the discharge time of the charging circuit 02 reaches the set discharge time, the control sub-circuit 032 can control the switching sub-circuit 031 to disconnect the word line driving circuit 114 from the detection node P0, so that the detection node P0 is in a floating state. Furthermore, the control sub-circuit 032 can also control the switching sub-circuit 031 to connect the detection node P0 to the input terminal of the internal detection circuit 116, so that the internal detection circuit 116 can perform a detection of the resistance value of the current path. Afterwards, the control sub-circuit 032 can obtain the detection result output by the internal detection circuit 116 and determine the target duration based on the detection result.

[0196] For example, during the execution of the above multiple charge-discharge operations, the control sub-circuit 032 can initially use a shorter discharge duration to perform the charge-discharge operation. Subsequently, as the number of charge-discharge operations increases, the control sub-circuit 032 can gradually increase the discharge duration. Furthermore, the control sub-circuit 032 can determine the discharge duration corresponding to the first output of the second mark by the internal detection circuit 116 as the target duration.

[0197] Optionally, such as Figure 10 As shown, the resistor configuration circuit 01 includes multiple resistors and at least one first switch. The control circuit 03 can also adjust the resistance value of the current path formed by the resistor configuration circuit 01 by controlling the on / off state of the at least one first switch. Therefore, for target resistors of different sizes, the control circuit 03 can obtain the target time required for the internal detection circuit 116 to detect that the resistance value reaches the target resistance. That is, the calibration circuit 117 can detect and calibrate the detection sensitivity of the internal detection circuit 116 for target resistors of different sizes to meet the needs of different application scenarios.

[0198] Based on the above analysis, it can be seen that the calibration circuit provided in this application embodiment can not only calibrate the floating time of WL during leakage current detection, but also calibrate the discharge time of WL during resistance detection. This calibration circuit is feature-rich and highly flexible in use.

[0199] Optionally, such as Figure 2 As shown, the calibration circuit 117 provided in this embodiment can be integrated into the memory 100.

[0200] In summary, this application provides a memory including an internal detection circuit and a calibration circuit. The control circuit in the calibration circuit can control the word line driving circuit to charge or discharge the charging circuit, and can form a current path between the charging circuit and the ground terminal through a resistor configuration circuit to simulate the voltage change process on the word lines in the memory. During the simulation of voltage changes, the control circuit can also acquire the detection results obtained by the internal detection circuit detecting the voltage of the detection node. Since this detection result reflects the detection sensitivity of the internal detection circuit to the voltage of the detection node, the detection parameters of the internal detection circuit when detecting the word lines in the memory (e.g., the floating time of WL during leakage current detection, or the discharge time of WL during resistance detection) can be calibrated based on this detection result. Therefore, the problem of inaccurate detection results due to differences in the detection sensitivity of the internal detection circuit itself can be effectively avoided.

[0201] This application also provides another calibration circuit, such as... Figure 8 , Figure 9 and Figure 13 As shown, the calibration circuit 117 includes: a resistor configuration circuit 01, a charging circuit 02, and a control circuit 03.

[0202] The resistor configuration circuit 01 is connected to the detection node P0 and the ground terminal GND in the calibration circuit 117. The resistor configuration circuit 01 is used to form a current path between the detection node P0 and the ground terminal GND, and the resistance value of the current path is the target resistance value.

[0203] The charging circuit 02 is connected to the detection node P0 and is used to store electrical energy.

[0204] The control circuit 03 is connected to the word line driving circuit 114, the detection node P0 and the internal detection circuit 116 in the memory 100 respectively. The control circuit 03 is used to control the on / off state between the word line driving circuit 114 and the detection node P0, and to control the on / off state between the detection node P0 and the internal detection circuit 116.

[0205] Specifically, after the word line driving circuit 114 is turned on with the detection node P0, the word line driving circuit 114 can charge or discharge the charging circuit 02. After the detection node P0 is turned on with the internal detection circuit 116, the internal detection circuit 116 can detect the current or resistance value of the current path.

[0206] This application also provides a calibration system for an internal detection circuit. (See reference...) Figure 13 The calibration system includes: a monitoring circuit 130, and such as Figure 13 The calibration circuit 117 is shown.

[0207] The monitoring circuit 130 is connected to the output of the internal detection circuit 116. As a first possible example, the monitoring circuit 130 can be used to: acquire the target duration taken by the internal detection circuit 116 to detect that the current value in the current path of the calibration circuit 117 reaches the target current. This target duration can be used to calibrate the floating duration of WL when the internal detection circuit 116 performs leakage current detection on WL.

[0208] As a second possible example, the monitoring circuit 130 can be used to obtain a target duration based on the resistance detection results of the internal detection circuit 116 after multiple charge-discharge operations. This target duration is the discharge duration of one charge-discharge operation that causes a jump in the detection result output by the internal detection circuit 116. Furthermore, this target duration can be used to calibrate the discharge duration of WL when the internal detection circuit 116 performs resistance detection on WL.

[0209] The specific process by which the monitoring circuit 130 acquires the target duration can be referred to the relevant descriptions in the foregoing embodiments, and will not be repeated here.

[0210] Optionally, such as Figure 13 As shown, the calibration system may further include a current detection circuit 04, which is used to detect the current in the current path of the calibration circuit 117 so that the control circuit 03 in the calibration circuit 117 can calibrate the resistance value of the current path to the target resistance value based on the detected circuit.

[0211] In this embodiment, the calibration circuit 117 in the calibration system can be integrated into the memory 100, while the monitoring circuit 130 and the current detection circuit 04 can be set independently of the memory 100. For example, the monitoring circuit 130 and the current detection circuit 04 can be integrated into the test base of the memory 100.

[0212] Understandable Figure 13 The calibration circuit 117 shown is compared to Figures 8 to 10 The difference in the calibration circuit 117 shown is: Figure 13 The control circuit 03 in the calibration circuit 117 shown does not need to be connected to the output of the internal detection circuit 116, nor does it need to obtain the target duration for calibrating the internal detection circuit 116. This target duration can be obtained by the monitoring circuit 130 external to the memory 100. Furthermore, the resistance of the resistor configuration circuit 01 in the calibration circuit 117 can also be detected and calibrated by the external current detection circuit 04. The calibration circuit 117 only needs to have pre-reserved detection pins for connection to the external monitoring circuit 130 and current detection circuit 04.

[0213] This application also provides a calibration method for an internal detection circuit, which can be used to calibrate the internal detection circuit in the memory provided in the above embodiments. For example... Figure 14 As shown, the method includes:

[0214] Step 201: Charge the charging circuit in the calibration circuit so that the voltage of the detection node in the calibration circuit is the target voltage.

[0215] The control circuit in the calibration circuit can connect the word line drive circuit to the detection node, so that the word line drive circuit can charge the charging circuit.

[0216] Step 202: Set the detection node to a floating state and control the internal detection circuit to detect the current value of the current path in the calibration circuit.

[0217] After the voltage of the detection node is charged to the target voltage by the charging circuit, the control circuit can disconnect the word line drive circuit from the detection node, so that the detection node is in a floating state. Furthermore, the control circuit can connect the detection node to the input terminal of the internal detection circuit, allowing the internal detection circuit to detect the current value of the current path in the calibration circuit by detecting the voltage of the detection node. This current path is formed by the resistor configuration circuit in the calibration circuit, and the resistance value of this current path is the target resistance value.

[0218] Step 203: Obtain the target time taken for the internal detection circuit to detect that the current value has reached the target current.

[0219] During the current detection process of the internal detection circuit, the control circuit in the calibration circuit, or the monitoring circuit in the calibration system, can monitor the output of the internal detection circuit to obtain the target time for the internal detection circuit to detect that the current value has reached the target current. For example, the control circuit or monitoring circuit can determine that the internal detection circuit has detected that the current value has reached the target current when it detects that the detection flag output by the internal detection circuit changes from the first flag to the second flag.

[0220] The target current is equal to the ratio of the target voltage to the target resistance. The target duration is used to calibrate the floating duration of WL in the memory when the internal detection circuit performs leakage current detection on WL.

[0221] Optionally, after step 203 above, the method may further include:

[0222] When the internal detection circuit performs leakage current detection on the WL in the memory, it controls the floating time of the WL to the target time.

[0223] This application also provides another calibration method for an internal detection circuit, which can be applied to the calibration circuit provided in the above embodiments. For example... Figure 15 As shown, the method includes:

[0224] Step 301: Charge the charging circuit in the calibration circuit.

[0225] The control circuit in the calibration circuit can connect the word line drive circuit to the detection node, so that the word line drive circuit can charge the charging circuit.

[0226] Step 302: During the discharge time after the charging circuit has finished charging, control the charging circuit to discharge.

[0227] The control circuit in the calibration circuit can control the word line drive circuit to apply a low voltage VSS to the charging circuit so that the charging circuit can discharge.

[0228] Step 303: Set the detection node to a floating state and control the internal detection circuit to detect the resistance value of the current path in the calibration circuit.

[0229] After the charging circuit has discharged for a preset duration, the control circuit can disconnect the word line drive circuit from the detection node, placing the detection node in a floating state. Furthermore, the control circuit can connect the detection node to the input of the internal detection circuit, allowing the internal detection circuit to detect the resistance value of the current path in the calibration circuit by detecting the voltage at the detection node. This current path is formed by the resistor configuration circuit in the calibration circuit, and its resistance value is the target resistance value.

[0230] Steps 301 to 303 described above can be referred to as a single charge-discharge operation. In the embodiments of this application, such as... Figure 15 As shown, the calibration circuit can repeatedly perform multiple charge-discharge operations, and the discharge duration in each of these multiple charge-discharge operations increases or decreases sequentially.

[0231] Step 304: Determine the target duration based on the detection results of the resistance value of the current path by the internal detection circuit after each charge and discharge operation.

[0232] In this embodiment, the calibration circuit can determine the target duration based on the detection results obtained from the internal detection circuit after multiple charge-discharge operations. Optionally, the calibration circuit can determine the discharge duration of one charge-discharge operation that causes a jump in the detection result output by the internal detection circuit as the target duration. This target duration can be used to calibrate the discharge duration of WL when the internal detection circuit performs resistance detection on WL in the memory. Accordingly, after step 304 above, the method may further include:

[0233] When the internal detection circuit performs resistance detection on WL in the memory, it controls the discharge duration of WL to the target duration.

[0234] Optionally, before step 201 or step 301 above, the method may further include:

[0235] Step S0: Adjust the resistance value of the current path to the target resistance value.

[0236] In this embodiment, the control circuit can control the on / off state of at least one first switch in the resistor configuration circuit, thereby adjusting the number of resistors in the resistor configuration circuit used to form a current path so that the resistance value of the current path is the target resistance value.

[0237] Optionally, in step S0 above, a target voltage can be applied to the detection node through a current detection circuit, and the current in the current path can be detected. Then, the control circuit can adjust the resistance value of the current path based on the current detected by the current detection circuit until the current in the current path reaches the target current. This allows for precise adjustment of the resistance value of the current path.

[0238] It is understood that the implementation process of the calibration method for the internal detection circuit provided in the embodiments of this application can refer to the relevant description in the above memory embodiments, and will not be repeated here.

[0239] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" means one or more, and the term "multiple" means two or more, unless otherwise expressly defined.

[0240] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. The scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory (100), characterized in that, The memory (100) includes: a word line driving circuit (114), an internal detection circuit (116), and a calibration circuit (117). The calibration circuit (117) includes: a resistor configuration circuit (01), a charging circuit (02), and a control circuit (03). The resistor configuration circuit (01) is connected to the detection node (P0) and the ground terminal (GND) in the calibration circuit (117) respectively, and is used to form a current path between the detection node (P0) and the ground terminal (GND), wherein the resistance value of the current path is the target resistance value. The charging circuit (02) is connected to the detection node (P0); The control circuit (03) is connected to the word line driving circuit (114), the detection node (P0), and the internal detection circuit (116) respectively, and is used for: The word line driving circuit (114) is controlled to charge or discharge the charging circuit (02); Set the detection node (P0) to a floating state and control the internal detection circuit (116) to detect the voltage of the detection node (P0); In addition, the detection result output by the internal detection circuit (116) is obtained.

2. The memory (100) according to claim 1, characterized in that, The resistor configuration circuit (01) includes: one resistor or multiple resistors (R1, R2, R3); The multiple resistors (R1, R2, R3) are connected in series or in parallel between the detection node (P0) and the ground terminal (GND).

3. The memory (100) according to claim 2, characterized in that, The resistor configuration circuit (01) further includes at least one first switch (M1, M2, M3) connected to at least one of the plurality of resistors (R1, R2, R3); The control circuit (03) is also used to control the on / off state of the at least one first switch (M1, M2, M3) to adjust the number of resistors used to form the current path so that the resistance value of the current path is the target resistance value.

4. The memory (100) according to claim 3, characterized in that, If the plurality of resistors (R1, R2, R3) are connected in series between the detection node (P0) and the ground terminal (GND), then the two ends of each first switch are connected in parallel with at least one of the plurality of resistors (R1, R2, R3). If the plurality of resistors (R1, R2, R3) are connected in parallel between the detection node (P0) and the ground terminal (GND), then one end of each first switch is connected to one end of a resistor, and the other end of each first switch is connected to either the detection node (P0) or the ground terminal (GND).

5. The memory (100) according to claim 1, characterized in that, The calibration circuit (117) further includes: a current detection circuit (04); The current detection circuit (04) is connected to the detection node (P0). The current detection circuit (04) is used to apply a target voltage to the detection node (P0) and detect the current in the current path. The control circuit (03) is also connected to the current detection circuit (04), and the control circuit (03) is used to adjust the resistance value of the resistor configuration circuit (01) according to the current detected by the current detection circuit (04).

6. The memory (100) according to claim 5, characterized in that, The calibration circuit (117) further includes a switching circuit (05), which is connected to the current detection circuit (04), the resistor configuration circuit (01) and the detection node (P0) respectively. The switching circuit (05) is used to adjust the on / off state of the current detection circuit (04) and the resistor configuration circuit (01) and the on / off state of the resistor configuration circuit (01) and the detection node (P0) under the control of the control circuit (03).

7. The memory (100) according to claim 6, characterized in that, The switching circuit (05) includes: a second switch (SW12) and a third switch (SW13); The control terminal of the second switch (SW12) is connected to the control circuit (03), the first terminal of the second switch (SW12) is connected to the current detection circuit (04), and the second terminal of the second switch (SW12) is connected to the resistor configuration circuit (01). The control terminal of the third switch (SW13) is connected to the control circuit (03), the first terminal of the third switch (SW13) is connected to the resistor configuration circuit (01), and the second terminal of the third switch (SW13) is connected to the detection node (P0).

8. The memory (100) according to any one of claims 1 to 7, characterized in that, The charging circuit (02) includes a capacitor (C10), one end of which is connected to the detection node (P0), and the other end of which is connected to the ground terminal (GND).

9. The memory (100) according to any one of claims 1 to 7, characterized in that, The control circuit (03) includes: a switching sub-circuit (031) and a control sub-circuit (032); The switch sub-circuit (031) is connected to the input terminals of the word line driving circuit (114), the detection node (P0), the internal detection circuit (116), and the control sub-circuit (032), respectively; The control sub-circuit (032) is also connected to the output terminal of the internal detection circuit (116), and the control sub-circuit (032) is used for: Control the on / off state of the switch sub-circuit (031) so that the switch sub-circuit (031) adjusts the on / off state of the word line driving circuit (114) and the detection node (P0), and adjusts the on / off state of the detection node (P0) and the input terminal of the internal detection circuit (116); In addition, the detection result output by the output terminal of the internal detection circuit (116) is obtained.

10. The memory (100) according to claim 9, characterized in that, The switching sub-circuit (031) includes: a fourth switch (SW14) and a fifth switch (SW15); The control terminal of the fourth switch (SW14) is connected to the control sub-circuit (032), the first terminal of the fourth switch (SW14) is connected to the word line driving circuit (114), and the second terminal of the fourth switch (SW14) is connected to the detection node (P0). The control terminal of the fifth switch (SW15) is connected to the control sub-circuit (032), the first terminal of the fifth switch (SW15) is connected to the detection node (P0), and the second terminal of the fifth switch (SW15) is connected to the input terminal of the internal detection circuit (116).

11. The memory (100) according to claim 10, characterized in that, The switching sub-circuit (031) also includes: a sixth switch (SW16); The control terminal of the sixth switch (SW16) is connected to the control sub-circuit (032), the first terminal of the sixth switch (SW16) is connected to the word line driving circuit (114), and the second terminal of the sixth switch (SW16) is connected to the input terminal of the internal detection circuit (116).

12. A calibration method for an internal detection circuit, characterized in that, The method for calibrating an internal detection circuit in a memory as described in any one of claims 1 to 11 includes: The charging circuit in the calibration circuit is charged so that the voltage of the detection node in the calibration circuit is the target voltage; The detection node is set to a floating state, and the internal detection circuit is controlled to detect the current value of the current path in the calibration circuit, wherein the resistance value of the current path is the target resistance value. The target time taken for the internal detection circuit to detect that the current value reaches the target current is obtained, where the target current is the ratio of the target voltage to the target resistance.

13. The method according to claim 12, characterized in that, The method further includes: When the internal detection circuit performs leakage current detection on the word lines in the memory, it controls the floating duration of the word lines to the target duration.

14. The method according to claim 12, characterized in that, Before charging the charging circuit in the calibration circuit, the method further includes: Adjust the resistance value of the current path to the target resistance value.

15. The method according to claim 14, characterized in that, Adjusting the resistance value of the current path to the target resistance value includes: After applying the target voltage to the detection node, the resistance value of the current path is adjusted according to the detected current value of the current path until the current value of the current path is the target current.

16. A calibration method for an internal detection circuit, characterized in that, The method for calibrating an internal detection circuit in a memory as described in any one of claims 1 to 11 includes: Perform multiple charge-discharge operations; The target duration is determined based on the resistance value of the current path in the calibration circuit detected by the internal detection circuit after each charge / discharge operation; wherein each charge / discharge operation includes: Charge the charging circuit in the calibration circuit; During the discharge duration after the charging circuit has completed charging, the charging circuit is controlled to discharge; wherein the discharge duration in the multiple charge and discharge operations increases or decreases sequentially. The detection node is set to a floating state, and the internal detection circuit is controlled to detect the resistance value of the current path.

17. The method according to claim 16, characterized in that, The determination of the target duration based on the detection results of the resistance value of the current path in the calibration circuit by the internal detection circuit after each charge and discharge operation includes: The discharge duration of the charge-discharge operation that causes a jump in the detection result output by the internal detection circuit during the multiple charge-discharge operations is determined as the target duration.

18. The method according to claim 16, characterized in that, The method further includes: When the internal detection circuit performs resistance detection on the word lines in the memory, it controls the discharge duration of the word lines to the target duration.

19. A storage system (10), characterized in that, The storage system (10) includes: a memory controller (101), and at least one memory (100) as described in any one of claims 1 to 11.

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