Chip interconnection component and preparation method thereof

Abstract

The present invention provides a chip interconnection component and a preparation method thereof. The interconnection component includes: a first solder joint having an accommodating space, arranged between the first conductive column and the first conductive pad, for enabling a conductive connection between the first conductive column and the first conductive pad, and forming a first conductive height after welding; a second solder joint, arranged between the second conductive column and the second conductive pad, for enabling a conductive connection between the second conductive column and the second conductive pad, and forming a second conductive height after welding; wherein the first conductive height is the same as the second conductive height; the interconnection component solves the problem of poor interconnection between reflow solder balls with smaller diameters and the conductive pads when I / O pins of different sizes on the same chip are interconnected with the conductive pads on the interconnection carrier in the prior art, thereby ensuring the electrical stability of the chip package.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a component suitable for chip interconnection and a preparation method thereof. Background Art

[0002] In the prior art, I / O pins of different sizes are provided on the same chip. When preparing conductive pillars and solder bumps on the said I / O pins, the same sputtering metal nucleation layer process and electroplating conductive pillar process are usually adopted, resulting in the corresponding conductive pillars, solder bumps and interconnecting conductive pads on the I / O pins having the same overall height. However, in the subsequent high-temperature reflow soldering process, solder bumps of the same height form spheres under the action of surface tension, resulting in the shrinkage of the solder balls in height; the larger the diameter of the solder bump, the smaller the shrinkage of the formed sphere in the vertical direction, resulting in poor conductivity between the solder balls formed by the solder bumps with smaller diameters and the interconnecting conductive pads. In addition, the greater the difference in the horizontal cross-sectional area of the chip I / O pins, the more serious the degree of poor conductivity between the solder balls and the interconnecting conductive pads.

[0003] It can be seen that in the prior art, when I / O pins of different sizes on the same chip are interconnected with conductive pads on an interconnect carrier, there is a problem of poor interconnection between reflow solder balls with smaller diameters and the interconnect conductive pads. Summary of the Invention

[0004] In response to the deficiencies in the prior art, the present invention provides a chip interconnection component and a method for preparing the same, which solves the problem in the prior art of poor interconnection between reflow solder balls with smaller diameters and conductive pads when I / O pins of different sizes on the same chip are interconnected with conductive pads on an interconnection carrier.

[0005] In a first aspect, the present invention provides a chip interconnect component for use in welding a chip interconnect base and an interconnect carrier, wherein the chip interconnect base includes a first stacked metal layer and a second stacked metal layer, a first conductive column and a second conductive column, and the interconnect carrier includes a first interconnect conductive pad corresponding to the first conductive column and a second interconnect conductive pad corresponding to the second conductive column, wherein the cross-sectional area of the first conductive column is greater than the cross-sectional area of the second conductive column, and the chip interconnect component includes: a first solder joint having an accommodation space, disposed between the first conductive column and the first conductive pad, for enabling a conductive connection between the first conductive column and the first conductive pad, and forming a first conductive height after welding; a second solder joint, disposed between the second conductive column and the second conductive pad, for enabling a conductive connection between the second conductive column and the second conductive pad, and forming a second conductive height after welding; wherein the accommodation space in the first solder joint enables the first conductive height formed after welding to be the same as the second conductive height.

[0006] Optionally, the accommodating space is: with the horizontal surface of the first conductive column in contact with the first weld body as the reference plane, when the outer circumference of the reference plane extends along the direction of the first weld body to a length equal to the axial height of the first weld body, the space remaining after the first weld body is dug out from the constructed virtual cylinder.

[0007] Optionally, when the first welded body includes a weld body, the accommodating space is formed by the space remaining after the weld body is dug out from the virtual cylinder.

[0008] Optionally, when the first welded body includes at least two welded bodies separated from each other, the accommodating space is formed between the at least two welded bodies.

[0009] Optionally, the first welded body includes a welded body having a cavity, so that the accommodating space is formed in the cavity.

[0010] Optionally, the welding body includes a column or a platform.

[0011] Optionally, the material of the first conductive pillar includes copper; or / and the material of the second conductive pillar includes copper.

[0012] In a second aspect, the present invention provides a method for preparing a chip interconnection component, the method comprising: providing a chip interconnection substrate, coating a photoresist on a first conductive column and a second conductive column of the chip interconnection substrate to obtain a first component photoresist layer; exposing and developing the first component photoresist layer to obtain a first component mask layer having a first interconnection opening array and a first separation opening array, wherein the first separation opening array corresponds to the first conductive column, and the first interconnection opening array corresponds to the second conductive column; depositing solder at the first interconnection opening array and the first separation opening array to form a first solder joint body with an accommodating space on the first conductive column and a second solder joint body on the second conductive column, and cleaning and removing the first component mask layer to obtain the chip interconnection component.

[0013] Optionally, a chip interconnect substrate is provided, comprising: providing a carrier and a silicon wafer comprising a plurality of chips, the carrier being bonded to the passive surface of the silicon wafer by a bonding adhesive, wherein the chip comprises a first built-in conductive pad and a second built-in conductive pad, and the cross-sectional area of the first built-in conductive pad is larger than the cross-sectional area of the second built-in conductive pad; applying photoresist on the active surface of the silicon wafer to obtain a first chip photoresist layer, exposing and developing the first chip photoresist layer to obtain a first chip mask layer having a first opening array, wherein the first opening array comprises a first chip opening corresponding to the first built-in conductive pad and a second chip opening corresponding to the first built-in conductive pad. A second chip opening corresponding to the second built-in conductive pad; preparing a laminated metal layer on the first chip mask layer; applying photoresist on the laminated metal layer to obtain a second chip photoresist layer, and exposing and developing the second chip photoresist layer to obtain a second chip mask layer having a second opening array, wherein the second opening array includes a third chip opening corresponding to the first chip opening and a fourth chip opening corresponding to the second chip opening; electroplating copper at the third chip opening and the fourth chip opening to prepare a first conductive column and a second conductive column, thereby obtaining the chip interconnection substrate.

[0014] Optionally, copper is electroplated at the third chip opening and the fourth chip opening to prepare the first conductive pillar and the second conductive pillar, and then the chip interconnection matrix is obtained, including: after copper is electroplated at the third chip opening and the fourth chip opening to prepare the first conductive pillar and the second conductive pillar, the second chip mask layer, the laminated metal layer and the first chip mask layer are cleaned and removed to obtain the chip interconnection matrix; or, after copper is electroplated at the third chip opening and the fourth chip opening to prepare the first conductive pillar and the second conductive pillar, the second chip mask layer, the laminated metal layer and the first chip mask layer are retained to obtain the chip interconnection matrix.

[0015] Optionally, the volume of each solder block column is adjusted by adjusting the horizontal cross-sectional diameter of each separation opening in the first separation opening array; or, the volume of each solder block platform is adjusted by adjusting the inclination angle of the platform busbar of each separation opening in the first separation opening array.

[0016] Optionally, solder is deposited at the first interconnection opening array and the first separation opening array to form a first solder joint body with an accommodation space on the first conductive column and a second solder joint body on the second conductive column to obtain a chip interconnection component, including: depositing solder at the first separation opening array to form a first solder joint body with an accommodation space on the first conductive column; depositing solder at the first interconnection opening array to form a second solder joint body on the second conductive column to obtain the chip interconnection component.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] The present invention utilizes a structural design of a first solder joint having an accommodation space, so that the solder on the large-sized first conductive pillar reflows into the accommodation space at a high temperature. This can reduce the volume and ball diameter of the solder ball of the first solder joint after high-temperature reflow, as well as the solder height obtained after reflow, thereby ensuring that the obtained solder ball height is consistent with the solder ball height obtained by soldering the small-sized second conductive pillar after high-temperature reflow. Therefore, the present invention utilizes the first solder joint having an accommodation space, so that the first conductive pillar with a larger cross-sectional area on the chip interconnect substrate and the corresponding interconnect conductive pad on the interconnect carrier are welded to form a first conductive height, and the second conductive pillar with a smaller cross-sectional area on the chip interconnect substrate and the corresponding interconnect conductive pad on the interconnect carrier are welded to form a second conductive height, and the first conductive height and the second conductive height are the same. This solves the problem of poor interconnection between the reflow solder ball with a smaller diameter and the conductive pad when different-sized I / O pins on the same chip are connected to the interconnect conductive pad on the interconnect carrier in the prior art, thereby ensuring the electrical reliability of the chip package. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 The figure shows a schematic diagram of poor soldering between I / O pins of different sizes on the same chip and conductive pads on an interconnect carrier in the prior art;

[0020] Figure 2 FIG2 is a schematic structural diagram of a chip interconnection component provided by an embodiment of the present invention;

[0021] Figure 3 FIG. 1 is a schematic diagram of a first structure of a first welded body provided by an embodiment of the present invention;

[0022] Figure 4 FIG2 is a schematic diagram of a second structure of the first welded body provided by an embodiment of the present invention;

[0023] Figure 5 FIG. 1 is a schematic diagram of a third structure of the first welded body provided by an embodiment of the present invention;

[0024] Figure 6 Shown are two longitudinal cross-sectional views of a first welded body provided by an embodiment of the present invention;

[0025] Figure 7 FIG2 is a flow chart of a method for preparing a chip interconnect substrate according to an embodiment of the present invention;

[0026] Figure 8 FIG2 is a schematic diagram of bonding a carrier board and a chip according to an embodiment of the present invention;

[0027] Figure 9 FIG2 is a schematic diagram of preparing a first chip mask layer according to an embodiment of the present invention;

[0028] Figure 10 FIG2 is a schematic diagram of preparing a laminated metal layer according to an embodiment of the present invention;

[0029] Figure 11 FIG2 is a schematic diagram of preparing a second chip mask layer according to an embodiment of the present invention;

[0030] Figure 12 FIG2 is a schematic diagram of preparing a first conductive column and a second conductive column according to an embodiment of the present invention;

[0031] Figure 13 FIG2 is a schematic structural diagram of a chip interconnection substrate provided by an embodiment of the present invention;

[0032] Figure 14 FIG2 is a flow chart of a method for preparing a chip interconnection component provided by an embodiment of the present invention;

[0033] Figure 15 FIG2 is a schematic diagram of preparing a photoresist layer of a first component provided by an embodiment of the present invention;

[0034] Figure 16 FIG2 is a schematic diagram of preparing a mask layer of a first component according to an embodiment of the present invention;

[0035] Figure 17 Shown are two schematic diagrams of different shapes of the first separation opening array provided by an embodiment of the present invention;

[0036] Figure 18 Schematic diagram of preparing the first welded body and the second welded body in an embodiment of the present invention;

[0037] Figure 19 Shown is a schematic diagram of an application scenario of a chip interconnect component provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0038] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0039] Before describing this embodiment, it is necessary to elaborate on the problems mentioned in the background technology: In the prior art, due to the special circuit design built into the chip, it is usually necessary to realize the transmission of different current densities and / or different signal strengths on the same chip, so there will be I / O pins of different sizes on the same chip, such as Figure 1 a and Figure 1 As shown in b, the conductive pillar 11 in the chip 100 is electrically connected to the built-in conductive pad 10 thereof, and the solder block 12 arranged on the conductive pillar 11, and the interconnection conductive pad 13 is arranged on the interconnection carrier 1, wherein the interconnection conductive pad 13 can be designed as an interconnection conductive pad 13a corresponding to the larger solder block 12a on the chip 100, or an interconnection conductive pad 13b corresponding to the smaller solder block 12b on the chip 100 according to the manufacturer's design requirements, or all the interconnection conductive pads on the interconnection carrier 1 can be designed as interconnection conductive pads 13a corresponding to the larger solder block 12a on the chip 100. After the solder blocks 12 correspond one-to-one with the interconnection conductive pads 13 on the interconnection carrier 1, the solder blocks are melted by a high-temperature reflow process, and the solder blocks form tin-based alloy solder balls under the action of surface tension, that is, an alloy interconnection structure is formed between the conductive pillar 11 and the interconnection conductive pad 13. However, if there are conductive pillars 11 and solder blocks 12 of different sizes in the same chip, the use of conventional interconnection structure and preparation process will result in the following Figure 1 b shows the phenomenon of poor welding. The reason for this is that, when preparing the conductive pillars 11 and solder bumps 12 for I / O pins of different sizes on a chip, the chip is typically uniformly subjected to photolithographic openings, deposition of stacked metal layers, and copper electroplating. Since the copper electroplating process takes the same time, the heights of the copper pillars and solder bumps deposited at the corresponding positions of I / O pins of different sizes are consistent. During high-temperature reflow soldering, the solder bumps form spheres under the action of surface tension, and the solder bumps expand in height to a certain extent. The diameter or height of the reflow solder balls is positively correlated with the horizontal cross-sectional area of the solder bumps. Therefore, the reflow solder balls formed with larger diameter solder bumps can form good electrical interconnections with the interconnecting conductive pads, while the reflow solder balls formed with smaller diameter solder bumps cannot form good interconnections with the interconnecting conductive pads due to their smaller diameters. This significantly increases the interconnection resistance between the smaller diameter solder balls and the interconnecting conductive pads. If the cross-sectional areas corresponding to different I / O pins on the same chip differ significantly, the smaller diameter solder balls may become unable to connect with the interconnecting conductive pads.

[0040] The interconnection carrier 1 includes but is not limited to: a packaging substrate, a metal wiring layer structure, a silicon carrier with TSV conductive vias, a bridge chip with TSV conductive vias, and a chip package with an electrical connection layer.

[0041] In a first aspect, in order to solve the above-mentioned problems, the present invention provides a chip interconnection component, which specifically includes the following embodiments:

[0042] Example 1

[0043] Figure 2 FIG. 1 is a schematic structural diagram of a chip interconnection component provided by an embodiment of the present invention; Figure 2 As shown, the chip interconnection component is used in the welding of the chip interconnection base and the interconnection carrier, wherein the chip interconnection base includes a first stacked metal layer 22a and a second stacked metal layer 22b, a first conductive column 24a and a second conductive column 24b, and the interconnection carrier includes a first interconnection conductive pad 13a corresponding to the first conductive column 24a and a second interconnection conductive pad 13b corresponding to the second conductive column 24. The cross-sectional area of the first conductive column 24a is larger than the cross-sectional area of the second conductive column 24b. The chip interconnection component includes:

[0044] A first solder joint 53 having an accommodating space is disposed between the first conductive column 24a and the first conductive pad, and is used to connect the first conductive column 24a to the first conductive pad and form a first conductive height after soldering;

[0045] A second solder joint 54 is provided between the second conductive column 24b and the second conductive pad, and is used to connect the second conductive column 24b to the second conductive pad and form a second conductive height after soldering;

[0046] The accommodation space in the first welded body 53 makes the first conductive height and the second conductive height formed after welding the same.

[0047] It should be noted that if Figure 2 As shown, the silicon wafer S1 includes multiple chips 100, and the active surface of the chip 100 includes a first built-in conductive pad 10a and a second built-in conductive pad 10b, and the cross-sectional area of the first built-in conductive pad 10a is larger than the cross-sectional area of the second built-in conductive pad 10b; the carrier C1 is connected to the passive surface of the silicon wafer S1 through bonding glue F1.

[0048] It should be noted that the accommodation space in the present invention is defined as: taking the horizontal surface of the first conductive column in contact with the first welded body as the reference plane, when the outer circumference of the reference plane extends along the direction of the first welded body to a length equal to the axial height of the first welded body, the space remaining after the first welded body is dug out from the constructed virtual cylinder forms the accommodation space. Figure 3For example, the outer circumference of the horizontal cross-section of the first conductive column 24a extends along the direction of the first weld body. When the extension length is equal to the axial height of the first weld body, a virtual cylinder 60 is constructed. The space remaining after the first weld body is dug out of the virtual cylinder is the accommodating space 61.

[0049] In the first implementation of this embodiment, Figure 3 As shown, when the first welded body 53 includes a welding body, the space remaining after the welding body is dug out from the virtual cylinder 60 forms the accommodating space 61; it should be noted that, in this embodiment, the position and shape of the welding body are not specifically limited, as long as the welding body and the first conductive column form a conductive interconnection, they fall within the scope of protection of this solution.

[0050] In a second implementation of this embodiment, the first welded body 53 includes at least two welded bodies separated from each other, so that the accommodation space is formed between the at least two welded bodies.

[0051] Figure 4 a and Figure 4 b shows the arrangement diagrams of multiple welded bodies with different numbers and separation from each other, where Figure 4 a and Figure 4 b The longitudinal section of the first welded body 53 formed is as follows Figure 2 As shown; it should be noted that, in this embodiment, the number and arrangement of the welded bodies are not specifically limited, as long as an accommodation space can be formed between at least two mutually separated welded bodies, they fall within the scope of protection of this solution.

[0052] In a third implementation of this embodiment, the first welded body 53 includes a welded body having a cavity, so that the accommodation space is formed in the cavity.

[0053] like Figure 5 As shown, the welding body with a cavity includes a second welding body 53b with a solid body structure and a first welding body 53a and / or a third welding body 53c surrounding the solid body structure, and a cavity is provided between the second welding body 53b and the first welding body 53a; wherein, Figure 5 The longitudinal cross-sectional structure of the first welded body 53 formed in Figure 2 As shown; it should be noted that, in this embodiment, the position and shape of the cavity in the welded body are not specifically limited, as long as an accommodating space is formed in the welded body, it falls within the scope of protection of this solution.

[0054] Furthermore, the welding body provided in the above embodiment includes a column or a platform.

[0055] Figure 6 a is Figure 2The first longitudinal cross-sectional enlarged view of the first welded body shows that the first welded body includes a plurality of mutually separated columns, so that a plurality of mutually separated welding columns are arranged correspondingly on the first conductive column 24a; wherein, Figure 6 The second soldering body 53b in a corresponds to the central cylindrical portion of the first conductive column 24a, and the first soldering body 53a and the third soldering body 53c correspond to the edges of the first conductive column 24a. Due to the cavity between the second soldering body 53b, the first soldering body 53a and the third soldering body 53c, the volume and diameter of the solder ball of the first soldering body after high-temperature reflow, as well as the soldering height obtained after reflow, can be reduced. It should be noted that the second soldering body 53b, the first soldering body 53a and the third soldering body 53c in this embodiment are relative to Figure 6 The structure defined by the first longitudinal cross-sectional view of the first welded body shown in a does not mean that the first welded body only includes the second welded body 53b, the first welded body 53a and the third welded body 53c; Figure 3 and Figure 4 It can be seen that the first welded body composed of various forms may form Figure 6 a is the longitudinal section shown.

[0056] Figure 6 b is Figure 2 The enlarged longitudinal cross-section of the second deformed design of the first welded body shows that the first welded body includes a plurality of mutually separated platforms, so that a plurality of mutually separated platforms are arranged correspondingly on the first conductive column 24a; wherein, Figure 6 b) corresponds to the central cylinder of the first conductive column 24a, and the first and third welding bodies 53a and 53c correspond to the edges of the first conductive column 24a; the end of the second welding body 53b, the first welding body 53a and the third welding body 53c close to the first conductive column 24a is defined as the first end, and the end corresponding to the first end is the second end. The cross-sectional diameter of the welding body gradually increases from the first end to the second end. Figure 6 b shows the stage body.

[0057] Compared with the prior art, the beneficial effects of this embodiment are:

[0058] This embodiment utilizes the structural design of the first solder joint with an accommodation space to allow the solder on the large first conductive pillar to be filled into the accommodation space after high-temperature reflow. This can reduce the volume and diameter of the solder balls formed on the first solder joint after high-temperature reflow, as well as the resulting solder ball height after reflow, thereby ensuring that the resulting solder ball height is consistent with the solder ball height formed on the smaller second conductive pillars after high-temperature reflow. Therefore, through the second solder joint and the first solder joint with an accommodation space, the present invention allows the first conductive pillars with a larger cross-sectional area on the chip interconnect substrate to be soldered to the corresponding interconnect conductive pads on the interconnect carrier to form a first conductive height, while the second conductive pillars with a smaller cross-sectional area on the chip interconnect substrate to be soldered to the corresponding interconnect conductive pads on the interconnect carrier to form a second conductive height. Furthermore, the first conductive height and the second conductive height are the same, thereby resolving the prior art problem of poor interconnection between the smaller reflow solder balls and the interconnect conductive pads when different-sized I / O pins on the same chip are connected to the interconnect conductive pads on the interconnect carrier.

[0059] In a second aspect, this embodiment provides a method for preparing a chip interconnect substrate, which specifically includes the following embodiments:

[0060] Example 2

[0061] Figure 7 FIG. 1 is a flow chart of a method for preparing a chip interconnect substrate according to an embodiment of the present invention; FIG. Figure 7 As shown, the method for preparing the chip interconnect substrate specifically includes the following steps:

[0062] Step S101 : providing a carrier board and a silicon wafer including a plurality of chips, wherein the carrier board is bonded to the passive surface of the silicon wafer by bonding adhesive.

[0063] In this embodiment, if Figure 8 As shown, silicon wafer S1 includes multiple chips 100. The active surface of chip 100 includes a first internal conductive pad 10a and a second internal conductive pad 10b, with the cross-sectional area of the first internal conductive pad 10a being larger than that of the second internal conductive pad 10b. The active surface corresponds to the passive surface of the silicon wafer. A carrier C1 is connected to the passive surface of silicon wafer S1 via bonding adhesive F1. The silicon wafer is thinned before being bonded to the bonding adhesive.

[0064] In step S102 , a photoresist is applied on the active surface of the silicon wafer to obtain a first chip photoresist layer, and the first chip photoresist layer is exposed and developed to obtain a first chip mask layer having a first opening array.

[0065] It should be noted that if Figure 9As shown in FIG. a, a layer of photoresist is coated on the active surface of the silicon wafer S1 to obtain a first chip photoresist layer 20a; wherein, a dielectric film with a UV photosensitive agent can also be used as a mask layer by hot pressing. Figure 9 As shown in FIG. 2 , the first chip photoresist layer 20a is exposed and developed by a photolithography process to obtain a first chip mask layer 20b having a first opening array, wherein the first opening array includes a first chip opening 211 corresponding to the first built-in conductive pad 10a and a second chip opening 212 corresponding to the second built-in conductive pad 10b.

[0066] Step S103: preparing a laminated metal layer on the first chip mask layer.

[0067] In this embodiment, if Figure 10 As shown, several layers of stacked metal layers 22 are sputtered on the first chip mask layer 20b. In a specific stacked metal layer structure, the stacked metal layer includes a sputtered metal barrier layer and a copper seed layer; the metal barrier layer includes Ti, Ni, Cu, Pd, Pt or Ti-W, and its function is to prevent copper atoms from diffusing to the chip substrate.

[0068] Furthermore, the stacked metal layer 22 includes an open copper seed layer on the first opening array and a mask seed layer outside the first opening array.

[0069] Step S104 , coating photoresist on the stacked metal layer to obtain a second chip photoresist layer, and exposing and developing the second chip photoresist layer to obtain a second chip mask layer having a second opening array.

[0070] It should be noted that if Figure 11 As shown in a, a photoresist is coated on the laminated metal layer and subjected to a low-temperature baking process to obtain a second chip photoresist layer 23a;

[0071] like Figure 11 As shown in FIG. 2 , the second chip photoresist layer 23a is exposed and developed by a photolithography process to obtain a second chip mask layer 23b having a second opening array, wherein the second opening array includes a third chip opening 221 corresponding to the first chip opening 211 and a fourth chip opening 222 corresponding to the second chip opening 212.

[0072] Step S105 , electroplating copper at the third chip opening and the fourth chip opening to prepare first conductive pillars and second conductive pillars, and then obtaining the chip interconnection substrate.

[0073] In this embodiment, copper is electroplated at the third chip opening and the fourth chip opening to prepare the first conductive pillar and the second conductive pillar, and then the chip interconnection matrix is obtained, including: after copper is electroplated at the third chip opening and the fourth chip opening to prepare the first conductive pillar and the second conductive pillar, the second chip mask layer, the laminated metal layer and the first chip mask layer are cleaned and removed to obtain the chip interconnection matrix.

[0074] Optionally, copper is electroplated at the third chip opening and the fourth chip opening to prepare the first conductive pillar and the second conductive pillar, and then the chip interconnection matrix is obtained, including: after copper is electroplated at the third chip opening and the fourth chip opening to prepare the first conductive pillar and the second conductive pillar, the second chip mask layer, the stacked metal layer and the first chip mask layer are retained to obtain the chip interconnection matrix.

[0075] In this embodiment, if Figures 11-12 As shown, a copper electroplating process is performed on the stacked metal layers corresponding to the third chip opening 221 and the fourth chip opening 222 to prepare first conductive pillars 24a and second conductive pillars 24b. The height of the conductive pillars can be greater than, less than, or equal to the height of the second chip mask layer 23b.

[0076] In the first embodiment of the obtained chip interconnection matrix, as shown in FIG. Figure 13 As shown in a, the second chip mask layer 23b, the laminated metal layer outside the first opening array, and the first chip mask layer 20b are cleaned and removed in sequence to prepare a chip interconnect substrate P1 connected to the chip's built-in conductive pad on the chip active surface, wherein the chip interconnect substrate P1 includes a laminated metal layer, a first conductive column 24a, and a second conductive column 24b.

[0077] In the second embodiment of the obtained chip interconnect matrix, Figure 13 As shown in b, copper is electroplated at the third chip opening and the fourth chip opening to prepare the first conductive pillar and the second conductive pillar. Different from the first method mentioned above, the chip interconnection substrate P1' here does not need to remove the second chip mask layer, the laminated metal layer outside the first opening array and the first chip mask layer, that is, the chip mask layer and the laminated metal layer jointly surround the first conductive pillar and the second conductive pillar.

[0078] In a second aspect, this embodiment provides a method for preparing a chip interconnect component, which specifically includes the following embodiments:

[0079] Example 3

[0080] Figure 14FIG2 is a flow chart of a method for preparing a chip interconnection component according to an embodiment of the present invention; the method for preparing the chip interconnection component specifically comprises the following steps:

[0081] Step S201, providing a chip interconnection substrate, coating a photoresist on a first conductive pillar and a second conductive pillar of the chip interconnection substrate to obtain a first component photoresist layer;

[0082] like Figure 15 As shown, photoresist is coated on the chip interconnect substrate to obtain a first component photoresist layer 50a; wherein, a dielectric film with ultraviolet photosensitizer that is hot-pressed can also be used as a mask layer to replace the first component photoresist layer 50a.

[0083] This process step can also refer to Figure 13 As shown in b, photoresist is directly coated on the chip interconnect substrate P1' to save photoresist materials and simplify the process flow.

[0084] Step S202 : exposing and developing the first component photoresist layer to obtain a first component mask layer having a first interconnected opening array and a first separated opening array.

[0085] The first separation opening array corresponds to the first conductive pillar, and the first interconnection opening array corresponds to the second conductive pillar.

[0086] like Figure 16 As shown, the first component photoresist layer 50a is exposed and developed to obtain a first component mask layer 50b having a first separation opening array 51 and a first interconnection opening array 52; wherein the first conductive column 24a corresponds to the first separation opening array 51, and the first separation opening array 51 includes a first separation opening 51a, a second separation opening 51b, and a third separation opening 51c; the second conductive column 24b corresponds to the first interconnection opening array 52.

[0087] In this embodiment, when the first separated opening array includes a plurality of cylindrical openings, the volume of each solder bump column is adjusted by adjusting the horizontal cross-sectional diameter of each separated opening in the first separated opening array.

[0088] It should be noted that if Figure 17 Schematic diagram of the first shape of the first separation opening array shown in a, by adopting a special opening pattern design on the mask plate for photoetching the first component photoresist layer 50a, the length of the horizontal cross-sectional diameter of the separation opening 51a is L1, and the length of the corresponding cross-sectional diameter on the first component mask layer 50b is L2. The volume of each solder block column can be adjusted by adjusting the ratio of L1 / L2.

[0089] In this embodiment, when the first separated opening array includes a plurality of terrace-shaped openings, the volume of each solder bump column is adjusted by adjusting the inclination angle of the terrace generatrix of each separated opening in the first separated opening array.

[0090] It should be noted that if Figure 17 b is a schematic diagram of the second shape of the first separation opening array. When the size distribution of each separation opening in the first separation opening array presents a table shape with a larger upper part and a smaller lower part, the angle between the table busbar and the longitudinal axis is θ. The inclination angle of the table busbar of each separation opening can be changed by adjusting the size of θ, thereby adjusting the volume of each solder block column.

[0091] Step S203 , depositing solder at the first interconnection opening array and the first separation opening array to form a first solder joint with an accommodation space on the first conductive pillar and a second solder joint on the second conductive pillar, and cleaning and removing the first component mask layer to obtain a chip interconnection component.

[0092] like Figure 18 As shown, solder is deposited at the first interconnected opening array 52 and the first separated opening array 51, a first solder joint having an accommodation space is formed on the first conductive column and a second solder joint is formed on the second conductive column, and the first component mask layer 50b is removed after cleaning to obtain the following: Figure 2 The chip interconnect components shown.

[0093] When cleaning the chip interconnect substrate P1', it is necessary to clean and remove the first component mask layer, the second chip mask layer, the laminated metal layer in the non-conductive pillar area, and the first chip mask layer respectively.

[0094] In this embodiment, after the chip interconnection substrate P1 is prepared to obtain the chip interconnection component and interconnected with the interconnection carrier, the following steps are further included:

[0095] like Figure 19 As shown in FIG. 1 , the chips are segmented, and the bonding glue F1 and the carrier C1 are removed by debonding to obtain separated chips with chip interconnection components. The first solder joints and the second solder joints on the chip interconnection components correspond one-to-one with the interconnection conductive pads on the interconnection carrier, respectively. The first solder joints 53 correspond to the first interconnection conductive pad 13a, and the second solder joints 54 correspond to the second interconnection conductive pad 13b.

[0096] like Figure 19As shown in FIG. 2 , the high-temperature reflow process melts the first solder joint 53 and the second solder joint 54, and the first interconnected solder ball 55a and the second interconnected solder ball 55b are respectively prepared under the combined action of surface tension and gravity. Since the first solder joint 53 includes a plurality of cavity structures arranged around mutually separated columns or platforms, although the heights of the first solder joint 53 and the second solder joint 54 are the same, the cavity structure design in the first solder joint 53 enables the molten first solder joint 53 to fill the cavity structure under the action of surface tension and / or gravity, ensuring that the welding height of the first interconnected solder ball 55a and the welding height of the second interconnected solder ball 55b are the same.

[0097] Compared with the prior art, the beneficial effects of this embodiment are:

[0098] This embodiment utilizes a first solder joint with a receiving space to allow solder on the large first conductive pillar to reflow into the receiving space at high temperature. This reduces the volume and diameter of the solder balls formed by the first solder joint after high-temperature reflow, as well as the resulting solder ball height, thereby ensuring that the resulting solder ball height is consistent with the solder ball height formed by solder on the smaller second conductive pillars after high-temperature reflow. Therefore, the present invention utilizes the first and second solder joints with receiving spaces to achieve a first conductive height after soldering the first conductive pillars with a larger cross-sectional area on the chip interconnect substrate to the corresponding conductive pads on the interconnect carrier, and a second conductive height after soldering the second conductive pillars with a smaller cross-sectional area on the chip interconnect substrate to the corresponding conductive pads on the interconnect carrier. Furthermore, the first conductive height and the second conductive height are the same, thereby resolving the prior art issue of poor interconnection between reflowed solder balls with smaller diameters and the conductive pads when connecting I / O pins of different sizes on the same chip to the conductive pads on the interconnect carrier, thereby ensuring the electrical reliability of the chip package.

[0099] Furthermore, this embodiment can adjust the volume ratio of the solder area and the non-solder area through the pattern design of the photolithography mask plate, and prepare tin-based alloy solder balls with uniform longitudinal height on conductive pillars of different sizes, effectively avoiding the phenomenon in the prior art that small-sized conductive pillars and interconnected conductive pads cannot be interconnected and conductive.

[0100] Furthermore, the solder joint described in this embodiment corresponds to the solder area and includes a tin-based alloy solder block.

[0101] Furthermore, solder is deposited at the first interconnection opening array and the first separation opening array to form a first solder joint with an accommodating space on the first conductive column, and a second solder joint is formed on the second conductive column to obtain a chip interconnection component, including: depositing solder at the first separation opening array to form a first solder joint with an accommodating space on the first conductive column; depositing solder at the first interconnection opening array to form a second solder joint on the second conductive column; making the first solder joint and the second solder joint on the chip interconnection component correspond one-to-one to the interconnection conductive pads on the interconnection carrier respectively; and preparing the first interconnection solder ball and the second interconnection solder ball by high-temperature reflow to obtain the chip interconnection component.

[0102] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

Claims

1. A chip interconnection component, characterized in that: The invention is applied to the welding of a chip interconnection base and an interconnection carrier, wherein the chip interconnection base includes a first stacked metal layer and a second stacked metal layer, a first conductive column and a second conductive column, the interconnection carrier includes a first interconnection conductive pad corresponding to the first conductive column and a second interconnection conductive pad corresponding to the second conductive column, the cross-sectional area of the first conductive column is larger than the cross-sectional area of the second conductive column, and the chip interconnection component includes: A first solder joint having a space for accommodating solder on the first conductive post, disposed between the first conductive post and the first conductive pad, for providing conductive connection between the first conductive post and the first conductive pad and forming a first conductive height after soldering, wherein the space is defined as the space remaining after the first solder joint is removed from a virtual cylinder constructed by taking the horizontal surface of the first conductive post in contact with the first solder joint as a reference plane and extending the outer circumference of the reference plane along the direction of the first solder joint by a length equal to the axial height of the first solder joint; a second solder joint, disposed between the second conductive column and the second conductive pad, for connecting the second conductive column and the second conductive pad and forming a second conductive height after soldering; The accommodation space in the first welded body makes the first conductive height and the second conductive height formed after welding the same.

2. The chip interconnection component according to claim 1, wherein: When the first welded body includes a welded body, the remaining space after the welded body is hollowed out from the virtual cylinder forms the accommodating space.

3. The chip interconnection component according to claim 1, wherein: When the first welded body includes at least two welded bodies separated from each other, the accommodation space is formed between the at least two welded bodies.

4. The chip interconnection component according to claim 1, wherein: The first welded body includes a welded body having a cavity, so that the accommodation space is formed in the cavity.

5. The chip interconnection component according to claim 2, 3 or 4, characterized in that: The welding body includes a column or a platform.

6. The chip interconnection component according to claim 1, wherein: The material of the first conductive pillar includes copper; or / and the material of the second conductive pillar includes copper.

7. A method for preparing a chip interconnection component, characterized in that: The method comprises: Providing a chip interconnect substrate, coating a photoresist on a first conductive pillar and a second conductive pillar of the chip interconnect substrate to obtain a first component photoresist layer, wherein the cross-sectional area of the first conductive pillar is greater than the cross-sectional area of the second conductive pillar; exposing and developing the first component photoresist layer to obtain a first component mask layer having a first interconnected opening array and a first separated opening array, wherein the first separated opening array corresponds to the first conductive pillars, and the first interconnected opening array corresponds to the second conductive pillars; Solder is deposited at the first interconnection opening array and the first separation opening array to form a first solder joint body having an accommodating space for accommodating the solder on the first conductive pillar on the first conductive pillar and a second solder joint body on the second conductive pillar, and the first component mask layer is cleaned and removed to obtain a chip interconnection component, wherein, after the chip interconnection structure is obtained, when interconnecting with the interconnection carrier, the first solder joint body and the second solder joint body are respectively made to correspond to the interconnection conductive pads on the interconnection carrier, and the first solder joint body and the second solder joint body are melted by a high-temperature reflow process to obtain first interconnection solder balls and second interconnection solder balls of the same height; wherein, the accommodating space is: with the horizontal surface of the first conductive pillar in contact with the first solder joint body as the reference plane, when the outer circumference of the reference plane extends along the direction of the first solder joint body to a length equal to the axial height of the first solder joint body, the space remaining after the first solder joint body is dug out from the constructed virtual cylinder.

8. The method for preparing a chip interconnection component according to claim 7, wherein: A chip interconnect substrate is provided, comprising: A carrier board and a silicon wafer including a plurality of chips are provided, wherein the carrier board is bonded to the passive surface of the silicon wafer by bonding adhesive, wherein the chip includes a first built-in conductive pad and a second built-in conductive pad, and the cross-sectional area of the first built-in conductive pad is greater than the cross-sectional area of the second built-in conductive pad; Applying photoresist on the active surface of the silicon wafer to obtain a first chip photoresist layer, exposing and developing the first chip photoresist layer to obtain a first chip mask layer having a first opening array, wherein the first opening array includes a first chip opening corresponding to the first built-in conductive pad and a second chip opening corresponding to the second built-in conductive pad; preparing a laminated metal layer on the first chip mask layer; Applying photoresist on the laminated metal layer to obtain a second chip photoresist layer, and exposing and developing the second chip photoresist layer to obtain a second chip mask layer having a second opening array, wherein the second opening array includes a third chip opening corresponding to the first chip opening and a fourth chip opening corresponding to the second chip opening; The chip interconnection substrate is obtained by electroplating copper at the third chip opening and the fourth chip opening to prepare the first conductive pillar and the second conductive pillar.

9. The method for preparing a chip interconnection component according to claim 8, wherein: The chip interconnection substrate is obtained by electroplating copper at the third chip opening and the fourth chip opening to prepare first conductive pillars and second conductive pillars, comprising: Electroplating copper at the third chip opening and the fourth chip opening to prepare a first conductive pillar and a second conductive pillar, and then cleaning and removing the second chip mask layer, the laminated metal layer and the first chip mask layer to obtain the chip interconnection substrate; Alternatively, after copper is electroplated at the third chip opening and the fourth chip opening to prepare the first conductive pillar and the second conductive pillar, the second chip mask layer, the stacked metal layer and the first chip mask layer are retained to obtain the chip interconnection substrate.

10. The method for preparing a chip interconnection component according to claim 7, wherein: The volume of each solder block column is adjusted by adjusting the horizontal cross-sectional diameter of each separation opening in the first separation opening array; or, the volume of each solder block mesa is adjusted by adjusting the inclination angle of the mesa busbar of each separation opening in the first separation opening array.

11. The method for preparing a chip interconnection component according to claim 7, wherein: Depositing solder at the first interconnection opening array and the first separation opening array to form a first solder joint with an accommodation space on the first conductive pillar and a second solder joint on the second conductive pillar to obtain a chip interconnection component, including: Depositing solder at the first separation opening array to form a first solder joint having an accommodation space on the first conductive column; The chip interconnection component is obtained by depositing solder at the first interconnection opening array and forming a second solder joint on the second conductive pillar.

Images