An array substrate and a display panel

Abstract

This invention discloses an array substrate and a display panel. The array substrate includes: a substrate; at least one thin-film transistor (TFT) located on one side of the substrate, the TFT including an active layer, a gate, a source, and a drain; the active layer including a source region, a drain region, and a channel region, the source region being connected to the source, and the drain region being connected to the drain; the contact resistance between the source and the source region is less than the contact resistance between the drain and the drain region. The technical solution provided by the embodiments of this invention alleviates the latency during black-and-white dynamic image switching on the display panel and the image ghosting phenomenon.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to an array substrate and a display panel. Background Technology

[0002] With continuous innovation and development in the display field, display panels have become an indispensable major invention, and are used in products such as smartphones and smartwatches, bringing many conveniences to people's lives.

[0003] However, there is a significant display defect in current display panels: when switching between black and white dynamic images, the displayed image has a certain delay, which leads to ghosting during the image transition. Summary of the Invention

[0004] This invention provides an array substrate and a display panel, which alleviates the latency and ghosting phenomenon when the display panel switches between black and white dynamic images.

[0005] According to one aspect of the present invention, an array substrate is provided, comprising:

[0006] Substrate;

[0007] At least one thin-film transistor, the thin-film transistor being located on one side of the substrate, the thin-film transistor including an active layer, a gate, a source, and a drain;

[0008] The active layer includes a source region, a drain region, and a channel region, wherein the source region is connected to the source electrode, and the drain region is connected to the drain electrode;

[0009] The contact resistance between the source and the source region is less than the contact resistance between the drain and the drain region.

[0010] This technical solution reduces the voltage drop between the source and the source region by setting the contact resistance between the source and the source region to be less than the contact resistance between the drain and the drain region. This reduces the potential difference between the source and the drain, alleviates the delay and ghosting phenomenon during black-and-white dynamic image switching of the array substrate and display panel, and thus improves the image display quality.

[0011] Optionally, the area of ​​the source electrode projected onto the substrate is larger than the area of ​​the drain electrode projected onto the substrate.

[0012] In this technical solution, the area of ​​the source electrode projected onto the substrate is larger than the area of ​​the drain electrode projected onto the substrate, which reduces the contact resistance between the source electrode and the source region, thereby reducing the potential difference between the source electrode and the drain electrode. This alleviates the delay in the black-and-white dynamic image switching of the array substrate and the display panel, as well as the image ghosting phenomenon, and thus improves the image display quality.

[0013] Optionally, a buffer layer, the active layer, a first insulating layer, and a second insulating layer are sequentially disposed on the substrate.

[0014] The active layer is disposed on the side of the buffer layer away from the substrate and is covered by the first insulating layer; the gate is disposed on the side of the first insulating layer away from the buffer layer and is covered by the second insulating layer; the source and the drain are disposed on the side of the second insulating layer away from the first insulating layer.

[0015] The area of ​​the first via projected onto the substrate is greater than the area of ​​the second via projected onto the substrate.

[0016] This technical solution further limits the area of ​​the first via projected onto the substrate to be greater than the area of ​​the second via projected onto the substrate. This makes the contact resistance between the source and the source region in the first via less than the contact resistance between the drain and the drain region in the second via. This further reduces the potential difference between the source and the drain, effectively alleviating the latency and ghosting phenomenon during black-and-white dynamic image switching of the array substrate and display panel, thereby improving the image display quality.

[0017] Optionally, the number of the first vias is greater than or equal to 1, and the diameter of each first via is greater than the diameter of the second via.

[0018] In this technical solution, the aperture of a single first via is larger than that of a single second via, which reduces the contact resistance in each conductive path of the source and source region, thereby further reducing the potential difference between the source and drain. This effectively alleviates the delay and ghosting phenomenon during the switching of black and white dynamic images on the array substrate and display panel, thereby improving the image display quality.

[0019] Optionally, the number of the first vias is greater than or equal to 2, and different first vias are insulated from each other within the second insulating layer;

[0020] Preferably, the diameter of each of the first vias is equal.

[0021] In this technical solution, the number of first vias is greater than or equal to two. These first vias are insulated within the second insulating layer, providing at least two conductive paths between the source electrode and the source region. This avoids display abnormalities caused by the failure of one conductive path, thereby improving display efficiency. Preferably, when the apertures of the first vias are equal, the contact resistance within each conductive path between the source electrode and the source region is equal, ensuring minimal difference in electrical signals within each conductive path and thus improving the uniformity of the displayed image.

[0022] Optionally, it further includes a gate connection electrode, and the second insulating layer further includes at least one third via, through which the gate connection electrode is connected to the gate;

[0023] The gate connection electrode and the source electrode are located on the same layer and are insulated from each other.

[0024] In this technical solution, the gate connection electrode applies the driving signal to the gate, and the contact resistance between the gate connection electrode and the gate can be controlled by controlling the area of ​​the gate connection electrode, thereby controlling the voltage drop of the gate and thus controlling the display quality.

[0025] Optionally, the number of the third vias is greater than or equal to 2, and different third vias are insulated from each other within the second insulating layer;

[0026] Preferably, the diameters of the third vias are equal.

[0027] In this technical solution, the number of third vias is greater than or equal to two. These third vias are insulated within the second insulating layer, providing two conductive paths between the gate connection electrode and the gate. This avoids display abnormalities caused by the failure of one conductive path, thereby improving display efficiency. Preferably, when the apertures of the third vias are equal, the contact resistance within each conductive path between the gate connection electrode and the gate is equal, ensuring minimal difference in electrical signals within each conductive path and thus improving the uniformity of the displayed image.

[0028] Optionally, the thin-film transistor includes at least two, and the thin-film transistor includes a first thin-film transistor and a second thin-film transistor;

[0029] The active layer of the first thin-film transistor is low-temperature polycrystalline silicon, and the active layer of the second thin-film transistor is oxide semiconductor.

[0030] In this technical solution, the first and second thin-film transistors constitute an array substrate for an LTPO display panel, which has advantages such as low power consumption, self-illumination, and excellent flexibility. Furthermore, the thickness of each film layer of the first and second thin-film transistors can be set within their respective optimal ranges, avoiding the problem of incompatibility between the optimal film layer thicknesses of the first and second thin-film transistors in the array substrate, thus fully utilizing the optimal performance of the first and second thin-film transistors in the array substrate. The source electrode of the first thin-film transistor is low-temperature polycrystalline silicon, which results in high electron mobility and high switching speed. The active layer of the second thin-film transistor is an oxide semiconductor, which, due to its high carrier mobility, low deposition temperature, and high transparency, has become a mainstream display panel driving technology.

[0031] Optionally, it further includes at least one capacitor structure, wherein the first electrode of the capacitor structure and the gate are located on the same layer;

[0032] The second insulating layer comprises a stack of a first sub-insulating layer and a second sub-insulating layer;

[0033] The second electrode of the capacitor structure is located between the first sub-insulating layer and the second sub-insulating layer.

[0034] In this technical solution, the capacitor structure ensures the stability of the driving signal, while the first electrode and the gate are located on the same layer. The first electrode and the gate can use the same mask, which reduces the number of masks used in the array substrate fabrication process, thereby simplifying the process and reducing costs.

[0035] According to another aspect of the present invention, a display panel is provided, comprising the array substrate described in any embodiment of the present invention.

[0036] In this technical solution, the display panel, including the array substrate described in any embodiment of the present invention, also has the beneficial effects described in the above embodiments.

[0037] The technical solution provided in this embodiment reduces the voltage drop between the source and the source region by setting the contact resistance between the source and the source region to be less than the contact resistance between the drain and the drain region. This reduces the potential difference between the source and the drain, alleviates the delay and ghosting phenomenon during black-and-white dynamic image switching of the array substrate and the display panel, and thus improves the image display quality.

[0038] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of the structure of an array substrate provided according to an embodiment of the present invention;

[0041] Figure 2 This is a schematic diagram of another array substrate provided according to an embodiment of the present invention;

[0042] Figure 3This is a schematic diagram of another array substrate provided according to an embodiment of the present invention;

[0043] Figure 4 This is a schematic diagram of another array substrate provided according to an embodiment of the present invention;

[0044] Figure 5 This is a schematic diagram of another array substrate provided according to an embodiment of the present invention;

[0045] Figure 6 This is a schematic diagram of the structure of a display panel according to an embodiment of the present invention. Detailed Implementation

[0046] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0047] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0048] As described in the background section, a significant display defect exists in current display panels: a certain delay in the display image during black-and-white dynamic image transitions, resulting in ghosting. Through careful research, the inventors discovered that the display panel's array substrate contains a driving circuit composed of thin-film transistors. A large potential difference exists between the source and drain of these thin-film transistors over a long period, causing a delay in the black-and-white dynamic image transitions and resulting in ghosting.

[0049] To address the above problems, embodiments of the present invention provide the following technical solutions:

[0050] An embodiment of the present invention provides an array substrate. Figure 1This is a schematic diagram of an array substrate according to an embodiment of the present invention. See also... Figure 1 The array substrate includes: a substrate 10; at least one thin-film transistor T0, located on one side of the substrate 10, the thin-film transistor T0 including an active layer 20, a gate 30, a source 40, and a drain 50; the active layer 20 includes a source region, a drain region, and a channel region, the source region being connected to the source 40, and the drain region being connected to the drain 50; the contact resistance between the source 40 and the source region is less than the contact resistance between the drain 50 and the drain region. For example, Figure 1 Only one thin-film transistor T0 is shown.

[0051] In this embodiment, the thin-film transistor T0 in the array substrate is used to construct pixel driving circuits such as 2T1C and 7T1C for driving the light-emitting units to emit light. In this embodiment of the invention, the thin-film transistor T0 can be an NMOS transistor or a PMOS transistor, and the channel type of the thin-film transistor T0 is not limited in this embodiment of the invention.

[0052] Through careful research, the inventors discovered that in the array substrate of the display panel, a driving circuit composed of thin-film transistors is disposed, and a large potential difference exists between the source and drain of the thin-film transistors for a long time. The inventors also found that in the pixel driving circuit, the contact resistance between the source 40 and the source region and the contact resistance between the drain 50 and the drain region are not significantly different. Therefore, the inventors used the contact resistance between the drain 50 and the drain region as a benchmark, and reduced the voltage drop of the contact resistance between the source 40 and the source region by reducing the contact resistance between the source 40 and the source region, thereby reducing the potential difference between the source 40 and the drain 50.

[0053] The technical solution provided in this embodiment reduces the voltage drop between the source 40 and the source region by setting the contact resistance between the source 40 and the source region to be less than the contact resistance between the drain 50 and the drain region. This reduces the potential difference between the source 40 and the drain 50, alleviates the delay and ghosting phenomenon when the array substrate and the display panel switch between black and white dynamic images, and thus improves the image display quality.

[0054] Optionally, the area of ​​the source electrode projected onto the substrate is larger than the area of ​​the drain electrode projected onto the substrate.

[0055] See Figure 1 The area of ​​the source electrode 40 projected onto the substrate 10 is larger than the area of ​​the drain electrode 50 projected onto the substrate 10. For example... Figure 1As shown, an insulating layer is disposed between the source electrode 40 and the drain electrode 50 and the active layer 20. The source electrode 40 reaches the source region through a via in the insulating layer and is connected to the source region. The drain electrode 50 reaches the drain region through a via in the insulating layer and is connected to the drain region. The area of ​​the orthographic projection of the source electrode 40 onto the substrate 10 is the cross-sectional area of ​​the portion of the source electrode 40 located on the surface of the insulating layer on the substrate 10, and the area of ​​the orthographic projection of the drain electrode 50 onto the substrate 10 is the cross-sectional area of ​​the portion of the drain electrode 50 located on the surface of the insulating layer on the substrate 10. The cross-sectional area of ​​the portion of the source electrode 40 located on the surface of the insulating layer on the substrate 10 is larger than the cross-sectional area of ​​the portion of the drain electrode 50 located within the via in the insulating layer, so that the area of ​​the orthographic projection of the source electrode 40 onto the substrate 10 is larger than the area of ​​the orthographic projection of the drain electrode 50 onto the substrate 10.

[0056] Specifically, in this embodiment, the area of ​​the source electrode 40 projected onto the substrate 10 is larger than the area of ​​the drain electrode 50 projected onto the substrate 10, which reduces the contact resistance between the source electrode 40 and the source region, thereby reducing the potential difference between the source electrode 40 and the drain electrode 50. This alleviates the delay during the switching of black and white dynamic images on the array substrate and the display panel, as well as the ghosting phenomenon that occurs in the image, thereby improving the image display quality.

[0057] Optionally, the area of ​​the source electrode 40 projected onto the substrate 10 is greater than or equal to 20 square micrometers and less than or equal to 60 square micrometers.

[0058] Specifically, when the area of ​​the source 40 projected onto the substrate 10 is less than 20 square micrometers, the contact resistance between the source 40 and the source region is too high, failing to effectively reduce the potential difference between the source 40 and the drain 50. When the area of ​​the source 40 projected onto the substrate 10 is greater than 60 square micrometers, the cross-sectional area of ​​the portion of the source 40 located on the surface of the insulating layer is too large, which is detrimental to the miniaturization of thin-film transistors in the array substrate.

[0059] To further reduce the contact resistance between the source electrode 40 and the source region, embodiments of the present invention also provide the following technical solutions:

[0060] Optionally, a buffer layer, a first insulating layer, and a second insulating layer are sequentially disposed on the substrate; an active layer is disposed on the side of the buffer layer away from the substrate and is covered by the first insulating layer; a gate is disposed on the side of the first insulating layer away from the buffer layer and is covered by the second insulating layer; a source and a drain are disposed on the side of the second insulating layer away from the first insulating layer; the second insulating layer is provided with a first via and a second via, the source being connected to the source region through the first via; the drain being connected to the drain region through the second via; the area of ​​the first via projected onto the substrate is larger than the area of ​​the second via projected onto the substrate.

[0061] For example, see Figure 1A buffer layer 11, a first insulating layer 12, and a second insulating layer 13 are sequentially disposed on a substrate 10. An active layer 20 is disposed on the side of the buffer layer 11 away from the substrate 10 and is covered by the first insulating layer 12. A gate 30 is disposed on the side of the first insulating layer 12 away from the buffer layer 11 and is covered by the second insulating layer 13. A source 40 and a drain 50 are disposed on the side of the second insulating layer 13 away from the first insulating layer 12. The second insulating layer 13 has a first via 130 and a second via 131. The source 40 is connected to the source region through the first via 130, and the drain 50 is connected to the drain region through the second via 131. The area of ​​the first via 130 projected onto the substrate 10 is larger than the area of ​​the second via 131 projected onto the substrate 10. For example, see [link to example]. Figure 2 There are two first vias 130, and the area of ​​the orthogonal projection of each first via 130 onto the substrate 10 is greater than the area of ​​the orthogonal projection of the second via 131 onto the substrate 10.

[0062] Specifically, based on the above technical solution, the area of ​​the orthogonal projection of all first vias 130 onto the substrate 10 is further limited to be greater than the area of ​​the orthogonal projection of the second vias 131 onto the substrate 10. This makes the contact resistance between the source 40 and the source region in the first via 130 less than the contact resistance between the drain 50 and the drain region in the second via 131. This further reduces the potential difference between the source 40 and the drain 50, effectively alleviating the delay and ghosting phenomenon during the black-and-white dynamic image switching of the array substrate 10 and the display panel, thereby improving the image display quality.

[0063] Optionally, the number of first vias is greater than or equal to 1, and the diameter of each first via is greater than the diameter of the second via.

[0064] For example, see Figure 1 and Figure 2 The diameter of each first via 130 is larger than that of the second via 131, which reduces the contact resistance in each conductive path of the source 40 and the source region, thereby further reducing the potential difference between the source 40 and the drain 50. This effectively alleviates the delay and ghosting phenomenon when the array substrate and the display panel switch between black and white dynamic images, thus improving the image display quality.

[0065] Optionally, the number of first vias is greater than or equal to 2, and different first vias are insulated from each other within the second insulating layer; preferably, the diameter of each first via is equal.

[0066] For example, see Figure 2The number of first vias 130 is two. The two first vias 130 are insulated within the second insulating layer 13, providing two conductive paths between the source electrode 40 and the source region. This avoids display abnormalities caused by the failure of one conductive path, thereby improving display efficiency. It should be noted that the number of first vias 130 includes, but is not limited to, two.

[0067] Preferably, when the aperture of each first via 130 is equal, the contact resistance in each conductive path between the source electrode 40 and the source region is equal, thereby ensuring that the difference in electrical signal in each conductive path is small, and thus improving the uniformity of the display screen.

[0068] Optionally, it also includes a gate connection electrode, and the second insulating layer further includes at least one third via, through which the gate connection electrode is connected to the gate; the gate connection electrode and the source are located in the same layer and are insulated from each other.

[0069] For example, see Figure 3 and Figure 4 It also includes a gate connection electrode 31, and the second insulating layer 13 further includes at least one third via 132. The gate connection electrode 31 is connected to the gate 30 through the third via 132. The gate connection electrode 31 and the source 40 are located in the same layer and are insulated from each other.

[0070] Specifically, the gate connection electrode 31 applies a driving signal to the gate 30, and the contact resistance between the gate connection electrode 31 and the gate 30 can be controlled by controlling the area of ​​the gate connection electrode 31, thereby controlling the voltage drop of the gate 30 and thus controlling the display quality.

[0071] Optionally, the number of third vias is greater than or equal to 2, and different third vias are insulated from each other within the second insulating layer; preferably, the diameters of the third vias are equal.

[0072] For example, see Figure 4 The number of third vias 132 is two. The two third vias 132 are insulated within the second insulating layer 13, providing two conductive paths between the gate connection electrode 31 and the gate 30. This avoids display abnormalities caused by the failure of one conductive path, thereby improving display efficiency. It should be noted that the number of third vias 132 includes, but is not limited to, two.

[0073] Preferably, when the apertures of the third vias 132 are equal, the contact resistance in each conductive path between the gate connection electrode 31 and the gate 30 is equal, thereby ensuring that the difference in electrical signals in each conductive path is small, and thus improving the uniformity of the display screen.

[0074] Optionally, the thin-film transistor includes at least two, including a first thin-film transistor and a second thin-film transistor; the active layer of the first thin-film transistor is low-temperature polycrystalline silicon, and the active layer of the second thin-film transistor is an oxide semiconductor.

[0075] Figure 5 This is a schematic diagram of another array substrate provided according to an embodiment of the present invention. For example, see [link to example]. Figure 5 In the array substrate, there are two thin-film transistors, namely a first thin-film transistor T1 and a second thin-film transistor T2. The active layer 20a of the first thin-film transistor T1 is low-temperature polycrystalline silicon, and the active layer 20b of the second thin-film transistor T2 is oxide semiconductor. It should be noted that the number of thin-film transistors includes, but is not limited to, two. Specifically, there is at least one first thin-film transistor T1 and at least one second thin-film transistor T2. A first gate insulating layer 12a is included above the source 20a of the first thin-film transistor T1, and a second gate insulating layer 12b is included above the source 20b of the second thin-film transistor T2.

[0076] In this embodiment, the first thin-film transistor T1 and the second thin-film transistor T2 constitute an array substrate for an LTPO display panel, which has advantages such as low power consumption, self-illumination, and good flexibility. The thickness of each film layer of the first thin-film transistor T1 and the second thin-film transistor T2 can be set within their respective optimal ranges to avoid the problem of incompatibility between the optimal film layer thicknesses of the first thin-film transistor T1 and the second thin-film transistor T2 in the array substrate, thus fully utilizing the optimal performance of the first thin-film transistor T1 and the second thin-film transistor T2 in the array substrate. Specifically, the source 20a of the first thin-film transistor T1 is made of low-temperature polycrystalline silicon, which results in high electron mobility and high switching speed. The active layer 20b of the second thin-film transistor T2 is made of oxide semiconductor, which, due to its high carrier mobility, low deposition temperature, and high transparency, has become the mainstream display panel driving technology.

[0077] Optionally, see Figure 5 The array substrate also includes a planarization layer 14, a fourth via 70, a light-emitting display unit 80, and a pixel defining layer 90. The anode of the light-emitting display unit 80 is connected to the drain 50 of either the first thin-film transistor T1 or the drain 50 of the second thin-film transistor T2 via the fourth via 70. Figure 5 The diagram illustrates, by way of example, a schematic diagram showing the connection between the anode of the organic light-emitting display unit 80 and the drain 50 of the first thin-film transistor T1 via a fourth via 70. Exemplarily, when the light-emitting display panel emits light, under a certain voltage drive, electrons and holes are injected from the cathode and anode of the light-emitting display unit into the light-emitting device layer, respectively. After meeting, they form excitons and excite the light-emitting molecules, which then emit visible light through radiative relaxation.

[0078] Optionally, see Figure 5 It also includes at least one capacitor structure 60, wherein the first electrode of the capacitor structure 60 and the gate 30 are located on the same layer; the second insulating layer 13 includes a stack of a first sub-insulating layer 13a and a second sub-insulating layer 13b; the second electrode of the capacitor structure 60 is located between the first sub-insulating layer 13a and the second sub-insulating layer 13b. For example, Figure 5 Only one capacitor structure 60 is shown in the figure, but the number of capacitor structures 60 included in the array substrate in the embodiments of the present invention includes, but is not limited to, one.

[0079] Specifically, while ensuring the stability of the driving signal, the capacitor structure 60 has the first electrode and the gate 30 located on the same layer. The first electrode and the gate 30 can use the same mask, which reduces the number of masks used in the array substrate fabrication process, thus simplifying the process and reducing costs.

[0080] It should be noted that, in the embodiments of the present invention, "same layer" refers to a layer structure formed by using the same film deposition process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through a single patterning process. Depending on the characteristic pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0081] This invention also provides a display panel. Figure 6 This is a schematic diagram of the structure of a display panel according to an embodiment of the present invention. Figure 6 As shown, the display panel includes any of the array substrates 100 described in the above technical solutions. The display panel provided in this embodiment of the invention includes the array substrates in the above embodiments; therefore, the display panel provided in this embodiment of the invention also has the beneficial effects described in the above embodiments, which will not be repeated here. It should be noted that the display panel provided in this embodiment of the invention can be an organic light-emitting display panel, a quantum dot light-emitting display panel, or a liquid crystal display panel. Exemplarily, the display panel can be any product or component with display function, such as a laptop computer, tablet computer, or monitor.

[0082] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. An array substrate, characterized in that, include: Substrate; At least one thin-film transistor, the thin-film transistor being located on one side of the substrate, the thin-film transistor including an active layer, a gate, a source, and a drain; The active layer includes a source region, a drain region, and a channel region, wherein the source region is connected to the source electrode, and the drain region is connected to the drain electrode; The contact resistance between the source and the source region is less than the contact resistance between the drain and the drain region; A buffer layer, a first insulating layer, and a second insulating layer are sequentially disposed on the substrate. The active layer is disposed on the side of the buffer layer away from the substrate and is covered by the first insulating layer; the gate is disposed on the side of the first insulating layer away from the buffer layer and is covered by the second insulating layer; the source and the drain are disposed on the side of the second insulating layer away from the first insulating layer. The second insulating layer is provided with a first via and a second via, and the source electrode is connected to the source region through the first via; The drain electrode is connected to the drain region through the second via; The number of the first vias is greater than or equal to 2, and different first vias are insulated from each other within the second insulating layer; The number of the first vias is greater than the number of the second vias; The area of ​​the source electrode projected onto the substrate is larger than the area of ​​the drain electrode projected onto the substrate. The area of ​​the source electrode projected onto the substrate is the cross-sectional area of ​​the portion of the source electrode located on the surface of the insulating layer on the substrate, and the area of ​​the drain electrode projected onto the substrate is the cross-sectional area of ​​the portion of the drain electrode located on the surface of the insulating layer on the substrate. The area of ​​each of the first vias projected onto the substrate is greater than the area of ​​the second via projected onto the substrate.

2. The array substrate according to claim 1, characterized in that, The diameter of each of the first vias is larger than the diameter of the second via.

3. The array substrate according to claim 1, characterized in that, The diameter of each of the first vias is equal.

4. The array substrate according to claim 1, characterized in that, It also includes a gate connection electrode, and the second insulating layer further includes at least one third via, through which the gate connection electrode is connected to the gate; The gate connection electrode and the source electrode are located on the same layer and are insulated from each other.

5. The array substrate according to claim 4, characterized in that, The number of the third vias is greater than or equal to 2, and different third vias are insulated from each other within the second insulating layer.

6. The array substrate according to claim 5, characterized in that, The diameters of the third through holes are equal.

7. The array substrate according to any one of claims 1-6, characterized in that, The thin-film transistor includes at least two, and the thin-film transistor includes a first thin-film transistor and a second thin-film transistor; The active layer of the first thin-film transistor is low-temperature polycrystalline silicon, and the active layer of the second thin-film transistor is oxide semiconductor.

8. The array substrate according to claim 7, characterized in that, It also includes at least one capacitor structure, wherein the first electrode of the capacitor structure and the gate are located on the same layer; The second insulating layer comprises a stack of a first sub-insulating layer and a second sub-insulating layer; The second electrode of the capacitor structure is located between the first sub-insulating layer and the second sub-insulating layer.

9. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-8.

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