Semiconductor device and method for manufacturing the same

Abstract

The present invention discloses a semiconductor device and a manufacturing method thereof, wherein the semiconductor device includes a substrate, a metal oxide semiconductor layer, a first gate, a source electrode and a drain electrode. The material of the metal oxide semiconductor layer includes at least one of indium zinc oxide, indium tungsten oxide, indium tungsten zinc oxide, indium zinc tin oxide, indium gallium tin oxide and indium gallium zinc tin oxide. The metal oxide semiconductor layer includes a first doping region, a second doping region, a channel region located between the first doping region and the second doping region, a first crystal region located in the first doping region, and a second crystal region located in the second doping region. The crystallinity of the first crystal region and the second crystal region is greater than that of the channel region. The source electrode and the drain electrode are electrically connected to the first crystal region and the second crystal region, respectively.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and in particular to a semiconductor device including a metal oxide semiconductor layer and a manufacturing method thereof. Background Art

[0002] At present, common thin film transistors usually use amorphous silicon semiconductors as channels, wherein amorphous silicon semiconductors are widely used in various thin film transistors due to their simple manufacturing process and low cost.

[0003] Indium gallium zinc oxide (IGZO) has the advantages of small area and high carrier mobility, so it is regarded as an important new semiconductor material. However, in transistors made of IGZO, the contact between the electrode and IGZO is poor, which affects the current flow that can pass through the transistor. Therefore, a method that can solve the above problems is urgently needed. Summary of the invention

[0004] The invention provides a semiconductor device, which can improve the problem of poor contact between a metal oxide semiconductor layer and a source electrode and between the metal oxide semiconductor layer and a drain electrode.

[0005] The invention provides a method for manufacturing a semiconductor device, which can improve the problem of poor contact between a metal oxide semiconductor layer and a source electrode and between the metal oxide semiconductor layer and a drain electrode.

[0006] At least one embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate, a metal oxide semiconductor layer, a first gate, a source and a drain. The metal oxide semiconductor layer is located on the substrate. The material of the metal oxide semiconductor layer includes at least one of indium zinc oxide, indium tungsten oxide, indium tungsten zinc oxide, indium zinc tin oxide, indium gallium tin oxide and indium gallium zinc tin oxide. The metal oxide semiconductor layer includes a first doping region, a second doping region, a channel region between the first doping region and the second doping region, a first crystalline region in the first doping region, and a second crystalline region in the second doping region. The crystallinity of the first crystalline region and the second crystalline region is greater than the crystallinity of the channel region. The carrier mobility of the channel region is 30cm 2 / Vs to 100cm 2 / Vs, and the indium concentration in the channel region is 25mol% to 40mol%. The first gate overlaps the channel region of the metal oxide semiconductor layer. The source and the drain are electrically connected to the first crystal region and the second crystal region respectively.

[0007] At least one embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: forming a metal oxide layer on a substrate, wherein the material of the metal oxide layer comprises at least one of indium zinc oxide, indium tungsten oxide, indium tungsten zinc oxide, indium zinc tin oxide, indium gallium tin oxide and indium gallium zinc tin oxide; forming a first gate, wherein the first gate overlaps the metal oxide layer; performing a doping process on the metal oxide layer to form a doped metal oxide layer; forming a source and a drain, wherein the source and the drain are respectively connected to the doped metal oxide layer; performing an annealing process on the doped metal oxide layer to form a metal oxide semiconductor layer, wherein the metal oxide semiconductor layer comprises a first doping region, a second doping region, a channel region located between the first doping region and the second doping region, a first crystalline region located in the first doping region, and a second crystalline region located in the second doping region, wherein the crystallinity of the first crystalline region and the second crystalline region is greater than that of the channel region, wherein the carrier mobility of the channel region is 30 cm 2 / Vs to 100cm 2 / Vs, and the indium concentration in the channel region is 25 mol% to 40 mol%. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0009] Figure 1B yes Figure 1A A partial top view schematic diagram of a semiconductor device;

[0010] FIG. 2A to FIG. 2E yes Figure 1A A schematic cross-sectional view of a method for manufacturing a semiconductor device;

[0011] Figure 3 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0012] FIG. 4A to FIG. 4D yes Figure 3 A schematic cross-sectional view of a method for manufacturing a semiconductor device;

[0013] Figure 5 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0014] Figure 6 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0015] Fig. 7A is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0016] Figure 7B yes Fig. 7AA partial top view schematic diagram of a semiconductor device;

[0017] Figure 8 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0018] Fig. 9 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0019] Fig.10 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0020] Fig.11A is a high-resolution transmission electron microscope photograph of a semiconductor device according to an embodiment of the present invention;

[0021] Fig. 11B yes Fig.11A Nanobeam electron diffraction photograph of region R;

[0022] Fig. 12A is a high-resolution transmission electron microscope photograph of a semiconductor device according to an embodiment of the present invention;

[0023] Fig. 12B yes Fig. 12A Nanobeam electron diffraction (NBED) photograph of region R.

[0024] Explanation of symbols

[0025] 10,20,30,40,50:Semiconductor devices

[0026] 100:Substrate

[0027] 102: Dielectric layer

[0028] 110: Gate dielectric layer

[0029] 110a, 120a: dielectric layer

[0030] 120: interlayer dielectric layer

[0031] 210: Metal oxide semiconductor layer

[0032] 210': doped metal oxide layer

[0033] 210”: Metal oxide layer

[0034] 212: First crystallization zone

[0035] 214: first doping region

[0036] 215: Channel area

[0037] 216: second doping region

[0038] 218: Second crystallization zone

[0039] 220,220A: First gate

[0040] 220B: Second gate

[0041] 242: Source

[0042] 243: First oxide layer

[0043] 244: Drain

[0044] 245: Second oxide layer

[0045] P: Doping process

[0046] R: Region

[0047] TH1: First through hole

[0048] TH2: Second through hole DETAILED DESCRIPTION

[0049] Figure 1A is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 1B yes Figure 1A A partial top view schematically showing a semiconductor device of FIG. Figure 1B The dielectric layer 102 , the metal oxide semiconductor layer 210 and the first gate 220 are shown, and other components are omitted.

[0050] Please refer to Figure 1A and Figure 1B The semiconductor device 10 includes a substrate 100, a metal oxide semiconductor layer 210, a first gate 220, a source 242, and a drain 244. In the present embodiment, the semiconductor device 10 further includes a first oxide layer 243, a second oxide layer 245, a dielectric layer 102, a gate dielectric layer 110, and an interlayer dielectric layer 120.

[0051] The material of the substrate 100 is, for example, glass, quartz, organic polymer, or opaque / reflective material (eg, conductive material, metal, wafer, ceramic or other applicable material) or other applicable materials. In some embodiments, the substrate 100 includes a hard substrate or a flexible substrate.

[0052] The dielectric layer 102 is formed on the substrate 100. The dielectric layer 102 includes a single layer or a multilayer structure. In some embodiments, the material of the dielectric layer 102 is, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, organic insulating material or other suitable insulating material. In some embodiments, other metal materials (not shown) or light absorbing materials (not shown) are further included between the dielectric layer 102 and the substrate 100, but the present invention is not limited thereto.

[0053] The metal oxide semiconductor layer 210 is located on the substrate 100. In the present embodiment, the metal oxide semiconductor layer 210 is formed on the dielectric layer 102. The metal oxide semiconductor layer 210 includes a first doping region 214, a second doping region 216, a channel region 215 located between the first doping region 214 and the second doping region 216, a first crystalline region 212 located in the first doping region 214, and a second crystalline region 218 located in the second doping region 216. The crystallinity of the first crystalline region 212 and the second crystalline region 218 is greater than the crystallinity of the channel region 215. In some embodiments, the crystallinity of the first crystalline region 212 and the second crystalline region 218 is greater than the crystallinity of the first doping region 214 and the second doping region 216. In some embodiments, the channel region 215, the first doping region 214, and the second doping region 216 are all amorphous.

[0054] In this embodiment, the first crystalline region 212 is surrounded by the first doped region 214 and separated from the sidewall of the metal oxide semiconductor layer 210 . Similarly, the second crystalline region 218 is surrounded by the second doped region 216 and separated from the sidewall of the metal oxide semiconductor layer 210 .

[0055] In some embodiments, the first doped region 214 , the second doped region 216 , the first crystalline region 212 , and the second crystalline region 218 are hydrogen-doped regions, and the hydrogen concentrations of the first doped region 214 , the second doped region 216 , the first crystalline region 212 , and the second crystalline region 218 are greater than the hydrogen concentration of the channel region 215 .

[0056] The material of the metal oxide semiconductor layer 210 includes at least one of indium zinc oxide (IZO), indium tungsten oxide (IWO), indium tungsten zinc oxide (IWZO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO) and indium gallium zinc tin oxide (IGZTO). In the present embodiment, the metal oxide semiconductor layer 210 has a higher carrier mobility than the general indium gallium zinc oxide (IGZO).

[0057] In some embodiments, the carrier mobility of the first crystalline region 212 and the second crystalline region 218 is greater than the carrier mobility of the first doped region 214 and the second doped region 216 , and the carrier mobility of the first doped region 214 and the second doped region 216 is greater than the carrier mobility of the channel region 215 .

[0058] In some embodiments, the indium concentration of the first crystalline region 212 and the second crystalline region 218 is greater than the indium concentration of the first doping region 214 and the second doping region 216 and the indium concentration of the channel region 215. In some embodiments, the indium concentration of the first crystalline region 212 and the second crystalline region 218 is 30 mol% to 50 mol%, the indium concentration of the first doping region 214 and the second doping region 216 is 25 mol% to 40 mol%, and the indium concentration of the channel region 215 is 25 mol% to 40 mol%.

[0059] In some embodiments, the metal oxide semiconductor layer 210 has a thickness of 100 angstroms to 500 angstroms.

[0060] The gate dielectric layer 110 is formed on the metal oxide semiconductor layer 210. The gate dielectric layer 110 is a single layer or multi-layer structure. In the present embodiment, the gate dielectric layer 110 covers the top surface and the side surface of the metal oxide semiconductor layer 210, and has a through hole overlapping a portion of the first doping region 214 and a portion of the second doping region 216. In some embodiments, the material of the gate dielectric layer 110 is, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, organic insulating material or other suitable insulating material. In some embodiments, the thickness of the gate dielectric layer 110 is 50 nanometers to 300 nanometers.

[0061] The first gate 220 is formed on the gate dielectric layer 110. The first gate 220 overlaps the channel region 215 of the metal oxide semiconductor layer 210. The metal oxide semiconductor layer 210 is located between the first gate 220 and the substrate 100. In some embodiments, the material of the first gate 220 includes metal, such as silver, copper, molybdenum, aluminum, titanium, gold, platinum, or alloys of the above metals, or stacked layers of the above metals, or other materials.

[0062] The interlayer dielectric layer 120 is formed on the gate dielectric layer 110 and has a through hole overlapping a portion of the first doped region 214 and a portion of the second doped region 216. The interlayer dielectric layer 120 covers the first gate 220. In some embodiments, the material of the interlayer dielectric layer 120 is, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, organic insulating material or other suitable insulating material or a stacked layer of the above materials. In some embodiments, the thickness of the interlayer dielectric layer 120 is 50 nanometers to 600 nanometers.

[0063] The source 242 and the drain 244 are formed in the interlayer dielectric layer 120 and filled in the first through hole TH1 and the second through hole TH2 of the interlayer dielectric layer 120 and the gate dielectric layer 110 to respectively electrically connect the first crystalline region 212 and the second crystalline region 214 of the metal oxide semiconductor layer 210. The first through hole TH1 overlaps the first crystalline region 212 in the normal direction of the top surface of the substrate 100, and the second through hole TH2 overlaps the second crystalline region 214 in the normal direction of the top surface of the substrate 100. In some embodiments, the vertical projection area of ​​the bottom of the first through hole TH1 on the substrate 100 is smaller than the vertical projection area of ​​the first crystalline region 212 on the substrate 100, and the vertical projection area of ​​the bottom of the second through hole TH2 on the substrate 100 is smaller than the vertical projection area of ​​the second crystalline region 218 on the substrate 100.

[0064] The first oxide layer 243 is located between the source 242 and the first crystalline region 212 , and the second oxide layer 245 is located between the drain 244 and the second crystalline region 218 .

[0065] In some embodiments, the material of the source 242 and the drain 244 includes titanium. For example, the source 242 and the drain 244 are each titanium metal, a stacked layer of titanium metal / aluminum metal / titanium metal, a titanium alloy, or other suitable materials. In some embodiments, the first oxide layer 243 and the second oxide layer 245 include oxygen elements and metal elements (such as titanium elements) in the source 242 and the drain 244. For example, the first oxide layer 243 and the second oxide layer 245 include titanium oxide.

[0066] Based on the above, the presence of the first crystalline region 212 and the second crystalline region 218 can improve the contact between the source 242 and the metal oxide semiconductor layer 210 and the contact between the drain 244 and the metal oxide semiconductor layer 210, thereby increasing the amount of current passing through the semiconductor device 10. In some embodiments, the first oxide layer 243 and the second oxide layer 245 are non-conductive materials, and the source 242 and the metal oxide semiconductor layer 210 and the drain 244 and the metal oxide semiconductor layer 210 have ohmic contact through the tunneling effect in the first oxide layer 243 and the second oxide layer 245.

[0067] FIG. 2A to FIG. 2E yes Figure 1A A schematic cross-sectional view of a method for manufacturing a semiconductor device.

[0068] Please refer to Figure 2A , forming a metal oxide layer 210" on the substrate 100. In the present embodiment, the metal oxide layer 210" is formed on the dielectric layer 102. The material of the metal oxide layer 210" includes at least one of indium zinc oxide, indium tungsten oxide, indium tungsten zinc oxide, indium zinc tin oxide, indium gallium tin oxide and indium gallium zinc tin oxide.

[0069] Please refer to Figure 2B , forming a gate dielectric layer 110 on the metal oxide layer 210 ″. Then, forming a first gate 220 on the gate dielectric layer 110 , wherein the first gate 220 overlaps the metal oxide layer 210 ″ in the normal direction of the top surface of the substrate 100 .

[0070] Please refer to Figure 2C , a doping process P is performed on the metal oxide layer 210″ to form a doped metal oxide layer 210′, wherein the doped metal oxide layer 210′ ​​includes a first doping region 214, a second doping region 216 and a channel region 215. In the present embodiment, a doping process P is performed on the metal oxide layer 210″ using the first gate 220 as a mask, so that the channel region 215 overlaps the first gate 220. In some embodiments, the doping process P includes a hydrogen plasma process, an ion implantation process, or other suitable processes.

[0071] Please refer to Figure 2D An interlayer dielectric layer 120 is formed on the gate dielectric layer 110, and a first through hole TH1 and a second through hole TH2 are formed in the interlayer dielectric layer 120 and the gate dielectric layer 110. The first through hole TH1 and the second through hole TH2 overlap the first doping region 214 and the second doping region 216 of the doped metal oxide layer 210', respectively.

[0072] It should be noted that, although in this embodiment, by Figure 2C The doping process P shown is to dope the metal oxide layer 210 ″, but the present invention is not limited thereto. In other embodiments, the interlayer dielectric layer 120 includes hydrogen elements, and after the interlayer dielectric layer 120 is formed, the hydrogen elements in the interlayer dielectric layer 120 are diffused into the metal oxide layer 210 ″ by heat treatment to form a doped metal oxide layer 210 ′, and then the first through hole TH1 and the second through hole TH2 are formed in the interlayer dielectric layer 120 and the gate dielectric layer 110.

[0073] Please refer to Figure 2E , forming a source 242 and a drain 244. The source 242 and the drain 244 are respectively filled into the first through hole TH1 and the second through hole TH2, and the source 242 and the drain 244 are respectively connected to the first doping region 214 and the second doping region 216 of the doped metal oxide layer 210'.

[0074] While forming the source 242 and the drain 244 or after forming the source 242 and the drain 244, an annealing process is performed on the doped metal oxide layer 210' to form the metal oxide semiconductor layer 210, such as Figure 1A Specifically, the source 242 and the drain 244 react with the oxygen in the first doping region 214 and the oxygen in the second doping region 216 during the annealing process, and form a first crystalline region 212 and a second crystalline region 218 with a lower oxygen concentration in the first doping region 214 and the second doping region 216, respectively. The crystallinity of the first crystalline region 212 and the second crystalline region 218 is greater than the crystallinity of the channel region 215. In some embodiments, the annealing process includes heating the doped metal oxide layer 210' at a temperature range of 250°C to 500°C for 0.5 hours to 4 hours.

[0075] During the annealing process, the oxygen element in the doped metal oxide layer 210' reacts with the source 242 and the drain 244 to form a first oxide layer 243 and a second oxide layer 245, wherein the first oxide layer 243 is located between the source 242 and the first crystal region 212, and the second oxide layer 245 is located between the drain 244 and the second crystal region 218. At this point, the semiconductor device 10 is substantially completed.

[0076] Figure 3 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. It must be noted here that Figure 3 The implementation examples are used Figure 1A and Figure 1BThe component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0077] Figure 3 The semiconductor device 20 and Figure 1A The main difference of the semiconductor device 10 is that the interlayer dielectric layer 120 of the semiconductor device 20 contacts the first doped region 214 and the second doped region 216 of the metal oxide semiconductor layer 210, and the first through hole TH1 and the second through hole TH2 are formed in the interlayer dielectric layer 120 but not in the gate dielectric layer 110.

[0078] FIG. 4A to FIG. 4D yes Figure 3 A schematic cross-sectional view of a method for manufacturing a semiconductor device.

[0079] Please refer to Figure 4A , continued Figure 2B In the structure shown, the gate dielectric layer 110 is patterned using the first gate electrode 220 as a mask to expose the metal oxide layer 210.

[0080] Please refer to Figure 4B , a doping process P is performed on the metal oxide layer 210″ to form a doped metal oxide layer 210′, wherein the doped metal oxide layer 210′ ​​includes a first doping region 214, a second doping region 216 and a channel region 215. In the present embodiment, a doping process P is performed on the metal oxide layer 210″ using the first gate 220 as a mask, so that the channel region 215 overlaps the first gate 220. In some embodiments, the doping process P includes a hydrogen plasma process, an ion implantation process, or other suitable processes.

[0081] Please refer to Figure 4C An interlayer dielectric layer 120 is formed on the metal oxide layer 210', and a first through hole TH1 and a second through hole TH2 are formed in the interlayer dielectric layer 120. The first through hole TH1 and the second through hole TH2 overlap the first doping region 214 and the second doping region 216 of the doped metal oxide layer 210', respectively.

[0082] It should be noted that, although in this embodiment, by Figure 4BThe doping process P shown is to dope the metal oxide layer 210 ″, but the present invention is not limited thereto. In other embodiments, the interlayer dielectric layer 120 includes hydrogen elements, and after the interlayer dielectric layer 120 is formed, the hydrogen elements in the interlayer dielectric layer 120 are diffused into the metal oxide layer 210 ″ by heat treatment to form a doped metal oxide layer 210 ′, and then the first through hole TH1 and the second through hole TH2 are formed in the interlayer dielectric layer 120.

[0083] Please refer to Figure 4D , forming a source electrode 242 and a drain electrode 244. The source electrode 242 and the drain electrode 244 are respectively filled into the first through hole TH1 and the second through hole TH2, and the source electrode 242 and the drain electrode 244 are respectively connected to the doped metal oxide layer 210'.

[0084] While forming the source 242 and the drain 244 or after forming the source 242 and the drain 244, an annealing process is performed on the doped metal oxide layer 210' to form the metal oxide semiconductor layer 210, such as Figure 3 Specifically, the source 242 and the drain 244 react with the oxygen in the first doping region 214 and the oxygen in the second doping region 216 during the annealing process, and form a first crystalline region 212 and a second crystalline region 218 with a lower oxygen concentration in the first doping region 214 and the second doping region 216, respectively. The crystallinity of the first crystalline region 212 and the second crystalline region 218 is greater than the crystallinity of the channel region 215. In some embodiments, the annealing process includes heating the doped metal oxide layer 210' at a temperature range of 250°C to 500°C for 0.5 hours to 4 hours.

[0085] During the annealing process, the oxygen element in the doped metal oxide layer 210' reacts with the source 242 and the drain 244 to form a first oxide layer 243 and a second oxide layer 245, wherein the first oxide layer 243 is located between the source 242 and the first crystalline region 212, and the second oxide layer 245 is located between the drain 244 and the second crystalline region 218. At this point, the semiconductor device 20 is substantially completed.

[0086] Figure 5 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. It must be noted here that Figure 5 The implementation examples are used Figure 1A and Figure 1B The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0087] Figure 5 The semiconductor device 30 and Figure 1A The main difference between the semiconductor device 10 and the semiconductor device 30 is that the semiconductor device 10 is a top-gate thin film transistor, while the semiconductor device 30 is a bottom-gate thin film transistor.

[0088] Please refer to Figure 5 , the first gate 220 of the semiconductor device 30 is located between the metal oxide semiconductor layer 210 and the substrate 100 .

[0089] Please refer to Figure 5 The first gate electrode 220 is formed on the substrate 100. The gate dielectric layer 110 is formed on the first gate electrode 220. The metal oxide semiconductor layer 210 is formed on the gate dielectric layer 110. The dielectric layer 110a is formed on the metal oxide semiconductor layer 210.

[0090] Figure 6 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. It must be noted here that Figure 6 The implementation examples are used Figure 1A and Figure 1B The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0091] Figure 6 The semiconductor device 40 and Figure 1A The main difference between the semiconductor device 10 and the semiconductor device 40 is that the semiconductor device 10 is a top-gate thin film transistor, while the semiconductor device 40 is a double-gate thin film transistor.

[0092] Please refer to Figure 6 The semiconductor device 40 includes a first gate 220A and a second gate 220B, and the metal oxide semiconductor layer 210 is located between the first gate 220A and the second gate 220B. The dielectric layer 110a is located between the metal oxide semiconductor layer 210 and the first gate 220A. The gate dielectric layer 110 is located between the metal oxide semiconductor layer 210 and the second gate 220B.

[0093] Fig. 7A is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 7B yes Fig. 7A A partial top view schematically showing a semiconductor device of FIG. Figure 7B The dielectric layer 102, the metal oxide semiconductor layer 210 and the first gate 220 are shown, and other components are omitted. It must be explained here that Fig. 7A and Figure 7B The implementation examples are used Figure 1A and Figure 1B The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0094] Fig. 7A The semiconductor device 50 and Figure 1A The main difference between the semiconductor device 10 and the semiconductor device 50 is that the source 242 and the drain 244 of the semiconductor device 50 overlap a portion of the sidewall of the metal oxide semiconductor layer 210 .

[0095] Please refer to Fig. 7A and Figure 7B , the first through hole TH1 and the second through hole TH2 of the interlayer dielectric layer 120 and the gate dielectric layer 110 overlap a portion of the sidewall of the metal oxide semiconductor layer 210 in the normal direction of the top surface of the substrate 100. In the present embodiment, the first crystal region 212 is located on a portion of the sidewall of the metal oxide semiconductor layer 210, and the second crystal region 218 is located on a portion of the sidewall of the metal oxide semiconductor layer 210. The first oxide layer 243 and the second oxide layer 245 cover a portion of the sidewall of the metal oxide semiconductor layer 210.

[0096] Figure 8 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. It must be noted here that Figure 8 The implementation examples are used Figure 5 The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0097] Figure 8 The semiconductor device 60 and Figure 5 The main difference between the semiconductor device 30 and the semiconductor device 60 is that the source 242 and the drain 244 of the semiconductor device 60 are formed by a back channel etch (BCE) process.

[0098] Please refer to Figure 8 The method for manufacturing the source 242 and the drain 244 includes, for example, depositing a metal material on the metal oxide semiconductor layer 210 , then etching the metal material to form the source 242 and the drain 244 separated from each other. Finally, a dielectric layer 120 a is formed on the source 242 and the drain 244 .

[0099] Fig. 9 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. It must be noted here that Fig. 9 The implementation examples are used Figure 8The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0100] Fig. 9 The semiconductor device 70 and Figure 8 The main difference between the semiconductor device 60 and the semiconductor device 70 is that the semiconductor device 70 further includes a first etch stop layer ESL1.

[0101] Please refer to Fig. 9 Before forming the source 242 and the drain 244, a first etching stop layer ESL1 is formed on the channel region 215 of the metal oxide semiconductor layer 210, thereby preventing the etching process used when forming the source 242 and the drain 244 from damaging the channel region 215. In some embodiments, the source 242 and the drain 244 cover a portion of the first etching stop layer ESL1. In some embodiments, the first etching stop layer ESL1 also covers a portion of the first doped region 214 and the second doped region 216. In some embodiments, the first crystalline region 212 and the second crystalline region 218 extend below the first etching stop layer ESL1.

[0102] Fig.10 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. It must be noted here that Fig.10 The implementation examples are used Fig. 9 The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0103] Fig.10 The semiconductor device 80 and Fig. 9 The main difference between the semiconductor device 70 and the semiconductor device 80 is that the semiconductor device 80 further includes a second etch stop layer ESL2.

[0104] Please refer to Fig.10 Before forming the source 242 and the drain 244, a first etch stop layer ESL1 and a second etch stop layer ESL2 are formed on the channel region 215 of the metal oxide semiconductor layer 210, thereby preventing the etching process used in forming the source 242 and the drain 244 from damaging the channel region 215. In some embodiments, the first etch stop layer ESL1 and the second etch stop layer ESL2 also cover a portion of the first doped region 214 and the second doped region 216. In some embodiments, the first crystalline region 212 and the second crystalline region 218 extend below the first etch stop layer ESL1 and the second etch stop layer ESL2.

[0105] Fig.11A is a high-resolution transmission electron microscope photograph of a semiconductor device according to an embodiment of the present invention. Fig. 11B yes Fig.11A Nanobeam electron diffraction photograph of region R. Fig. 12A is a high-resolution transmission electron microscope photograph of a semiconductor device according to an embodiment of the present invention. Fig. 12B yes Fig. 12A Nanobeam electron diffraction photograph of region R.

[0106] For example, Fig.11A and Fig. 11B Corresponding Figure 1A The semiconductor device 10 is located around the channel region 215, and Fig.11A and Fig. 11B Corresponding Figure 1A The semiconductor device 10 is located around the first oxide layer 243 or the second oxide layer 245 .

[0107] Depend on Fig. 11B It can be seen that the channel region 215 of the metal oxide semiconductor layer 210 is amorphous. Fig. 12B It can be known that the first crystalline region 212 and the second crystalline region 218 of the metal oxide semiconductor layer 210 are crystalline. In other words, at least part of the crystal lattices in the first crystalline region 212 and the second crystalline region 218 are arranged along the same direction.

[0108] In summary, the present invention can improve the contact between the source and the metal oxide semiconductor layer and the contact between the drain and the metal oxide semiconductor layer through the presence of the first crystal region and the second crystal region, thereby increasing the amount of current passing through the semiconductor device.

Claims

1. A semiconductor device comprising: substrate; A metal oxide semiconductor layer is located on the substrate, and the material of the metal oxide semiconductor layer includes at least one of indium zinc oxide, indium tungsten oxide, indium tungsten zinc oxide, indium zinc tin oxide, indium gallium tin oxide and indium gallium zinc tin oxide, and the metal oxide semiconductor layer includes a first doping region, a second doping region, a channel region between the first doping region and the second doping region, a first crystalline region located in the first doping region, and a second crystalline region located in the second doping region, and the crystallinity of the first crystalline region and the second crystalline region is greater than the crystallinity of the channel region, wherein the carrier mobility of the channel region is 30cm 2 / Vs to 100cm 2 / Vs, and the indium concentration in the channel region is 25mol% to 40mol%; A first gate, overlapping the channel region of the metal oxide semiconductor layer; A source electrode and a drain electrode are electrically connected to the first crystalline region and the second crystalline region, respectively, wherein the indium concentration of the first crystalline region and the second crystalline region is greater than the indium concentration of the channel region; A first oxide layer is located between the source electrode and the first crystalline region; A second oxide layer is located between the drain and the second crystalline region, wherein the first oxide layer and the second oxide layer are non-conductive materials, and the first oxide layer and the second oxide layer contain oxygen elements and metal elements in the source and the drain; as well as The dielectric layer is located on the metal oxide semiconductor layer and has a first through hole overlapping the first crystal region and a second through hole overlapping the second crystal region, wherein the source electrode and the drain electrode are respectively filled in the first through hole and the second through hole, and wherein the vertical projection area of ​​the bottom of the first through hole on the substrate is smaller than the vertical projection area of ​​the first crystal region on the substrate, and the vertical projection area of ​​the bottom of the second through hole on the substrate is smaller than the vertical projection area of ​​the second crystal region on the substrate, and the first oxide layer and the second oxide layer are respectively located in the first through hole and the second through hole. 2 . The semiconductor device as claimed in claim 1 , wherein at least a portion of crystal lattices in the first crystal region and the second crystal region are arranged along the same direction. 3 . The semiconductor device as claimed in claim 1 , wherein the first gate is located between the metal oxide semiconductor layer and the substrate, or the metal oxide semiconductor layer is located between the first gate and the substrate.

4. The semiconductor device according to claim 1, further comprising: The second gate is provided, wherein the metal oxide semiconductor layer is located between the first gate and the second gate. The semiconductor device as claimed in claim 1 , wherein the channel region is amorphous. 6 . The semiconductor device as claimed in claim 1 , wherein the metal oxide semiconductor layer has a thickness of 100 angstroms to 500 angstroms. 7 . The semiconductor device as claimed in claim 1 , wherein materials of the source and the drain include titanium. 8 . The semiconductor device as claimed in claim 1 , wherein the first oxide layer and the second oxide layer cover a portion of a sidewall of the metal oxide semiconductor layer. 9 . The semiconductor device as claimed in claim 1 , wherein the first crystal region and the second crystal region are separated from a sidewall of the metal oxide semiconductor layer. 10 . The semiconductor device as claimed in claim 1 , wherein the hydrogen concentrations of the first doped region, the second doped region, the first crystalline region, and the second crystalline region are greater than the hydrogen concentration of the channel region.

11. A method for manufacturing a semiconductor device, comprising: Forming a metal oxide layer on the substrate, wherein the material of the metal oxide layer includes at least one of indium zinc oxide, indium tungsten oxide, indium tungsten zinc oxide, indium zinc tin oxide, indium gallium tin oxide and indium gallium zinc tin oxide; forming a first gate, the first gate overlapping the metal oxide layer; Performing a doping process on the metal oxide layer to form a doped metal oxide layer; forming a dielectric layer on the metal oxide layer, and forming a first through hole and a second through hole in the dielectric layer; Forming a source electrode and a drain electrode, filling the first through hole and the second through hole respectively, wherein the source electrode and the drain electrode are respectively connected to the doped metal oxide layer; as well as An annealing process is performed on the doped metal oxide layer to form a metal oxide semiconductor layer, wherein the metal oxide semiconductor layer includes a first doping region, a second doping region, a channel region located between the first doping region and the second doping region, a first crystallization region located in the first doping region, and a second crystallization region located in the second doping region, and the crystallinity of the first crystallization region and the second crystallization region is greater than the crystallinity of the channel region, wherein the carrier mobility of the channel region is 30 cm 2 / Vs to 100cm 2 / Vs, and the indium concentration of the channel region is 25mol% to 40mol%, wherein the indium concentrations of the first crystalline region and the second crystalline region are greater than the indium concentration of the channel region, wherein the first through hole overlaps the first crystallized region, the second through hole overlaps the second crystallized region, a vertical projection area of ​​the bottom of the first through hole on the substrate is smaller than a vertical projection area of ​​the first crystallized region on the substrate, and a vertical projection area of ​​the bottom of the second through hole on the substrate is smaller than a vertical projection area of ​​the second crystallized region on the substrate, During the annealing process, the oxygen element in the doped metal oxide layer reacts with the source and the drain to form a first oxide layer and a second oxide layer, wherein the first oxide layer is located between the source and the first crystal region, and the second oxide layer is located between the drain and the second crystal region, the first oxide layer and the second oxide layer are located in the first through hole and the second through hole respectively, the first oxide layer and the second oxide layer themselves are non-conductive materials, and the first oxide layer and the second oxide layer contain the metal elements in the source and the drain. 12 . The method for manufacturing a semiconductor device as claimed in claim 11 , wherein the annealing process comprises heating the doped metal oxide layer at a temperature ranging from 250° C. to 500° C. for 0.5 hour to 4 hours.

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