Transistor, manufacturing method thereof and driving substrate

Abstract

The application provides a transistor, a manufacturing method thereof and a driving substrate, wherein the transistor comprises an active layer, a gate insulating layer, a gate electrode and a source-drain electrode which are sequentially arranged on a substrate, and the source-drain electrode comprises a source electrode and a drain electrode which are arranged in the same layer; wherein in the area where the gate electrode overlaps with the active layer, the gate insulating layer comprises a first part with a first thickness and a second part with a second thickness, the first part extends to the side close to the source electrode, the second part extends to the side close to the drain electrode, and the second thickness is smaller than the first thickness.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a transistor, a manufacturing method thereof and a driving substrate. BACKGROUND

[0002] Currently, the driving circuit of an organic electroluminescent display panel (OLED) usually adopts low temperature polysilicon (LTPS) as the channel of a driving thin film transistor (DTFT). The LTPS has a higher mobility than a-Si, which can accelerate the charging speed of the pixel capacitor. However, the source-drain voltage of the DTFT is usually large, about 2V-3V, during the light-emitting stage of the light-emitting device, especially in the high-brightness state, which increases the power consumption. SUMMARY

[0003] The present application provides a transistor, a manufacturing method thereof and a driving substrate, which are used to reduce power consumption.

[0004] In a first aspect, an embodiment of the present application provides a transistor, comprising:

[0005] An active layer, a gate insulating layer, a gate electrode and a source-drain electrode are sequentially arranged on a substrate, the source-drain electrode comprises a source electrode and a drain electrode arranged in the same layer; wherein:

[0006] In a region where the gate electrode overlaps with the active layer, the gate insulating layer comprises a first part with a first thickness and a second part with a second thickness, the first part extends to the side close to the source electrode, and the second part extends to the side close to the drain electrode, and the second thickness is smaller than the first thickness.

[0007] In a possible implementation, the gate insulating layer is provided with an interface charge layer on the side of the second part close to the active layer.

[0008] In a possible implementation, the interface charge layer is negatively charged.

[0009] In a possible implementation, the interface charge layer is a charge layer formed by fluorine ions or oxygen ions.

[0010] In a possible implementation, the area of the orthographic projection of the first part on the substrate is equal to the area of the orthographic projection of the second part on the substrate.

[0011] In a second aspect, the embodiments of the present application further provide a driving substrate, comprising: a driving circuit, the driving circuit comprising a driving transistor, the driving transistor being the transistor according to any one of the above.

[0012] In a possible implementation, the driving circuit further comprises at least one switching transistor, a gate insulating layer between the gate and the active layer of each switching transistor is arranged in the same layer as the gate insulating layer in the driving transistor, and the corresponding gate insulating layer between the gate and the active layer of each switching transistor has the first thickness.

[0013] In a possible implementation, the driving transistor and each switching transistor are polycrystalline silicon transistors.

[0014] In a third aspect, the embodiments of the present application further provide a manufacturing method of a transistor, comprising:

[0015] forming a pattern of an active layer on a substrate;

[0016] forming a pattern of a gate insulating layer on a side of the active layer away from the substrate, the gate insulating layer comprising a first part having a first thickness and a second part having a second thickness, the first part extending to a side close to a source to be formed, and the second part extending to a side close to a drain to be formed, the second thickness being smaller than the first thickness;

[0017] forming a pattern of the gate on a side of the gate insulating layer away from the substrate;

[0018] forming an interlayer insulating layer on a side of the gate away from the substrate;

[0019] forming a pattern of a source and a drain penetrating through the interlayer insulating layer and coupled with the active layer.

[0020] In a possible implementation, forming a pattern of a gate insulating layer on a side of the active layer away from the substrate comprises:

[0021] depositing the gate insulating layer with the first thickness on the side of the active layer away from the substrate;

[0022] coating a photoresist on the gate insulating layer;

[0023] patterning the photoresist by using a patterning process, removing the photoresist at a position corresponding to the second part of the gate insulating layer to form a pattern of the photoresist;

[0024] etching the gate insulating layer at the position corresponding to the second part by a third thickness according to the pattern of the photoresist, wherein a difference between the first thickness and the third thickness is the second thickness.

[0025] forming a pattern of the gate insulating layer.

[0026] In one possible implementation, after forming the pattern of the gate insulating layer on the side of the active layer away from the substrate, the method further comprises:

[0027] forming an interface charge layer on the side of the second portion close to the active layer.

[0028] In one possible implementation, forming the interface charge layer on the side of the second portion close to the active layer comprises:

[0029] implanting fluorine ions or oxygen ions with an energy range of 15 keV to 50 keV and a dose range of 0.1E12 ions / cm2 to 3E12 ions / cm2 according to the pattern of the photoresist, so that the gate insulating layer forms the interface charge layer on the side of the second portion close to the active layer.

[0030] In one possible implementation, forming the interface charge layer on the side of the second portion close to the active layer comprises:

[0031] applying a positive bias to the gate and a negative bias to the drain, so that the gate insulating layer forms the interface charge layer on the side of the second portion close to the active layer.

[0032] The present application has the following advantages:

[0033] The present application provides a transistor, a manufacturing method thereof and a driving substrate. The transistor comprises an active layer, a gate insulating layer, a gate and a source / drain electrode which are sequentially arranged on a substrate, and the source / drain electrode comprises a source electrode and a drain electrode which are arranged in the same layer. In the region where the gate overlaps with the active layer, the gate insulating layer comprises a first portion with a first thickness and a second portion with a second thickness, the first portion extends to the side close to the source electrode, the second portion extends to the side close to the drain electrode, and the second thickness is smaller than the first thickness. The thickness of the second portion of the gate insulating layer which extends to the side close to the drain electrode is smaller than the thickness of the first portion which extends to the side close to the source electrode, so that the gate electric field control ability of the region corresponding to the second portion is enhanced. During the operation of the transistor, as the source / drain voltage increases, the channel conductive layer can quickly enter the pinch-off state, and the corresponding output curve quickly enters the saturation region, so that the saturation drain voltage is reduced, and the power consumption is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 FIG. 1 is a schematic structural diagram of one of the transistors provided by the present application;

[0035] Figure 2 A schematic structural diagram of one of the transistors provided by an embodiment of the present application is shown in FIG. 1.

[0036] Figure 3 A schematic structural diagram of one of the transistors provided by an embodiment of the present application is shown in FIG. 1.

[0037] Figure 4 A schematic structural diagram of one of the transistors provided by an embodiment of the present application is shown in FIG. 1.

[0038] Figure 5 A schematic structural diagram of one of the driving substrates provided by an embodiment of the present application is shown in FIG. 1.

[0039] Figure 6 A schematic structural diagram of one of the display devices provided by an embodiment of the present application is shown in FIG. 1.

[0040] Figure 7 A method flow chart of the manufacturing method of the transistor provided by an embodiment of the present application is shown in FIG. 1.

[0041] Figure 8 A method flow chart of one of the steps S102 is shown in FIG. 1. Figure 7

[0042] Legend of reference signs:

[0043] 10 - substrate; 20 - active layer; 30 - gate insulating layer; 40 - gate; 50 - source / drain; 501 - source; 502 - drain; 301 - first part; 302 - second part; 60 - buffer layer; 70 - light shielding layer; 80 - interlayer insulating layer; 90 - interface charge layer; 100 - driving circuit; 200 - driving transistor; 300 - switching transistor; 400 - driving substrate; 500 - light emitting device. DETAILED DESCRIPTION

[0044] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be described clearly and completely below with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. And the embodiments in the present application and the features in the embodiments can be combined with each other without conflict, if necessary. Based on the described embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the protection scope of the present application.

[0045] ​Unless otherwise defined, technical terms or scientific terms used in the present application shall have the ordinary meanings as understood by one of ordinary skill in the art to which this application pertains. The use of the terms "including", "containing", and "comprising" and the like in the present application are meant to be inclusive, and are intended to mean that the elements or objects listed following the word are present in the composition or method, but not excluding the presence of other elements or objects.

[0046] It should be noted that the size and shape of the various figures in the drawings are not to scale, and are intended merely to illustrate the present application. Identical or similar elements or elements having identical or similar functions are denoted throughout by identical reference numerals.

[0047] In the related art, the driving circuit of the OLED often uses LTPS as the channel of the DTFT. In this way, the source-drain voltage of the DTFT is usually large during the light-emitting stage of the light-emitting device, especially in the high-brightness state, resulting in large power consumption.

[0048] In view of this, the embodiments of the present application provide a transistor, a manufacturing method thereof and a driving substrate, for reducing power consumption.

[0049] As shown in Figure 1 The embodiments of the present application provide a transistor, which comprises:

[0050] An active layer 20, a gate insulating layer 30, a gate 40 and a source-drain electrode 50 are sequentially arranged on a substrate 10, and the source-drain electrode 50 comprises a source 501 and a drain 502 arranged in the same layer; wherein:

[0051] In the region where the gate 40 overlaps with the active layer 20, the gate insulating layer 30 comprises a first part 301 having a first thickness and a second part 302 having a second thickness, the first part 301 extends to the side close to the source 501, and the second part 302 extends to the side close to the drain 502, and the second thickness is smaller than the first thickness.

[0052] In the specific implementation process, the transistor comprises an active layer 20, a gate insulating layer 30, a gate 40 and a source-drain electrode 50 sequentially arranged on a substrate 10, wherein the source 501 and the drain 502 in the source-drain electrode 50 are arranged in the same layer, thereby simplifying the manufacturing process. In the region where the gate 40 overlaps with the active layer 20, the gate insulating layer 30 comprises a first part 301 having a first thickness and a second part 302 having a second thickness, the first part 301 extends to the side close to the source 501, and the second part 302 extends to the side close to the drain 502, and the second thickness is smaller than the first thickness. Figure 1As shown in region A, the gate insulating layer 30 includes a first portion 301 with a first thickness and a second portion 302 with a second thickness. The first portion 301 diffracts towards the side closer to the source 501, and the second portion 302 extends towards the side closer to the drain 502. The second thickness is less than the first thickness. For example, the first thickness is h1, and the second thickness is h2.

[0053] In one exemplary embodiment, such as Figure 2 As shown, a buffer layer 60 can also be disposed between the substrate 10 and the active layer 20, effectively preventing external water and oxygen from eroding the relevant film layers in the transistor, while ensuring the flatness of the film layer structure. In one exemplary embodiment, as... Figure 3 As shown, a light-shielding layer 70 is also disposed between the buffer layer 60 and the substrate 10, and the orthographic projection of the active layer 20 on the substrate 10 completely falls within the area of ​​the orthographic projection of the light-shielding layer 70 on the substrate 10. The light-shielding layer 70 can be made of a metal layer such as molybdenum. The light-shielding layer 70 effectively prevents interference from ambient light on the transistor, ensuring the transistor's performance. Figures 1 to 3 As shown, the transistor provided in this embodiment of the invention further includes an interlayer insulating layer 80 covering the gate 40. A via is formed in the interlayer insulating layer 80, exposing the active layer 20. The source 501 and drain 502 are respectively connected to the active layer 20 through the via.

[0054] In embodiments of the present invention, such as Figure 4 As shown, the gate insulating layer 30 has an interface charge layer 90 on the side of the second portion 302 near the active layer 20.

[0055] In one exemplary embodiment, the interface charge layer 90 is negatively charged.

[0056] ​In the implementation, the gate insulating layer 30 is provided with an interface charge layer 90 on the side of the second part 302 close to the active layer 20. During the operation of the transistor, the electric field generated by the interface charge layer 90 can be superimposed on the electric field of the gate 40. Especially when the interface charge layer 90 is negatively charged, the gate electric field control ability of the region corresponding to the second part 302 is enhanced after the superposition of the two electric fields. During the operation of the transistor, as the source-drain voltage increases, the channel conductive layer can quickly enter the pinch-off state, and the corresponding output curve quickly enters the saturation region, thereby reducing the saturation drain voltage and further reducing the power consumption.

[0057] In the embodiment of the application, the interface charge layer 90 is a charge layer formed by fluorine ions or oxygen ions.

[0058] In one of the exemplary embodiments, the interface charge layer 90 can be a charge layer formed by fluorine ions. In one of the exemplary embodiments, the interface charge layer 90 can also be a charge layer formed by oxygen ions. Accordingly, the interface charge layer 90 is negatively charged. Of course, according to actual application needs, the corresponding negative ions can also be used to form the interface charge layer 90, which is not limited herein.

[0059] In the embodiment of the application, the orthographic projection area of the first part 301 on the substrate 10 is equal to the orthographic projection area of the second part 302 on the substrate 10.

[0060] In one of the exemplary embodiments, the orthographic projection area of the first part 301 on the substrate 10 is equal to the orthographic projection area of the second part 302 on the substrate 10. In this way, while ensuring the processing efficiency of the patterning of the gate insulating layer 30, the gate electric field control ability of the region corresponding to the second part 302 is enhanced. Here, “equal” does not mean complete equality, but can be approximate equality or approximate equality.

[0061] In one of the exemplary embodiments, the orthographic projection area of the first part 301 on the substrate 10 is twice the orthographic projection area of the second part 302 on the substrate 10. Of course, the proportion of the first part 301 and the second part 302 can also be set according to actual application needs, which is not limited herein.

[0062] Based on the same inventive concept, as Figure 5As shown, the embodiment of the present application also provides a driving substrate, which comprises a driving circuit 100, wherein the driving circuit 100 comprises a driving transistor 200, and the driving transistor 200 is the transistor as described in any one of the preceding embodiments. In the implementation process, the specific structure of the driving transistor 200 can refer to the description of the transistor part in the preceding description, and will not be repeated here. When the driving transistor 200 adopts the structure of the transistor described above, the power consumption of the driving substrate is reduced while ensuring the gate 40 electric field control ability of the area corresponding to the second part 302.

[0063] In the embodiment of the present application, the driving circuit 100 further comprises at least one switching transistor 300, and the gate insulating layer 30 between the gate 40 and the active layer 20 of each switching transistor 300 is arranged in the same layer as the gate insulating layer 30 in the driving transistor 200, and the corresponding gate insulating layer 30 between the gate 40 and the active layer 20 of each switching transistor 300 has the first thickness.

[0064] Still in combination with Figure 5 As shown, the driving circuit 100 further comprises at least one switching transistor 300, and the specific number of the at least one switching transistor 300 can be set according to actual application needs, which will not be limited here. For example, in the 2T1C driving circuit 100, the driving circuit 100 comprises one driving transistor 200 and one switching transistor 300. For example, in the 7T1C driving circuit 100, the driving circuit 100 comprises one driving transistor 200 and six switching transistors 300. In addition, the specific structure of the driving circuit 100 can refer to the specific implementation in the related art, which will not be described in detail here. The gate insulating layer 30 between the gate 40 and the active layer 20 of each switching transistor 300 is made in the same layer as the gate insulating layer 30 in the driving transistor 200, thereby simplifying the manufacturing process. Moreover, the corresponding gate insulating layer 30 between the gate 40 and the active layer 20 of each switching transistor 300 has the first thickness, which is greater than the thickness of the second part 302 of the gate insulating layer 30 in the driving transistor 200, thereby reducing the manufacturing cost while ensuring the gate 40 electric field control ability of the area corresponding to the second part 302.

[0065] In the embodiment of the present application, the driving transistor 200 and each switching transistor 300 are polycrystalline silicon transistors.

[0066] In the implementation process, the driving transistor 200 and each switching transistor 300 are polycrystalline silicon transistors. In this way, the driving transistor 200 and each switching transistor 300 have higher mobility, and can be made thinner, smaller, and have lower power consumption, etc.

[0067] In the embodiment of the present application, the driving transistor 200 and each of the switching transistors 300 are P-type transistors. In an exemplary embodiment, the active layer 20 of the driving transistor 200 and each of the switching transistors 300 can be low-temperature polysilicon material, and the driving transistor 200 and each of the switching transistors 300 are P-type transistors, so that each transistor is turned on only when the control signal loaded on the control terminal of the transistor is at a low level. When the control signal loaded on the control terminal of each transistor is at a high level, each transistor is turned off. In this way, the on and off of each transistor can be controlled by loading a corresponding control signal on the control terminal of each transistor, thereby improving the control effect of the driving circuit 100.

[0068] In addition, the driving substrate 400 provided by the embodiment of the present application has a similar problem-solving principle as the aforementioned transistor, and therefore the implementation of the driving substrate 400 can be referred to the implementation of the aforementioned transistor, and the repeated parts will not be described herein.

[0069] Based on the same inventive concept, as Figure 6 shown, the embodiment of the present application further provides a display device, which comprises the aforementioned driving substrate 400 and light emitting devices 500 arranged in an array on the driving substrate 400, and each light emitting device is coupled with the driving circuit 100 in the driving substrate 400. Wherein, the light emitting device 500 can be set as at least one of an electroluminescent diode, such as an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), a micro light emitting diode (micro LED) or a mini light emitting diode (mini LED), without limitation. Wherein, the light emitting device 500 can include an anode, a light emitting layer, and a cathode arranged in a stack. Further, the light emitting layer can further include a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, and the like. Of course, in actual application, the light emitting device 500 can be designed according to the needs of the actual application environment, without limitation.

[0070] It should be noted that the display device provided by the embodiment of the present application further includes film layer structures arranged in the planarization layer, the passivation layer, the pixel definition layer, the isolation column, the encapsulation layer, and the like, and the specific arrangement can refer to the implementation in the related art, which will not be described in detail herein.

[0071] In addition, the display device provided by the embodiment of the present application has a similar problem-solving principle as the aforementioned driving substrate 400, and therefore the implementation of the display device can be referred to the implementation of the aforementioned driving substrate 400, and the repeated parts will not be described herein.

[0072] In the implementation, the display device provided by the embodiment of the present application can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. Other essential components of the display device are understood by those skilled in the art and will not be described here again, and should not be considered as a limitation to the present application.

[0073] Based on the same inventive concept, the embodiment of the present application also provides a transistor manufacturing method, as shown in Figure 7 the embodiment of the present application further provides a transistor manufacturing method, which comprises the following steps:

[0074] S101: forming a pattern of an active layer on a substrate;

[0075] S102: forming a pattern of a gate insulating layer on a side of the active layer away from the substrate, the gate insulating layer comprising a first part with a first thickness and a second part with a second thickness, the first part extending to a side close to a source to be formed, and the second part extending to a side close to a drain to be formed, the second thickness being smaller than the first thickness;

[0076] S103: forming a pattern of a gate on a side of the gate insulating layer away from the substrate;

[0077] S104: forming an interlayer insulating layer on a side of the gate away from the substrate;

[0078] S105: forming a pattern of a source and a drain penetrating through the interlayer insulating layer and coupled with the active layer.

[0079] In the implementation, taking the transistor shown in Figure 1 as an example, the specific implementation process of steps S101 to S105 is as follows:

[0080] First, a pattern of the active layer 20 is formed on the substrate 10; then, a pattern of the gate insulating layer 30 is formed on the side of the active layer 20 away from the substrate 10, the gate insulating layer 30 including a first portion 301 having a first thickness and a second portion 302 having a second thickness, the first portion 301 extending to the side close to the source electrode 501 to be formed, and the second portion 302 extending to the side close to the drain electrode 502 to be formed, the second thickness being less than the first thickness. In this way, on the side of the active layer 20 away from the substrate 10, the gate insulating layer 30 having two thicknesses is formed. Then, a pattern of the gate electrode 40 is formed on the side of the gate insulating layer 30 away from the substrate 10, wherein the gate electrode 40 overlaps the first portion 301 and the second portion 302. Then, an interlayer insulating layer 80 is formed on the side of the gate electrode 40 away from the substrate 10. Then, the source electrode 501 and the drain electrode 502 are formed by opening holes on the interlayer insulating layer 80, the source electrode 501 and the drain electrode 502 penetrating through the interlayer insulating layer 80 and being coupled with the active layer 20. In this way, the transistor including the active layer 20, the gate electrode 40, the source electrode 501 and the drain electrode 502 is prepared. Only the corresponding film layers need to be patterned in the whole preparation process, and the transistor is low in manufacturing cost and high in efficiency.

[0081] In the embodiment of the present application, as shown in Figure 8 Step S102: on the side of the active layer away from the substrate, a pattern of the gate insulating layer is formed, including:

[0082] S201: on the side of the active layer away from the substrate, the gate insulating layer of the first thickness is deposited;

[0083] S202: photoresist is coated on the gate insulating layer;

[0084] S203: the photoresist is patterned by using a patterning process, the photoresist at the positions corresponding to the second portion of the gate insulating layer is removed, and a pattern of the photoresist is formed;

[0085] S204: according to the pattern of the photoresist, the gate insulating layer at the positions corresponding to the second portion is etched by a third thickness, wherein the difference between the first thickness and the third thickness is the second thickness;

[0086] S205: a pattern of the gate insulating layer is formed.

[0087] In the specific implementation process, the specific implementation process of steps S201 to S205 is as follows:

[0088] First, a gate insulating layer 30 of a first thickness is deposited on the side of the active layer 20 facing away from the substrate. Then, photoresist is applied on the gate insulating layer 30. Then, the photoresist is patterned by a patterning process, and the photoresist in the positions corresponding to the second portion 302 of the gate insulating layer 30 is removed, forming a pattern of the photoresist. In an exemplary embodiment, a mask can be defined with a region corresponding to the first portion 301, and an optical proximity correction (OPC) technique can be used for exposure, which mainly uses optical proximity effect to control light intensity distribution, thereby modulating the exposure degree of the photoresist. Specifically, a certain width and spacing of light-shielding strips can be arranged at the edge of the mask to affect the diffraction of light so that the light intensity distribution is relatively steep at this position, thereby ensuring a larger slope angle at the edge of the photoresist. For example, the slope angle is greater than 70°. In this way, the shielding effect of the photoresist on the corresponding region is ensured. After the pattern of the photoresist is formed, the gate insulating layer 30 in the positions corresponding to the second portion 302 can be etched to a third thickness according to the pattern of the photoresist. For example, the third thickness is in the range of 10 nm to 40 nm. In this way, the final thickness of the second portion 302 of the gate insulating layer 30 is the second thickness, thereby forming a pattern of the gate insulating layer 30.

[0089] In an embodiment of the present application, after the step S102 of forming the pattern of the gate insulating layer on the side of the active layer facing away from the substrate, the method further comprises:

[0090] An interface charge layer is formed on the side of the second portion close to the active layer.

[0091] In an embodiment of the present application, the step of forming the interface charge layer 90 on the side of the second portion close to the active layer 20 can have the following two implementation manners, but is not limited to the following two implementation manners. In the first implementation manner, the step of forming the interface charge layer on the side of the second portion close to the active layer comprises:

[0092] According to the pattern of the photoresist, and by injecting fluorine ions or oxygen ions with an energy in the range of 15 keV to 50 keV and a dose in the range of 0.1E12 ions / cm2 to 3E12 ions / cm2, the gate insulating layer is formed with an interface charge layer on the side of the second portion close to the active layer.

[0093] In the implementation, after the photoresist pattern and the gate insulating layer 30 pattern are formed, the negative ions such as fluorine ions or oxygen ions are implanted in the second portion 302 near the active layer 20 side with an energy range of 15 keV to 50 keV and a dose range of 0.1E12 ions / cm2 to 3E12 ions / cm2, so as to form the interface charge layer 90 with negative electric property near the active layer 20 side of the second portion 302. In this way, the electric field generated by the negative space charge can be superimposed on the electric field of the gate 40, so that the channel conduction layer is more likely to be pinched off, the output curve can quickly enter the saturation region, and the saturation drain voltage is reduced.

[0094] In the second implementation, the interface charge layer is formed near the active layer side of the second portion, comprising:

[0095] A positive bias is applied to the gate, and a negative bias is applied to the drain, so that the gate insulating layer forms the interface charge layer near the active layer side of the second portion.

[0096] In the implementation, after the photoresist pattern and the gate insulating layer 30 pattern are formed, a positive bias can also be applied to the gate 40, and a negative bias can be applied to the drain 502. In an exemplary embodiment, the applied positive bias can be 5V to 30V, and the applied negative bias can be -30V to -5V. In this way, a strong electric field directed to the gate insulating layer 30 will be formed between the gate 40 and the drain 502, and the carriers can enter the gate insulating layer 30 through tunneling and other means under the strong electric field to form the interface charge layer 90 with negative electric property near the active layer 20 side of the second portion 302. In this way, the electric field generated by the negative space charge can be superimposed on the electric field of the gate 40, so that the channel conduction layer is more likely to be pinched off, the output curve can quickly enter the saturation region, and the saturation drain voltage is reduced.

[0097] The embodiment of the present application provides a transistor, a manufacturing method thereof and a driving substrate 400, wherein the transistor comprises an active layer 20, a gate insulating layer 30, a gate 40 and a source-drain electrode 50 which are sequentially arranged on a substrate 10, the source-drain electrode 50 comprises a source 501 and a drain 502 which are arranged in the same layer; in the region where the gate 40 and the active layer 20 overlap, the gate insulating layer 30 comprises a first part 301 with a first thickness and a second part 302 with a second thickness, the first part 301 extends to the side close to the source 501, the second part 302 extends to the side close to the drain 502, and the second thickness is smaller than the first thickness. Since the thickness of the second part 302 of the gate insulating layer 30 which extends to the side close to the drain 502 is smaller than the thickness of the first part 301 which extends to the side close to the source 501, the electric field control ability of the gate 40 in the region corresponding to the second part 302 is enhanced, and in the working process of the transistor, as the source-drain voltage increases, the channel conductive layer can quickly enter the pinch-off state, and the corresponding output curve quickly enters the saturation region, so that the saturation drain voltage is reduced, and the power consumption is further reduced.

[0098] Although preferred embodiments of the application have been described herein, after further studying the drawings and detailed description, those skilled in the art will readily devise additional changes and modifications to the embodiments without departing from the spirit and scope of the application. Therefore, the following claims are intended to cover all such changes and modifications which fall within the scope of the application.

[0099] Obviously, various modifications and changes can be made to the present application without departing from the spirit and scope of the application. Accordingly, it is intended that all such modifications and changes be included within the scope of the application as defined in the following claims and their equivalents.

Claims

1. A transistor, characterized in that, include: An active layer, a gate insulating layer, a gate, and source / drain electrodes are sequentially disposed on a substrate, wherein the source / drain electrodes include a source and a drain electrode disposed on the same layer; wherein: In the region where the gate overlaps with the active layer, the gate insulating layer includes a first portion having a first thickness and a second portion having a second thickness. The first portion extends towards the source, and the second portion extends towards the drain. The second thickness is less than the first thickness. The active layer is made of low-temperature polycrystalline silicon. An interface charge layer is disposed on the side of the second portion of the gate insulating layer near the active layer. The orthogonal projection of the interface charge layer onto the substrate completely falls within the region of the orthogonal projection of the second portion onto the substrate, and the interface charge layer is negatively charged. The electric field control capability of the gate in the region corresponding to the second portion is greater than that in the region corresponding to the first portion.

2. The transistor as claimed in claim 1, characterized in that, The interface charge layer is a charge layer formed by fluoride ions or oxygen ions.

3. The transistor as claimed in claim 1 or 2, characterized in that, The projected area of ​​the first part on the substrate is equal to the projected area of ​​the second part on the substrate.

4. A driving substrate, characterized in that, include: A driving circuit, the driving circuit including a driving transistor, the driving transistor being the transistor as described in any one of claims 1-3.

5. The driving substrate as described in claim 4, characterized in that, The driving circuit further includes at least one switching transistor, wherein the gate insulating layer between the gate and the active layer of each switching transistor is disposed in the same layer as the gate insulating layer in the driving transistor, and the gate insulating layer corresponding to the gate and the active layer of each switching transistor has the first thickness.

6. The driving substrate as described in claim 5, characterized in that, The driving transistor and each of the switching transistors are polycrystalline silicon transistors.

7. A method for manufacturing a transistor, characterized in that, include: A pattern of an active layer is formed on a substrate; wherein the active layer is a low-temperature polycrystalline silicon material; On the side of the active layer facing away from the substrate, a pattern of a gate insulating layer is formed. The gate insulating layer includes a first portion having a first thickness and a second portion having a second thickness. The first portion extends towards the side where the source electrode will be formed, and the second portion extends towards the side where the drain electrode will be formed. The second thickness is less than the first thickness. An interface charge layer is disposed on the side of the second portion of the gate insulating layer near the active layer. The orthogonal projection of the interface charge layer on the substrate completely falls within the area of ​​the orthogonal projection of the second portion on the substrate, and the interface charge layer is negatively charged. The electric field control capability of the gate in the corresponding region of the second portion is greater than that in the corresponding region of the first portion. The gate pattern is formed on the side of the gate insulating layer opposite to the substrate; An interlayer insulating layer is formed on the side of the gate opposite to the substrate; A source and drain pattern is formed that penetrates the interlayer insulation layer and is coupled to the active layer.

8. The manufacturing method as described in claim 7, characterized in that, On the side of the active layer opposite to the substrate, a pattern of a gate insulating layer is formed, including: On the side of the active layer opposite to the substrate, a gate insulating layer of the first thickness is deposited; Photoresist is coated on the gate insulating layer; The photoresist is patterned using a patterning process, and the photoresist at the corresponding positions of the gate insulating layer and the second part is removed to form the pattern of the photoresist; According to the pattern of the photoresist, the gate insulating layer is etched away at the corresponding position of the second part to remove a third thickness, wherein the difference between the first thickness and the third thickness is the second thickness; The pattern of the gate insulating layer is formed.

9. The manufacturing method as described in claim 8, characterized in that, After forming a pattern of a gate insulating layer on the side of the active layer opposite to the substrate, the method further includes: An interface charge layer is formed on the side of the second part near the active layer.

10. The manufacturing method as described in claim 9, characterized in that, An interface charge layer is formed on the side of the second portion near the active layer, including: According to the pattern of the photoresist, and with an energy range of 15keV to 50keV, fluorine ions or oxygen ions in the dose range of 0.1E12 ions / cm2 to 3E12 ions / cm2 are implanted to form an interface charge layer on the side of the gate insulating layer near the active layer in the second part.

11. The manufacturing method as described in claim 9, characterized in that, An interface charge layer is formed on the side of the second portion near the active layer, including: A positive bias is applied to the gate and a negative bias is applied to the drain, so that an interface charge layer is formed on the side of the gate insulating layer near the active layer in the second portion.

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