Switching Converters

Abstract

Embodiments of the present disclosure relate to a switching converter. In an embodiment, a switching converter includes: a switching stage, which includes a first switching device and a second switching device for receiving an input voltage and for providing an output voltage; a driving stage, which includes a first driving device and a second driving device for driving the first switching device and the second switching device respectively; a current sensing device, which is used to sense an output current provided by the switching stage; a voltage generating device, which is configured to generate a power supply voltage for powering the driving stage, the voltage generating device being configured to adjust the power supply voltage according to the sensed output current; and a charge recovery stage, which is configured to store a first charge lost from the first driving device during driving of the first switching device, and at least partially release the stored first charge to the second driving device during driving of the second switching device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian Patent Application No. 102020000028178, filed on November 24, 2020, which is incorporated herein by reference.

[0003] This application is related to the co-pending U.S. patent application 17 / 532,867, entitled “Switching Converter,” filed on the same day as this application, which is related to the application with agent case number ST-19-CA-0481US01 and claims the benefit of Italian patent application No. 102020000028199 filed on November 24, 2020, which is incorporated herein by reference. Technical Field

[0004] The present disclosure relates generally to electronic systems and methods and, in certain embodiments, to a switching converter. Background Art

[0005] A DC-DC switching converter can be used in any electronic system comprising a power source (such as a battery) and one or more electronic / electromechanical components, each of which operates at a corresponding voltage. In such an electronic system, the DC-DC switching converter can be configured to generate multiple controlled output voltages from a (single) input voltage provided by the power source. This allows space saving, because it avoids the use of multiple power sources within the electronic system to power its different components.

[0006] Among switching converters, a switching converter whose output voltage is equal to or lower than an input voltage (also called a step-down converter or buck converter) is widely used.

[0007] A conventional buck converter includes a switching stage (eg, a CMOS switching stage) and a driver stage for driving the switching stage.

[0008] According to a common embodiment, the switching stage includes a high-side switching device (such as a PMOS transistor) and a low-side switching device (such as an NMOS transistor), which is alternately turned on and off according to a corresponding driving signal.

[0009] According to a common embodiment, the driving stage includes a high-side driving device (e.g., a tapered buffer device) for receiving an oscillating signal (e.g., a pulse width modulation (PWM) signal) and for providing a corresponding driving signal to a high-side switching device, and a low-side driving device (e.g., a tapered buffer device) for receiving an oscillating signal and for providing a corresponding driving signal to a low-side switching device.

[0010] The high-side and low-side driver devices are usually powered by corresponding supply voltages.

[0011] The supply voltage for powering the high-side driver device generally includes a high or relatively high supply voltage (usually the input voltage) and a low or relatively low supply voltage.

[0012] The power supply voltage for powering the low-side driver device generally includes a high or relatively high power supply voltage and a low or relatively low power supply voltage (generally a ground voltage). Summary of the invention

[0013] Some embodiments of the present invention generally relate to the field of switching converters. Some embodiments relate to a DC-DC switching converter for converting a DC input voltage to a DC output voltage. Some embodiments relate to a switching converter, such as a buck converter, where the output voltage is equal to or lower than the input voltage.

[0014] The present inventors have appreciated that conventional switching converters, such as traditional buck converters, may not be satisfactory for modern technology requirements, and particularly for applications where high efficiency is desired or required.

[0015] In fact, the inventors have realized that in the solutions of the prior art, the low or relatively low power supply voltage for powering the high-side driver device and the high or relatively high power supply voltage for powering the low-side driver device are fixed (for example, they can be internally generated or externally provided), and therefore, they cannot be used to achieve power loss optimization.

[0016] Therefore, in conventional switching converters, the driving losses are usually optimized by taking measures on the design parameters of the switching devices. As examples only, introducing modularity for the switching devices or changing the switching frequency are methods commonly used to achieve power loss optimization.

[0017] However, introducing modularity for the switching devices may mean high design complexity for driving the devices, and changing the switching frequency may imply higher system complexity for managing the switching devices and a huge impact on the state machine.

[0018] The inventors have experienced the above problems and have designed an embodiment of a switching converter with optimized power loss and reduced complexity. To achieve it, the inventors have designed an embodiment of a switching converter in which a low or relatively low supply voltage for powering a high-side driver device and a high or relatively high supply voltage for powering a low-side driver device are variable and adjustable according to the output current of the switching converter, and in which the charge lost from the high-side driver device is at least partially recovered to at least partially compensate for the charge lost from the low-side driver device.

[0019] One or more aspects of some embodiments of the invention are set out in the independent claims, wherein advantageous features of some embodiments are indicated in the dependent claims, the wording of which corresponds verbatim to that herein by reference (where any advantageous features are provided with reference to a particular aspect of some embodiments of the invention, that particular aspect applies mutatis mutandis to any other aspect).

[0020] More specifically, one aspect of some embodiments of the present invention relates to a switching converter for converting a DC input voltage into a DC output voltage. The switching converter may include a switching stage, the switching stage including a first switching device and a second switching device, the first switching device and the second switching device being used to receive the DC input voltage and to provide the DC output voltage according to the DC input voltage. The switching converter may include a driving stage, the driving stage including a first driving device and a second driving device, the first driving device and the second driving device being used to drive the first switching device and the second switching device, respectively. The switching converter may include a current sensing device for sensing an output current provided by the switching stage. The switching converter may include a voltage generating device, the voltage generating device being configured to generate at least one power supply voltage for powering the driving stage; the voltage generating device may be configured to adjust the at least one power supply voltage according to the output current sensed by the sensing device. The switching converter may include a charge recovery stage, the charge recovery stage being configured to store a first charge lost from the first driving device during driving of the first switching device and to release the at least partially stored first charge to the second driving device during driving of the second switching device, so as to at least partially compensate for a second charge lost from the second driving device during driving of the second switching device.

[0021] According to an embodiment, which is additional or alternative to any of the features of the preceding embodiments, the voltage generating device comprises a first voltage generating stage and a second voltage generating stage, the first voltage generating stage being configured to generate a first power supply voltage for powering the second driving device according to the output current, and the second voltage generating stage being configured to generate a second power supply voltage for powering the first driving device according to a reference voltage corresponding to the first power supply voltage. The charge recovery stage may be configured to selectively store the first charge according to a comparison between the first power supply voltage and the second power supply voltage.

[0022] According to an embodiment, it is characterized in that, in addition or alternatively to any of the features of the preceding embodiments, the first power supply voltage and the second power supply voltage provide the same power supply voltage drop for the first drive device and the second drive device. The charge recovery stage can be configured to allow storage of the first charge if the second power supply voltage is higher than the first power supply voltage, or to prevent storage of the first charge if the second power supply voltage is lower than the first power supply voltage.

[0023] According to an embodiment, whose features are additional or alternative to any of the features of the preceding embodiments, the charge recovery stage comprises at least one of the following:

[0024] a storage capacitor configured to store the first charge;

[0025] a switch unit, configured to selectively allow or prevent the first charge from flowing into the storage capacitor;

[0026] A comparator unit is used to operate the switch unit according to a comparison between the first power supply voltage and the second power supply voltage.

[0027] According to an embodiment, characterized in that it is additional or alternative to any of the features of the aforementioned embodiments, the first voltage generating stage includes a decoupling stage, which is configured to receive the reference voltage and provide the first power supply voltage to a first power supply terminal while electrically decoupling the first voltage generating stage and the second driving device from each other; the storage capacitor can be electrically coupled to the first power supply terminal.

[0028] According to an embodiment, characterized in that it is additional or alternative to any of the features of the aforementioned embodiments, the second voltage generating stage includes: a first impedance network, configured to receive the first power supply voltage and provide a corresponding additional reference current; a second impedance network, for example equal to the first impedance network, configured to receive the input voltage and the additional reference current and provide the second power supply voltage to a second power supply terminal; the switching unit can electrically couple the second power supply terminal to the first power supply terminal or decouple the second power supply terminal from the first power supply terminal to allow or prevent the first charge from flowing into the storage capacitor, respectively.

[0029] According to an embodiment, which is characterized in that it is additional or alternative to any of the features of the aforementioned embodiments, the first voltage generating stage includes a reference current generator and a reference voltage generator, the reference current generator is configured to generate a reference current adjustable according to the output current, and the reference voltage generator is configured to generate the reference voltage according to the reference current; the reference voltage generator may include a third impedance network; the second voltage generating stage may share the first impedance network with the reference voltage generator of the first voltage generating stage.

[0030] According to an embodiment, which is additionally or alternatively to any of the features of the preceding embodiments, the switching converter is a buck converter, a boost converter or a buck-boost converter.

[0031] Another aspect of some embodiments of the invention relates to a system comprising one or more of such switching converters.

[0032] Another aspect of some embodiments of the present invention relates to a method for converting a DC input voltage into a DC output voltage in a switching converter. The switching converter includes a switching stage, the switching stage including a first switching device and a second switching device, the first switching device and the second switching device for receiving the DC input voltage and for providing the DC output voltage according to the DC input voltage; and a driving stage, the driving stage including a first driving device and a second driving device for driving the first switching device and the second switching device, respectively. The method may include sensing an output current provided by the switching stage. The method may include generating at least one power supply voltage for powering the driving stage; the generating may include adjusting the at least one power supply voltage according to the sensed output current. The method may include storing a first charge lost from the first driving device during driving of the first switching device, and releasing the at least partially stored first charge to the second driving device during driving of the second switching device, so as to at least partially compensate for a second charge lost from the second driving device during driving of the second switching device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] These and other features and advantages of the present invention will become apparent through the following description of some exemplary and non-limiting embodiments of the present invention. For better understandability thereof, the following description should be read with reference to the accompanying drawings, in which:

[0034] Figure 1 A simplified circuit diagram of a switching converter according to an embodiment of the present invention is shown;

[0035] Figure 2 A circuit implementation of a voltage generation stage of a switching converter according to an embodiment of the present invention is shown;

[0036] Figure 3 A circuit implementation of a voltage generation stage of a switching converter according to an embodiment of the present invention is shown;

[0037] Figure 4 A circuit implementation of a switching converter according to an embodiment of the present invention is shown;

[0038] Figure 5 A circuit implementation of a charge recovery stage of a switching converter according to an embodiment of the present invention is shown; and

[0039] Figure 6 A simplified block diagram of an electronic system including a switching converter according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0040] With reference to the accompanying drawings, Figure 1 A circuit diagram of a switching converter 100 according to an embodiment of the present invention is shown.

[0041] Hereinafter, when one or more features of the switching converter 100 are introduced with the phrase “according to an embodiment”, they will be interpreted as additional or alternative features to any previously introduced features unless otherwise specified and / or unless there is an obvious incompatibility between feature combinations.

[0042] According to an embodiment, the switching converter 100 is a DC-DC switching converter, that is, a converter configured to convert a direct current (DC) input voltage V IN Converted to DC output voltage V OUT of switching converters.

[0043] According to an embodiment, the output voltage V OUT Lower than or equal to the input voltage V IN , that is, the switching converter 100 is a step-down converter (or buck converter). However, the principles of some embodiments of the present invention are equally applicable to other switching converters, such as a step-up converter (or boost converter), in which the output voltage V OUT Higher than the input voltage V IN , or a combination of a buck and boost converter (or buck-boost converter).

[0044] Without loss of generality, the switching converter 100 may be used in any electronic system that includes a power source (such as a battery) and one or more electronic / electromechanical components, each of which operates at a respective voltage: in such an electronic system, the switching converter 100 (or more thereof) may be configured to generate multiple controlled output voltages from a single input voltage provided by the power source (thereby saving space, since the use of multiple power sources within the electronic system to power its different components is avoided). Examples of such electronic systems include desktop computers, servers, laptop computers, media players (such as MP3 players), appliances, subnotebooks / netbooks, tablet computers, smartphones, cellular phones, network devices, personal digital assistants (PDAs), toys, controllers, digital signal processors, game consoles, device controllers, portable computing devices, and / or portable electronic devices.

[0045] According to an embodiment, the switching converter 100 includes providing an input voltage VIN The input terminal T IN and provide output voltage V OUT The output terminal T OUT .

[0046] According to an embodiment, the switching converter 100 includes a switching stage 105 for receiving an input voltage V IN And according to the input voltage V IN and the driving signal driving the switch stage 105 to provide an output voltage V OUT (as described below).

[0047] According to an embodiment, the switch stage 105 comprises a CMOS switch stage.

[0048] According to an embodiment, the switching stage 105 includes a high-side switching device 105 HS and low side switching device 105 LS In the following, when the high-side switching device 105 HS With low side switch device 105 LS When distinguishing between the high-side switching devices 105 HS and low side switching device 105 LS The switching device 105 will also HS , 105 LS Simply put, this is not relevant for understanding the present invention.

[0049] According to an embodiment, the high-side switch device 105 HS In an exemplary embodiment, the PMOS transistor includes a transistor electrically coupled (eg, directly connected) to the input terminal T IN To receive the input voltage V IN The source terminal is used to receive the corresponding drive signal V DRIVE,HS The gate terminal of the switching converter 100 is electrically coupled to the output terminal T of the switching converter 100. OUT The drain terminal of

[0050] According to an embodiment, the low-side switch device 105 LS The NMOS transistor according to the embodiment includes: a transistor electrically coupled (eg, directly connected) to the ground terminal T GND The source terminal, the ground terminal T GND Provides a ground voltage (eg, 0V); is used to receive a corresponding drive signal V DRIVE,LS (hereinafter, low-side drive signal) of the gate terminal; and electrically coupled (eg, directly connected) to the PMOS transistor 105 HS The drain terminal of the drain terminal of the.

[0051] According to an embodiment, switching converter 100 includes a driver stage 110 for driving a switching stage.

[0052] In the exemplary embodiment considered, the driving stage 110 includes a high-side driving device (hereinafter referred to as a high-side driver) 110 for receiving an oscillating signal (eg, a PWM signal). HS (eg, a tapered snubber device), not shown, and for supplying power to the high-side switching device 105 HS (In particular, the gate terminal of the PMOS transistor) is provided with a high-side drive signal V DRIVE,HS (High-side drive signal V DRIVE,HS is, for example, a corresponding regenerated version of the oscillation signal), and a low-side driving device (hereinafter referred to as a low-side driver) 110 LS (eg, a tapered buffer device) for receiving the oscillating signal and for supplying power to the low-side switching device 105 LS (In particular, providing a low-side drive signal V to the gate terminal of the NMOS transistor) DRIVE,LS (Low-side drive signal V DRIVE,LS is, for example, a corresponding regenerated version of the oscillating signal).

[0053] According to an embodiment, the driver stage 110 is powered by one or more supply voltages.

[0054] According to an embodiment, the high-side driver 110 HS According to an embodiment, the high-side driver 110 HS The power supply voltage includes a high or relatively high power supply voltage and a low or relatively low power supply voltage V HS According to an embodiment, the high-side driver 110 HS Power supply high or relatively high supply voltage including input voltage V IN (As in Figure 1 As conceptually shown in FIG. 1 , the high-side driver 110 HS With input terminal T IN electrical connection between them).

[0055] According to an embodiment, the low-side driver 110 LS According to an embodiment, the low-side driver 110 LS The power supply voltage includes a high or relatively high power supply voltage V LS and a low or relatively low power supply voltage. According to an embodiment, the low-side driver 110 LS Low or relatively low power supply voltages including ground voltage (such as in Figure 1 In the low-side driver 110 LS and ground terminal T GND The electrical connections between are conceptually illustrated).

[0056] In the following, the high-side driver 110 HS Powered by a low or relatively low supply voltage V HS and the low side driver 110 LS Powered by a high or relatively high supply voltage V LS will be referred to as the high-side supply voltage V HS and the low-side supply voltage V LS , receiving the high-side supply voltage V HS The high side driver 110 HS The terminal will be referred to as the high-side power supply terminal and receives the low-side power supply voltage V LS The low-side driver 110 LS The terminals will be referred to as low-side power supply terminals.

[0057] According to an embodiment, the high-side driver 110 HS and low-side driver 110 L The corresponding supply voltage has the same supply voltage drop V CC In the example considered:

[0058] V CC =V IN -V HS

[0059] V CC =V LS

[0060] According to an embodiment, switching converter 100 includes a filtering stage 115 electrically coupled to switching stage 105. According to an embodiment, filtering stage 115 is electrically coupled to the drain terminal of the PMOS transistor (and thus to the drain terminal of the NMOS transistor).

[0061] According to an embodiment, the filter stage 115 comprises an LC filter stage.

[0062] According to an embodiment, the filter stage 115 comprises: an inductor element 115 L (or more thereof), having a first terminal electrically coupled (e.g., directly connected) to the drain terminal of the PMOS transistor (and thus directly connected to the drain terminal of the NMOS transistor); and a second terminal electrically coupled (e.g., directly connected) to the output terminal T of the switching converter 100. OUT ; and capacitor element 115 C (or more thereof) which is electrically coupled (eg, directly connected) to the inductive element 115 L The first terminal of the switching converter 100 (and thus directly connected to the output terminal T OUT ) and electrically coupled (eg, directly connected) to a ground terminal T GNDThe second terminal of

[0063] Thus, in the embodiment considered, the switching stage 105 is electrically coupled to the output terminal T of the switching converter 100 via the filtering stage 115. OUT .

[0064] According to an embodiment, each drive signal V DRIVE,HS 、V DRIVE,LS is a digital signal, that is, a signal that can adopt low logic level and high logic level. As a numerical example only, the low-side drive signal V DRIVE,LS The low logic level and high logic level of the high side drive signal V may correspond to a reference voltage or a ground voltage (such as 0V) and a positive voltage higher than the ground voltage (such as 3.4V), respectively. DRIVE,HS The low logic level and high logic level can correspond to the high-side power supply voltage V HS and higher than the high-side supply voltage V HS A positive voltage of 3.4 V.

[0065] According to an embodiment, as described above, each drive signal V DRIVE,HS 、V DRIVE,LS Provided (eg, generated) from an oscillating signal (eg, a PWM signal) (not shown).

[0066] According to an embodiment, the oscillation signal is a square wave signal with a duty cycle d, and the duty cycle d of the oscillation signal is dynamically variable, thereby changing the conversion factor (V OUT / V IN ).

[0067] According to an embodiment, depending on the corresponding driving signal V DRIVE,HS 、V DRIVE,LS The value of each switching device is 105 H , 105 L It can adopt a closed or ON state, in which current is allowed to flow through it, and an open or OFF state, in which current is not allowed to flow through it.

[0068] As described above, switching converter 100 may be used in any electronic system. According to an embodiment, switching converter 100 is configured to be electrically coupled to one or more modules of such an electronic system. Such modules are Figure 1 The equivalent resistor element R L (hereinafter referred to as a load resistor) is conceptually represented as having a structure electrically coupled (eg, directly connected) to the output terminal T of the switching converter 100. OUT The first terminal is electrically coupled (eg, directly connected) to the ground terminal T GND The second terminal of

[0069] According to an embodiment, the switching converter 100 includes a sensing device 120 configured to sense a current output by the switching stage 105 (hereinafter, for brevity, the output current I OUT In some embodiments, the current sensing device 120 may be implemented in any manner known in the art.

[0070] The switching converter disclosed so far may be regarded as a typical known switching converter.

[0071] The switching converter 100 according to some embodiments of the present invention is designed to output a current I OUT The high-side supply voltage V HS and the low-side supply voltage V LS The power loss is optimized by implementing a charge recovery mechanism in which charge lost from the high-side driver is at least partially recovered to at least partially compensate for charge lost from the low-side driver.

[0072] The following summarizes the output current I OUT The high-side supply voltage V HS and the low-side supply voltage V LS The basic principle of the variable concept.

[0073] Assume that the power loss P of the switching converter 100 is loss can be considered to be mainly composed of conduction losses P Joule and drive loss P Driving Determine (i.e., assuming that switching losses, dynamic losses, parasitic coil losses, and bias losses can be neglected):

[0074] P loss =P Joule +P Driving

[0075]

[0076] P Driving =C g *V CC *V IN *f sw

[0077] in:

[0078] d represents the duty cycle;

[0079] R switch Indicates that the high side switch device 105 HS In the ON state and by the low side switching device 105 LS The resistance exhibited in the ON state;

[0080] IOUT Indicates the output current;

[0081] C g Indicates on the high side 105 H and low side 105 L an equivalent capacitance presented at a control terminal of a switching device (e.g., at a gate terminal of a corresponding transistor);

[0082] V CC Indicates the high side driver 110 HS Both ends and low side driver 110 LS The voltage drop across the power supply;

[0083] f sw represents the switching frequency of the switching converter 110 .

[0084] By P OUT represents the output power of the switching converter 100, and the efficiency η of the switching converter 100 can be expressed as:

[0085]

[0086] Expressed by efficiency η D , as the output current I OUT The maximum value of the efficiency η of the function can be determined as:

[0087]

[0088] And the output current I corresponding to the maximum value of efficiency η OUT for:

[0089]

[0090] Therefore, the maximum value of the efficiency η is obtained when:

[0091] P Joule =P Driving =C g *V CC *V IN *f sw

[0092] In the switching device 105 HS , 105 LS In the considered example including MOS transistors, the conduction loss P Joule It can be expressed as:

[0093]

[0094] kV T is the threshold voltage of the transistor.

[0095] can be obtained as the power supply voltage drop V CC Power loss as a function of P loss of minimization.

[0096]

[0097]

[0098]

[0099] According to the principles of some embodiments of the present invention, the switching converter 100 includes a voltage generating device configured to generate a voltage according to the output current I sensed by the sensing device 120. OUT (e.g., its instructions) to generate and adjust the high-side power supply voltage V HS and the low-side supply voltage V LS According to an embodiment, the output current I OUT The corresponding control signal S OUT is fed to the voltage generating means (as better discussed below, the control signal S OUT One or more controllable elements that can be configured to control a voltage device).

[0100] According to an embodiment, as shown in the figure, the voltage generating device includes a circuit configured to generate a voltage according to a control signal S OUT Generates low-side supply voltage V LS The voltage generating stage (hereinafter referred to as the low-side voltage generating stage) 125, and is configured to generate a voltage according to the low-side power supply voltage V LS The reference voltage V REF,LS Generates the high-side supply voltage V HS A voltage generating stage (hereinafter referred to as a high-side voltage generating stage) 130 (as may be better understood from the following discussion).

[0101] According to the principles of some embodiments of the present invention, the switching converter 100 includes a charge recovery stage 135. As better discussed below, the charge recovery stage 135 is particularly, but not exclusively, advantageous in an optimized implementation of the switching converter 100, particularly in an optimized implementation of the low-side voltage generation stage 125 and the high-side voltage generation stage 130.

[0102] Broadly speaking, the charge recovery stage 135 allows the high-side switching device 105 to HS During the drive period, the storage from the high-side driver 110 HS lost charge, and the low-side switching device 105 LS During the driving period, at least part of the stored high-side charge loss is released to the low-side driver 110 LS .

[0103] Reference now Figure 2 , which shows a circuit implementation of the low-side voltage generating stage 125 according to an embodiment of the present invention.

[0104] According to an embodiment, the low-side voltage generation stage 125 includes a reference current generator 2051 configured to generate a reference current I REF,LS .

[0105] According to an embodiment, the reference current generator 2051 includes a current mirror based current generator.

[0106] According to an embodiment, the current mirror based current generator includes: a first generating transistor 210 (eg, a BJT transistor) having a first transistor 210 electrically coupled (eg, directly connected) to a reference terminal T GND an emitter terminal of the second generation transistor 210; a second generation transistor 215 (e.g., a BJT transistor) having a base terminal electrically coupled (e.g., directly connected) to the base terminal of the first generation transistor 210 and a collector terminal electrically coupled (e.g., directly connected) to the corresponding base terminal (thus, the second generation transistor 215 is in a diode-connected configuration); a third generation transistor 220 (e.g., an NMOS transistor) having a source terminal electrically coupled (e.g., directly connected) to the collector terminal of the second generation transistor 215 and a gate terminal electrically coupled (e.g., directly connected) to the collector terminal of the first generation transistor 210; and an impedance network R1 electrically coupled between the emitter terminal of the second generation transistor 215 and a ground terminal T GND between.

[0107] The impedance network R1 is Figure 2 1 is conceptually represented as a single resistor, but this should not be construed as limiting.

[0108] According to an embodiment, the impedance network R1 comprises a resistor network.

[0109] According to an embodiment, the impedance network R1 is electrically coupled (eg, directly connected) between the emitter terminal of the second generating transistor 215 and the ground terminal T GND between.

[0110] According to the well-known principle of a current generator based on a current mirror, the reference current I flowing through the generating transistors 210, 215, 220 REF,LS It can be expressed as:

[0111]

[0112] in

[0113] V this the thermal voltage (about 26 mV at room temperature of 300 K);

[0114] m represents the size ratio between the second generation transistor 215 and the first generation transistor 210;

[0115] R1 represents the impedance value of the impedance network R1.

[0116] According to an embodiment, a current generator based on a current mirror comprises at an input terminal T IN and a plurality of (eg, two) first mirror transistors between the first generation transistor 210, and at the input terminal T IN The same number (eg, two) of second mirror transistors between the first and third generation transistors 220, the first mirror transistors and the second mirror transistors are arranged in a current mirror configuration.

[0117] According to an embodiment, the first mirror transistor includes a mirror transistor 225 A (eg, a PMOS transistor) and a mirror transistor 230 A (eg, a PMOS transistor), a mirror transistor 225 A having an electrical coupling (eg, direct connection) to the input terminal T IN The source terminal of the mirror transistor 230 A (eg, a PMOS transistor) is electrically coupled (eg, directly connected) to the mirror transistor 225 A A source terminal of the drain terminal of the first generation transistor 210 and a drain terminal electrically coupled (eg, directly connected) to the gate terminal of the third generation transistor 220 (and thus electrically coupled to the collector terminal of the first generation transistor 210).

[0118] According to an embodiment, the second mirror transistor includes a mirror transistor 225 B (eg, a PMOS transistor), a mirror transistor 225 B (eg, a PMOS transistor) is electrically coupled (eg, directly connected) to the input terminal T IN The source terminal of the mirror transistor 225 is electrically coupled (eg, directly connected) to the source terminal of the mirror transistor 225. A A gate terminal of a gate terminal of a transistor 225 and a drain terminal electrically coupled (eg, directly connected) to a corresponding gate terminal (eg, a mirror transistor 225) B Thus in a diode connected configuration), and mirror transistor 230 B (eg, a PMOS transistor) that is electrically coupled (eg, directly connected) to the mirror transistor 225 B The source terminal of the drain terminal of the mirror transistor 230 is electrically coupled (eg, directly connected) to the source terminal of the mirror transistor 230. AA gate terminal of a gate terminal of a transistor 225 and a drain terminal electrically coupled (eg, directly connected) to a corresponding gate terminal (eg, a mirror transistor 225) B Thus in a diode-connected configuration) and electrically coupled (eg, directly connected) to the drain terminal of the third generation transistor 220. As shown in FIG.

[0119] According to an embodiment, the low-side voltage generation stage 125 includes a reference voltage generator 2052 configured to generate a voltage according to a reference current I REF,LS Generate reference voltage V REF,LS .

[0120] According to an embodiment, the reference voltage generator 2052 includes an impedance network R2 (at Figure 2 ) is conceptually represented as a single resistor, although this should not be construed as limiting).

[0121] According to an embodiment, the impedance network R2 comprises a resistor network.

[0122] According to an embodiment, the impedance network R2 is configured to be REF,LS flows through, so the reference voltage V REF,LS Depends on the reference current I REF,LS And the impedance value R2 of the impedance network R2.

[0123] According to an embodiment, the reference voltage generator 2052 includes a plurality of (e.g., two) mirror transistors (hereinafter, third mirror transistors) electrically coupled to the first mirror transistor and the second mirror transistor of the reference current generator 2051 so as to receive the reference current I REF,LS In other words, the first mirror transistor, the second mirror transistor and the third mirror transistor as a whole realize a current mirror device. According to an embodiment, the first mirror transistor, the second mirror transistor and the third mirror transistor are designed so that the same reference current I REF,LS The current is allowed to flow through the first circuit branch, the second circuit branch, and the third circuit branch, respectively, which are identified by the first mirror transistor, the second mirror transistor, and the third mirror transistor.

[0124] According to an embodiment, the third mirror transistor includes: mirror transistor 225 C (eg, a PMOS transistor) having an electrical coupling (eg, direct connection) to the input terminal T IN The source terminal of the mirror transistor 225 is electrically coupled (eg, directly connected) to the source terminal of the mirror transistor 225. A , 225 B and a mirror transistor 230 C (eg, a PMOS transistor) that is electrically coupled (eg, directly connected) to the mirror transistor 225C The source terminal of the drain terminal of the mirror transistor 230 is electrically coupled (eg, directly connected) to the source terminal of the mirror transistor 230. A , 230 B A gate terminal of a gate terminal of, and a drain terminal electrically coupled (eg, directly connected) to a first terminal of an impedance network R2.

[0125] According to one embodiment, the second terminal of the impedance network R2 is electrically coupled (eg, directly connected) to the ground terminal T GND , the reference voltage V across the impedance network R2 REF,LS It can be expressed as:

[0126]

[0127] Wherein R2 represents the impedance value of the impedance network R2.

[0128] According to an embodiment, the reference current I REF,LS With reference voltage V REF,LS At least one of the two depends on the output current I OUT Adjustable (variable).

[0129] As in Figure 2 As conceptually shown in FIG. 1 , according to an embodiment, the impedance network R1 may be a variable impedance network, the impedance value of which varies according to the control signal S OUT (and therefore according to the output current I OUT ) is controlled. Therefore, in this embodiment, in order to obtain the output current I OUT Variable low-side supply voltage V LS , the reference current I generated by the reference current generator 2051 REF,LS According to the output current I OUT In this embodiment, the impedance network R2 may alternatively be a conventional impedance network with a fixed impedance value R2.

[0130] As in Figure 2 As conceptually shown in FIG. 1 , according to an embodiment, the impedance network R2 may be a variable impedance network, the impedance value of which is variable according to the control signal S OUT (and therefore according to the output current I OUT ) to control. In this embodiment, the impedance network R1 can alternatively be a conventional impedance network with a fixed impedance value R1. Therefore, in this embodiment, in order to obtain the output current I OUT Variable low-side supply voltage V LS , the reference current I generated by the reference current generator 2051 REF,LS is fixed, while the reference voltage V generated by the reference voltage generator 2051 REF,LS According to the output current IOUT is mutable.

[0131] Therefore, regardless of the output current I OUT The adjustable current is the reference current I REF,LS Or the reference voltage V REF,LS In any case, the impedance network R1 and / or the impedance network R2 can be changed (according to the control signal S OUT ), so that the reference voltage V REF,LS (and therefore the low-side supply voltage V LS ) is equal to the power loss P of the switching converter 100 loss The quantity Z to be minimized eq *I OUT .

[0132] Without loss of generality, embodiments in which the impedance network R1 is a variable impedance network and the impedance network R2 is a fixed impedance network are particularly advantageous. OUT The low side voltage V is obtained by reducing LS The decrease of the modulation reference current I REF,LS (due to the variable impedance network R1) allows to reduce the power consumption (in contrast, the reference voltage V is modulated by the variable impedance network R2 REF,LS will involve the third mirror transistor 225 C , 230 C High power consumption of the third circuit branch identified).

[0133] Furthermore, in a practical (and optimized) implementation, an impedance network R2 can be used to generate a high-side supply voltage V HS , whereby the impedance network R2 can be shared by the low-side voltage generator stage and the high-side voltage generator stage (as better discussed below).

[0134] According to an embodiment, the low-side voltage generation stage 125 includes an output stage 2053, which is configured to generate a voltage according to a reference voltage V REF,LS Provides low-side supply voltage V LS .

[0135] According to an embodiment, the low-side power supply voltage V provided by the output stage 2053 LS Corresponding to the reference voltage V REF,LS .

[0136] According to an embodiment, the low-side power supply voltage V provided by the output stage 2053 LS Equal to the reference voltage V REF,LS .

[0137] According to an embodiment, the output stage 2053 is configured to receive the transistor 225 from the third mirror transistor.C , 230 C The third circuit branch identified provides a reference voltage V REF,LS Therefore, in the thyristor, the output stage 2053 acts as a circuit for connecting the low-side voltage generating stage 125 and the low-side driver 110 LS Decoupling stages that decouple from each other.

[0138] According to an embodiment, the output stage 2053 includes an output transistor 235 (eg, an NMOS transistor) having an output terminal electrically coupled (eg, directly connected) to the input terminal T IN The drain terminal of the resistor network R2 is electrically coupled (eg, directly connected) to the first terminal of the resistor network R2 so as to receive the reference voltage V REF,LS The gate terminal of the low-side driver 110 is electrically coupled to LS and an output transistor 240 (e.g., a PMOS transistor) having a source terminal electrically coupled (e.g., directly connected) to the source terminal of the output transistor 235 (and thus directly connected to the low-side power supply terminal), a gate terminal electrically coupled (e.g., directly connected) to the gate terminal of the output transistor 235, and a ground terminal T GND The drain terminal of

[0139] In other words, the output transistors 235, 240 implement a push-pull configuration in which the reference voltage V REF,LS The gate terminals of the output transistors 235 , 240 are transmitted unchanged to the output transistors 235 , 240 (and thus to the low-side driver 110 LS ) source terminal. In particular, when the reference voltage V REF,LS Equal to the low-side supply voltage V LS , the output stage 2053 is in a balanced state, in which both the output transistors 235 and 240 are in the OFF state; the reference voltage V REF,LS The increase or decrease of V respectively determines that the output transistor 235 or the output transistor 240 switches to the ON state until the low-side supply voltage V at the corresponding source terminal LS The reference voltage V REF,LS until.

[0140] Reference now Figure 3 , which shows a circuit implementation of the high-side voltage generating stage 130 according to an embodiment of the present invention.

[0141] According to an embodiment, the high-side voltage generation stage 130 includes a circuit configured to generate a reference current I REF,HS Reference current generator 3051.

[0142] According to an embodiment, as shown, the reference current generator 3051 is configured to generate a reference current based on a reference voltage V determined at the low-side voltage generation stage 125. REF,LS To generate the reference current I REF,HS .

[0143] According to an embodiment, the reference current generator 3051 includes a circuit electrically coupled to provide a reference voltage V REF,LS Terminal and ground terminal T GND Impedance network between.

[0144] According to an embodiment, the impedance network includes a plurality of (eg, three) transistors (hereinafter, dividing transistors), such as MOS transistors in a diode-connected configuration.

[0145] According to an embodiment, the impedance network includes: a first voltage dividing transistor 310 (eg, a PMOS transistor) having a voltage receiving portion V REF,LS a source terminal of the first voltage-dividing transistor 310 and gate and drain terminals electrically coupled (e.g., directly connected) to each other; a second voltage-dividing transistor 315 (e.g., a PMOS transistor) having a source terminal electrically coupled (e.g., directly connected) to the drain terminal of the first voltage-dividing transistor 310 and gate and drain terminals electrically coupled (e.g., directly connected) to each other; and a third voltage-dividing transistor 320 (e.g., an NMOS transistor) having a drain terminal electrically coupled to the drain terminal of the second voltage-dividing transistor 315, a gate terminal electrically coupled (e.g., directly connected) to the corresponding drain terminal, and electrically coupled (e.g., directly connected) to the ground terminal T GND source terminal.

[0146] According to an embodiment, the impedance network includes a voltage-dividing resistor R (or more voltage-dividing resistors R in alternative embodiments of the present invention). According to an embodiment, the drain terminal of the third voltage-dividing transistor 320 is electrically coupled to the drain terminal of the second voltage-dividing transistor 315 through the intervention of the voltage-dividing resistor R. According to an embodiment, the voltage-dividing resistor R includes a first terminal electrically coupled (e.g., directly connected) to the drain terminal of the voltage-dividing transistor 315 and a second terminal electrically coupled (e.g., directly connected) to the drain terminal of the voltage-dividing transistor 320.

[0147] According to the known principle of voltage divider, each drain terminal is connected to the ground terminal T GND The equivalent impedance between the reference voltage V REF,LS The voltage is divided across the drain terminal of the voltage divider transistor. Therefore, the reference current I flowing through the impedance network REF,HS It can be expressed as the ratio between the voltage at the drain terminals of the second 315 and third 320 voltage dividing transistors and the resistance value of the voltage dividing resistor R.

[0148] According to an embodiment, the high-side voltage generation stage 130 includes a high-side supply voltage generator 3052 configured to receive a reference current I REF,HS and input voltage V IN And according to the reference current I REF,HS and input voltage V IN Generates the high-side supply voltage V HS .

[0149] According to an embodiment, the high side supply voltage generator 3052 is based on an impedance network. According to an embodiment, the impedance network of the high side supply voltage generator 3052 is equal to the impedance network of the reference current generator 3051. In other words, the impedance network of the high side supply voltage generator 3052 has the same implementation as the impedance network of the reference current generator 3051 (i.e., it includes the first 310, second 315 and third 320 voltage dividing transistors and the voltage dividing resistor R) and the same size (i.e., where the voltage dividing transistors 310, 315, 320 and the voltage dividing resistor R of the high side supply voltage generator 3052 are respectively matched in size to the voltage dividing transistors 310, 315, 320 and the voltage dividing resistor R of the reference current generator 3051).

[0150] According to an embodiment, a source terminal of the first partitioning transistor 310 of the high-side power supply voltage generator 3052 is electrically coupled (eg, directly connected) to the input terminal T IN (for receiving input voltage V IN ), and the source terminal of the third voltage dividing transistor 320 of the high-side power supply voltage generator 3052 is electrically coupled (eg, directly connected) to the high-side power supply terminal (for providing the high-side power supply voltage V HS ). Therefore, after receiving the reference current I from the reference current generator 3051 REF,HS When the impedance network across the reference current generator 3051 and the impedance network across the high-side supply voltage generator 3052 experience the same voltage drop (equal to the reference voltage V REF,LS ), and the high-side supply voltage V HS equal:

[0151] V HS =V IN –V REF,LS

[0152] The high-side supply voltage V HS Generated at the source terminal of the third voltage dividing transistor 320 of the high side power supply voltage generator 3052 .

[0153] In which V REF,LS =V LSIn the example of the problem, the high-side power supply voltage V generated at the source terminal of the third voltage dividing transistor 320 of the high-side power supply voltage generator 3052 is HS equal:

[0154] V HS =V IN –V LS

[0155] According to an embodiment, each of the reference current generator 3051 and the high-side power supply voltage generator 3052 includes a circuit for providing a reference current I from an impedance network of the reference current generator 3051 to an impedance network of the high-side power supply voltage generator 3052. REF,HS The corresponding current mirror device.

[0156] According to an embodiment, each current mirror device includes: a first mirror transistor 325 (e.g., a PMOS transistor) having a gate terminal electrically coupled (e.g., directly connected) to a gate terminal of the first voltage-dividing transistor 310 of the corresponding impedance network; a second mirror transistor 330 (e.g., a PMOS transistor) having a source terminal electrically coupled (e.g., directly connected) to a drain terminal of the first mirror transistor 325 and a gate terminal electrically coupled (e.g., directly connected) to a gate terminal of the second voltage-dividing transistor 315 of the corresponding impedance network; and a third mirror transistor 335 (e.g., an NMOS transistor) having a drain terminal electrically coupled (e.g., directly connected) to a drain terminal of the second mirror transistor 330 and a gate terminal electrically coupled (e.g., directly connected) to a gate terminal of the third voltage-dividing transistor 320 of the corresponding impedance network.

[0157] According to an embodiment, the current mirror device of the reference current generator 3051 and the current mirror device of the high-side supply voltage generator 3052 are connected at the input terminal T IN With ground terminal T GND To achieve this, according to an embodiment, the source terminal of the first mirror transistor 325 of the reference current generator 3051 is electrically coupled (e.g., directly connected) to the source terminal of the third mirror transistor 335 of the high-side power supply voltage generator 3052, and the source terminal of the first mirror transistor 325 of the high-side power supply voltage generator 3052 is electrically coupled (e.g., directly connected) to the input terminal T IN , and the source terminal of the third mirror transistor 335 of the reference current generator 3051 is electrically coupled (eg, directly connected) to the ground terminal T GND In this way, the reference current I from the impedance network of the reference current generator 3051 is REF,HS is mirrored to the corresponding current mirror device, and then the reference current I REF,HSThe current mirror device flows to the high side supply voltage generator 3052 and thus it is mirrored to the corresponding impedance network.

[0158] According to an embodiment, the high-side voltage generation stage 130 includes a circuit for generating a voltage from the high-side driver 110 HS A clamping device for absorbing current peaks (or equivalently, charge loss). According to an embodiment, the clamping device includes a device electrically coupled between the high-side power supply voltage generator 3052 and the ground terminal T GND According to an embodiment, the clamp transistor 340 includes a PMOS transistor having a source terminal electrically coupled (e.g., directly connected) to the source terminal of the third voltage-dividing transistor 320 of the high-side power supply voltage generator 3052 (and thus directly connected to the high-side power supply terminal), a gate terminal electrically coupled (e.g., directly connected) to the source terminal of the third mirror transistor 335 of the high-side power supply voltage generator 3052, and a gate terminal electrically coupled (e.g., directly connected) to the ground terminal T GND The drain terminal of

[0159] According to an embodiment, as described above, the impedance network R2 of the reference voltage generator 2052 of the low-side voltage generating stage 125 is equal to the impedance network of the reference current generator 3051 of the high-side voltage generating stage 130 .

[0160] According to an embodiment, the high-side voltage generating stage 130 shares the impedance network of the reference current generator 3051 with the reference voltage generator 2052 of the low-side voltage generating stage 125, and thus the impedance network R2 of the reference voltage generator 2052 of the low-side voltage generating stage 125 also serves as the impedance network of the reference current generator 3051 of the high-side voltage generating stage 130 (it should be understood that in this embodiment, the impedance network R2 is a fixed impedance network and the impedance network R1 is a variable impedance network). This embodiment represents a practical and optimized implementation that allows obtaining a power loss optimized switching converter with substantially no or negligible additional area occupation.

[0161] exist Figure 4 A circuit diagram of a switching converter 100 featuring such an optimized implementation is shown in FIG. Figure 4 Also shown is a basic circuit diagram of a charge recovery stage 135, which is intended to provide a charge recovery circuit for the high-side switch device 105. HS As will be appreciated from the following discussion, although the charge recovery stage 135 is illustrated in the context of an optimized implementation of the low-side 125 and high-side 130 voltage generation stages, the charge recovery stage 135 can be equally applied regardless of the specific circuit implementation of the low-side 125 and high-side 130 voltage generation stages.

[0162] According to the principles of some embodiments of the present invention, the charge recovery stage 135 is configured to HS During the drive period, the storage from the high-side driver 110 HS The lost charge (hereinafter, high-side charge loss) and the LS During the driving period, at least part of the stored high-side charge loss is released to the low-side driver 110 LS , in order to at least partially compensate for the low-side switching device 105 LS During the drive period from the low side driver 110 LS Lost charge.

[0163] The high-side charge loss can be considered as the charge loss from the input terminal T IN Flows to the ground terminal T GND The charge is passed through the high-side driver 110 HS (In particular, through the high-side driver 110 HS The last buffer of the tapered buffer device) and the clamp transistor 340 (in fact, in the absence of the charge recovery stage 135, the drain terminal of the clamp transistor 340 will be electrically connected to the ground terminal T GND ).

[0164] The low-side charge loss can be considered as the charge loss from the input terminal T IN Through the output transistor 235 and the low-side driver 110 LS (In particular, through the low-side driver 110 LS The last buffer of the tapered buffer device) flows to the ground terminal T GND of charge.

[0165] According to an embodiment, the charge recovery stage 135 includes a storage unit, such as a storage capacitor 405, which is configured to store the high-side charge loss (and release the (stored) high-side charge loss (or at least a portion thereof) to the low-side driver 110. LS ).

[0166] According to an embodiment, the storage capacitor 405 is electrically coupled to the low-side power supply terminal (or equivalently, to the source terminals of the output transistors 235 , 240 ).

[0167] According to an embodiment, the storage capacitor 405 includes a first terminal electrically coupled (eg, directly connected) to the low-side power supply terminal and a first terminal electrically coupled (eg, directly connected) to the ground terminal T . GND The second terminal of

[0168] According to an embodiment, the charge recovery stage 135 includes a switch unit 410. The switch unit 410 is Figure 4In the figure, conventional general switch symbols are used to represent the switch unit 410, because the specific implementation of the switch unit 410 is not limiting to the present invention. In fact, without loss of generality, the switch unit 410 may include, for example, a switch diode (or more switch diodes), a switch transistor (or more switch diodes), or a combination thereof.

[0169] According to an embodiment, the switch unit 410 is configured to selectively allow the high-side charge losses to flow through (to be stored in) the storage capacitor 405 .

[0170] As in Figure 4 , according to an embodiment, the switch unit 410 is configured to operate between a first operating position and a second operating position, in which the storage capacitor 405 is allowed to receive the high-side charge loss (in the first operating position, the high-side driver 110 HS electrically coupled to the storage capacitor 405), in the second operating position, preventing the storage capacitor 405 from receiving high-side charge loss (in the second operating position, the high-side driver 110 HS and electrically decoupled from storage capacitor 405).

[0171] As in Figure 4 In the second operating position of the switch unit 410, the high-side charge loss is discharged to the ground terminal T GND , which reduces the actual waste of high-side charge loss (in the second operating position, the high-side driver 110 HS Electrically coupled to the ground terminal T GND According to an embodiment, the switch unit 410 includes a first terminal electrically coupled (eg, directly connected) to the drain terminal of the clamp transistor 340 (in order to receive the high-side driver 110). HS Flowing through it), and electrically coupled to the first terminal of the storage capacitor 405 in the first operating position of the switch unit 410 or electrically coupled to the ground terminal T in the second operating position of the switch unit 410. GND The second terminal of

[0172] Thus, in the considered embodiment, the switch unit 410 is configured to electrically couple or decouple the high-side power supply terminal with the low-side power supply terminal to allow or prevent, respectively, high-side charge losses from flowing into the storage capacitor 405 .

[0173] According to an embodiment, the charge recovery stage 135 is configured to be HS With the low-side supply voltage V LS The comparison between the high-side power supply terminals is used to selectively store the high-side charge loss (or equivalently, to selectively couple or decouple the high-side power supply terminal with the low-side power supply terminal).

[0174] According to an embodiment, the charge recovery stage 135 includes a comparator unit 415 for comparing the high-side power supply voltage V HS With the low-side supply voltage V LS The comparison is performed between the control unit 410 and the control unit 411, and is used to operate the switch unit 410 according to the comparison result.

[0175] As in Figure 4 As conceptually shown in FIG. 1 , the comparator unit 415 includes a first input terminal electrically coupled (eg, directly connected) to the high-side power supply terminal for receiving the high-side power supply voltage V HS A second input terminal electrically coupled (eg, directly connected) to the low-side power supply terminal for receiving a low-side power supply voltage V LS and an output terminal for controlling the switching unit 410 according to the comparison result.

[0176] As in Figure 4 As conceptually shown in FIG. 4 , comparator unit 415 comprises a comparator with hysteresis: this advantageously allows the high-side supply voltage V HS and / or the low-side supply voltage V LS In the case of parasitic oscillations, undesired switching of the switching unit 410 is avoided or at least strongly reduced.

[0177] According to an embodiment, when the high-side switch device 105 HS is in the ON state (and thus the low-side switch device 105 LS In the OFF state), if the high-side power supply voltage V HS Equal to or higher than the low-side supply voltage V LS (Or equivalently, if the high-side supply voltage V HS Equal to or higher than the power supply voltage drop V CC ), the switch unit 410 is switched in the first operating position: under this condition, the high-side charge loss is allowed to be stored in the storage capacitor 405 without damaging the high-side driver 110 HS Both ends and low side driver 110 LS The power supply voltage drop V CC .

[0178] According to an embodiment, when the high-side switch device 105 HS is in the ON state (and thus the low-side switch device 105 LS In the OFF state), if the high-side power supply voltage V HS Lower than the low-side supply voltage V LS (Or equivalently, if the high-side supply voltage V HS Below the power supply voltage drop V CC), the switch unit 410 is switched in the second operating position: in this case, the high-side charge losses are prevented from being stored in the storage capacitor 405 (so as not to damage the high-side driver 110 HS Both ends and low side driver 110 LS The power supply voltage drop V CC ), and is discharged to the ground terminal T GND (As it would occur without the charge recovery stage 135).

[0179] Therefore, in the basic embodiment of the present invention, the comparator unit 415 has a voltage equal to the low-side power supply voltage V LS The threshold voltage of the comparator (hereinafter referred to as the comparator threshold voltage).

[0180] According to alternative embodiments, as better understood from the following discussion of exemplary circuit implementations of the charge recovery stage 135, the comparator threshold voltage may be higher than the low-side supply voltage V LS .

[0181] According to an embodiment, when the high-side switch device 105 HS is in the OFF state (and thus the low-side switch device 105 LS When the switch unit 410 is in the ON state), the high-side charge loss that may be stored in the storage capacitor 405 may be used to at least partially compensate the low-side charge loss regardless of the operating position of the switch unit 410. In this case, the following two scenarios may occur:

[0182] - If the low-side charge loss is lower than the stored high-side charge loss, the low-side charge loss is fully compensated by the stored high-side charge loss; according to Kirchhoff's circuit law, the remaining (unused) amount of the stored high-side charge loss (hereinafter, the unused high-side charge loss) is discharged to the ground terminal T via the output transistor 240 GND Therefore, in this scenario, the actual charge loss affecting the switching converter 100 is determined by the unused high-side charge loss (which is a portion of the high-side charge loss) rather than the entire high-side charge loss;

[0183] If the low-side charge loss is higher than the stored high-side charge loss, the low-side charge loss is partially compensated by the stored high-side charge loss; according to Kirchhoff's circuit law, the remaining amount of the uncompensated low-side charge loss (hereinafter, the uncompensated low-side charge loss) is transferred from the input terminal T IN is obtained through output transistor 235. Therefore, in this scenario, the actual charge loss affecting switching converter 100 is determined by the uncompensated low-side charge loss (which is a portion of the low-side charge loss) rather than the entire low-side charge loss.

[0184] Therefore, in both cases, power loss optimization is achieved.

[0185] exist Figure 5 A circuit implementation of the charge recovery stage 135 according to an embodiment of the present invention is shown in FIG.

[0186] According to an embodiment, the switch unit 410 includes a transistor (e.g., an NMOS transistor) having a gate terminal electrically coupled (e.g., directly connected) to the output terminal of the comparator unit 415, an output terminal electrically coupled (e.g., directly connected) to the ground terminal T 214, and a ground terminal T 315. GND and a drain terminal electrically coupled (eg, directly connected) to the low-side power supply terminal and the drain terminal of the clamp transistor 340. As shown in FIG.

[0187] According to an embodiment, the charge recovery stage 135 includes a protection diode 502. According to an embodiment, the protection diode 502 has a cathode terminal electrically coupled (e.g., directly connected) to a drain terminal of a transistor implementing the switch unit 410 and an anode terminal electrically coupled (e.g., directly connected) to a first terminal of the storage capacitor 405.

[0188] According to an embodiment, the comparator unit 415 comprises a conventional input differential stage.

[0189] According to an embodiment, the input differential stage includes a first input transistor (e.g., a PMOS transistor) 5051 and a second input transistor (e.g., a PMOS transistor) 5052 coupled to each other in a conventional differential configuration (hereinafter, when distinguishing between the first 5051 and the second 5052 input transistors, the first 5051 and the second 5052 input transistors will also be globally represented as input transistors 5051, 5052).

[0190] According to an embodiment, the first input transistor 5051 has a gate terminal electrically coupled to the high-side power supply terminal for receiving the high-side power supply voltage V HS (the gate terminal of the first input transistor 5051 thus represents the first input terminal of the comparator unit 415) and source and drain terminals, and the second input transistor 5052 has a gate terminal electrically coupled to the low-side power supply terminal for receiving the low-side power supply voltage V LS (the gate terminal of the second input transistor 5052 thus represents the second input terminal of the comparator unit 415), a source terminal electrically coupled to the source terminal of the first input transistor 5051, and a drain terminal. According to an embodiment, as better discussed below, the drain terminals of the first 5051 and second 5052 input transistors are coupled to a current mirror arrangement.

[0191] According to an embodiment, the input differential stage includes a first input diode (or other electronic component, such as one or more resistors) 505 electrically coupled to first 5051 and second 5052 input transistors, respectively. 1D and a second input diode (or other electronic component, such as one or more resistors) 505 2D According to an embodiment, the first input diode 505 1D has a cathode terminal electrically coupled (eg, directly connected) to the source terminal of the first input transistor 5051, and the second input diode 505 2D has a cathode terminal electrically coupled (eg, directly connected) to a source terminal of the second input transistor 5052. According to an embodiment, the first 505 1D and the second 505 2D The anode terminals of the input diodes are electrically coupled to each other (eg, directly connected).

[0192] According to an embodiment, the input differential stage includes a circuit for setting a voltage higher than the low-side supply voltage V LS According to an embodiment, the electronic component includes one or more diodes electrically coupled between the source terminals of the input transistors 5051, 5052. According to an embodiment, the electronic component includes: a first diode 510 having an anode terminal electrically coupled (e.g., directly connected) to the source terminal of the first input transistor 5051; and a second diode 515 having an anode terminal electrically coupled (e.g., directly connected) to the cathode terminal of the first diode 510 and a cathode terminal electrically coupled (e.g., directly connected) to the source terminal of the second input transistor 5052.

[0193] In this configuration, the comparator threshold voltage is:

[0194] V HS =V LS +2*V DIODE

[0195] Where V DIODE is the voltage across each diode 510 , 515 .

[0196] In alternative embodiments (not shown), a different number of diodes may be used to set the comparator threshold voltage.

[0197] In alternative embodiments (not shown), electronic components other than diodes may be used to set the comparator threshold voltage. By way of example only, one or more resistors and / or one or more transistors may be used in addition or alternatively to the diode.

[0198] According to an embodiment, the comparator unit 415 includes a bias current source 520, which is generally represented by conventional electrical symbols for an ideal current generator, for generating a bias current I B .

[0199] According to an embodiment, the bias current source 520 is electrically coupled to the input terminal T IN and the source terminals of the input transistors 5051, 5052. In the example considered, the bias current source 520 is directly connected between the input terminal T IN and the first 505 1D and the second 505 2D between the anode terminals of the input diode.

[0200] According to well-known electronic principles, depending on the high-side power supply voltage V HS and the low-side supply voltage V LS The difference between the allowable bias current I B (completely or substantially completely) flows through the first input transistor 5051 or through the second input transistor 5052. In particular, if the high-side power supply voltage V HS is equal to or higher than the comparator threshold voltage, the second input transistor 5052 is more conductive than the first input transistor 5051 and allows the bias current I B flows completely or substantially completely through the second input transistor 5052, otherwise the first input transistor 5051 is more conductive than the second input transistor 5052 and allows the bias current I B The voltage flows completely or substantially completely through the first input transistor 5051 .

[0201] According to an embodiment, the comparator unit 415 comprises a current mirror device for mirroring a bias current I flowing through the first input transistor 5051 or through the second input transistor 5052 towards an output terminal of the comparator unit 415. B .

[0202] According to an embodiment, the current mirror device comprises: first mirror transistors 5251, 5252 (eg, NMOS transistors) having a first current mirror transistor 5251, 5252 electrically coupled (eg, directly connected) to a ground terminal T GND , drain terminals electrically coupled (e.g., directly connected) to the drain terminals of input transistors 5051, 5052, respectively, and gate terminals electrically connected to the respective drain terminals (first mirror transistors 5251, 5252 are thus in a diode-connected configuration); second mirror transistors 5301, 5302 (e.g., NMOS transistors) having gate terminals electrically coupled (e.g., directly connected) to the ground terminal T GNDA source terminal of the transistor 5251 and a gate terminal electrically coupled (e.g., directly connected) to the gate terminals of the corresponding first mirror transistors 5251, 5252; a third mirror transistor 535 (e.g., a PMOS transistor) having a gate terminal electrically coupled (e.g., directly connected) to the low-side power supply terminal for receiving the low-side power supply voltage V LS , a source terminal of the second mirror transistor 5301, a drain terminal electrically coupled (e.g., directly connected) to the drain terminal of the second mirror transistor 5301, and a gate terminal electrically connected to the corresponding drain terminal (the third mirror transistor 535 is therefore in a diode-connected configuration); and a fourth mirror transistor 540 (e.g., a PMOS transistor) having a gate terminal electrically coupled (e.g., directly connected) to the low-side power supply terminal for receiving the low-side power supply voltage V LS a source terminal of, a drain terminal electrically coupled (e.g., directly connected) to the drain terminal of the second mirror transistor 5302, and a gate terminal electrically coupled (e.g., directly connected) to the gate terminal of the third mirror transistor 535.

[0203] According to the well-known principle of current mirror, the first 5251, second 5301 and third 535 mirror transistors are configured to bias the bias current I flowing through the first input transistor 5051. B The first mirror transistor 5252 is configured to reduce the bias current I flowing through the second input transistor 5052 by mirroring to the fourth mirror transistor 540, which decrements the increase in the voltage (hereinafter, drain voltage) at its drain terminal (and therefore, at the output terminal of the comparator unit 415, as better discussed below), while the first mirror transistor 5252 is configured to reduce the bias current I flowing through the second input transistor 5052 by B Mirrored to the second mirror transistor 5302, this decrements the reduction of the drain voltage at its drain terminal (and therefore, at the output terminal of the comparator unit 415, as better discussed below).

[0204] According to an embodiment, the comparator unit 415 includes: a buffer unit 545 having an input terminal electrically coupled (e.g., directly connected) to the drain terminal of the second 5302 and a fourth 540 mirror transistor for receiving the drain voltage therefrom; and an output terminal electrically coupled (e.g., directly connected) to the gate terminal of the transistor implementing the switch unit 410 (the output terminal of the buffer unit 545 thus acts as the output terminal of the comparator unit 415) for providing a regenerated version of the drain voltage (in order to appropriately control the switch unit 410).

[0205] According to an embodiment, as in Figure 5 , the buffer unit 545 comprises a buffer with hysteresis in order to avoid or at least strongly reduce undesired switching of the switch unit 410 in case of parasitic oscillations of the drain voltage due to the high-side supply voltage V HSand / or the low-side supply voltage V LS The operation of the charge recovery stage 135 can be summarized as follows. HS In the ON state, if the high-side power supply voltage V HS is higher than the comparator threshold voltage, the second input transistor 5052 is more conductive than the first input transistor 5051 and allows the bias current I B The bias current I flows completely or substantially completely through the second input transistor 5052, after which the bias current I is converted by the first mirror transistor 5252. B Mirrored to the second mirror transistor 5302. This results in a decrease in the drain voltage, which determines that the switch unit 410 is switched in the OFF state and thus determines that the high-side driver 110 HS The high side charge loss is stored in the storage capacitor 405.

[0206] Otherwise, if the high-side supply voltage V HS Below the comparator threshold voltage, the first input transistor 5051 is more conductive than the second input transistor 5052 and allows the bias current I B flows completely or substantially completely through the first input transistor 5051, after which the bias current I B The first 5251, second 5301 and third 535 mirror transistors are mirrored to the fourth mirror transistor 540. This results in an increase in the drain voltage, which determines that the switch unit 410 is switched in the ON state and thus causes the high-side driver 110 to be switched. HS The high-side charge loss is directed toward the ground terminal T via the switch unit 410. GND Discharge.

[0207] Reference now Figure 6 , which shows a simplified block diagram of an electronic system 600 (ie, a portion thereof) including the switching converter 100 (or more thereof) according to an embodiment of the present invention.

[0208] According to an embodiment, the electronic system 600 is applicable to any electronic device.

[0209] According to an embodiment, the electronic system 600 includes a controller 605 (eg, one or more microprocessors and / or one or more microcontrollers).

[0210] According to an embodiment, the electronic system 600 includes an input / output device 610 (e.g., a keyboard and / or a screen). The input / output device 610 can, for example, be used to generate and / or receive messages. The input / output device 610 can, for example, be configured to receive / supply digital signals and / or analog signals.

[0211] According to an embodiment, the electronic system 600 includes a wireless interface 615 for exchanging messages with a wireless communication network (not shown), for example, by using radio frequency (RF) signals. Examples of the wireless interface may include an antenna and a wireless transceiver.

[0212] According to an embodiment, the electronic system 600 includes a power supply device (eg, a battery) 620 for supplying power to the electronic system 600 .

[0213] According to an embodiment, the electronic system 600 includes one or more communication channels (buses) 625 to allow data exchange between the switching converter 100, the controller 605 (when provided), the input / output device 610 (when provided), the wireless interface 615 (when provided), and the power supply device 620 (when provided).

[0214] Naturally, in order to meet local and specific requirements, those skilled in the art may apply to the embodiments of the present invention many of the logical and / or physical modifications and alterations described above. More specifically, although the present invention has been described with reference to the preferred embodiments of the present invention with a certain degree of particularity, it should be understood that various omissions, substitutions and changes to form and details and other embodiments are also possible. In particular, different embodiments of the present invention may be practiced even without the specific details set forth in the preceding description to provide a more thorough understanding of the present invention; on the contrary, well-known features may have been omitted or simplified so as not to hinder the description with unnecessary details. In addition, it is expressly intended that specific elements and / or method steps described in conjunction with any disclosed embodiment of the present invention may be incorporated in any other embodiment.

[0215] In particular, similar considerations apply if the switching converter has a different structure or includes equivalent components. In any case, any component thereof may be separated into several elements, or two or more components may be combined into a single element; moreover, each component may be replicated to support the execution of corresponding operations in parallel. It should also be noted that (unless otherwise stated) any interaction between different components generally does not need to be continuous and may be direct or indirect through one or more intermediate devices.

Claims

1. A switching converter for converting a DC input voltage into a DC output voltage, the switching converter comprising: a switching stage, comprising a first switching device and a second switching device, wherein the first switching device and the second switching device are configured to receive the DC input voltage and provide the DC output voltage according to the DC input voltage; a driving stage, comprising a first driving device and a second driving device, wherein the first driving device and the second driving device are configured to drive the first switching device and the second switching device, respectively; a current sensing circuit configured to sense an output current provided by the switching stage; a voltage generating circuit configured to generate at least one power supply voltage configured to power the driver stage, the voltage generating circuit configured to adjust the at least one power supply voltage according to the output current sensed by the current sensing circuit; as well as A charge recovery stage is configured to store a first charge lost from the first driving device during driving of the first switching device, and at least partially release the stored first charge to the second driving device during driving of the second switching device so as to at least partially compensate for a second charge lost from the second driving device during driving of the second switching device.

2. The switching converter of claim 1 , wherein the voltage generating circuit comprises a first voltage generating stage and a second voltage generating stage, the first voltage generating stage being configured to generate a first power supply voltage configured to power the second driving device based on the output current, and the second voltage generating stage being configured to generate a second power supply voltage configured to power the first driving device based on a reference voltage corresponding to the first power supply voltage, and the charge recovery stage being configured to selectively store the first charge based on a comparison between the first power supply voltage and the second power supply voltage.

3. The switching converter of claim 2 , wherein the first supply voltage and the second supply voltage are configured to provide the same supply voltage drop for powering the first drive device and the second drive device, and wherein the charge recovery stage is configured to allow the first charge to be stored when the second supply voltage is higher than the first supply voltage, or the charge recovery stage is configured to prevent the first charge from being stored when the second supply voltage is lower than the first supply voltage.

4. The switching converter of claim 2 , wherein the charge recovery stage comprises: a storage capacitor configured to store the first charge; a switch circuit configured to selectively allow or prevent the first charge from flowing into the storage capacitor; as well as A comparator circuit is configured to operate the switch circuit based on a comparison between the first power supply voltage and the second power supply voltage. 5 . The switching converter of claim 4 , wherein the charge recovery stage further comprises a protection diode having an anode coupled to the switching circuit and a cathode coupled to the storage capacitor. The switching converter of claim 4 , wherein the comparator circuit has hysteresis.

7. The switching converter of claim 4 , wherein the first voltage generating stage comprises a decoupling stage configured to receive the reference voltage and provide the first power supply voltage to a first power supply terminal while electrically decoupling the first voltage generating stage and the second driving device from each other, the storage capacitor being electrically coupled to the first power supply terminal.

8. The switching converter of claim 7 , wherein the second voltage generating stage comprises: a first impedance network configured to receive the first supply voltage and provide a corresponding further reference current; a second impedance network, which is the same as the first impedance network, and is configured to receive the DC input voltage and the additional reference current and provide the second power supply voltage to a second power supply terminal, and the switching circuit electrically couples the second power supply terminal to the first power supply terminal or electrically decouples the second power supply terminal from the first power supply terminal to respectively allow or prevent the first charge from flowing into the storage capacitor.

9. The switching converter of claim 8 , wherein the first voltage generating stage comprises a reference current generator and a reference voltage generator, the reference current generator being configured to generate a reference current adjustable according to the output current, and the reference voltage generator being configured to generate the reference voltage according to the reference current, and wherein the reference voltage generator comprises a third impedance network, and the second voltage generating stage shares the first impedance network with the reference voltage generator of the first voltage generating stage.

10. The switching converter of claim 1, wherein the switching converter is a buck converter, a boost converter, or a buck-boost converter.

11. An electronic system comprising: Controller; power supply; as well as Switching converters, including: A switching stage, comprising: a first switching device and a second switching device, configured to receive an input voltage and provide an output voltage, The driving stage includes: a first driving device and a second driving device, configured to drive the first switching device and the second switching device respectively, a current sensing circuit configured to sense an output current provided by the switching stage, a voltage generating circuit configured to generate at least one power supply voltage configured to power the driver stage, the voltage generating circuit configured to adjust the at least one power supply voltage according to the output current sensed by the current sensing circuit, and A charge recovery stage is configured to store a first charge lost from the first driving device during driving of the first switching device, and at least partially release the stored first charge to the second driving device during driving of the second switching device so as to at least partially compensate for a second charge lost from the second driving device during driving of the second switching device.

12. The electronic system of claim 11, further comprising a wireless interface, wherein the power source comprises a battery.

13. An electronic system according to claim 11, wherein the voltage generating circuit includes a first voltage generating stage and a second voltage generating stage, the first voltage generating stage is configured to generate a first power supply voltage configured to power the second driving device based on the output current, and the second voltage generating stage is configured to generate a second power supply voltage configured to power the first driving device based on a reference voltage corresponding to the first power supply voltage, and the charge recovery stage is configured to selectively store the first charge based on a comparison between the first power supply voltage and the second power supply voltage.

14. The switching converter of claim 13 , wherein the charge recovery stage comprises: a storage capacitor configured to store the first charge; a switch circuit configured to selectively allow or prevent the first charge from flowing into the storage capacitor; as well as A comparator circuit is configured to operate the switch circuit based on a comparison between the first power supply voltage and the second power supply voltage.

15. The switching converter of claim 14 , wherein the first voltage generating stage comprises a decoupling stage configured to receive the reference voltage and provide the first power supply voltage to a first power supply terminal while electrically decoupling the first voltage generating stage and the second driving device from each other, the storage capacitor being electrically coupled to the first power supply terminal.

16. The switching converter of claim 15, wherein the second voltage generating stage comprises: a first impedance network configured to receive the first supply voltage and provide a corresponding further reference current; a second impedance network, identical to the first impedance network, configured to receive the input voltage and the additional reference current and to provide the second power supply voltage to a second power supply terminal, the switch circuit electrically coupling the second power supply terminal to the first power supply terminal or electrically decoupling the second power supply terminal from the first power supply terminal to respectively allow or prevent the first charge from flowing into the storage capacitor.

17. A method for converting a DC input voltage to a DC output voltage using a switching converter, the method comprising: driving a switching stage of the switching converter using a driving stage of the switching converter, wherein the switching stage comprises a first switching device and a second switching device, the first switching device and the second switching device being used to receive the DC input voltage and provide the DC output voltage according to the DC input voltage, and wherein the driving stage comprises a first driving device and a second driving device for driving the first switching device and the second switching device respectively; sensing an output current provided by the switching stage; generating at least one power supply voltage for powering the driver stage, wherein generating the at least one power supply voltage comprises: adjusting the at least one power supply voltage according to the sensed output current; as well as A first charge lost from the first driving device is stored during driving of the first switching device, and the stored first charge is at least partially released to the second driving device during driving of the second switching device so as to at least partially compensate for a second charge lost from the second driving device during driving of the second switching device.

18. The method according to claim 17, further comprising: generating a first power supply voltage for powering the second driving device; generating a second power supply voltage for powering the first driving device according to a reference voltage corresponding to the first power supply voltage; as well as A first charge is selectively stored based on a comparison between the first power supply voltage and the second power supply voltage.

19. The method of claim 18, wherein selectively storing the first charge comprises: A switch circuit is controlled using an output of a comparator circuit for comparing the first power supply voltage with the second power supply voltage, the switch circuit having a first terminal coupled to a storage capacitor and a second terminal coupled to a first power supply terminal.

20. The method of claim 17, wherein the DC output voltage is lower than the DC input voltage.

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