Push-pull converter and driving method thereof

Abstract

The application discloses a push-pull converter and a driving method thereof. The push-pull converter comprises a transformer, a first switch tube and a second switch tube connected to a primary side of the transformer, and further comprises a driving circuit, a detection circuit, a dead time control circuit and a logic control circuit. The push-pull converter and the driving method thereof optimize and improve the efficiency by configuring the turn-on and turn-off of the first switch tube and the second switch tube on the primary side according to the characteristics of the push-pull converter. The turn-on speed of the first switch tube and the second switch tube is fast, and the driving in the turn-off stage is controlled in multiple sections. The driving rate in each section can be adjusted to reduce the voltage stress of the first switch tube and the second switch tube. The part of the turn-off stage that does not affect the spike is accelerated, so that the spike is generated only by the magnetizing current. ZVS (zero voltage turn-on) can be realized by setting a large dead time, and the system's ability to correct the magnetic bias is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of switching power supply technology, in particular to a push-pull converter and a driving method thereof. BACKGROUND

[0002] The push-pull topology is a common topology, and its structural diagram is shown in Figure 1 . Because the transformer T works in four quadrants, the power density of the transformer T is higher. The peripheral components are less, so the cost is lower. These characteristics make it widely used in various isolation occasions such as industrial and automotive. However, because the transformer T and the switching tubes Q1 and Q2 (usually MOSFET) work in a symmetrical state, the drive circuit has high requirements in dead time, driving speed, etc. The existence of the leakage inductance of the transformer T makes the switching tube bear a voltage spike in addition to the 2*Vin voltage stress of the topology itself when it is turned off. At the same time, this topology belongs to the hard switching category, so the switching loss of the switching tubes Q1 and Q2 also needs to be carefully considered. These factors that have a greater relationship with the performance of the push-pull converter are greatly related to the drive circuit of the power tube. A reasonable drive circuit can balance the efficiency, voltage stress, etc., so that the overall performance is optimized.

[0003] A commonly used push-pull MOSFET drive circuit structure is shown in Figure 2 . The circuit uses the structure of upper PMOS and lower NMOS. When the PWM output is high, the NMOS is turned on, the gate voltage of the switching tube Q1 is pulled to low through the drive resistor Rg, and the driven switching tube Q1 is not turned on. When the PWM output is low, the PMOS is turned on, the gate of the switching tube Q1 is pulled high to Vg through the drive resistor Rg, and the driven switching tube Q1 is turned on. Some drive circuits replace NMOS and PMOS with NPN and PNP triodes, and the working principle is similar. Some special applications require different opening and closing speeds, so a resistance and a diode are connected in parallel on the drive resistor Rg based on Figure 2 to achieve separate control of the opening and closing speeds, and the principle is similar.

[0004] The drive requirements of the push-pull converter for the switching tubes Q1 and Q2 are as follows: 1. During the opening stage of the switching tube Q1 or Q2, the voltage and current overlap are as low as possible without causing EMI problems, so as to reduce the switching loss; 2. During the off stage of the switching tube Q1 or Q2, the load energy in the magnetic core is discharged through the secondary diode, so only the magnetizing current produces a voltage spike under the action of the leakage inductance, and therefore the off speed cannot be too fast; 3. During the off stage of the switching tube Q1 or Q2, the conversion time generated by the non-load current transmission is as low as possible, so as to improve the conversion efficiency.

[0005] The driving on and off processes of the switch tube Q1 or Q2 are shown as Figure 3 Figure 3 In terms of the driving requirements, the specific requirements are: 1, the rate in the on stage is moderate, both the efficiency and the EMI are taken into account; 2, the t5 in the off stage is reduced as much as possible, the t6 and t7 are increased as much as possible, and the t8 stage is reduced as much as possible.

[0006] Therefore, the general push-pull type MOS driving circuit is not the most ideal as the power MOSFET driving circuit of the push-pull converter, and it is urgent to optimize the existing push-pull type MOS driving circuit and improve the performance of the push-pull converter such as the efficiency, the voltage stress, the EMI, the load capacity and the like.

[0007] The information disclosed in this BACKGROUND section is only for the purpose of increasing the understanding of the general background of the application, and should not be regarded as acknowledging or implying in any form that it constitutes prior art known to those of ordinary skill in the art. SUMMARY

[0008] The purpose of the present application is to provide a push-pull converter and a driving method thereof, which can improve the performance of the push-pull converter such as the efficiency, the voltage stress, the EMI and the load capacity.

[0009] To achieve the above-mentioned purpose, an embodiment of the present application provides a push-pull converter, comprising a transformer and a first switch tube and a second switch tube connected to a primary side of the transformer, the first switch tube and the second switch tube have at least two off stages in the off process, and the push-pull converter further comprises a driving circuit, a detection circuit and a logic control circuit.

[0010] The driving circuit is used to control the off speed of the first switch tube or the second switch tube in the off stage; the detection circuit is used to output a corresponding detection signal when the first switch tube or the second switch tube is at a critical point between two adjacent off stages; the logic control circuit is used to control the driving circuit, and the logic control circuit outputs a control signal after receiving the detection signal, and the driving circuit changes the off speed of the first switch tube or the second switch tube in the next off stage according to the control signal.

[0011] In one or more embodiments of the present application, the push-pull converter further comprises a dead time control circuit, which is used to provide a dead time for the current first switch tube or second switch tube before the other switch tube is turned on and output a dead time detection signal after the dead time ends, and the logic control circuit turns on the other switch tube after receiving the dead time detection signal.

[0012] In one or more embodiments of the present application, the off stage comprises a first off stage and a second off stage; and the detection circuit comprises:

[0013] ​a first off-stage detection circuit configured to output a first detection signal when the first switch tube or the second switch tube is in a first off-stage; and

[0014] a second off-stage detection circuit configured to output a second detection signal when the first switch tube or the second switch tube is in a second off-stage.

[0015] In one or more embodiments of the present application, the driving circuit comprises a plurality of MOS tubes connected in series, and the on-resistances of at least some of the MOS tubes are different, and different MOS tubes are controlled to output voltage signals of different sizes to control the first switch tube and the second switch tube.

[0016] In one or more embodiments of the present application, the driving circuit comprises a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube, the source of the first MOS tube is connected to a power supply voltage, the drains of the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are connected and output a voltage signal, the sources of the second MOS tube, the third MOS tube and the fourth MOS tube are connected to ground, and the gates of the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are respectively configured to receive corresponding control signals.

[0017] In one or more embodiments of the present application, the on-resistance of the second MOS tube is 0.8-1.2 times the on-resistance of the first MOS tube, or the on-resistance of the fourth MOS tube is 0.8-1.2 times the on-resistance of the first MOS tube, or the on-resistances of the second MOS tube and the fourth MOS tube are both 0.8-1.2 times the on-resistance of the first MOS tube, the on-resistance of the third MOS tube is 4.5-5.5 times the on-resistance of the first MOS tube, the on-resistance of the third MOS tube is 13-15 times the on-resistance of the second MOS tube, and / or the on-resistance of the third MOS tube is 13-15 times the on-resistance of the fourth MOS tube.

[0018] In one or more embodiments of the present application, the first off-stage detection circuit comprises a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a first inverter, a second inverter and a first D flip-flop;

[0019] The source of the fifth MOS is connected with the D input of the first D flip-flop and connected with the power voltage, the gate of the fifth MOS, the sixth MOS and the seventh MOS is connected to form the first detection end receiving the voltage signal, the drain of the fifth MOS and the sixth MOS is connected, the source of the sixth MOS is connected with the ground, the drain of the seventh MOS is connected with the drain of the fifth MOS and the input of the first inverter, the gate of the seventh MOS is connected with the output of the first inverter, the source of the seventh MOS and the drain of the eighth MOS is connected, the source of the eighth MOS is connected with the ground, the input of the second inverter is connected with the output of the first inverter, the output of the second inverter is connected with the CLK input of the first D flip-flop, and the Q output of the first D flip-flop is used for outputting the first detection signal.

[0020] In one or more embodiments of the present application, the second off phase detection circuit comprises a ninth MOS, a tenth MOS, an eleventh MOS, a twelfth MOS, a third inverter, a fourth inverter and a second D flip-flop.

[0021] The source of the ninth MOS is connected with the D input of the second D flip-flop and connected with the power voltage, the gate of the ninth MOS, the tenth MOS and the twelfth MOS is connected to form the second detection end receiving the voltage signal, the drain of the ninth MOS and the tenth MOS is connected, the source of the tenth MOS is connected with the ground, the drain of the eleventh MOS is connected with the drain of the ninth MOS and the input of the third inverter, the gate of the eleventh MOS is connected with the output of the third inverter, the source of the eleventh MOS and the drain of the twelfth MOS is connected, the source of the twelfth MOS is connected with the ground, the input of the fourth inverter is connected with the output of the third inverter, the output of the fourth inverter is connected with the CLK input of the second D flip-flop, and the Q output of the second D flip-flop is used for outputting the second detection signal.

[0022] In one or more embodiments of the present application, the dead time control circuit comprises a thirteenth MOS, a fourteenth MOS, a fifteenth MOS, a sixteenth MOS, a seventeenth MOS, an eighteenth MOS, a nineteenth MOS, a twentieth MOS, a twenty-first MOS, a first resistance, a second resistance, a first capacitor and a logic circuit.

[0023] The gate of the thirteenth MOS and the fourteenth MOS is connected to form a third detection end for receiving a second detection signal, the source of the thirteenth MOS is connected with a power supply voltage, the drain of the thirteenth MOS is connected with a first end of a first resistor, the second end of the first resistor is connected with the drain of the fourteenth MOS, the source of the fourteenth MOS is connected with the ground, the source of the fifteenth MOS is connected with the power supply voltage, the drain of the fifteenth MOS is connected with the second end of a second resistor and a first end of a first capacitor, the second end of the first capacitor is connected with the ground, the first end of the first resistor and the drain of the thirteenth MOS are connected with the first end of the second resistor, the source of the sixteenth MOS is connected with the power supply voltage, the gate of the sixteenth MOS, the seventeenth MOS and the nineteenth MOS is connected and connected with the first end of the first capacitor, the drains of the sixteenth MOS and the seventeenth MOS are connected, the source of the seventeenth MOS is connected with the ground, the drain of the eighteenth MOS is connected with the drains of the sixteenth MOS and the seventeenth MOS, the source of the eighteenth MOS is connected with the drain of the nineteenth MOS, the source of the nineteenth MOS is connected with the ground, the gate of the twentieth MOS and the twenty-first MOS is connected and connected with the drain of the eighteenth MOS, the source of the twentieth MOS is connected with the power supply voltage, the drains of the twentieth MOS and the twenty-first MOS are connected and connected with the gate of the eighteenth MOS and a first output end of a logic circuit, the source of the twenty-first MOS is connected with the ground, and the output end of the logic circuit is used for outputting a dead zone detection signal.

[0024] In one or more embodiments of the present application, the drive circuit is further configured to accelerate the turn-on speed of the first switch or the second switch during the turn-on process.

[0025] The present application also provides a driving method of a push-pull converter, the push-pull converter comprising a transformer and a first switch and a second switch connected to a primary side of the transformer, the first switch and the second switch having at least two turn-off stages during the turn-off process, the driving method comprising:

[0026] controlling the turn-off speed of the first switch or the second switch in the first turn-off stage;

[0027] detecting the turn-off stage in which the first switch or the second switch is located, and obtaining a corresponding detection signal when the first switch or the second switch is at a critical point between two adjacent turn-off stages;

[0028] if the detection signal is obtained, changing the turn-off speed of the first switch or the second switch in the next turn-off stage.

[0029] In one or more embodiments of the present application, the driving method further comprises:

[0030] providing a dead time for the current first switch tube or second switch tube before another switch tube is turned on, and obtaining a dead time detection signal after the dead time ends;

[0031] turning on the other switch tube after the dead time detection signal is obtained.

[0032] In one or more embodiments of the present application, the off stage comprises a first off stage and a second off stage; the detection of the off stage in which the first switch tube or second switch tube is located comprises detecting a corresponding detection signal when the first switch tube or second switch tube is at a critical point between two adjacent off stages, comprising:

[0033] detecting a voltage signal used for driving the first switch tube or second switch tube;

[0034] determining whether the first off stage and the second off stage in which the first switch tube or second switch tube is located end according to a change of the voltage signal;

[0035] if the first off stage ends, obtaining a first detection signal representing the end of the first off stage;

[0036] if the second off stage ends, obtaining a second detection signal representing the end of the second off stage.

[0037] In one or more embodiments of the present application, if the detection signal is obtained, the turn-off speed of the first switch tube or second switch tube in the next off stage is controlled, comprising:

[0038] if the first detection signal is obtained, the turn-off speed of the first switch tube or second switch tube in the second off stage is slowed down;

[0039] if the second detection signal is obtained, the turn-off speed of the first switch tube or second switch tube in the next off stage is accelerated.

[0040] In one or more embodiments of the present application, the control of the turn-off speed of the first switch tube or second switch tube in the first off stage comprises accelerating the turn-off speed of the first switch tube or second switch tube in the first off stage.

[0041] In one or more embodiments of the present application, the driving method further comprises accelerating the turn-on speed of the first switch tube or second switch tube in the turn-on process.

[0042] Compared with the prior art, the push-pull converter and the driving method thereof according to the present application optimize and improve the efficiency by configuring the turn-on and turn-off of the first switch tube and the second switch tube of the primary side differently according to the characteristics of the push-pull converter; the turn-on speed of the first switch tube and the second switch tube is fast, and the driving in the turn-off stage is controlled in multiple segments, and the driving rate in each segment can be adjusted, thereby reducing the voltage stress of the first switch tube and the second switch tube; the spike is generated only by the magnetizing current by accelerating the part of the turn-off stage that does not affect the spike; ZVS (zero voltage switching) is realized by setting a large dead time, and the system's ability to correct the magnetic bias is improved. The driving circuit of the present application realizes the output of different voltage values by setting MOS tubes with different conduction resistances, controls the turn-off speed in different turn-off stages, optimizes the configuration of the driving circuit and the dead time, and makes the push-pull converter achieve a relatively optimal load regulation rate. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 is a circuit principle diagram of a push-pull converter in the prior art.

[0044] Figure 2 is a circuit principle diagram of a driving circuit of a push-pull converter in the prior art.

[0045] Figure 3 is a signal waveform diagram of the turn-on and turn-off of MOS tubes of the driving circuit of the push-pull converter in the prior art.

[0046] Figure 4 is a circuit principle diagram of a push-pull converter according to an embodiment of the present application.

[0047] Figure 5 is a waveform diagram of the voltage and current of each node in Figure 4 .

[0048] Figure 6 is a circuit principle diagram of a driving circuit according to an embodiment of the present application.

[0049] Figure 7 is a timing logic diagram of the driving circuit according to an embodiment of the present application.

[0050] Figure 8 is a circuit principle diagram of a first turn-off stage detection circuit according to an embodiment of the present application.

[0051] Figure 9 is a signal waveform diagram of each node in Figure 8 .

[0052] Figure 10 is a circuit principle diagram of a second turn-off stage detection circuit according to an embodiment of the present application.

[0053] Figure 11 is Figure 10 a signal waveform diagram of each node in

[0054] Figure 12 is a circuit schematic diagram of a dead time control circuit according to an embodiment of the present application.

[0055] Figure 13 is a flow chart of a driving method of a push-pull converter according to an embodiment of the present application. DETAILED DESCRIPTION

[0056] The specific embodiments of the present application will be described below in detail with reference to the accompanying drawings, but the scope of protection of the present application is not limited by the specific embodiments.

[0057] Unless otherwise clearly indicated, throughout the description and the claims, the term "comprise" or variations such as "comprises" or "comprising" will be understood to imply the inclusion of a stated element or group of elements but not the exclusion of any other element or group of elements.

[0058] It should be understood that, in the following description, "circuitry" can comprise a single or multiple components of hardware, programmable circuitry, state machine circuitry, and / or elements that can store instructions for execution by the programmable circuitry. When an element or circuitry is referred to as being "connected to" another element, or "connected in" with another element, or "connected between" two nodes, it can be directly coupled or connected to the other element or can exist with intervening elements therebetween, and the connection between the elements can be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements therebetween.

[0059] The present application will be further described below with reference to the accompanying drawings and embodiments.

[0060] As shown in Figure 4 , the push-pull converter comprises a transformer T, a first switch Q1 and a second switch Q2 connected to the primary side of the transformer T, a driving circuit 10, a detection circuit 20, a dead time control circuit 30, and a logic control circuit 40. The first switch Q1 and the second switch Q2 have at least two off phases in the off process.

[0061] The first switch tube Q1 and the second switch tube Q2 in the embodiment are N-channel MOS tubes, two of the driving circuit 10, the detection circuit 20 and the dead time control circuit 30 are provided to form two groups to control the first switch tube Q1 and the second switch tube Q2 respectively, and one of the logic control circuit 40 is provided to form a total control unit; in other embodiments, two of the logic control circuit 40 can also be provided correspondingly, or one of the driving circuit 10, the detection circuit 20, the dead time control circuit 30 and the logic control circuit 40 is provided, and the first switch tube Q1 and the second switch tube Q2 can be P-channel MOS tubes or triodes.

[0062] The first switch tube Q1 and the second switch tube Q2 correspond to a group of driving circuit 10, detection circuit 20 and dead time control circuit 30 respectively. The driving circuit 10 and the detection circuit 20 of one group are connected with the gate of the first switch tube Q1 and the logic control circuit 40, and the dead time control circuit 30 is connected with the detection circuit 20 and the logic control circuit 40; the driving circuit 10 and the detection circuit 20 of the other group are connected with the gate of the second switch tube Q2 and the logic control circuit 40, and the dead time control circuit 30 is connected with the detection circuit 20 and the logic control circuit 40.

[0063] Since the first switch tube Q1 and the second switch tube Q2 are symmetrically driven, the first switch tube Q1 is taken as an example to be described in detail below in combination with the drawings.

[0064] In combination with Figure 4 and Figure 5 shown, the driving circuit 10 connected with the gate of the first switch tube Q1 is used to output voltage signals of different sizes to accelerate the opening speed of the first switch tube Q1 in the opening process and control the turn-off speed of the first switch tube Q1 in the turn-off stage. In the embodiment, the turn-off stage includes a first turn-off stage , a second turn-off stage and a third turn-off stage .

[0065] As Figure 6 shown, the driving circuit 10 includes a plurality of connected MOS tubes, at least part of the MOS tubes have different conduction resistances, and different MOS tubes are controlled to output voltage signals of different sizes .

[0066] Specifically, the driving circuit 10 includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3 and a fourth MOS tube M4. The source of the first MOS tube M1 is connected with a power supply voltage Vdd, and the drains of the first MOS tube M1, the second MOS tube M2, the third MOS tube M3 and the fourth MOS tube M4 are connected and output voltage signals The gate of the first switching transistor Q1 is connected to the ground. The sources of the second MOSFET M2, the third MOSFET M3, and the fourth MOSFET M4 are connected to ground.

[0067] The gate of the first MOSFET M1 is used to receive the first control signal. The gate of the second MOSFET M2 is used to receive the second control signal. The gate of the third MOSFET M3 is used to receive the third control signal. The gate of the fourth MOSFET M4 is used to receive the fourth control signal. First control signal Second control signal Third control signal and the fourth control signal All are generated by the logic control circuit 40.

[0068] In this embodiment, the on-resistance of the first MOSFET M1 is relatively small, typically around 500 ohms. The on-resistance of the second MOSFET M2 is 0.8 to 1.2 times that of the first MOSFET M1, or the on-resistance of the fourth MOSFET M4 is 0.8 to 1.2 times that of the first MOSFET M1, or the on-resistances of both the second and fourth MOSFETs are 0.8 to 1.2 times that of the first MOSFET. Preferably, the on-resistances of the second MOSFET M2 and the fourth MOSFET M4 can be set to be equal to the on-resistance of the first MOSFET M1. The on-resistance of the third MOSFET M3 is 4.5 to 5.5 times that of the first MOSFET M1. Preferably, the on-resistance of the third MOSFET M3 can be set to 5 times that of the first MOSFET M1. The on-resistance of the third MOSFET M3 is 13 to 15 times that of the second MOSFET M2 and / or the on-resistance of the third MOSFET M3 is 13 to 15 times that of the fourth MOSFET M4. Preferably, the on-resistance of the third MOSFET M3 is set to 10 times that of the second MOSFET M2 and / or the on-resistance of the third MOSFET M3 is set to 10 times that of the fourth MOSFET M4.

[0069] like Figure 6 As shown, since the first MOSFET M1 is a P-channel MOSFET, and the second MOSFET M2, the third MOSFET M3, and the fourth MOSFET M4 are N-channel MOSFETs, the first control signal should be... When the signal is low, the first MOSFET M1 is turned on, and the second control signal... Third control signal and the fourth control signal When the signal is high, the corresponding second MOSFET M2, third MOSFET M3, and fourth MOSFET M4 are turned on, but when... Figure 7 For ease of illustration, regardless of whether the first MOSFET M1, the second MOSFET M2, the third MOSFET M3, and the fourth MOSFET M4 are N-channel or P-channel MOSFETs, they are all uniformly assumed to be connected to the first control signal. Second control signal Third control signal and the fourth control signal When the signal is high, the corresponding first MOSFET M1, second MOSFET M2, third MOSFET M3, and fourth MOSFET M4 are turned on. In the first control signal... Second control signal Third control signal and the fourth control signal When the signal is low, the corresponding first MOSFET M1, second MOSFET M2, third MOSFET M3 and fourth MOSFET M4 are turned off.

[0070] Through observation Figure 7 As can be seen from Drv1_Q1 to Drv4_Q1, during the turn-on phase of the first switch Q1, the small on-resistance of the first MOSFET M1 facilitates the rapid rise of the gate voltage of the first switch Q1, thus enabling it to turn on quickly and effectively reducing switching losses.

[0071] During the first turn-off phase of the first switch Q1 and the third shut-off phase The second MOSFET M2 and the fourth MOSFET M4 are turned on. Because the on-resistance of the second MOSFET M2 and the fourth MOSFET M4 is relatively small, they can respectively turn off during the first turn-off phase when the first switch Q1 is turned off. and the third shut-off phase Accelerated shutdown is performed. During the subsequent complete shutdown of the first switch Q1, the fourth MOSFET M4 also remains on until the first switch Q1 is turned on again.

[0072] During the second turn-off phase of the first switch Q1 The third MOSFET M3 is turned on. Because the on-resistance of the third MOSFET M3 is relatively large, it is turned off during the first turn-off phase. At this time, the third MOSFET M3 is turned on and remains on until the first switch Q1 is turned on again. The relatively large on-resistance of the third MOSFET M3 allows the primary current of the transformer T to be reduced during the second turn-off phase. A gradual decrease in voltage is beneficial for reducing the voltage stress on the first switching transistor Q1 and optimizing EMI.

[0073] In the embodiment, the detection circuit 20 is configured to output a corresponding detection signal when the first switch tube Q1 is at a critical point between two adjacent off stages. The critical point between two adjacent off stages is a critical point corresponding to the end of a previous off stage and the beginning of a next off stage.

[0074] As shown in Figure 6 , the detection circuit 20 includes a first off stage detection circuit 21 and a second off stage detection circuit 22.

[0075] In the embodiment, the first off stage detection circuit 21 is configured to determine whether the first off stage of the first switch tube Q1 ends according to the magnitude of the voltage signal output by the driving circuit 10 and output a first detection signal when the first off stage ends. .

[0076] As shown in Figure 8 , the first off stage detection circuit 21 includes a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, a first inverter INV1, a second inverter INV2 and a first D flip-flop D1.

[0077] Specifically, the source of the fifth MOS tube M5 is connected to the D input end of the first D flip-flop D1 and connected to the power supply voltage Vdd. The gates of the fifth MOS tube M5, the sixth MOS tube M6 and the seventh MOS tube M7 are connected to form a first detection end receiving the voltage signal , the drains of the fifth MOS tube M5 and the sixth MOS tube M6 are connected to form an output end outputting a voltage , the source of the sixth MOS tube M6 is connected to the ground. The drain of the seventh MOS tube M7 is connected to the drain of the fifth MOS tube M5 and the input end of the first inverter INV1, the gate of the seventh MOS tube M7 is connected to the output end of the first inverter INV1, the source of the seventh MOS tube M7 is connected to the drain of the eighth MOS tube M8, and the source of the eighth MOS tube M8 is connected to the ground. The input end of the second inverter INV2 is connected to the output end of the first inverter INV1, the output end of the second inverter INV2 is connected to the CLK input end of the first D flip-flop D1, and the Q output end of the first D flip-flop D1 is configured to output the first detection signal .

[0078] In combination with Figure 8 and Figure 9 , the first reverse module composed of the fifth MOS tube M5 and the sixth MOS tube M6 is configured to reverse the voltage signal ​​The first hysteresis module is composed of the seventh MOS transistor M7 and the eighth MOS transistor M8, and the hysteresis window is obtained through the seventh MOS transistor M7 and the eighth MOS transistor. In the first off stage , the voltage signal starts to drop, and when the drop amplitude exceeds the turn-on threshold of the fifth MOS transistor M5, the voltage starts to rise. When the voltage rises to a set voltage threshold k*Vdd (0.3<k<0.9), the first inverter INV1 and the second inverter INV2 start to flip, the signal is shaped through the inverters and input into the first D flip-flop D1, and the Q output end of the first D flip-flop D1 outputs the first off stage end, the second off stage opening first detection signal . By reasonably setting the width-length ratio of the fifth MOS transistor M5 and the sixth MOS transistor M6, the threshold voltage of the first off stage switching is obtained.

[0079] In the embodiment, the second off stage detection circuit 22 is used to judge whether the first switch Q1 is in the second off stage and whether the second off stage ends according to the size of the voltage signal output by the driving circuit 10 and output the second detection signal when the second off stage ends.

[0080] Figure 10 As shown in the figure, the second off stage detection circuit 22 includes the ninth MOS transistor M9, the tenth MOS transistor M10, the eleventh MOS transistor M11, the twelfth MOS transistor M12, the third inverter INV3, the fourth inverter INV4 and the second D flip-flop D2.

[0081] Specifically, the source of the ninth MOS transistor M9 is connected with the D input end of the second D flip-flop D2 and connected with the power voltage Vdd, the gates of the ninth MOS transistor M9, the tenth MOS transistor M10 and the twelfth MOS transistor M12 are connected to form the second detection end receiving the voltage signal . The drains of the ninth MOS transistor M9 and the tenth MOS transistor M10 are connected to form the voltage The output end of the ninth MOS transistor M9 is connected with the input end of the third inverter INV3, the output end of the third inverter INV3 is connected with the input end of the fourth inverter INV4, the output end of the fourth inverter INV4 is connected with the CLK input end of the second D flip-flop D2, and the Q output end of the second D flip-flop D2 is used for outputting the second detection signal .

[0082] In combination Figure 10 with Figure 11 the ninth MOS transistor M9 and the tenth MOS transistor M10 constitute a second reverse module for modulating the voltage signal , the width-length ratio of the ninth MOS transistor M9 and the width-length ratio of the tenth MOS transistor M10 are set to be different, so that the slope of the voltage is changed, and the corresponding flip threshold is also different, to correspond to the second off phase with slow off speed. The eleventh MOS transistor M11 and the twelfth MOS transistor M12 constitute a second hysteresis module to obtain a hysteresis window. When the second off phase starts, the voltage signal starts to drop, and when the drop amplitude exceeds the on threshold of the ninth MOS transistor M9, the voltage starts to rise. When the voltage signal drops to the of the ninth MOS transistor M9, the third inverter INV3 and the fourth inverter INV4 start to flip, the signal is shaped by the inverter and input into the second D flip-flop D2, and the Q output end of the second D flip-flop D2 outputs the second detection signal indicating that the second off phase ends and the third off phase starts. .

[0083] In this embodiment, the dead time control circuit 30 is used to provide a dead time for the first switch Q1 before the second switch Q2 is turned on, and output a dead time detection signal after the dead time ends, that is, to provide a dead time for the first switch Q1 when the first switch Q1 is in the third off phase . The logic control circuit 40 receives the dead time detection signal and controls the drive circuit 10 to completely turn off the first switch Q1 and turn on the second switch Q2 after the dead time ends, so as to prevent the second switch Q2 from being turned on too early by setting the dead time.

[0084] AsFigure 12 As shown, the dead time control circuit 30 comprises a thirteenth MOS transistor M13, a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, a sixteenth MOS transistor M16, a seventeenth MOS transistor M17, an eighteenth MOS transistor M18, a nineteenth MOS transistor M19, a twentieth MOS transistor M20, a twenty-first MOS transistor M21, a first resistor R1, a second resistor R2, a first capacitor C1 and a logic circuit U.

[0085] Specifically, the gates of the thirteenth MOS transistor M13 and the fourteenth MOS transistor M14 are connected to form a third detection end for receiving a second detection signal . The third detection end can also be connected to the second turn-off stage detection circuit 22 through a plurality of logic operation circuits to receive the second detection signal , and the logic operation circuits ensure the stability of the circuit operation. The source of the thirteenth MOS transistor M13 is connected to the power supply voltage Vdd, the drain of the thirteenth MOS transistor M13 is connected to the first end of the first resistor R1, the second end of the first resistor R1 is connected to the drain of the fourteenth MOS transistor M14, and the source of the fourteenth MOS transistor M14 is connected to the ground. The source of the fifteenth MOS transistor M15 is connected to the power supply voltage Vdd, the drain of the fifteenth MOS transistor M15 is connected to the second end of the second resistor R2 and the first end of the first capacitor C1 to form a first connection point , the second end of the first capacitor C1 is connected to the ground, and the first end of the second resistor R2 is connected to the first end of the first resistor R1 and the drain of the thirteenth MOS transistor M13.

[0086] The source of the sixteenth MOS transistor M16 is connected to the power supply voltage Vdd, the gates of the sixteenth MOS transistor M16, the seventeenth MOS transistor M17 and the nineteenth MOS transistor M19 are connected to the first end of the first capacitor C1, and the drains of the sixteenth MOS transistor M16 and the seventeenth MOS transistor M17 are connected to form a second connection point . The source of the seventeenth MOS transistor M17 is connected to the ground. The drain of the eighteenth MOS transistor M18 is connected to the drains of the sixteenth MOS transistor M16 and the seventeenth MOS transistor M17, the source of the eighteenth MOS transistor M18 is connected to the drain of the nineteenth MOS transistor M19, and the source of the nineteenth MOS transistor M19 is connected to the ground.

[0087] The gates of the twentieth MOS transistor M20 and the twenty-first MOS transistor M21 are connected to the drain of the eighteenth MOS transistor M18, the source of the twentieth MOS transistor M20 is connected to the power supply voltage Vdd, and the drains of the twentieth MOS transistor M20 and the twenty-first MOS transistor M21 are connected to the gate of the eighteenth MOS transistor M18 and the first output end of the logic circuit U to form a third connection point The source of the twenty-first MOS transistor M21 is connected to the ground, and the output terminal of the logic circuit U is used to output the dead zone detection signal .

[0088] In this embodiment, the sixteenth MOS transistor M16 and the seventeenth MOS transistor M17 form the third reverse module. The eighteenth MOS transistor M18, the nineteenth MOS transistor M19, the twentieth MOS transistor M20 and the twenty-first MOS transistor M21 form the hysteresis control module. The gate of the fifteenth MOS transistor M15 and the second input terminal of the logic circuit U receive the enable signal .

[0089] Before the second off stage detection circuit 22 outputs the second detection signal , the fifteenth MOS transistor M15 is kept on to charge the first capacitor C1 by the power supply voltage Vdd. After receiving the second detection signal , the third off stage begins, the enable signal enables to turn off the fifteenth MOS transistor M15, at this time, the first capacitor C1 discharges through the first resistor R1, the second resistor R2 and the fourteenth MOS transistor M14. When the voltage at the first connection point drops to the flip threshold of the third reverse module, the second connection point outputs a signal, When the signal rises to the flip threshold of the hysteresis control module, the third connection point outputs a signal and outputs the dead zone detection signal through the logic circuit U. In this embodiment, a fixed dead zone time is obtained by discharging the first resistor R1, the second resistor R2 and the first capacitor C1.

[0090] As shown in Figure 4 , the logic control circuit 40 is used to control the driving circuit 10 to output voltage signals of different sizes , and the logic control circuit 40 outputs corresponding control signals after receiving the detection signal. The driving circuit 10 changes the off speed of the first switch tube Q1 in the next off stage according to the control signal.

[0091] As shown in Figure 6 , the logic control circuit 40 outputs a first control signal to control the opening of the first MOS transistor M1, at this time, the driving circuit 10 outputs a high level voltage signal to control the opening of the first switch tube Q1.

[0092] In combination with Figure 6 and Figure 4As shown, when the first switch Q1 is in the transition from the on stage to the off stage, the first MOS M1 is turned off, and the logic control circuit 40 outputs a second control signal to turn on the second MOS M2. At this time, the driving circuit 10 outputs a corresponding voltage signal so that the first switch Q1 enters the first off stage . At the end of the first off stage , the first off stage detection circuit 21 outputs a first detection signal according to the change of the voltage signal outputted by the driving circuit 10, to represent the end of the first off stage .

[0093] As shown in Figure 6 and Figure 4 , the logic control circuit 40 receives the first detection signal and outputs a third control signal to turn on the third MOS M3, which can be turned on at the first off stage . At this time, the driving circuit 10 outputs a corresponding voltage signal so that the first switch Q1 enters the second off stage . At the end of the second off stage , the second off stage detection circuit 22 outputs a second detection signal according to the change of the voltage signal outputted by the driving circuit 10, to represent the end of the second off stage .

[0094] As shown in Figure 6 and Figure 4 , the logic control circuit 40 receives the second detection signal and outputs a fourth control signal to turn on the fourth MOS M4. At this time, the driving circuit 10 outputs a corresponding voltage signal so that the first switch Q1 enters the third off stage . When the second detection signal is generated, the dead time control circuit 30 starts to work, and according to the internal circuit structure, the dead time control circuit 30 provides a long dead time with a delay from the signal input to the output. After a period of dead time, the dead time control circuit 30 outputs a dead time detection signal to represent the end of the third off stage . The logic control circuit 40 receives the dead time detection signal and then turns on the second switch Q2.

[0095] In this embodiment, the second MOSFET M2, the third MOSFET M3, the fourth MOSFET M4, the sixth MOSFET M6, the eighth MOSFET M8, the tenth MOSFET M10, the twelfth MOSFET M12, the fourteenth MOSFET M14, the seventeenth MOSFET M17, the eighteenth MOSFET M18, the nineteenth MOSFET M19, and the twenty-first MOSFET M21 are N-channel MOSFETs; the first MOSFET M1, the fifth MOSFET M5, the seventh MOSFET M7, the ninth MOSFET M9, the eleventh MOSFET M11, the thirteenth MOSFET M13, the fifteenth MOSFET M15, the sixteenth MOSFET M16, and the twentieth MOSFET M20 are P-channel MOSFETs; in other embodiments, the N-channel MOSFETs and the P-channel MOSFETs can be interchanged.

[0096] In conjunction with the push-pull converter described above, this invention also discloses a driving method for the push-pull converter. This method includes driving a first switch Q1 and a second switch Q2. The first switch Q1 and the second switch Q2 have at least two turn-off phases during the turn-off process. In this embodiment, the turn-off phase includes a first turn-off phase. Second shut-off phase and the third shut-off phase Since the first switch Q1 and the second switch Q2 are driven symmetrically, that is, the methods for driving the first switch Q1 and the second switch Q2 are the same, the following detailed description will take the first switch Q1 as an example.

[0097] Combination Figure 13 and Figures 4-12 As shown, the driving method includes:

[0098] First, control the first switch Q1 during the first turn-off phase. The turn-off speed is generally increased by accelerating the first switch Q1 during the first turn-off phase. The turn-off speed. Specifically, if the first switch Q1 is an N-channel MOSFET, then the voltage signal driving the first switch Q1 is increased. The rising speed is used to accelerate the first switch Q1 during the first turn-off phase. The turn-off speed; if the first switch Q1 is a P-channel MOSFET, then increase the voltage signal driving the first switch Q1. The decreasing speed is used to accelerate the first switch Q1 during the first turn-off phase. The shutdown speed.

[0099] Then, the turn-off stage of the first switch Q1 is detected. When the first switch Q1 is at the critical point between two adjacent turn-off stages, the corresponding detection signal is acquired; the critical point between two adjacent turn-off stages is the first turn-off stage. End, Second Shutdown Phase Start of the corresponding critical point and the second turn-off phase End, third turn-off phase Start of the corresponding critical point, acquisition in the first turn-off phase and the second turn-off phase End of the corresponding detection signal.

[0100] In particular, the voltage signal for driving the first switch Ql is detected;

[0101] The first turn-off phase and the second turn-off phase of the first switch Ql are determined from the change of the voltage signal ;

[0102] If the first turn-off phase is ended, a first detection signal is acquired which characterizes the end of the first turn-off phase ; the first detection signal is acquired by the first turn-off phase detection circuit 21.

[0103] If the second turn-off phase is ended, a second detection signal is acquired which characterizes the end of the second turn-off phase . The second detection signal is acquired by the second turn-off phase detection circuit 22.

[0104] In addition, if a detection signal is acquired, the turn-off speed of the first switch Ql in the next turn-off phase is changed.

[0105] In particular, if the first detection signal is acquired, the turn-off speed of the first switch Ql in the second turn-off phase is slowed down. If the first switch Ql is an N-channel MOSFET, the turn-off speed of the first switch Ql in the second turn-off phase is slowed down by lowering the falling speed of the voltage signal for driving the first switch Ql; if the first switch Ql is a P-channel MOSFET, the turn-off speed of the first switch Ql in the second turn-off phase is slowed down by lowering the rising speed of the voltage signal for driving the first switch Ql.

[0106] If the second detection signal is acquired, the turn-off speed of the first switch Ql in the next turn-off phase, i.e. the third turn-off phase If the first switching transistor Q1 is an N-channel MOSFET, then the voltage signal driving the first switching transistor Q1 is increased. The decreasing speed is used to accelerate the first switch Q1 in the third turn-off phase. The turn-off speed; if the first switching transistor Q1 is a P-channel MOSFET, then the voltage signal driving the first switching transistor Q1 is used to determine the turn-off speed. The rising speed is used to accelerate the first switch Q1 in the third turn-off stage. The shutdown speed.

[0107] Meanwhile, before the second switch Q2 turns on, i.e., during the second turn-off phase... End, third shutdown phase Initially, a dead time is provided for the current first switching transistor Q1, and a dead time detection signal is acquired after the dead time expires. This dead time is obtained through a delay by the dead time control circuit 30.

[0108] After acquiring the dead zone detection signal, the second switch Q2 is turned on.

[0109] The voltage signal mentioned above Provided by drive circuit 10. The first control signal is output through logic control circuit 40. The control drive circuit 10 is used to turn on the first switching transistor Q1.

[0110] The second control signal is output through the logic control circuit 40. The control drive circuit 10 accelerates the first switching transistor Q1 during the first turn-off phase. The shutdown speed.

[0111] The first detection signal is received through the logic control circuit 40. And output the third control signal via the third control signal Control drive circuit 10 changes voltage signal The size is reduced to slow down the first switch Q1 during the second turn-off phase. The shutdown speed.

[0112] The second detection signal is received through the logic control circuit 40. And output the fourth control signal via the fourth control signal Control drive circuit 10 changes voltage signal The size is adjusted to accelerate the first switch Q1 in the third turn-off phase. The shutdown speed.

[0113] The dead-zone detection signal is received through the logic control circuit 40. The control drive circuit 10 completely turns off the first switch tube Q1 and turns on the second switch tube Q2 through the drive circuit 10 corresponding to the second switch tube Q2.

[0114] The foregoing description of specific exemplary embodiments of the application has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the application to the precise forms disclosed, and various modifications and variations are possible in light of the above teachings. It is intended that the application encompass all such modifications and variations as fall within the scope of the claims and their equivalents. It is intended that the scope of the application extend to all alternative combinations of the constituting elements set forth in the description herein sustained by the claims.

Claims

1. A push-pull converter, comprising a transformer and a first switch and a second switch connected to the primary side of the transformer, wherein the first switch and the second switch have at least two turn-off stages during the turn-off process, characterized in that, The push-pull converter also includes: The driving circuit is connected to the gate of the first switching transistor or the gate of the second switching transistor, and is used to output a corresponding voltage signal to control the turn-off speed of the first switching transistor or the second switching transistor in the turn-off phase. A detection circuit, connected to the gate of a first switching transistor or a second switching transistor, is used to detect the voltage signal at the gate of the first switching transistor or the gate of the second switching transistor to output a corresponding detection signal when the first switching transistor or the second switching transistor is at a critical point between two adjacent turn-off stages; and A logic control circuit, connected to a drive circuit and a detection circuit, is used to control the drive circuit. After receiving a detection signal, the logic control circuit outputs a control signal, and the drive circuit changes the turn-off speed of the first or second switch in the next turn-off stage according to the control signal. The shutdown phase includes a first shutdown phase and a second shutdown phase; the detection circuit includes: A first turn-off stage detection circuit, connected to the gate of a first switch or a second switch, is used to detect the voltage signal at the gate of the first switch or the gate of the second switch to output a first detection signal at the end of the first turn-off stage of the first switch or the second switch; and The second turn-off stage detection circuit is connected to the gate of the first switch or the gate of the second switch, and is used to detect the voltage signal of the gate of the first switch or the gate of the second switch so as to output a second detection signal when the second turn-off stage of the first switch or the second switch ends. The driving circuit includes multiple connected MOSFETs, at least some of which have different on-resistances. The logic control circuit outputs corresponding control signals based on the first detection signal and the second detection signal, and controls the turn-on of different MOSFETs through the corresponding control signals to output voltage signals of different magnitudes to control the turn-off speed of the first switch or the second switch during the second turn-off stage and after the second turn-off stage.

2. The push-pull converter as described in claim 1, characterized in that, The push-pull converter also includes: A dead-time control circuit is used to provide a dead time for the current first or second switching transistor before another switching transistor is turned on, and to output a dead-time detection signal after the dead time is over. The logic control circuit turns on another switching transistor after receiving the dead-time detection signal.

3. The push-pull converter as described in claim 1, characterized in that, The driving circuit includes a first MOSFET, a second MOSFET, a third MOSFET, and a fourth MOSFET. The source of the first MOSFET is connected to the power supply voltage. The drains of the first, second, third, and fourth MOSFETs are all connected and output voltage signals. The sources of the second, third, and fourth MOSFETs are connected to ground. The gates of the first, second, third, and fourth MOSFETs are respectively used to receive corresponding control signals.

4. The push-pull converter as described in claim 3, characterized in that, The on-resistance of the second MOSFET is 0.8 to 1.2 times that of the first MOSFET, or the on-resistance of the fourth MOSFET is 0.8 to 1.2 times that of the first MOSFET, or the on-resistances of both the second and fourth MOSFETs are 0.8 to 1.2 times that of the first MOSFET, the on-resistance of the third MOSFET is 4.5 to 5.5 times that of the first MOSFET, the on-resistance of the third MOSFET is 13 to 15 times that of the second MOSFET, and / or the on-resistance of the third MOSFET is 13 to 15 times that of the fourth MOSFET.

5. The push-pull converter as described in claim 1, characterized in that, The first turn-off stage detection circuit includes a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, an eighth MOSFET, a first inverter, a second inverter, and a first D flip-flop; The source of the fifth MOS transistor is connected to the D input of the first D flip-flop and to the power supply voltage. The gates of the fifth, sixth, and seventh MOS transistors are connected to form a first detection terminal for receiving voltage signals. The drains of the fifth and sixth MOS transistors are connected. The source of the sixth MOS transistor is connected to ground. The drain of the seventh MOS transistor is connected to the drain of the fifth MOS transistor and the input of the first inverter. The gate of the seventh MOS transistor is connected to the output of the first inverter. The source of the seventh MOS transistor is connected to the drain of the eighth MOS transistor. The source of the eighth MOS transistor is connected to ground. The input of the second inverter is connected to the output of the first inverter. The output of the second inverter is connected to the CLK input of the first D flip-flop. The Q output of the first D flip-flop is used to output the first detection signal.

6. The push-pull converter as described in claim 1, characterized in that, The second turn-off stage detection circuit includes a ninth MOSFET, a tenth MOSFET, an eleventh MOSFET, a twelfth MOSFET, a third inverter, a fourth inverter, and a second D flip-flop; The source of the ninth MOS transistor is connected to the D input of the second D flip-flop and is also connected to the power supply voltage. The gates of the ninth, tenth, and twelfth MOS transistors are connected to form a second detection terminal for receiving voltage signals. The drains of the ninth and tenth MOS transistors are connected, and the source of the tenth MOS transistor is connected to ground. The drain of the eleventh MOS transistor is connected to the drain of the ninth MOS transistor and the input of the third inverter. The gate of the eleventh MOS transistor is connected to the output of the third inverter. The source of the eleventh MOS transistor is connected to the drain of the twelfth MOS transistor, and the source of the twelfth MOS transistor is connected to ground. The input of the fourth inverter is connected to the output of the third inverter. The output of the fourth inverter is connected to the CLK input of the second D flip-flop. The Q output of the second D flip-flop is used to output the second detection signal.

7. The push-pull converter as described in claim 2, characterized in that, The dead time control circuit includes a thirteenth MOSFET, a fourteenth MOSFET, a fifteenth MOSFET, a sixteenth MOSFET, a seventeenth MOSFET, an eighteenth MOSFET, a nineteenth MOSFET, a twentieth MOSFET, a twenty-first MOSFET, a first resistor, a second resistor, a first capacitor, and logic circuitry. The gates of the thirteenth and fourteenth MOSFETs are connected to form a third detection terminal for receiving the second detection signal. The source of the thirteenth MOSFET is connected to the power supply voltage, and the drain of the thirteenth MOSFET is connected to the first terminal of the first resistor. The second terminal of the first resistor is connected to the drain of the fourteenth MOSFET, and the source of the fourteenth MOSFET is connected to ground. The source of the fifteenth MOSFET is connected to the power supply voltage, and the drain of the fifteenth MOSFET is connected to the second terminal of the second resistor and the first terminal of the first capacitor. The second terminal of the first capacitor is connected to ground. The first terminal of the second resistor is connected to the first terminal of the first resistor and the drain of the thirteenth MOSFET. The source of the sixteenth MOSFET is connected to the power supply voltage. The gates of the sixteenth, seventeenth, and nineteenth MOSFETs are connected... It is connected to the first terminal of the first capacitor. The drains of the sixteenth and seventeenth MOS transistors are connected. The source of the seventeenth MOS transistor is connected to ground. The drain of the eighteenth MOS transistor is connected to the drains of the sixteenth and seventeenth MOS transistors. The source of the eighteenth MOS transistor is connected to the drain of the nineteenth MOS transistor. The source of the nineteenth MOS transistor is connected to ground. The gates of the twentieth and twenty-first MOS transistors are connected to the drain of the eighteenth MOS transistor. The source of the twentieth MOS transistor is connected to the power supply voltage. The drains of the twentieth and twenty-first MOS transistors are connected to the gate of the eighteenth MOS transistor and the first output terminal of the logic circuit. The source of the twenty-first MOS transistor is connected to ground. The output terminal of the logic circuit is used to output a dead-time detection signal.

8. The push-pull converter as described in claim 1, characterized in that, The driving circuit is also used to accelerate the turn-on speed of the first or second switching transistor during the turn-on process.

9. A driving method for a push-pull converter, characterized in that, Based on the push-pull converter as described in any one of claims 1 to 8, the driving method includes: Control the turn-off speed of the first or second switching transistor during the first turn-off phase; The turn-off phase of the first or second switch is detected, and the corresponding detection signal is obtained when the first or second switch is at the critical point between two adjacent turn-off phases. If a detection signal is obtained, the turn-off speed of the first or second switch in the next turn-off stage is changed.

10. The driving method for the push-pull converter as described in claim 9, characterized in that, The driving method further includes: Before another switch is turned on, a dead time is provided for the current first or second switch, and a dead time detection signal is acquired after the dead time ends. After acquiring the dead zone detection signal, another switching transistor is turned on.

11. The driving method for the push-pull converter as described in claim 9, characterized in that, The turn-off phase includes a first turn-off phase and a second turn-off phase; the detection of the turn-off phase of the first or second switch, and the acquisition of a corresponding detection signal when the first or second switch is at a critical point between two adjacent turn-off phases, includes: The voltage signal used to drive the first or second switching transistor is detected; Determine whether the first turn-off phase or the second turn-off phase of the first or second switching transistor has ended based on the change in the voltage signal. If the first shutdown phase ends, a first detection signal representing the end of the first shutdown phase is acquired; If the second shutdown phase ends, a second detection signal representing the end of the second shutdown phase is acquired.

12. The driving method for the push-pull converter as described in claim 11, characterized in that, If a detection signal is obtained, controlling the turn-off speed of the first or second switch in the next turn-off stage includes: If the first detection signal is obtained, the turn-off speed of the first or second switch is slowed down during the second turn-off phase. If a second detection signal is obtained, the turn-off speed of the first or second switch in the next turn-off stage will be accelerated.

13. The driving method for the push-pull converter as described in claim 9, characterized in that, The control of the turn-off speed of the first switch or the second switch in the first turn-off phase includes: accelerating the turn-off speed of the first switch or the second switch in the first turn-off phase.

14. The driving method for the push-pull converter as described in claim 9, characterized in that, The driving method further includes: accelerating the turn-on speed of the first or second switching transistor during the turn-on process.

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