An ultra-low power consumption and high-speed dual positive feedback comparator circuit

Abstract

The present invention belongs to the field of analog-to-digital conversion integrated circuits, and in particular to an ultra-low power consumption high-speed dual positive feedback comparator circuit, including a dual positive feedback comparator circuit, which is provided with a first common source positive feedback circuit and a second latch positive feedback circuit; and a self-resetting clock circuit. The first positive feedback of the dual voltage positive feedback circuit adopts a symmetrical common source type circuit, and the drain output is respectively connected to the complementary circuit gate of the symmetrical circuit, and the symmetrical circuits form positive feedback with each other; the second positive feedback adopts a latch structure, and through a back-to-back inverter structure, the output of the first positive feedback is used as input, so that signals with slight differences can be accurately and quickly compared. When sampling is performed by using a self-resetting clock control, the comparator clock is at a low level, and after the sampling is completed, the comparator clock automatically changes to a high level, and the comparator starts to work. Since there is no static current directly connected to the ground during operation, extremely low power consumption can be achieved.

Description

Technical Field

[0001] The invention belongs to the field of analog-to-digital conversion integrated circuits, and in particular relates to an ultra-low power consumption and high-speed dual positive feedback comparator circuit. Background Art

[0002] With the development of integrated circuits, the functions of on-chip systems can become more and more complex, and the circuit complexity is greatly improved, which brings a serious problem: chip power consumption. Although the chip power consumption can be reduced by reducing the supply voltage or using multiple voltage domains, the heat generated by chip power consumption cannot be ignored due to the increase in chip integration and power density. In addition, due to the increase in power consumption, for battery-powered on-chip systems, the sustainable use time of the system will be reduced, so reducing chip power consumption is crucial for chip design.

[0003] Generally speaking, an analog-to-digital conversion module is integrated on the chip to convert the analog signal in reality into a digital signal for digital calculation. The comparator is an indispensable module in all analog-to-digital converters, which greatly affects the conversion speed and power loss of the analog-to-digital converter. Although the traditional pre-amplification latch structure comparator has a higher speed, it sacrifices the power consumption of the chip and is not suitable for low-power analog-to-digital converters. Although the dynamic comparator has lower power consumption, its kickback noise and offset voltage are large, which is not suitable for high-precision analog-to-digital converters. It can be seen that designing a high-speed voltage comparator with low power consumption is of great significance to reducing chip power consumption and improving chip operation speed. Summary of the invention

[0004] In order to solve or improve the above problems, the present invention provides an ultra-low power consumption and high-speed dual positive feedback comparator circuit, and the specific technical solution is as follows:

[0005] The present invention provides an ultra-low power consumption and high-speed dual positive feedback comparator circuit, comprising:

[0006] A double positive feedback comparison circuit is provided with a first common source positive feedback circuit and a second latch positive feedback circuit;

[0007] The self-resetting clock circuit is used for providing a clock signal based on the sampling signal, the OUT+ signal and the OUT- signal.

[0008] Preferably, the first positive feedback circuit is composed of a common source circuit with left and right sides being symmetrical to each other.

[0009] Preferably, the common source circuit comprises:

[0010] The symmetrical circuit on the left side includes a PMOS tube M9, an NMOS tube M10, an NMOS tube M11 and an NMOS tube M12;

[0011] The symmetrical circuit on the right side includes a PMOS tube M13, an NMOS tube M14, an NMOS tube M15 and an NMOS tube M16; wherein,

[0012] The source of the PMOS tube M9 is connected to VDD, and the drain of the PMOS tube M9 is connected to the drain of the NMOS tube M10;

[0013] The source of the NMOS tube M10 is connected to the drain of the NMOS tube M11;

[0014] The source of the NMOS tube M11 is connected to the NMOS tube M12, and the source of the NMOS tube M12 is grounded;

[0015] The source of the PMOS tube M13 is connected to VDD, and the drain is connected to the drain of the NMOS tube M14;

[0016] The source of the NMOS tube M14 is connected to the drain of the NMOS tube M15;

[0017] The source of the NMOS tube M15 is connected to the NMOS tube M16, and the source of the NMOS tube M16 is grounded;

[0018] The gate of the PMOS tube M9 is connected to the gate of the NMOS tube M12, and then connected to the drain of the PMOS tube M13 and the drain of the NMOS tube M14;

[0019] The gates of the NMOS transistor M10 and the NMOS transistor M14 are connected to the clock signal CLK;

[0020] The gate of the NMOS tube M11 is connected to the same-phase input signal;

[0021] The gate of the PMOS tube M13 is connected to the gate of the NMOS tube M16, and then connected to the drain of the PMOS tube M9 and the drain of the NMOS tube M10;

[0022] The gate of the NMOS tube M15 is connected to a reverse input signal.

[0023] Preferably, the second positive feedback circuit adopts a Latch positive feedback structure, including two back-to-back inverters, four clock control MOS tubes, two common source MOS tubes, and a tail current NMOS tube M19.

[0024] Preferably, of the two back-to-back inverters, the left inverter is composed of a PMOS tube M2 and an NMOS tube M4, and the right inverter is composed of a PMOS tube M5 and an NMOS tube M7;

[0025] The four clock control MOS tubes are composed of a PMOS tube M1, a PMOS tube M3, a PMOS tube M6 and a PMOS tube M8;

[0026] The common source MOS tube is composed of an NMOS tube M17 and an NMOS tube M18;

[0027] The source of the PMOS tube M1 is connected to the source of the PMOS tube M2 and connected to VDD, the drain of the PMOS tube M1 is connected to the drain of the PMOS tube M2, and then connected to the drain of the NMOS tube M4;

[0028] The source of the PMOS tube M3 is connected to VDD;

[0029] The source of the NMOS tube M4 is connected to the drain of the NMOS tube M17, connected to the source of the PMOS tube M20, and connected to the drain of the PMOS tube M3;

[0030] The source of the PMOS tube M5 is connected to the source of the PMOS tube M6 and is connected to VDD, the drain of the PMOS tube M5 is connected to the drain of the NMOS tube M7, the source of the NMOS tube M7 is connected to the drain of the NMOS tube M18;

[0031] The source of the PMOS tube M8 is connected to VDD;

[0032] The drain of the PMOS tube M8 is connected to the drain of the NMOS tube M18, connected to the drain of the PMOS tube M20, and connected to the source of the NMOS tube M7;

[0033] The gates of the PMOS tube M1, the PMOS tube M3, the PMOS tube M6, the PMOS tube M8, the NMOS tube M19, and the PMOS tube M20 are connected to CLK;

[0034] The gate of the PMOS tube M2 is connected to the gate of the NMOS tube M4 and the drains of the PMOS tube M5 and the PMOS tube M6, and an OUT+ signal of the comparison result of the comparator is output from this connection point;

[0035] The gate of the PMOS tube M5 is connected to the gate of the NMOS tube M7 and the drains of the PMOS tube M1 and the PMOS tube M2, and an OUT- signal of the comparison result of the comparator is output from this connection point;

[0036] The gate of the NMOS tube M17 is connected to the gates of the PMOS tube M9 and the NMOS tube M12, and the source of the NMOS tube M17 is connected to the drain of the NMOS tube M19;

[0037] The gate of the NMOS tube M18 is connected to the gates of the PMOS tube M13 and the NMOS tube M16, the source of the NMOS tube M18 is connected to the drain of the NMOS tube M19, and the source of the NMOS tube M19 is grounded.

[0038] Preferably, the self-resetting clock circuit comprises:

[0039] An OR gate with two inputs and one output, a PMOS tube M21, an NMOS tube M22, a PMOS tube M23, a PMOS tube M24 and a delay circuit;

[0040] The source of the PMOS tube M21 is connected to VDD, and the drain of the PMOS tube M21 is connected to the drain of the NMOS tube M22, the source of the PMOS tube M23, and the source of the PMOS tube M24;

[0041] The source of the NMOS tube M22 is grounded, and the drains of the PMOS tube M23 and the PMOS tube M24 are grounded;

[0042] The drain of the NMOS tube M22, the source of the PMOS tube M23 and the source output of the PMOS tube M24 are connected to the clock input CLK, and are connected to an input of an OR gate through a delay circuit;

[0043] The gate of the NMOS tube M22 is connected to the Enable signal, the gate of the PMOS tube M23 is connected to the OUT+ signal, and the gate of the PMOS tube M24 is connected to the OUT- signal;

[0044] The two-input single-output OR gate has one input connected to the delayed output, the other input connected to the Enable signal, and the output connected to the gate of the PMOS tube M21.

[0045] The beneficial effects of the present invention are as follows: the first positive feedback of the dual voltage positive feedback circuit adopts a symmetrical common source circuit, the drain output is respectively connected to the gate of the complementary circuit of the symmetrical circuit, and the symmetrical circuits form positive feedback with each other. The second positive feedback adopts a latch structure, and the circuit uses the output of the first positive feedback as the input of the latch circuit through a back-to-back inverter structure, so that signals with slight differences can be accurately and quickly compared. At the same time, a self-resetting clock control is adopted. During sampling, the comparator clock is at a low level. After sampling is completed, the comparator clock automatically changes to a high level, and the comparator starts to work. Moreover, since there is no static current directly connected to the ground during operation, extremely low power consumption can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1is a schematic diagram of an ultra-low power consumption and high speed dual positive feedback comparator circuit according to the present invention;

[0047] Figure 2 is a schematic diagram of a self-resetting clock circuit according to the present invention. DETAILED DESCRIPTION

[0048] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0050] It should also be understood that the terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0051] It should be further understood that the term "and / or" used in the present description and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0052] In order to solve or improve the problem of reducing chip power consumption and increasing chip operating speed, the following is proposed Figure 1 The present invention shown provides an ultra-low power consumption and high-speed dual positive feedback comparator circuit, including: a dual positive feedback comparison circuit, which is provided with a first common source level positive feedback circuit and a second latch positive feedback circuit; a self-resetting clock circuit, which is used to provide a clock signal based on a sampling signal, an OUT+ signal and an OUT- signal.

[0053] The first positive feedback circuit is composed of common source circuits with left and right sides being symmetrical to each other.

[0054] The common source type circuit includes: a left symmetrical circuit, including a PMOS tube M9, an NMOS tube M10, an NMOS tube M11 and an NMOS tube M12;

[0055] The right symmetrical circuit includes a PMOS tube M13, an NMOS tube M14, an NMOS tube M15 and an NMOS tube M16; wherein the source of the PMOS tube M9 is connected to VDD, and the drain of the PMOS tube M9 is connected to the drain of the NMOS tube M10;

[0056] The source of the NMOS tube M10 is connected to the drain of the NMOS tube M11;

[0057] The source of the NMOS tube M11 is connected to the NMOS tube M12, and the source of the NMOS tube M12 is grounded; the source of the PMOS tube M13 is connected to VDD, and the drain is connected to the drain of the NMOS tube M14; the source of the NMOS tube M14 is connected to the drain of the NMOS tube M15; the source of the NMOS tube M15 is connected to the NMOS tube M16, and the source of the NMOS tube M16 is grounded; the gate of the PMOS tube M9 is connected to the gate of the NMOS tube M14. 2, and then connected to the drain of the PMOS tube M13 and the drain of the NMOS tube M14; the gates of the NMOS tubes M10 and M14 are connected to the clock signal CLK; the gate of the NMOS tube M11 is connected to the in-phase input signal; the gate of the PMOS tube M13 is connected to the gate of the NMOS tube M16, and then connected to the drain of the PMOS tube M9 and the drain of the NMOS tube M10; the gate of the NMOS tube M15 is connected to the reverse input signal.

[0058] The second positive feedback circuit adopts a latch positive feedback structure, including two back-to-back inverters, four clock control MOS tubes, two common source MOS tubes, and a tail current NMOS tube M19.

[0059] In the two back-to-back inverters, the inverter on the left is composed of a PMOS tube M2 and an NMOS tube M4, and the inverter on the right is composed of a PMOS tube M5 and an NMOS tube M7; the four clock control MOS tubes are composed of a PMOS tube M1, a PMOS tube M3, a PMOS tube M6 and a PMOS tube M8; the common source MOS tube is composed of an NMOS tube M17 and an NMOS tube M18; The source of the PMOS tube M1 is connected to the source of the PMOS tube M2 and is connected to VDD, the drain of the PMOS tube M1 is connected to the drain of the PMOS tube M2, and is further connected to the drain of the NMOS tube M4; the source of the PMOS tube M3 is connected to VDD; the source of the NMOS tube M4 is connected to the drain of the NMOS tube M17, is connected to the source of the PMOS tube M20, and is further connected to the drain of the PMOS tube M3; the source of the PMOS tube M5 is connected to the source of the PMOS tube M6 and is connected to VDD, the drain of the PMOS tube M5 is connected to the source of the NMOS tube M7, and is further connected to the drain of the NMOS tube M18;

[0060] The drain of the NMOS tube M7 is connected to VDD; the drain of the PMOS tube M8 is connected to the drain of the NMOS tube M18, to the drain of the PMOS tube M20, and to the source of the NMOS tube M7; the gates of the PMOS tubes M1, M3, M6, M8, M19, and M20 are connected to CLK; the gate of the PMOS tube M2 is connected to the gate of the NMOS tube M4 and to the drains of the PMOS tubes M5 and M6, and the OUT+ signal of the comparison result of the comparator is output from this connection point; the PMOS tube M1 is connected to the gate of the NMOS tube M4 and to the drains of the PMOS tubes M5 and M6, and the PMOS tube M2 is connected to the gate of the PMOS tube M5 and M6, and the PMOS tube M2 ... The gate of the MOS tube M5 is connected to the gate of the NMOS tube M7 and the drains of the PMOS tube M1 and the PMOS tube M2, and an OUT-signal of the comparison result of the comparator is output from this connection point; the gate of the NMOS tube M17 is connected to the gates of the PMOS tube M9 and the NMOS tube M12, and the source of the NMOS tube M17 is connected to the source of the PMOS tube M19; the gate of the NMOS tube M18 is connected to the gates of the PMOS tube M13 and the NMOS tube M16, the source of the NMOS tube M18 is connected to the source of the NMOS tube M19, and the source of the NMOS tube M19 is grounded.

[0061] The working process of the ultra-low power high-speed dual positive feedback comparator circuit is divided into three stages, as follows:

[0062] 1) Pre-charge stage:

[0063] When the clock signal CLK is low, M1, M3, M5, and M7 are turned on, making OUT+, OUT-, Vrst+, and Vrst- high, and the comparator is in a reset state. Since M10, M14, and M19 are turned off when CLK is low, there is no direct current from the power supply to the ground in the pre-charging stage.

[0064] 2) The first positive feedback stage:

[0065] When the clock signal CLK is at a high level, M10 and M14 are turned on. Since Vrst+ and Vrst- are at high levels, M12 and M16 are turned on. When Vin+ is larger than Vin-, the current flowing through M11 is larger than that flowing through M15, so that the potential at point a drops faster than that at point b. The drop in the potential at point a reduces the on-current of M16, causing M13 to tend to be turned on, so that the potential at point b drops more slowly and has an upward trend. The higher potential at point b will make the on-current of M12 larger, causing the potential at point a to drop further. The drop in the potential at point a will cause M13 to turn on faster, causing the potential at point b to rise. This forms positive feedback, which will eventually cause the potential at point a to approach 0 and the potential at point b to approach VDD. After the comparison is completed, M13 is turned on, M16 is turned off, and M9 is turned off, while M12 is turned on. There is no through current from the power supply to the ground.

[0066] On the contrary, when Vin- is larger than Vin+, the current flowing through M15 is larger than that flowing through M11, so that the potential at point b drops faster than that at point a. The drop in the potential at point b reduces the on-current of M12, causing M9 to turn on, so that the potential at point a drops more slowly and has an upward trend. The higher potential at point a will cause the on-current of M16 to be larger, causing the potential at point b to drop further. The drop in the potential at point b will cause M9 to turn on faster, causing the potential at point a to rise. This forms a positive feedback, which will eventually cause the potential at point b to approach 0 and the potential at point a to approach VDD. After the comparison is completed, M9 is turned on, M12 is turned off, and M13 is turned off, and M16 is turned on. There is no through current from the power supply to the ground.

[0067] 3) The second latch positive feedback stage:

[0068] The clock signal CLK is at a high level, and M19 is turned on. Since the potential at point a is lower than that at point b, the on-current of M17 is larger than that of M18, so that OUT- drops faster than OUT+. The drop of OUT- will reduce the on-current of M7, causing M5 to turn on, so that OUT+ drops more slowly and has an upward trend. The upward trend of OUT+ will further increase the on-current of M4, and the potential of OUT- will be further reduced. The reduction of the potential of OUT- will further cause M5 to turn on and M7 to cut off, thereby further increasing OUT+. In this way, positive feedback is formed, and finally OUT- will tend to 0 and OUT+ will tend to VDD, so that M7 and M2 will be turned off. After the comparison is completed, there is no direct current from the power supply to the ground.

[0069] On the contrary, since the potential at point b is lower than that at point a, the on-current of M18 is larger than that of M17, so that OUT+ decreases faster than OUT-. The decrease of OUT+ will reduce the on-current of M4, causing M2 to turn on, thus making OUT- decrease slower and have an upward trend. The upward trend of OUT- will further increase the on-current of M7, and further reduce the potential of OUT+. The reduction of the potential of OUT+ further causes M2 to turn on and M4 to turn off, thus further increasing OUT-. In this way, positive feedback is formed, and finally OUT+ will tend to 0 and OUT- will tend to VDD, thus turning off M4 and M5. After the comparison is completed, there is no direct current from the power supply to the ground.

[0070] Through the double positive feedback comparison circuit, the slightly different signals can be made very different in the positive feedback process, so that accurate and fast comparison can be achieved. At the same time, since there is no direct current from the power supply to the ground when the circuit is not working or has completed work, there is no static power consumption, which can reduce the power loss of the comparator.

[0071] like Figure 2The self-reset clock circuit shown includes: a two-input single-output OR gate, a PMOS tube M21, an NMOS tube M22, a PMOS tube M23, a PMOS tube M24 and a delay circuit; the source of the PMOS tube M21 is connected to VDD, the drain of the PMOS tube M21 is connected to the drain of the NMOS tube M22, the source of the PMOS tube M23 and the source of the PMOS tube M24; the source of the NMOS tube M22 and the drains of the PMOS tube M23 and the PMOS tube M24 are grounded; The drain of the S tube M22 and the source outputs of the PMOS tube M23 and the PMOS tube M24 are connected to the clock input CLK, and are connected to an input of an OR gate through a delay circuit; the gate of the NMOS tube M22 is connected to an Enable signal, the gate of the PMOS tube M23 is connected to the OUT+ signal, and the gate of the PMOS tube M24 is connected to the OUT- signal; the OR gate with two inputs and one output, one input of which is connected to the delayed output, the other input is connected to the Enable signal, and the output is connected to the gate of the PMOS tube M21.

[0072] Self-reset clock control, its working process is as follows:

[0073] When the sampling signal SAMP is high, M22 is turned on, so that the clock signal CLK is pulled to a low level, and the comparator is in the pre-charge stage. When the sampling signal SAMP is low, after a short delay, the OR gate outputs a low level, so that M21 is turned on, and the clock signal is pulled up to VDD. At this time, the comparator starts to work. After the comparison is completed, one of OUT+ and OUT- must be output at a low level, which will turn on M23 or M24, and the clock signal CLK is pulled to a low level, and the comparator automatically enters the pre-charge stage.

[0074] It should be noted that before M23 or M24 is turned on, M21 must be turned off in advance, otherwise a direct connection from the power supply to the ground will be formed. Therefore, a delay is added to this circuit to make the output of the OR gate high before the clock signal CLK becomes low, thereby turning off M21.

[0075] By using the self-resetting clock control method, there is no need for an external clock to provide a control signal. The comparator can automatically reset after outputting a valid result and enter the next comparison waiting period, thereby increasing the stability of the high-speed comparator.

[0076] Those of ordinary skill in the art will appreciate that the units of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition of each example has been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0077] In the embodiments provided in the present application, it should be understood that the division of units is merely a logical function division, and there may be other division methods in actual implementation, for example, multiple units may be combined into one unit, one unit may be split into multiple units, or some features may be ignored.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be included in the scope of the claims and specification of the present invention.

Claims

1. An ultra-low power consumption high speed dual positive feedback comparator circuit, characterized in that: include: A double positive feedback comparison circuit is provided with a first common source positive feedback circuit and a second latch positive feedback circuit; A self-resetting clock circuit, used for providing a clock signal based on a sampling signal, an OUT+ signal and an OUT- signal; The first common source positive feedback circuit is composed of common source circuits with symmetric left and right sides; the common source circuit includes: The symmetrical circuit on the left side includes a PMOS tube (M9), an NMOS tube (M10), an NMOS tube (M11) and an NMOS tube (M12); The symmetrical circuit on the right side includes a PMOS tube (M13), an NMOS tube (M14), an NMOS tube (M15) and an NMOS tube (M16); wherein, The source of the PMOS tube (M9) is connected to VDD, and the drain of the PMOS tube (M9) is connected to the drain of the NMOS tube (M10); The source of the NMOS tube (M10) is connected to the drain of the NMOS tube (M11); The source of the NMOS tube (M11) is connected to the NMOS tube (M12), and the source of the NMOS tube (M12) is grounded; The source of the PMOS tube (M13) is connected to VDD, and the drain is connected to the drain of the NMOS tube (M14); The source of the NMOS tube (M14) is connected to the drain of the NMOS tube (M15); The source of the NMOS tube (M15) is connected to the NMOS tube (M16), and the source of the NMOS tube (M16) is grounded; The gate of the PMOS tube (M9) is connected to the gate of the NMOS tube (M12), and then connected to the drain of the PMOS tube (M13) and the drain of the NMOS tube (M14); The gates of the NMOS tube (M10) and the NMOS tube (M14) are connected to a clock signal CLK; The gate of the NMOS tube (M11) is connected to the same-phase input signal; The gate of the PMOS tube (M13) is connected to the gate of the NMOS tube (M16), and then connected to the drain of the PMOS tube (M9) and the drain of the NMOS tube (M10); The gate of the NMOS tube (M15) is connected to a reverse input signal.

2. The ultra-low power consumption high speed dual positive feedback comparator circuit according to claim 1, characterized in that: The second latch positive feedback circuit adopts a latch positive feedback structure, including two back-to-back inverters, four clock control MOS tubes, two common source MOS tubes, and a tail current NMOS tube (M19).

3. The ultra-low power consumption high speed dual positive feedback comparator circuit according to claim 2, characterized in that: Of the two back-to-back inverters, the left inverter is composed of a PMOS tube (M2) and an NMOS tube (M4), and the right inverter is composed of a PMOS tube (M5) and an NMOS tube (M7); The four clock control MOS tubes are composed of a PMOS tube (M1), a PMOS tube (M3), a PMOS tube (M6) and a PMOS tube (M8); The common source MOS tube is composed of an NMOS tube (M17) and an NMOS tube (M18); The source of the PMOS tube (M1) is connected to the source of the PMOS tube (M2) and is connected to VDD, the drain of the PMOS tube (M1) is connected to the drain of the PMOS tube (M2), and is then connected to the drain of the NMOS tube (M4); The source of the PMOS tube (M3) is connected to VDD; The source of the NMOS tube (M4) is connected to the drain of the NMOS tube (M17), connected to the source of the PMOS tube (M20), and connected to the drain of the PMOS tube (M3); The source of the PMOS tube (M5) is connected to the source of the PMOS tube (M6) and is connected to VDD, the drain of the PMOS tube (M5) and the drain of the PMOS tube (M6) are connected to the drain of the NMOS tube (M7), and the source of the NMOS tube (M7) is connected to the drain of the NMOS tube (M18); The source of the PMOS tube (M8) is connected to VDD; The drain of the PMOS tube (M8) is connected to the drain of the NMOS tube (M18), connected to the drain of the PMOS tube (M20), and connected to the source of the NMOS tube (M7); The gates of the PMOS tube (M1), the PMOS tube (M3), the PMOS tube (M6), the PMOS tube (M8), the NMOS tube (M19), and the PMOS tube (M20) are connected to CLK; The gate of the PMOS tube (M2) is connected to the gate of the NMOS tube (M4) and the drains of the PMOS tube (M5) and the PMOS tube (M6), and an OUT+ signal of the comparison result of the comparator is output from this connection point; The gate of the PMOS tube (M5) is connected to the gate of the NMOS tube (M7) and the drains of the PMOS tube (M1) and the PMOS tube (M2), and an OUT- signal of the comparison result of the comparator is output from this connection point; The gate electrode of the NMOS tube (M17) is connected to the gate electrodes of the PMOS tube (M9) and the NMOS tube (M12), and the source electrode of the NMOS tube (M17) is connected to the drain electrode of the PMOS tube (M19); The gate of the NMOS tube (M18) is connected to the gates of the PMOS tube (M13) and the NMOS tube (M16), the source of the NMOS tube (M18) is connected to the drain of the NMOS tube (M19), and the source of the NMOS tube (M19) is grounded.

4. The ultra-low power consumption and high-speed dual positive feedback comparator circuit according to claim 3, characterized in that: The self-resetting clock circuit comprises: A two-input single-output OR gate, a PMOS tube (M21), an NMOS tube (M22), a PMOS tube (M23), a PMOS tube (M24) and a delay circuit; The drain of the PMOS tube (M21) is connected to VDD, and the source of the PMOS tube (M21) is connected to the drain of the NMOS tube (M22), the drain of the PMOS tube (M23) and the drain of the PMOS tube (M24); The sources of the NMOS tube (M22), the PMOS tube (M23), and the PMOS tube (M24) are grounded; The drain outputs of the NMOS tube (M22), the PMOS tube (M23), and the PMOS tube (M24) are connected to the clock input CLK, and are connected to an input of an OR gate through a delay circuit; The gate of the NMOS tube (M22) is connected to the Enable signal, the gate of the PMOS tube (M23) is connected to the OUT+ signal, and the gate of the PMOS tube (M24) is connected to the OUT- signal; The two-input single-output OR gate has one input connected to the delayed output, the other input connected to the Enable signal, and the output connected to the gate of the PMOS tube (M21).

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