Network-on-chip simulation model generation method and device, electronic equipment and computer readable storage medium

Abstract

Embodiments of the present disclosure disclose a method and device for generating a simulation model of a network-on-chip, electronic equipment and a computer readable storage medium. The method comprises: generating a directed path table according to characteristics of a network-on-chip to be simulated, wherein each row in the directed path table corresponds to a data transmission path; each row includes a data sending port of the data transmission path, a data receiving port of the data transmission path, a data transmission delay of the data transmission path, and a state of the data transmission path; and generating a simulation model of the network-on-chip according to the directed path table. The model generation method solves the technical problems of complex simulation methods with low efficiency or simple simulation methods with low precision in the prior art by generating a directed path table representing a network-on-chip.

Description

Technical Field

[0001] This disclosure relates to the fields of program compilation and processors, and more particularly to a method, apparatus, electronic device, and computer-readable storage medium for generating simulation models of on-chip networks. Background Technology

[0002] Before designing multi-core chips for neural network computing, simulation models of each component module are typically built for functional verification and performance evaluation. Once the chip is manufactured and put into application, the efficiency of the neural network computing program needs to be evaluated in real time during each compilation process to optimize the generated program. This necessitates the development of an accurate and efficient neural network chip simulator.

[0003] In most multi-core chips, communication between cores and between a core and other modules within the chip is handled through a Network on Chip (NoC). Developing an accurate and efficient NoC simulation model is a challenge.

[0004] When establishing a NoC simulation model, the usual practice is as follows, depending on the specific requirements:

[0005] 1. Focus on Precision: In this approach, the NoC circuit is expressed in software, allowing for a more accurate evaluation of the NoC's performance, including precise data delay. However, this method results in complex software design, long simulation times, and high demands on the machine running the simulation program.

[0006] 2. Focus on high efficiency: In this approach, the NoC is treated as a functional module with certain behavioral characteristics. The simulation results only express the behavior of each port of the NoC, resulting in fast simulation speed and low requirements for the machine running the simulation program. However, this method lacks an expression of the actual characteristics of the NoC. For example, it cannot obtain accurate timing information, cannot simulate the congestion situation of the NoC, and the performance evaluation of the entire chip is too coarse. Summary of the Invention

[0007] This summary section is provided to briefly introduce the concepts, which will be described in detail in the detailed description section below. This summary section is not intended to identify key or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0008] To address the aforementioned technical problems in the prior art, the present disclosure proposes the following technical solutions:

[0009] In a first aspect, embodiments of this disclosure provide a method for generating a simulation model of an on-chip network, including:

[0010] A directed path table is generated based on the characteristics of the on-chip network to be simulated, wherein each row in the directed path table corresponds to a data transmission path; each row includes the data transmission port of the data transmission path, the data transmission port of the data transmission path, the data transmission delay of the data transmission path, and the status of the data transmission path;

[0011] The simulation model of the on-chip network is generated based on the directed path table.

[0012] Furthermore, generating the simulation model of the on-chip network based on the directed path table includes:

[0013] Read the directed path table according to the simulation task command;

[0014] The simulation model of the on-chip network is generated based on the read directed path table.

[0015] Furthermore, the state of the data transmission path includes: busy state or idle state.

[0016] Furthermore, the data sending port and data receiving port located in the same row of the directed path table have a direct physical connection.

[0017] Furthermore, the data transmission delay represents the number of clock cycles required for a single piece of data to be transmitted from the data sending port to the data receiving port.

[0018] Secondly, embodiments of this disclosure provide a simulation method for an on-chip network, comprising:

[0019] Receive bus emulation tasks, wherein the emulation tasks include data transmission tasks between ports of the on-chip network;

[0020] The simulation task is input into the simulation model generated by any of the on-chip network simulation model generation methods in the first aspect, causing the simulation model to perform the following steps:

[0021] Obtain the data sending port, data receiving port, and data to be sent in the data transmission task;

[0022] The directed path table is used to query whether there is a connection between the data sending port and the data receiving port;

[0023] If there is a connection between the data sending port and the data receiving port, the path status between the data sending port and the data receiving port is queried through the directed path table;

[0024] If the path status is idle, the data to be sent is sent from the sending port to the receiving port;

[0025] The path state is set to busy, and the duration of the busy state is determined based on the data transmission delay in the directed path table.

[0026] Furthermore, a data relay port is included between the data sending port and the data receiving port, and the path status being idle includes: the path from the sending port to the relay port and the path from the relay port to the data receiving port are both in an idle state.

[0027] Furthermore, setting the path status to a busy state includes setting both the path from the sending port to the relay port and the path from the relay port to the data receiving port to a busy state.

[0028] Furthermore, the method also includes: when the data to be sent has been sent, checking whether there is any unsent data to be sent; if not, ending the simulation task; if so, continuing the above process of sending the data to be sent.

[0029] Thirdly, embodiments of this disclosure provide an apparatus for generating simulation models of on-chip networks, comprising:

[0030] A directed path table generation module is used to generate a directed path table based on the characteristics of the on-chip network to be simulated, wherein each row in the directed path table corresponds to a data transmission path; each row includes the data transmission port of the data transmission path, the data transmission port of the data transmission path, the data transmission delay of the data transmission path, and the state of the data transmission path; a model generation module is used to generate a simulation model of the on-chip network based on the directed path table.

[0031] Fourthly, this disclosure provides an on-chip network emulation device, comprising:

[0032] A task receiving module is used to receive simulation tasks from the on-chip network, wherein the simulation tasks include data transmission tasks between ports of the on-chip network; a task input module is used to input the simulation tasks into the simulation model generated by the on-chip network simulation model generation method, so that the simulation model performs the following steps: obtaining the data sending port, data receiving port, and data to be sent in the data transmission task; querying the directed path table to see if there is a connection between the data sending port and the data receiving port; if there is a connection between the data sending port and the data receiving port, querying the path status between the data sending port and the data receiving port through the directed path table; if the path status is idle, sending the data to be sent from the sending port to the data receiving port; setting the path status to busy, and determining the duration of the busy state according to the data transmission delay in the directed path table.

[0033] Fifthly, embodiments of this disclosure provide an electronic device, including: a memory for storing computer-readable instructions; and one or more processors for executing the computer-readable instructions such that the processors, when running, implement the method described in or any of the methods described in the second aspect above.

[0034] In a sixth aspect, embodiments of this disclosure provide a computer-readable storage medium that stores computer instructions for causing a computer to perform the methods described in or any of the second aspects.

[0035] In a seventh aspect, embodiments of this disclosure provide a computer program product including computer instructions, which, when executed by a computing device, enable the computing device to perform the methods described in or any of the preceding second aspects.

[0036] This disclosure provides a method, apparatus, electronic device, and computer-readable storage medium for generating simulation models of on-chip networks. The method includes: generating a directed path table based on the characteristics of the on-chip network to be simulated, wherein each row in the directed path table corresponds to a data transmission path; each row includes a data transmission port, a data reception port, a data transmission delay, and a state of the data transmission path; and generating a simulation model of the on-chip network based on the directed path table. This model generation method, by generating a directed path table representing the on-chip network, solves the technical problems of existing simulation methods being either complex and inefficient or simple but inaccurate.

[0037] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0038] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0039] Figure 1 This is a schematic diagram of the on-chip network structure;

[0040] Figure 2 A flowchart illustrating the method for generating a simulation model of an on-chip network provided in this embodiment of the disclosure;

[0041] Figure 3 A schematic diagram of a directed path table provided in an embodiment of this disclosure;

[0042] Figure 4 A flowchart illustrating the simulation method for an on-chip network provided in this embodiment of the disclosure;

[0043] Figure 5a A schematic diagram illustrating an example of an on-chip network provided in an embodiment of this disclosure;

[0044] Figure 5b A schematic diagram of an example of a directed path table for a model of an on-chip network provided in an embodiment of this disclosure;

[0045] Figures 6a-6j This diagram illustrates the changes in the directed path table and data transmission when the simulation model of the on-chip network provided in this embodiment performs a simulation task. Detailed Implementation

[0046] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0047] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0048] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0049] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0050] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0051] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0052] Figure 1 This is a schematic diagram of the on-chip network structure. (Example:) Figure 1 As shown, NoC includes N ports P(P1-P2). N Each port connects to one processing core of the chip, enabling simultaneous input and output. Some ports may be unidirectional, serving only as input or output, while others are bidirectional, allowing simultaneous input and output. Data can be transferred between N processing cores through N ports.

[0053] Figure 2 This is a flowchart illustrating the method for generating a simulation model of an on-chip network provided in an embodiment of this disclosure.

[0054] The on-chip network simulation model generation method is used to generate a NoC model in a chip, wherein the chip includes multiple processing cores. The on-chip network simulation model generation method can be executed by an on-chip network simulation model generation device, which can be implemented as software or hardware, or a combination of software and hardware. The on-chip network simulation model generation device can be integrated into a device in an on-chip network simulation model generation system, such as an on-chip network simulation model generation terminal device.

[0055] like Figure 2 As shown, the method includes the following steps:

[0056] Step S201: Generate a directed path table based on the characteristics of the on-chip network to be simulated, wherein each row in the directed path table corresponds to a data transmission path; each row includes the data transmission port of the data transmission path, the data reception port of the data transmission path, the data transmission delay of the data transmission path, and the status of the data transmission path.

[0057] like Figure 1 As shown, an on-chip network (BTC) is used to transmit data between multiple processing cores through multiple ports. Therefore, by using a directed path table to express the connection relationships between ports on the BTC, the data transmission latency between connected ports, and the current state of the data transmission path, the characteristics of the BTC can be expressed. Specifically, the characteristics of the BTC to be simulated include the ports of the BTC, the connection relationships between the ports, and the data transmission latency when transmitting data between the ports.

[0058] Optionally, the data sending port and the data receiving port located in the same row of the directed path table have a direct physical connection.

[0059] Optionally, the directed path table's attributes can be configured by receiving user input of attribute values ​​through a human-computer interaction interface, such as menus, options, or input fields in the interface. These attributes could include the number of ports on the on-chip network, whether two ports are connected, and if so, the data transmission latency.

[0060] like Figure 3 The diagram shows a directed path table. Figure 3In the schematic diagram shown, the directed path table includes N rows, each row representing a data transmission path between two directional ports in the on-chip network; wherein, each of the N rows in the directed path table includes 4 entries: data sending port SP (Start Port), data receiving port EP (End Port), data transmission delay L (Latency) between the data sending port and the data receiving port, and status information S (Status) of the transmission path.

[0061] The data transmission delay refers to the number of clock cycles required to transmit a single piece of data from SP to EP; the path status information S indicates whether the data transmission path is currently transmitting data. Optionally, the status of the data transmission path includes a busy state or a current state; a first preset value is used to represent the busy state, and a second preset value is used to represent the idle state, and the status information S of the data transmission path is either the first preset value or the second preset value. For example, the first preset value is 1, and the second preset value is 0.

[0062] The number of rows N in the directed path table is equal to the number of paths between ports in the on-chip network to be simulated, wherein the paths are directional and are directed paths, such as port P. X to port P Y Path and port P Y to port P X The paths are two different paths.

[0063] For example, such as Figure 3 As shown, obtain the port information of the on-chip network to be simulated. When port P X To another port P Y If there is a directly connected physical path, then generate a row of 4 entries in the directed path table, specifying the identifier P of the data transmission port. X Assign the value to the table entry SP, and set the identifier P of the data receiving port. Y Assign the value to entry EP; obtain the data transmission delay between the two ports of the on-chip network to be simulated, and fill in the number of clock cycles L required for data transmission in entry L. XY Latency, representing the latency from data transmission port P. X Transmit a single piece of data to the data receiving port P Y The number of clock cycles required; when generating the directed path table, there is no data transmission between all directed paths, therefore all entries S in the directed path table are assigned a second preset value, such as 0. Through the above path status information, the port occupancy status during the simulation can be recorded to simulate port congestion during actual data transmission.

[0064] For example, such as Figure 3As shown, there is a direct physical path between port P1 and port P3. Therefore, the directed path table includes a row where SP = P1 and EP = P3, and the data transmission delay from P1 to P3 is L. 13 One clock cycle; initial state S = S 13 .

[0065] The directed path table is a dynamic table where the path status information S is dynamically updated every clock cycle based on the actual path occupancy. Other information in the table, such as the data transmission port SP, data reception port EP, and data transmission delay L, is static and remains unchanged for the designed or manufactured chip. Before performance simulation and program compilation optimization, the directed path table is generated based on the actual chip conditions, and the relevant information in the table is initialized. During simulation or program compilation optimization, the path status information S needs to be updated in real time. For on-chip network performance prediction simulation and optimization during chip design, the directed path table can be adjusted as needed, which is equivalent to changing the on-chip network design, i.e., changing and optimizing the chip design. The performance of the on-chip network can be predicted in advance before the chip is designed or manufactured.

[0066] return Figure 2 The method for generating the simulation model of the on-chip network further includes:

[0067] Step S202: Generate the simulation model of the on-chip network based on the directed path table.

[0068] The simulation model of the on-chip network may only include the directed path table, and the parsing and control of the simulation task can be controlled by a program outside the model. Alternatively, the simulation model may also include the parameters of the simulation task, and the simulation model is generated based on the parameters of the simulation task and the directed path table. In this case, the simulation model is a simulation mode instance for the simulation task.

[0069] Optionally, step S203 includes:

[0070] Read the directed path table according to the simulation task command;

[0071] The simulation model of the on-chip network is generated based on the read directed path table.

[0072] The simulation task includes simulation task parameters, such as a clock cycle, data transmission ports, and data reception ports within that clock cycle. Based on the simulation task read command, the directed path table is read according to the simulation task parameters, and then a simulation model of the on-chip network is generated based on the read directed path table. At this point, the generated simulation model is a simulation model specific to a particular simulation task.

[0073] The simulation model generation method based on the directed path table described above avoids simulating the complex behavior of on-chip network circuits. It simply uses the directed paths and states of the on-chip network to achieve accurate simulation of the on-chip network, greatly reducing the demand for computing power, speeding up the simulation, and improving work efficiency.

[0074] Furthermore, the above simulation model generation method is universal and can be applied to various on-chip networks. This is because different on-chip networks differ only in the port connection characteristics and implemented circuits, which can be expressed using the data sending port, data receiving port, and data transmission delay in the directed path table. The state during operation can be expressed by the path state information in the directed path table. Thus, various on-chip networks can be expressed by generating a single table.

[0075] The above embodiments disclose a method for generating a simulation model of an on-chip network. This method includes: generating a directed path table based on the characteristics of the on-chip network to be simulated, wherein each row in the directed path table corresponds to a data transmission path; each row includes the data transmission port of the data transmission path, the data reception port of the data transmission path, the data transmission delay of the data transmission path, and the state of the data transmission path; and generating a simulation model of the on-chip network based on the directed path table. This model generation method solves the technical problems of existing simulation methods being complex but inefficient, or simple but inaccurate, by generating a directed path table representing the on-chip network.

[0076] Figure 4 This is a flowchart illustrating the on-chip network simulation method provided in this embodiment. The on-chip network simulation method is used to simulate an on-chip network in a multi-processor core system. This simulation method can be executed by an on-chip network simulation device, which can be implemented as software, hardware, or a combination of both. The on-chip network simulation device can be integrated into a device within the on-chip network simulation system, such as an on-chip network simulation terminal device. Figure 4 As shown, the method includes the following steps:

[0077] Step S401: Receive an on-chip network simulation task, wherein the simulation task includes a data transmission task between ports of the on-chip network.

[0078] The on-chip network simulation task is used to simulate the execution of on-chip network data transmission tasks in order to test the performance of the on-chip network.

[0079] For example, the on-chip network simulation task includes a clock cycle, a data transmission port, a data reception port, and a data size. A simulation task can be defined by these four parameters. Before the simulation begins, the user can configure the parameters of the simulation task to generate the on-chip network simulation task to be executed. Then, the terminal device executing the simulation task receives the on-chip network simulation task.

[0080] return Figure 4 The simulation method for the on-chip network further includes:

[0081] Step S402: Input the simulation task into the simulation model generated by the above-described on-chip network simulation model generation method, so that the simulation model performs the following steps:

[0082] Step S4021: Obtain the data sending port, data receiving port, and data to be sent in the data transmission task;

[0083] Step S4022: Query the directed path table to see if there is a connection between the data sending port and the data receiving port;

[0084] Step S4023: If there is a connection between the data sending port and the data receiving port, query the path status between the data sending port and the data receiving port through the directed path table;

[0085] Step S4024: If the path status is idle, send the data to be sent from the sending port to the data receiving port;

[0086] Step S4025: Set the path status to busy state, and determine the duration of the busy state based on the data transmission delay in the directed path table.

[0087] Inputting a simulation task into a simulation model generated by the above simulation model generation method includes parsing the simulation task into simulation parameters and inputting the simulation parameters into the simulation model; or, inputting the simulation task into the simulation model, and the simulation model parsing the simulation task to obtain simulation parameters through its own simulation task execution control instructions.

[0088] In step S5021, the simulation model obtains the parameters of the simulation task: data sending port, data receiving port, and data to be sent. The data to be sent includes the size of the data to be sent. The size of the data to be sent is based on the data size that the data sending port and the data receiving port can transmit at one time. For example, if port 1 sends two data to port 2 in the simulation task, it means that port 1 needs to send two data to port 2 consecutively.

[0089] After obtaining the data sending port and data receiving port, the system first checks the directed path table of the simulation model to see if there is a connection between the data sending port and the data receiving port. This connection includes indirect connections, meaning the data receiving port can be reached via a relay port from the data sending port. If there is no connection, a prompt message is output indicating that the simulation task cannot be executed. If there is a connection between the data sending port and the data receiving port, the system further checks the path status between them using the directed path table of the simulation model. If the path status is idle, the data to be sent is sent from the sending port to the receiving port. After sending the data, the path status is set to busy, and the duration of the busy state is determined based on the data transmission delay in the directed path table. The duration of the busy state is determined by the single data transmission delay and the size of the data. After the duration is reached, the path status is set to idle so that other data transmission tasks in the simulation task can use the path. If the path status is busy, then wait. At this time, the path status can be determined once every clock cycle until the path status is idle.

[0090] Optionally, when the connection relationship is an indirect connection, a data relay port is included between the data sending port and the data receiving port; the path state being idle includes: the paths between the sending port, the relay port, and the data interface port are all in an idle state. For example, if there is no direct physical path between the data sending port and the data receiving port in the simulation task, then the directed path table is searched for an optional combination path starting from SP, passing through other relay ports, and finally reaching EP. The optimal path is selected as the final combined path. Here, "optimal" can be determined based on different strategies, such as shortest path, shortest delay, or currently usable criteria.

[0091] Optionally, the path status being busy includes: at least one of the paths between the sending port, the relay port, and the data interface port being busy.

[0092] Optionally, setting the path status to a busy state includes setting all paths between the sending port, relay port, and data interface port to a busy state.

[0093] Furthermore, the method also includes: after the data to be sent has been sent, checking whether there is any unsent data to be sent; if not, ending the simulation task; if so, continuing the above process of sending data to be sent. Here, the data to be sent is the data to be sent in the next clock cycle. If there is no unsent data to be sent, it means there is no more data to be sent in the simulation task, and the simulation task ends; if so, continuing steps S4021-S4025 continues until there is no more unsent data to be sent.

[0094] The following example illustrates the model generation method and simulation method of the on-chip network.

[0095] Figure 5a This is a schematic diagram of an example of a network-on-a-chip. Figure 5a The on-chip network is a shared bus with 6 input / output ports, connected sequentially from P1 to P6. The bus width ensures that one data transmission is possible per clock cycle. There is only a physical connection between adjacent ports. There are two physical connections between ports, one from left to right and one from right to left, meaning that two ports can simultaneously receive and transmit data. The bus segments can transmit data in parallel. That is, at any given time, if there is communication between two ports, for example, port P2 sends data to port P3, then the bus segment from P2 to P3 is busy and cannot be requested by other ports for data transmission. However, bus segments other than P2 to P3 can still be requested for use. For example, the bus segment from P3 to P2 can transmit data simultaneously with the bus segment from P2 to P3. However, since there is only a physical connection between adjacent ports, when a port requests a path, it cannot include a bus segment that is currently in use. For example, if the path from P1 to P3 needs to pass through the bus segment from P2 to P3, then at this moment, the path from P1 to P3 will be busy and will need to wait until the data transmission from P2 to P3 is completed before the path from P1 to P3 can be opened.

[0096] Based on the above-described on-chip network model generation method, a directed path table is generated; there are only physical connections between adjacent ports; there are two physical connections between each port, one from left to right and one from right to left. The directed path table is generated based on the characteristics of the above-described on-chip network as follows: Figure 5bAs shown, P1 is physically connected only to P2, P2 is physically connected to P1 and P3, and so on, resulting in a total of 10 direct directed paths. Therefore, the directed path table contains 10 rows. The transmission delay between two ports is 2 clock cycles, so the value of the corresponding entry L is set to 2. The initial state of the on-chip network to be simulated is that all paths are idle, so the value of each entry S is assigned to 0.

[0097] Thus, a model for representing on-chip networks is obtained, which includes a directed path table.

[0098] Then, the simulation task can be performed using the above-mentioned on-chip network model.

[0099] For example, the simulation task to be performed is as follows:

[0100] 1. In the first clock cycle, P2 requests to send two data packets to P3;

[0101] 2. On the second clock cycle, P4 requests to send two data packets to P5;

[0102] 3. In the third clock cycle, P1 requests to send two data packets to P3;

[0103] 4. On the fourth clock cycle, P6 requests to send two data packets to P4.

[0104] The simulation method for the on-chip network is as follows:

[0105] The simulation task described above was analyzed to obtain the data transmission port, data interface port, and amount of data transmitted in each clock cycle.

[0106] 1. In the first clock cycle, P2 requests to send two data packets to P3:

[0107] Search the directed path table to obtain S 23 =0 indicates that the physical path from P2 to P3 is free and can be used, then set S. 23 =1, send the first data to the bus, and start data transmission. The changes in the directed path table at this time are as follows: Figure 6a As shown; the data transmission diagram at this time is as follows. Figure 6b As shown.

[0108] 2. In the second clock cycle, P4 requests to send two data packets to P5:

[0109] Search the directed path table to obtain S 45 =0 indicates that the physical path from P4 to P5 is free and can be used, then set S. 45=1, the first data is sent to the bus, and data transmission begins; at this time, the data transmission from P2 to P3 is not yet complete, the first data is in the process of transmission, the second data is sent to the bus, so S 23 No change. The changes to the directed path table at this point are as follows: Figure 6c As shown; the data transmission diagram at this time is as follows. Figure 6d As shown.

[0110] 3. In the third clock cycle, P1 requests to send two data packets to P3:

[0111] The path from P1 to P3 consists of two paths: the path from P1 to P2 and the path from P2 to P3.

[0112] Search the directed path table to obtain S 12 =0, but S 23 =1 indicates that the path from P2 to P3 is busy and unavailable, so we need to wait; since the data transmission from P2 to P3 and from P4 to P5 has not yet been completed, the directed path table and transmission diagram remain unchanged.

[0113] 4. On the 4th clock cycle, P6 requests to send 2 data packets to P4;

[0114] The path from P6 to P4 consists of two paths: the path from P6 to P5 and the path from P5 to P4.

[0115] Search the directed path table to obtain S 65 =0, and S 54 =0 indicates that the path from P6 to P4 is idle and can be used, so the state of both paths is set to 1, i.e., S. 65 =1, and S 54 =1; Since the data transmission from P2 to P3 has been completed at this time, the data transmission request from P1 to P3 is successful. Therefore, the states of both paths from P1 to P3 are set to 1, i.e., S. 12 =1, and S 23 =1; At this point, the data transmission from P4 to P5 is not yet complete, so it remains unchanged. The changes to the directed path table at this time are as follows: Figure 6e As shown; the data transmission diagram at this time is as follows. Figure 6f As shown.

[0116] 5. Fifth clock cycle, data transmission in progress;

[0117] No new data transmission requests were made, but in the original transmission, the data transmission from P4 to P5 ended, and its path status information was cleared to 0, i.e., S was set. 45 =0; other data transfers are in progress and remain unchanged. The changes to the directed path table at this time are as follows: Figure 6g As shown; the data transmission diagram at this time is as follows. Figure 6h As shown.

[0118] 6. From the 6th to the 8th clock cycle, data is continuously being transmitted, the directed path table is not updated, and the transmission diagram remains unchanged;

[0119] 7. On the 9th clock cycle, data transmission ends.

[0120] Data transfer from P1 to P3 and from P6 to P4 are now complete. The path status from P1 to P3 is now cleared to 0, and S is set. 12 =0, S 23 =0; Clear the path status from P6 to P4 to 0, and set S 65 =0, S 54 =0. At this point, the directed path table and transmission diagram will revert to their initial state. The changes to the directed path table at this time are as follows: Figure 6i As shown; the data transmission diagram at this time is as follows. Figure 6j As shown.

[0121] As can be seen from the above examples, the model generated by the on-chip network model generation method in this embodiment can accurately simulate the data latency performance brought by the on-chip network. Thus, the simulation results can serve as effective parameters of chip performance and as an effective basis for data path selection. It avoids the need to write complex programs to simulate circuit behavior, and the simulation program greatly reduces the simulation time. Accurate simulation of the on-chip network can be achieved simply by looking up and updating the table and performing simple calculations. Based on a table, data routing can be planned in real time to optimize the program and improve efficiency. The simulation model has high versatility and can be used for any type of on-chip network. Different on-chip networks only require modification of the corresponding content in the table.

[0122] This disclosure provides an apparatus for generating a simulation model of an on-chip network, comprising: a directed path table generation module, configured to generate a directed path table based on the characteristics of the on-chip network to be simulated, wherein each row in the directed path table corresponds to a data transmission path; each row includes a data transmission port of the data transmission path, a data reception port of the data transmission path, a data transmission delay of the data transmission path, and a state of the data transmission path; and a model generation module, configured to generate a simulation model of the on-chip network based on the directed path table.

[0123] This disclosure provides an on-chip network (PCN) simulation device, comprising: a task receiving module for receiving PCN simulation tasks, wherein the simulation tasks include data transmission tasks between PCN ports; and a task input module for inputting the simulation tasks into a simulation model generated by the PCN simulation model generation method, such that the simulation model performs the following steps: obtaining a data sending port, a data receiving port, and data to be sent in the data transmission task; querying a directed path table to determine if there is a connection between the data sending port and the data receiving port; if there is a connection between the data sending port and the data receiving port, querying the directed path table to determine the path status between the data sending port and the data receiving port; if the path status is idle, sending the data to be sent from the sending port to the data receiving port; setting the path status to busy, and determining the duration of the busy state based on the data transmission delay in the directed path table.

[0124] This disclosure also provides an electronic device, including: a memory for storing computer-readable instructions; and one or more processors for executing the computer-readable instructions such that the processors, when running, implement any of the methods described in the embodiments.

[0125] This disclosure also provides a non-transitory computer-readable storage medium that stores computer instructions for causing a computer to perform any of the methods described in the foregoing embodiments.

[0126] This disclosure also provides a computer program product, which includes computer instructions that, when executed by a computing device, can perform any of the methods described in the foregoing embodiments.

[0127] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0128] The units described in the embodiments of this disclosure can be implemented in software or hardware. The names of the units are not, in some cases, intended to limit the specific unit.

[0129] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), System-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), and so on.

[0130] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

Claims

1. A method for generating a simulation model of a network-on-chip, characterized in that, include: A directed path table is generated based on the characteristics of the on-chip network to be simulated, wherein each row in the directed path table corresponds to a data transmission path. Each row includes the data sending port of the data transmission path, the data receiving port of the data transmission path, the data transmission delay of the data transmission path, and the status of the data transmission path. The data sending port, the data receiving port, and the data transmission delay are static data input by the user through a human-computer interaction interface. The status of the data transmission path is updated according to the actual occupancy status of the corresponding path. The actual occupancy status is determined according to the size of the data to be sent in the simulation task and the data transmission delay. The data sending port and the data receiving port located in the same row of the directed path table have a direct physical connection relationship. The simulation model of the on-chip network is generated based on the directed path table.

2. The method of claim 1, wherein, The step of generating the simulation model of the on-chip network based on the directed path table includes: Read the directed path table according to the simulation task command; The simulation model of the on-chip network is generated based on the read directed path table.

3. The method of any one of claims 1 and 2, wherein, The data transmission path is in either a busy state or an idle state.

4. The method of any one of claims 1 and 2, wherein, The data transmission delay represents the number of clock cycles required to transmit a single piece of data from the data sending port to the data receiving port.

5. A method of simulating a network-on-chip, characterized by, include: Receive simulation tasks from the on-chip network, wherein the simulation tasks include data transmission tasks between ports of the on-chip network; The simulation task is input into the simulation model generated by the simulation model generation method for the on-chip network according to any one of claims 1-4, so that the simulation model performs the following steps: Obtain the data sending port, data receiving port, and data to be sent in the data transmission task; The directed path table is used to query whether there is a connection between the data sending port and the data receiving port; If there is a connection between the data sending port and the data receiving port, the path status between the data sending port and the data receiving port is queried through the directed path table; If the path status is idle, the data to be sent is sent from the sending port to the receiving port; The path state is set to busy, and the duration of the busy state is determined based on the data transmission delay in the directed path table.

6. The method as described in claim 5, characterized in that, The data sending port and the data receiving port include a data relay port. The path status being idle includes the path from the sending port to the relay port and the path from the relay port to the data receiving port being idle.

7. The method as described in claim 6, characterized in that, Setting the path status to busy includes setting both the path from the sending port to the relay port and the path from the relay port to the data receiving port to busy.

8. The method as described in claim 5, characterized in that, The method further includes: when the data to be sent has been sent, checking whether there is any unsent data to be sent; if not, ending the simulation task; if so, continuing the above process of sending the data to be sent.

9. An electronic device, comprising: A memory for storing computer-readable instructions; and one or more processors for executing the computer-readable instructions, causing the electronic device to perform the method of any one of claims 1-8.

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