A method, system, device, and storage medium for accessing an internal bus

Abstract

The present invention provides a method, system, device and storage medium for accessing an internal bus. The method includes: serially interacting data with a host computer; combining a plurality of received data into data of a preset length as a universal asynchronous receiver / transmitter (UART) command; analyzing and disassembling the UART command into the most basic address read / write; and converting the address read / write into read / write signals conforming to a bus protocol. The present invention uses UART and logic design to connect the host computer and the bus interface to be tested, and can realize the interleaving of continuous read / write transactions through the combination of commands, as well as the behavior of first judging conditions and then performing read / write transactions.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and more particularly, to a method, system, device, and storage medium for accessing an internal bus. Background Art

[0002] FPGA (Field Programmable Gate Array) prototype verification is a necessary and efficient verification step in the current digital IC (Integration Circuit) design process. Different from software simulation, it is not easy for verification personnel to apply stimuli to the circuit. When verifying a module with a bus interface, generally, the on-chip processor of the FPGA and additional bus IP are called to form a SoC (System on Chip), and then the processor executes software code to read and write the module under test.

[0003] The existing solution, that is, calling the on-chip processor and bus IP to form a SoC with the circuit under test, has some limitations and disadvantages. First, not all FPGA development boards have an on-chip processor. In addition, the on-chip processor and bus IP are relatively complex and are often much larger than the logic under test, occupying FPGA resources. It is also necessary to establish Block Design and SDK projects, and the usage process is complex. Summary of the Invention

[0004] In view of this, an object of the embodiments of the present invention is to provide a method, system, computer device, and computer-readable storage medium for accessing an internal bus. The present invention obtains UART data as commands or data, converts them into transactions conforming to the bus protocol, and outputs them to the bus or a module with a bus interface. Through the combination of various commands, it is possible to perform conditional checks first and then register reads and writes, and it is also possible to achieve the interleaved execution of multiple continuous transmission transactions.

[0005] Based on the above object, an aspect of the embodiments of the present invention provides a method for accessing an internal bus, including the following steps: serially interacting data with a host computer; combining multiple received data into data of a preset length as a universal asynchronous receiver / transmitter command; analyzing and disassembling the universal asynchronous receiver / transmitter command into the most basic address reads and writes; and converting the address reads and writes into read and write signals conforming to the bus protocol.

[0006] In some embodiments, the analyzing and disassembling the universal asynchronous receiver / transmitter command into the most basic address reads and writes includes: loading a single universal asynchronous receiver / transmitter command input from outside the circuit into a command set; determining the currently executed command set in the form of a command set queue; and disassembling the currently executed command set into basic read and write requirements and executing them.

[0007] In some embodiments, loading a single Universal Asynchronous Receiver / Transmitter (UART) command input from outside the circuit into the command set includes: in response to receiving a UART command, determining whether the UART command is a condition check-related command; in response to the UART command not being a condition check-related command, storing the UART command in the command set and passing it to the subsequent link; and in response to the UART command being a condition check-related command, forming a check fragment with other UART commands and storing the check fragment in the command set.

[0008] In some embodiments, disassembling the currently executed command set into basic read / write requirements and executing it includes: in response to the current UART command being a condition check-related command, controlling the pointer to check the condition check-related command; and in response to the check passing, controlling the pointer to sequentially read out and execute the read / write commands within the corresponding check fragment.

[0009] Another aspect of the embodiments of the present invention provides a system for accessing an internal bus, including: a Universal Asynchronous Receiver / Transmitter (UART) module configured to serially interact with a host computer for data; a data integration module configured to combine multiple received data into data of a preset length as a UART command; an execution module configured to analyze and disassemble the UART command into the most basic address read / write; and a protocol module configured to convert the address read / write into read / write signals conforming to the bus protocol.

[0010] In some embodiments, the execution module is configured to: load a single UART command input from outside the circuit into the command set; determine the currently executed command set in the form of a command set queue; and disassemble the currently executed command set into basic read / write requirements and execute it.

[0011] In some embodiments, the execution module is configured to: in response to receiving a UART command, determine whether the UART command is a condition check-related command; in response to the UART command not being a condition check-related command, store the UART command in the command set and pass it to the subsequent link; and in response to the UART command being a condition check-related command, form a check fragment with other UART commands and store the check fragment in the command set.

[0012] In some embodiments, the execution module is configured to: in response to the current UART command being a condition check-related command, control the pointer to check the condition check-related command; and in response to the check passing, control the pointer to sequentially read out and execute the read / write commands within the corresponding check fragment.

[0013] In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, and when the instructions are executed by the processor, the steps of the above method are implemented.

[0014] In yet another aspect of the embodiments of the present invention, there is also provided a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above method.

[0015] The present invention has the following beneficial technical effects: obtaining UART data as commands or data, converting them into transactions conforming to the bus protocol and outputting them to the bus or a module with a bus interface, and through the combination of various commands, it is possible to implement the behavior of first performing conditional checks and then reading and writing registers, and it is also possible to implement the interleaved execution of multiple continuous transmission transactions. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention, and for those of ordinary skill in the art, other embodiments can be obtained based on these drawings without creative efforts.

[0017] Figure 1 Schematic diagram of an embodiment of the method for accessing an internal bus provided by the present invention;

[0018] Figure 2 Architecture diagram of an embodiment of the access to an internal bus provided by the present invention;

[0019] Figure 3 Schematic diagram of the structure of the command set provided by the present invention;

[0020] Figure 4 Schematic diagram of the structure of the command set and pointers provided by the present invention;

[0021] Figure 5 Schematic diagram of an embodiment of the system for accessing an internal bus provided by the present invention;

[0022] Figure 6 Hardware structure schematic diagram of an embodiment of the computer device for accessing an internal bus provided by the present invention;

[0023] Figure 7 Schematic diagram of an embodiment of the computer storage medium for accessing an internal bus provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] To make the objectives, technical solutions, and advantages of the present invention more clearly understood, the following further elaborates on the embodiments of the present invention in detail with reference to specific embodiments and the accompanying drawings.

[0025] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are for distinguishing two entities or parameters with the same name but different identities. It can be seen that "first" and "second" are only for the convenience of expression and should not be construed as limitations on the embodiments of the present invention. This will not be elaborated one by one in the subsequent embodiments.

[0026] In the first aspect of the embodiments of the present invention, an embodiment of a method for accessing an internal bus is proposed. Figure 1 Shown is a schematic diagram of an embodiment of the method for accessing an internal bus provided by the present invention. As Figure 1 shown, the embodiments of the present invention include the following steps:

[0027] S1. Serially interact with the host computer for data;

[0028] S2. Combine the received multiple data into data of a preset length as a universal asynchronous receiver / transmitter (UART) command;

[0029] S3. Analyze and disassemble the UART command into the most basic address read / write; and

[0030] S4. Convert the address read / write into read / write signals conforming to the bus protocol.

[0031] Figure 2 Shown is an architecture diagram of an embodiment of accessing an internal bus provided by the present invention. In combination with Figure 2 this, the embodiments of the present invention are described. The present invention is described by taking the example of UART to APB. The UART module is used to serially interact with the host computer for data. Uart_data_join combines multiple Bytes received by the UART into a 9-Byte data as a command (referred to as UCMD, that is, the universal asynchronous receiver / transmitter command). The Ucmd_process module processes the UCMD and analyzes and disassembles the UCMD into the most basic address read / write. The protocol module then converts the above address read / write into read / write signals conforming to the bus protocol. W_MEM and R_MEM are used as buffers for multi-data read / write. Data_ctrl is the module that controls these two buffers. The processing core of the circuit is the ucmd_process module.

[0032] First, introduce UCMD. Each time the UART can receive 1 Byte of data, and 9 consecutive Bytes are combined into a command data, referred to as UCMD (uart command). There are multiple UCMDs, and their functions and the data placed in the bit field are as follows in the table:

[0033]

[0034] Multiple transmission actions can be achieved by combining the above 7 commands. Among the above table, 1-3 are read / write commands, called RW_UCMD, and 4-7 are commands related to conditional checking, called IFS_UCMD.

[0035] The set of UCMDs obtained by wrapping RW_UCMD with IFS_UCMD is called the check fragment. To illustrate the check fragment, to achieve such an action: read the data of addr0 to check whether its bit 0 is high level and whether its bit 3 is low level. If so, write a data data6 to addr1 and write data data7 to addr2, otherwise keep checking. The command sequence to be used is:

[0036] (IF,addr0,0x1); / / Check whether bit0 of the data of addr0 is high level Hi

[0037] (IFN,addr0,0x8); / / Check whether bit3 of the data of addr0 is low level Lo

[0038] (SW,addr1,data6); / / Write data6 to addr1

[0039] (SW,addr2,data7); / / Write data7 to addr2

[0040] (FIB,0,1); / / The current check fragment needs to pass 1 time to continue the subsequent commands

[0041] Next, introduce Magazine (command set). Magazine is a set of multiple UCMDs, which together achieve a transmission action and are the basic input data in the Perform stage, hereinafter referred to as MGZ. Figure 3 It is a schematic diagram of the Magazine structure.

[0042] The low address of the MGZ places the Read / Write command (RW_UCMD) to be executed, and the high address places the conditions (IFS_UCMD) to be met for executing these RW commands. The highest address of the MGZ places the end command FI_UCMD for the check. The MGZ can be an independent RW_UCMD or a check segment. An independent RW_UCMD, especially an MGZ formed by repeatedly executed RW_UCMDs, is non-blocking. During its cyclic execution, other MGZs can be interspersed. For an MGZ formed by a check segment, the N in the segment end command FIN means Non-blocking, indicating that the involved check segment can be split and executed, and the circuit card does not need to keep performing checks on the MGZ here. Correspondingly, the B in FIB means Blocking, indicating that the currently involved check segment must pass a sufficient number of times before exiting the current MGZ.

[0043] In some embodiments, the disassembling of the universal asynchronous receiver / transmitter command into the most basic address reads and writes includes: loading a single universal asynchronous receiver / transmitter command input from outside the circuit into a command set; determining the currently executed command set in the form of a command set queue; and disassembling the currently executed command set into basic read / write requirements and executing them. The working process of Ucmd_process is mainly divided into a loading stage (Load), a dispatching stage (Dispatch), and an execution stage (Perform).

[0044] In some embodiments, the loading of a single universal asynchronous receiver / transmitter command input from outside the circuit into a command set includes: in response to receiving a universal asynchronous receiver / transmitter command, determining whether the universal asynchronous receiver / transmitter command is a condition check-related command; in response to the universal asynchronous receiver / transmitter command not being a condition check-related command, storing the universal asynchronous receiver / transmitter command in the command set and handing it to the subsequent link; and in response to the universal asynchronous receiver / transmitter command being a condition check-related command, forming a check segment with other universal asynchronous receiver / transmitter commands and storing it in the command set. This stage is to load a single UCMD input from outside the circuit into Catch_MGZ. After receiving the UCMD, first determine whether it is an IFS_UCMD. If not, it means the UCMD is an independent RW_UCMD and forms an MGZ by itself and is handed to the subsequent link; if it is an IFS_UCMD, it needs to form a complete check segment with more UCMDs before being stored in the MGZ and handed to the subsequent link. The MGZ obtained in the Load stage is called Catch_MGZ.

[0045] To achieve conditional checks (register reading and data comparison) interspersed during multi-data reading and writing, ucmd_process uses the MGZ queue method to execute multiple MGZs in a time-sharing and interleaved manner. The scheduling phase determines the currently executing MGZ. The Catch_MGZ obtained in the Load phase is copied to the local idle TH_MGZ, and the Load phase is released and can resume operation to obtain the next MGZ from the outside.

[0046] Take the case where there are two TH_MGZs in the circuit as an example. Figure 4 In it, in addition to the TH_MGZ itself, each TH_MGZ is also accompanied by a "pointer" pointing to a certain UCMD within the TH_MGZ. The UCMD pointed to by the pointer will be extracted as the current UCMD and handed over to the subsequent link for execution. And the operating state of the subsequent link will also return to control the position of the pointer. Dispatch will alternately select their cur_UCMD according to the queuing situation of the TH_MGZ and hand it over to the Perform phase for execution.

[0047] Once the execution phase is completed and returns to the scheduling phase, the scheduling phase will check the completion status of the MGZ, check whether the number of passes of the IFS_UCMD is sufficient, check whether the number of executions of the RW_UCMD is sufficient. The completed MGZ will be cleared to free up space for the new MGZ; the uncompleted MGZ will determine whether it is Blocking. The Blocking MGZ needs to be executed again and cannot be switched to another MGZ.

[0048] In some embodiments, the disassembling the currently executed command set into basic read / write requirements and executing includes: in response to the current universal asynchronous receiver / transmitter command being a condition check-related command, controlling the pointer to check the condition check-related command; in response to passing the check, controlling the pointer to sequentially read out the read / write commands within the corresponding check segment for execution. After the Dispatch phase prepares the specific UCMD to be executed, the Perform phase disassembles the UCMD into basic Read / Write (read / write) requirements and hands them over to the subprocess RW_issue for execution. If the current UCMD is an independent RW_UCMD, it can be directly handed over to RW_issue for execution. If the current UCMD is an IFS_UCMD, it means that a check segment will be executed next. First, control the pointer of the MGZ in the subprocess IF_check to read all the IFS_UCMDs for checking. If the check fails, directly exit the current execution phase; if the check passes, control the pointer to sequentially read out the RW_UCMDs within the corresponding check segment for execution, and the number of required check passes recorded in the MGZ will be decremented by one. The RW_UCMDs in the check segment are Blocking. Once there are multiple reads and writes, the execution phase will execute the required number of times before continuing with subsequent actions.

[0049] The RW_issue stage is a sub - process of the execution stage and is used to execute the basic read - writes obtained by splitting. For a Read, the read address and transfer request can be directly output; for a single - data write, the data to be written is in the command, while for a multi - data write, the data to be written is not in the command but in the external storage area W_MEM. This storage area stores the specified number of data received immediately after the UART receives a Multi (multi) Write command. However, even for multi - read - writes, only single read - writes are executed in the RW_issue sub - process, and then it returns to Perform to determine whether to continue read - writing. After one read - write is completed, the Exec times of the corresponding RW_UCMD stored in TH_MGZ will be decremented by one to record the execution progress.

[0050] It should be particularly noted that each step in each embodiment of the above - mentioned method for accessing the internal bus can be crossed, replaced, added, or deleted from each other. Therefore, these reasonable permutation and combination transformations for the method of accessing the internal bus should also fall within the protection scope of the present invention, and the protection scope of the present invention should not be limited to the embodiments.

[0051] For the above - mentioned purpose, the second aspect of the embodiments of the present invention proposes a system for accessing an internal bus. As Figure 5 shown, the system 200 includes the following modules: a Universal Asynchronous Receiver - Transmitter (UART) module configured to serially interact with a host computer for data; a data integration module configured to combine multiple received data into data of a preset length as a UART command; an execution module configured to analyze and disassemble the UART command into the most basic address read - writes; and a protocol module configured to convert the address read - writes into read - write signals conforming to the bus protocol.

[0052] In some embodiments, the execution module is configured to: load a single UART command input from outside the circuit into a command set; determine the currently executed command set in the form of a command - set queue; and disassemble the currently executed command set into basic read - write requirements and execute them.

[0053] In some embodiments, the execution module is configured to: in response to receiving a UART command, determine whether the UART command is a condition - check - related command; in response to the UART command not being a condition - check - related command, deposit the UART command into the command set for the subsequent link; and in response to the UART command being a condition - check - related command, form a check segment with other UART commands and deposit it into the command set.

[0054] In some embodiments, the execution module is configured to: in response to the current universal asynchronous transceiver command being a condition check related command, control a pointer to check the condition check related command; and in response to passing the check, control the pointer to sequentially read and execute the read and write commands within the corresponding check segment.

[0055] Based on the above object, a third aspect of the embodiments of the present invention proposes a computer device, including: at least one processor; and a memory storing computer instructions that can run on the processor, and the instructions are executed by the processor to implement the following steps: S1, serially interact with a host computer for data; S2, combine multiple received data into data of a preset length as a universal asynchronous transceiver command; S3, analyze and disassemble the universal asynchronous transceiver command into the most basic address reads and writes; and S4, convert the address reads and writes into read and write signals conforming to the bus protocol.

[0056] In some embodiments, the analyzing and disassembling the universal asynchronous transceiver command into the most basic address reads and writes includes: loading a single universal asynchronous transceiver command input from outside the circuit into a command set; determining the currently executed command set in the manner of a command set queue; and disassembling the currently executed command set into basic read and write requirements and executing them.

[0057] In some embodiments, the loading a single universal asynchronous transceiver command input from outside the circuit into a command set includes: in response to receiving a universal asynchronous transceiver command, determining whether the universal asynchronous transceiver command is a condition check related command; in response to the universal asynchronous transceiver command not being a condition check related command, storing the universal asynchronous transceiver command in the command set and handing it over to the subsequent link; and in response to the universal asynchronous transceiver command being a condition check related command, forming a check segment with other universal asynchronous transceiver commands and storing the check segment in the command set.

[0058] In some embodiments, the disassembling the currently executed command set into basic read and write requirements and executing them includes: in response to the current universal asynchronous transceiver command being a condition check related command, controlling a pointer to check the condition check related command; and in response to passing the check, controlling the pointer to sequentially read and execute the read and write commands within the corresponding check segment.

[0059] As Figure 6 shown, it is a schematic hardware structure diagram of an embodiment of the above computer device for accessing an internal bus provided by the present invention.

[0060] Taking the device as Figure 6 shown as an example, in this device, there is a processor 301 and a memory 302.

[0061] The processor 301 and the memory 302 can be connected by a bus or other means. Figure 6 Taking the connection through the bus as an example.

[0062] As a non-volatile computer-readable storage medium, the memory 302 can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the method of accessing the internal bus in the embodiments of the present application. By running the non-volatile software programs, instructions, and modules stored in the memory 302, the processor 301 executes various functional applications and data processing of the server, that is, realizes the method of accessing the internal bus.

[0063] The memory 302 can include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the method of accessing the internal bus, etc. In addition, the memory 302 can include high-speed random access memory, and can also include non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 302 can optionally include a memory remotely set relative to the processor 301, and these remote memories can be connected to the local module through a network. Examples of the above network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0064] One or more computer instructions 303 corresponding to the method of accessing the internal bus are stored in the memory 302. When executed by the processor 301, the method of accessing the internal bus in any of the above method embodiments is executed.

[0065] Any embodiment of the computer device executing the above method of accessing the internal bus can achieve the same or similar effects as any of the foregoing method embodiments corresponding thereto.

[0066] The present invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, executes the method of accessing the internal bus.

[0067] As Figure 7 shown, it is a schematic diagram of an embodiment of the above computer storage medium for accessing the internal bus provided by the present invention. Taking the computer storage medium as shown in Figure 7 as an example, the computer-readable storage medium 401 stores a computer program 402 that, when executed by a processor, executes the above method.

[0068] Finally, it should be noted that those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The program for the method of accessing the internal bus can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. Among them, the storage medium of the program can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc. The embodiments of the above computer program can achieve the same or similar effects as those of any of the foregoing method embodiments corresponding thereto.

[0069] The above are exemplary embodiments disclosed by the present invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments disclosed by the present invention as defined by the claims. The functions, steps, and / or actions of the method claims according to the disclosed embodiments herein need not be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention can be described or claimed in individual form, they can also be understood as plural unless explicitly limited to the singular.

[0070] It should be understood that, as used herein, unless the context clearly supports exceptions, the singular form "a" is also intended to include the plural form. It should also be understood that the "and / or" used herein refers to any and all possible combinations of one or more of the associated listed items.

[0071] The serial numbers of the disclosed embodiments of the present invention above are only for description and do not represent the superiority or inferiority of the embodiments.

[0072] Those of ordinary skill in the art can understand that all or part of the steps of the above embodiments can be completed by hardware or by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk, or an optical disk, etc.

[0073] Those of ordinary skill in the art should understand that: the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the embodiments disclosed by the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features between the above embodiments or different embodiments can also be combined, and there are many other variations in different aspects of the embodiments of the present invention as above, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present invention shall be included within the protection scope of the embodiments of the present invention.

Claims

1. A method for accessing an internal bus, characterized in that, It includes the following steps: Interact with the host computer serially to exchange data; Combine multiple received data into data of a preset length as a Universal Asynchronous Receiver-Transmitter (UART) command; Analyze and disassemble the UART command into the most basic address read and write operations; And Convert the address read and write operations into read and write signals that conform to the bus protocol; The step of analyzing and disassembling the UART command into the most basic address read and write operations includes: Load a single externally input UART command into the command set; Determine the currently executed command set in the form of a command set queue; and Disassemble the currently executed command set into basic read and write requirements and execute them; The step of loading a single externally input UART command into the command set includes: In response to receiving a UART command, determine whether the UART command is a condition check-related command; In response to the UART command not being a condition check-related command, store the UART command in the command set and hand it over to the subsequent link; and In response to the UART command being a condition check-related command, combine the UART command with other UART commands to form a check segment and store it in the command set; The step of disassembling the currently executed command set into basic read and write requirements and executing them includes: In response to the current UART command being a condition check-related command, control the pointer to check the condition check-related command; In response to the check passing, control the pointer to sequentially read out the read and write commands within the corresponding check segment and execute them; Among them, multiple commands are executed in a time-sharing and interleaved manner in the form of a command set queue.

2. A system for accessing an internal bus, characterized in that, It includes: A Universal Asynchronous Receiver-Transmitter (UART) module configured to interact with the host computer serially to exchange data; A data integration module configured to combine multiple received data into data of a preset length as a UART command; An execution module configured to analyze and disassemble the UART command into the most basic address read and write operations; the execution module is configured to: load a single externally input UART command into the command set; determine the currently executed command set in the form of a command set queue; and disassemble the currently executed command set into basic read and write requirements and execute them; among them, multiple commands are executed in a time-sharing and interleaved manner in the form of a command set queue; the execution module is configured to: in response to receiving a UART command, determine whether the UART command is a condition check-related command; in response to the UART command not being a condition check-related command, store the UART command in the command set and hand it over to the subsequent link; and in response to the UART command being a condition check-related command, combine the UART command with other UART commands to form a check segment and store it in the command set; the execution module is configured to: in response to the current UART command being a condition check-related command, control the pointer to check the condition check-related command; in response to the check passing, control the pointer to sequentially read out the read and write commands within the corresponding check segment and execute them and A protocol module, configured to convert the address read / write into read / write signals conforming to a bus protocol.

3. A computer device, characterized in that, It includes: At least one processor; And A memory, where computer instructions that can run on the processor are stored, and when the instructions are executed by the processor, the steps of the method described in claim 1 are implemented.

4. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, the steps of the method described in claim 1 are implemented.

Images