A sensitive amplifier circuit

Abstract

The application provides a sensitive amplifier circuit, which comprises a first PMOS tube, a first current path, a second current path, a third current path, a first inverter, a second inverter, a latch circuit and a substrate voltage adjusting circuit. The first current path is connected between the gate of the first PMOS tube and the ground, a storage unit is arranged in the first current path, the second current path is connected between the gate of the first PMOS tube and a power supply voltage, the source of the first PMOS tube is connected to the power supply voltage, the third current path is connected between the drain of the first PMOS tube and the ground, the substrate voltage adjusting circuit is composed of a resistance and a current source in series, the current source is grounded, one end of the resistance is connected to the power supply voltage, and the other end of the resistance is connected to the substrate of the first PMOS tube and used for adjusting the voltage of the substrate end of the first PMOS tube. The substrate voltage adjusting circuit is added, the threshold voltage of the first PMOS tube is reduced, the output flip speed of the sensitive amplifier is improved, the sensitive amplifier circuit with fast response is realized, and the circuit performance is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic technology, in particular to a sensitive amplifier circuit. BACKGROUND

[0002] Static random access memory (SRAM) is initially used as a cache between CPU and memory. In recent years, it has been widely used in high-performance communication networks, portable devices and SOC systems, showing a trend of developing towards high-speed devices and low-power performance. Therefore, designing high-speed and low-power SRAM has become the mainstream direction of current SRAM technology.

[0003] The sensitive amplifier is an important part of SRAM, which amplifies the small signal difference on the bit line to full swing mode quickly, thereby effectively reducing the readout delay of data, and also reducing the power consumption to some extent because it does not need to fully charge and discharge the bit line capacitor. Therefore, an effective way to get high-speed and low-power SRAM is to design the existing sensitive amplifier and improve its performance.

[0004] Figure 1 A schematic diagram of an existing sensitive amplifier circuit is shown. As shown in Figure 1 The sensitive amplifier determines the data stored in the storage unit by comparing the voltage values generated by the different current values of the DET point under the erase cell (E cell) and the program cell (P cell). After the voltage comparator, the comparison data is latched and output. In the process of reading the selected storage unit, if the storage unit is an erase cell (E cell), the storage unit is turned on, there is current, and the corresponding signal output node DET potential will be quickly pulled down to ground GND, and the DET2 point potential will be pulled up to the power supply voltage potential VDDA, and the Dout output is 0; if the storage unit is a program cell (P cell), the storage unit is not turned on, and the corresponding signal output node DET point potential is VDDA, and the DET2 point is pulled to low level GND by the bias voltage NBIAS, and the Dout output is 1. How to design it to realize a high-performance sensitive amplifier is a problem to be solved at present. SUMMARY

[0005] Therefore, the present application provides a sensitive amplifier circuit to speed up the output flip speed of the sensitive amplifier, realizes a sensitive amplifier circuit with fast response, and improves the performance of the sensitive amplifier.

[0006] The application provides a sensitive amplifier circuit, comprising a first PMOS tube, a first current path, a second current path, a third current path, a first inverter, a second inverter, a latch circuit and a substrate voltage adjustment circuit.

[0007] The first current path is connected between the gate of the first PMOS tube and the ground, and a storage unit is arranged in the first current path, and the first current path is used for providing a storage unit current in the amplification process.

[0008] The second current path is connected between the gate of the first PMOS tube and a power supply voltage, and the second current path is used for providing a storage unit comparison current in the amplification process.

[0009] The third current path is connected between the drain of the first PMOS tube and the ground.

[0010] The source of the first PMOS tube is connected to the power supply voltage, and the drain is connected to the input end of the first inverter; the output end of the first inverter is connected to the input end of the second inverter through the latch circuit; and the output end of the second inverter serves as the output end of the sensitive amplifier circuit and outputs a read data output signal.

[0011] The substrate voltage adjustment circuit is used for adjusting the voltage of the substrate end of the first PMOS tube, and is composed of a resistance and a current source in series; the current source is grounded, one end of the resistance is connected to the power supply voltage, and the other end is connected to the substrate of the first PMOS tube.

[0012] Preferably, the sensitive amplifier circuit further comprises a pre-charge unit, which is connected between the power supply voltage and the output end of the first current path, and is used for charging a bit line node in the first current path in a pre-charge process.

[0013] Preferably, the pre-charge unit is composed of a second PMOS tube, the source of the second PMOS tube is connected to the power supply voltage, the drain of the second PMOS tube is connected to the output end of the first current path, and the gate of the second PMOS tube is connected to a pre-charge signal.

[0014] Preferably, the first current path comprises a bit line adjustment unit, which is composed of a first NMOS tube and a third inverter; the drain of the first NMOS tube is the output end of the first current path, the source of the first NMOS tube is connected to a bit line node of the storage unit, the storage unit is connected between the bit line node and the ground; and the third inverter is connected between the source and the gate of the first NMOS tube, and the bit line node potential after the pre-charge is completed in the pre-charge process is clamped according to the inversion point size of the third inverter.

[0015] Preferably, the second current path is composed of a first switch and a first mirror current source in series, the first switch controls the turn-on and turn-off of the second current path, and the first mirror current source provides the storage unit comparison current when the second current path is turned on.

[0016] Preferably, the first switch is composed of a third PMOS tube, the source of the third PMOS tube is connected to the output end of the first mirror current source, the drain of the third PMOS tube serves as the output end of the second current path and is connected to the gate of the first PMOS tube, and the gate of the third PMOS tube is connected to an amplifier working enable signal.

[0017] Preferably, the first mirror current source is composed of a fourth PMOS tube, the source of the fourth PMOS tube is connected to a power supply voltage, the drain of the fourth PMOS tube serves as the output end of the first mirror current source and is connected to the first switch, and the gate of the fourth PMOS tube is connected to a first bias voltage.

[0018] Preferably, the third current path is composed of a second mirror current source.

[0019] Preferably, the second mirror current source is composed of a second NMOS tube, the source of the second NMOS tube is grounded, the drain of the second NMOS tube serves as the output end of the second mirror current source and is connected to the drain of the first PMOS tube, and the gate of the second NMOS tube is connected to a second bias voltage.

[0020] Preferably, the latch circuit is composed of a first NOR gate and a second NOR gate, the first NOR gate includes two input ends connected to the output end of the first inverter and the output end of the second NOR gate respectively, the second NOR gate includes two input ends connected to the output end of the first NOR gate and the inverted signal of the pre-charge signal respectively, and the output end of the first NOR gate is connected to the input end of the second inverter.

[0021] The sensitive amplifier circuit of the present application introduces a substrate voltage adjustment circuit on the basis of the existing sensitive amplifier circuit, adjusts the voltage at the substrate end of the first PMOS tube, reduces the threshold voltage of the first PMOS tube, accelerates the output flip speed of the sensitive amplifier, realizes a sensitive amplifier circuit with fast response, and improves the performance of the sensitive amplifier. BRIEF DESCRIPTION OF DRAWINGS

[0022] The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application taken in conjunction with the accompanying drawings, in which:

[0023] Figure 1A circuit structure diagram of a prior sensitive amplifier circuit is shown.

[0024] Figure 2 A circuit structure diagram of a sensitive amplifier circuit according to an embodiment of the present application is shown.

[0025] Figure 3 A circuit structure diagram of a sensitive amplifier circuit according to an embodiment of the present application is shown. Figure 1 A comparison diagram of signal output effects of the circuit shown in the figure and the circuit shown in the embodiment of the present application. DETAILED DESCRIPTION

[0026] The present application is described in the following based on embodiments, but the present application is not limited to these embodiments only. In the following detailed description of the present application, some specific details are described in detail. The present application can also be completely understood without the description of these details by those skilled in the art. In order to avoid confusion of the essence of the present application, well-known methods, processes, procedures, elements and circuits are not described in detail.

[0027] In addition, those skilled in the art should understand that the drawings provided herein are for illustrative purposes only, and the drawings are not necessarily drawn to scale.

[0028] Unless the context clearly requires otherwise, throughout the description, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in the sense of "including, but not limited to".

[0029] In the description of the present application, it should be understood that the terms "first", "second", and the like are used only for the purpose of description and should not be construed as indicating or implying relative importance. In addition, in the description of the present application, unless otherwise specified, the meaning of "multiple" is two or more.

[0030] The embodiment of the present application further designs to improve the performance of the sensitive amplifier on the basis of the existing sensitive amplifier, and proposes a new sensitive amplifier circuit.

[0031] Figure 2 A circuit structure diagram of a sensitive amplifier circuit according to an embodiment of the present application is shown. As shown in the figure, Figure 2 It includes a first PMOS tube P1, a pre-charge unit 11, a first current path 12, a second current path 13, a third current path 14, a first inverter INV1, a second inverter INV2, a latch circuit 15 and a substrate voltage adjustment circuit 16.

[0032] The pre-charge unit 11 is connected between the power voltage VDDA 50 and the output end of the first current path 12, and is used to charge the bit line node in the first current path 12 during the pre-charge process. In the embodiment of the present application, the pre-charge unit 11 is composed of a second PMOS tube P2, the source of the P2 is connected to the power voltage VDDA 50, the drain is connected to the output end of the first current path 12, and the gate is connected to the pre-charge signal end Precharge.

[0033] The first current path 12 is connected between the gate of the first PMOS tube P1 and the ground, and is used to provide the storage unit current during the amplification process. The storage unit (not shown in the figure) is located in the first current path 12, and is generally composed of a SONOS tube for storing data information and a selection tube, the gate of the SONOS tube is connected to the word line WLS, and the gate of the selection tube is connected to the word line WL.

[0034] The first current path 12 further comprises a bit line adjustment unit, which is connected to the bit line node of the storage unit through a column multiplexing circuit (CMUX), and the storage unit is connected between the bit line node and the ground. In the embodiment of the present application, the bit line adjustment unit is composed of a first NMOS tube N1 and a third inverter INV3, the drain of the first NMOS tube N1 is the output end of the first current path 12, and the source of the first NMOS tube N1 is connected to the bit line node of the storage unit. The third inverter INV3 is connected between the source and the gate of the first NMOS tube N1, and the bit line node voltage is clamped according to the inversion point size of the third inverter INV3 after the pre-charge is completed during the pre-charge process. The bit line adjustment unit clamps the bit line node voltage during the pre-charge process and outputs the storage unit current during the amplification process.

[0035] The second current path 13 is connected between the gate of the first PMOS tube P1 and the power voltage VDDA 50, and the second current path 13 provides the storage unit comparison current during the amplification process. The second current path 13 is composed of a first switch and a first mirror current source in series, the first switch controls the conduction and the shutdown of the second current path 13, and the first mirror current source provides the storage unit comparison current when the second current path 13 is turned on. In the embodiment of the present application, the first switch is composed of a third PMOS tube P3, the source of the P3 is connected to the output end of the first mirror current source, the drain is used as the output end of the second current path 13 and is connected to the gate of the first PMOS tube P1, and the gate is connected to the inverted signal Saenb of the amplifier working enable signal. The first mirror current source is composed of a fourth PMOS tube P4, the source of the P4 is connected to the power voltage VDDA 50, the drain is used as the output end of the first mirror current source and is connected to the first switch, and the gate is connected to the first bias voltage Pbias.

[0036] The third current path 14 is connected between the drain of the first PMOS and the ground. The third current path 14 is composed of a second mirror current source. In the embodiment of the present application, the second mirror current source is composed of a second NMOS N2, the source of which is connected to the ground, the drain of which is connected to the drain of the first PMOS P1 as the output of the second mirror current source, and the gate of which is connected to the second bias voltage Nbias.

[0037] The source of the first PMOS P1 is connected to the power supply voltage VDDA 50, and the drain of the first PMOS P1 is connected to the input of the first inverter INV1. The output of the first inverter INV1 is connected to the input of the second inverter INV2 through the latch circuit 15, and the output of the second inverter INV2 is the output of the sense amplifier circuit and outputs the read data output signal.

[0038] The latch circuit 15 is composed of a first NOR gate 17 and a second NOR gate 18. The first NOR gate 17 has two inputs, one of which is connected to the output of the first inverter INV1 and the other of which is connected to the output of the second NOR gate 18. The second NOR gate 18 has two inputs, one of which is connected to the output of the first NOR gate 17 and the other of which is connected to the inverted signal Preb of the pre-charge signal. The output of the first NOR gate 17 is connected to the input of the second inverter INV2. When the signal output by the first inverter INV1 is a low-level signal, the first NOR gate 17 and the second NOR gate 18 are equivalent to a latch composed of two non-gates with opposite directions, and therefore, the data can be latched without static current.

[0039] The substrate voltage adjustment circuit 16 is composed of a resistor R1 and a current source DC connected in series. The current source is connected to the ground, and one end of the resistor R1 is connected to the power supply voltage and the other end of the resistor R1 is connected to the substrate of the first PMOS P1, which is used to adjust the voltage at the substrate of the first PMOS P1 and reduce the threshold voltage of the first PMOS P1.

[0040] In the embodiment of the present application, the first current path 12 is used to provide a storage cell current during amplification, the second current path 13 is used to provide a storage cell comparison current during amplification, and the gate of the first PMOS is controlled according to the comparison of the storage cell current and the storage cell comparison current.

[0041] The first value is the current of the memory cell when the memory data is 1, and the second value is the current of the memory cell when the memory data is 0. The third value is determined by the first bias voltage Pbias. When the third value is set to be greater than the first value, the memory data is 1, and the gate of the first PMOS transistor P1 is pulled high, so that the first PMOS transistor P1 is turned off. When the third value is set to be less than the second value, the memory data is 0, and the gate of the first PMOS transistor P1 is pulled low, so that the first PMOS transistor P1 is turned on.

[0042] The current of the third current path 14 is the fourth value, which is determined by the second bias voltage Nbias. The fourth value satisfies: during the amplification process, when the first PMOS transistor is turned off, the third current path 14 connects the drain of the first PMOS transistor to the ground, so as to keep the low level. When the first PMOS transistor is turned on, the current flowing through the first PMOS transistor is greater than the current of the third current path, so as to pull up the drain voltage of the first PMOS transistor to the high level.

[0043] When the cell read is selected:

[0044] First, the pre-charge process is performed: when the pre-charge control signal changes from high to low, the PMOS transistor P2 is turned on, and the bit line voltage of the memory cell is increased. As the bit line node voltage rises, when the voltage rises to the flip point of the inverter INV3, the inverter INV3 outputs low to turn off the NMOS transistor N1, and the potential of the last node c1 is clamped near the flip point of the inverter INV3. During pre-charge, the PMOS transistor P1 is closed.

[0045] After the pre-charge is completed, the amplification process is entered: if the E cell is read, the potential of the node DET will quickly decrease, the first PMOS transistor P1 is turned on, so that the drain potential DET2 of the first PMOS transistor P1 is pulled up to VDDA50, and the Dout output is 0; if the P cell is read, the potential of the node DET will not be pulled down, so that the first PMOS transistor P1 cannot be turned on, and the drain of the first PMOS transistor P1 is pulled to the GND potential by NBIAS, and the Dout output is 1. When the e cell is read, the substrate voltage adjusting circuit 16 lowers the substrate end potential Vb of the first PMOS transistor P1, so that the threshold voltage of the first PMOS transistor P1 is lowered, and the speed of pulling up the drain potential DET2 of the first PMOS transistor P1 to the VDDA50 potential is accelerated, thereby accelerating the flip speed of the output of the sensitive amplifier.

[0046] Figure 3 The display isFigure 1 The signal output effect comparison chart of the circuit shown in the embodiment of the present application and the circuit shown in the prior art. As shown in the figure Figure 3 At a voltage of 1.65V, Figure 1 The output time of the circuit shown in the figure is 4.781us, and the output time of the circuit shown in the embodiment of the present application is 4.777us. Compared with the prior art sensitive amplifier circuit, the embodiment of the present application is accelerated by 4ns.

[0047] The introduction of the substrate voltage adjustment circuit in the embodiment of the present application can effectively accelerate the output flip speed, realize the sensitive amplifier circuit with fast response, and improve the performance of the sensitive amplifier.

[0048] The above only describes the preferred embodiments of the present application and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A sense amplifier circuit, characterized by, The application relates to a sensitive amplifier circuit. The first current path is connected between the gate of the first PMOS tube and the ground, a storage unit is arranged in the first current path, and the first current path is used for providing a storage unit current during amplification. The second current path is connected between the gate of the first PMOS tube and a power supply voltage, and the second current path is used for providing a storage unit comparison current during amplification. The third current path is connected between the drain of the first PMOS tube and the ground. The first value is the size of the storage unit current when the storage data of the storage unit is 1, the second value is the size of the storage unit current when the storage data of the storage unit is 0, and the size of the storage unit comparison current is the third value; when the third value is set to be greater than the first value so that the storage data of the storage unit is 1, the gate of the first PMOS tube is pulled up to the high level so as to disconnect the first PMOS tube; when the third value is set to be less than the second value so that the storage data of the storage unit is 0, the gate of the first PMOS tube is pulled down to the low level so as to turn on the first PMOS tube. The size of the current of the third current path is the fourth value, and the size of the fourth value satisfies that, during amplification, the third current path connects the drain of the first PMOS tube and the ground when the first PMOS tube is disconnected so as to keep the low level, and the current flowing through the first PMOS tube is greater than the current of the third current path when the first PMOS tube is turned on so as to pull up the drain voltage of the first PMOS tube to the high level. The source of the first PMOS tube is connected to the power supply voltage, the drain is connected to the input end of the first inverter, the output end of the first inverter is connected to the input end of the second inverter through the latch circuit, the output end of the second inverter serves as the output end of the sensitive amplifier circuit and outputs the read data output signal. The substrate voltage adjustment circuit is used for adjusting the voltage of the substrate end of the first PMOS tube, is composed of a resistance and a current source in series, the current source is grounded, one end of the resistance is connected to the power supply voltage, and the other end is connected to the substrate of the first PMOS tube. The sensitive amplifier circuit further comprises a pre-charging unit, the pre-charging unit is connected between the power supply voltage and the output end of the first current path, and the pre-charging unit is used for charging the bit line node in the first current path during pre-charging.

2. The sensitive amplifier circuit of claim 1, wherein, The pre-charging unit is composed of a second PMOS tube, the source of the second PMOS tube is connected to the power supply voltage, the drain of the second PMOS tube is connected to the output end of the first current path, and the gate of the second PMOS tube is connected to a pre-charging signal.

3. The sensitive amplifier circuit of claim 2, wherein, ​ 4. The sensitive amplifier circuit of claim 1, wherein, The first current path comprises a bit line adjusting unit composed of a first NMOS tube and a third inverter, the drain of the first NMOS tube is the output end of the first current path, the source of the first NMOS tube is connected to the bit line node of the storage unit, and the storage unit is connected between the bit line node and the ground; the third inverter is connected between the source and the gate of the first NMOS tube, and the bit line node voltage after the pre-charge process is completed is clamped according to the inversion point size of the third inverter.

5. The sensitive amplifier circuit of claim 1, wherein, The second current path is composed of a first switch and a first mirror current source in series, the first switch controls the conduction and turn-off of the second current path, and the first mirror current source provides the comparison current of the storage unit when the second current path is turned on.

6. The sensitive amplifier circuit of claim 5, wherein, The first switch is composed of a third PMOS tube, the source of the third PMOS tube is connected to the output end of the first mirror current source, the drain of the third PMOS tube is the output end of the second current path and is connected to the gate of the first PMOS tube, and the gate of the third PMOS tube is connected to the inverted signal of the amplifier working enable signal.

7. The sensitive amplifier circuit of claim 5, wherein, The first mirror current source is composed of a fourth PMOS tube, the source of the fourth PMOS tube is connected to the power supply voltage, the drain of the fourth PMOS tube is the output end of the first mirror current source and is connected to the first switch, and the gate of the fourth PMOS tube is connected to the first bias voltage.

8. The sensitive amplifier circuit of claim 1, wherein, The third current path is composed of a second mirror current source.

9. The sensitive amplifier circuit of claim 8, wherein, The second mirror current source is composed of a second NMOS tube, the source of the second NMOS tube is grounded, the drain of the second NMOS tube is the output end of the second mirror current source and is connected to the drain of the first PMOS tube, and the gate of the second NMOS tube is connected to the second bias voltage.

10. The sensitive amplifier circuit of claim 1, wherein, The latch circuit is composed of a first NOR gate and a second NOR gate, the first NOR gate comprises two input ends connected to the output end of the first inverter and the output end of the second NOR gate respectively, the second NOR gate comprises two input ends connected to the output end of the first NOR gate and the inverted signal of the pre-charge signal respectively, and the output end of the first NOR gate is connected to the input end of the second inverter.

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