Data processing circuit and device

Abstract

An embodiment of the present application provides a data processing circuit and device. The circuit includes: a first storage group 301, a second storage group 302, a writing circuit 303 including a writing input buffer circuit 3031, a writing circuit 304 including a writing input buffer circuit 3041. The two writing circuits 303 and 304 respectively receive stored data from the same writing bus 306 through the writing input buffer circuits 3031 and 3041, write the stored data to the first storage group 301 through a first read / write bus 307, and write the stored data to the second storage group 302 through a second read / write bus 308. The frequencies of the control signals adopted by the two writing input buffer circuits 3031 and 3041 are both half of the clock frequency of writing the stored data on the writing bus 306, and the falling edges appear alternately. Each writing circuit in the embodiment of the present application includes a writing input buffer circuit, which can reduce the circuit size.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of integrated circuit technologies, and in particular, to a data processing circuit and device. Background Art

[0002] In a memory, data is stored through a storage array, and the storage array in the memory can be one or more. One common type of memory can be DRAM (dynamic random access memory), and DRAM is a type of memory. To improve the read and write efficiency of DRAM, in DDR (double data rate) DRAM, the internal storage array is usually divided into several BGs (bank groups), and cross-read and write operations are performed between different BGs. The data lines connected to each BG need to be merged in the central area, and the merged data lines share a data bus to achieve data reading.

[0003] However, the circuit size of the central area in the above solution is relatively large. Summary of the Invention

[0004] The embodiments of the present application provide a data processing circuit and device, which can solve the problem of the relatively large circuit size of the current central area.

[0005] In a first aspect, the embodiments of the present application provide a data processing circuit, including:

[0006] A first storage group and a second storage group;

[0007] Two write circuits, each write circuit includes a write input buffer circuit, and the two write circuits respectively receive stored data from the same write bus through the write input buffer circuit, write the stored data to the first storage group through a first read / write bus, and write the stored data to the second storage group through a second read / write bus; the frequencies of the control signals adopted by the two write input buffer circuits are both half of the clock frequency of writing stored data to the write bus, and the falling edges appear alternately.

[0008] Optionally, each write circuit further includes:

[0009] A write control circuit, which is respectively connected to the write input buffer circuit, the first write output buffer circuit, and the second write output buffer circuit in its own write circuit, and sends the stored data sent by the write input buffer circuit to the first write output buffer circuit or the second write output buffer circuit;

[0010] The first write-output buffer circuit, connected to the first memory bank, sends the stored data sent by the write control circuit to the first memory bank;

[0011] The second write-output buffer circuit, connected to the second memory bank, sends the stored data sent by the write control circuit to the second memory bank.

[0012] Optionally, the first write-output buffer circuits in the two write circuits use the same second control signal, the second write-output buffer circuits in the two write circuits use the same third control signal, the frequencies of the second control signal and the third control signal are both one-fourth of the clock frequency for writing stored data, and the falling edges of the second control signal and the third control signal appear alternately.

[0013] Optionally, the frequencies of the control signals used by the write control circuits in the two write circuits are the same as the frequencies of the control signals used by the write-input buffer circuits.

[0014] Optionally, the first write-output buffer circuit and the second write-output buffer circuit in one of the write circuits both use full latches, and the first write-output buffer circuit and the second write-output buffer circuit in the other write circuit both use half latches.

[0015] Optionally, the first read-write bus and the second read-write bus are arranged in a cross pattern.

[0016] Optionally, the first read-write bus includes first sub-buses of multiple bits, the second read-write bus includes second sub-buses of multiple bits, after the first sub-bus and the second sub-bus corresponding to the same bit extend to the same height, they are respectively connected to the first memory bank and the second memory bank.

[0017] Optionally, the two write circuits are arranged side by side on a first straight line, the first memory bank and the second memory bank are arranged side by side on a second straight line, and the first straight line and the second straight line are parallel.

[0018] Optionally, the first area where the two write circuits are located, and the second area where the first memory bank and the second memory bank are located are arranged side by side on a third straight line, and the third straight line is perpendicular to the first straight line.

[0019] Optionally, the data writing times of the first memory bank and the second memory bank are different, and the data writing logics of the first memory bank and the second memory bank are the same.

[0020] Optionally, the write control circuit controls data writing with a time delay between column address strobes, and the time delay between column address strobes includes four clock cycles.

[0021] In a second aspect, an embodiment of the present application provides a memory, including the data processing circuit described in the first aspect, and the write circuits in the two data processing circuits are connected to the same write bus.

[0022] Optionally, the memory is a double data rate dynamic random access memory DDR DRAM.

[0023] Optionally, the write circuits in the two data processing circuits are located in the central area, the first storage group and the second storage group in one of the data processing circuits are located on one side of the central area, and the first storage group and the second storage group in the other data processing circuit are located on the other side of the central area.

[0024] In a third aspect, an embodiment of the present application provides an electronic device, including the memory described in the second aspect.

[0025] An embodiment of the present application provides a data processing circuit and device, where the data processing circuit includes: a first storage group and a second storage group; two write circuits, each write circuit includes a write input buffer circuit, the two write circuits respectively receive stored data from the same write bus through the write input buffer circuit, write the stored data to the first storage group through the first read / write bus, and write the stored data to the second storage group through the second read / write bus; the frequencies of the control signals adopted by the two write input buffer circuits are both half of the clock frequency of writing stored data on the write bus, and the falling edges appear alternately. Each write circuit in the embodiment of the present application includes a write input buffer circuit. Since the write circuit is located in the central area, the circuit size of the central area can be reduced. Description of the Drawings

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required to be used in the description of the embodiments of the present application or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0027] Figure 1 Exemplarily shows a schematic structural diagram of a memory DDR DRAM in the prior art;

[0028] Figure 2 、 Figure 3Exemplarily shown is a schematic structural diagram of two data processing circuits provided by an embodiment of the present application;

[0029] Figure 4 Exemplarily shown is a schematic arrangement diagram of a first read / write bus and a second read / write bus provided by an embodiment of the present application;

[0030] Figure 5 、 Figure 6 Exemplarily shown is a schematic structural diagram of two data processing circuits provided by an embodiment of the present application;

[0031] Figure 7 Exemplarily shown is a timing diagram of a data writing process provided by an embodiment of the present application;

[0032] Figures 8 to 11 Exemplarily shown is a structural diagram of four memories provided by an embodiment of the present application;

[0033] Figure 12 Exemplarily shown is a schematic circuit structure diagram of a semi-latch provided by an embodiment of the present application;

[0034] Figure 13 Exemplarily shown is a schematic circuit structure diagram of a full-latch provided by an embodiment of the present application;

[0035] Figure 14 、 Figure 15 Exemplarily shown are two specific schematic structural diagrams of a data processing circuit provided by an embodiment of the present application. Detailed implementation manners

[0036] To make the objectives, implementation manners, and advantages of the present application clearer, the following will clearly and completely describe the exemplary implementation manners of the present application in conjunction with the accompanying drawings in the exemplary embodiments of the present application. Apparently, the described exemplary embodiments are only a part rather than all of the embodiments of the present application.

[0037] Based on the exemplary embodiments described in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope protected by the appended claims of the present application. In addition, although the disclosed content in the present application is introduced according to one or several exemplary instances, it should be understood that each aspect of these disclosed contents can also constitute a complete implementation manner alone.

[0038] It should be noted that the brief description of the terms in the present application is only for the convenience of understanding the subsequent described implementation manners, rather than intending to limit the implementation manners of the present application. Unless otherwise specified, these terms should be understood according to their ordinary and common meanings.

[0039] In this application, terms such as "first", "second", "third", etc. in the description, claims and the above-mentioned drawings are used to distinguish similar or like objects or entities, and do not necessarily mean to limit a specific order or sequence, unless otherwise indicated. It should be understood that such terms can be interchanged under appropriate circumstances, for example, it is possible to implement in an order other than those given in the illustration or description of the embodiments of this application.

[0040] In addition, the terms "comprise" and "have" and any variations thereof are intended to cover but not exclude inclusion. For example, a product or device comprising a series of components does not necessarily have to be limited to those components clearly listed, but may include other components not clearly listed or inherent to these products or devices.

[0041] The embodiments of this application can be applied to a data access scenario. For example, storing data in a memory or reading stored data from a memory. Among them, the memory in the embodiments of this application is a memory.

[0042] Figure 1 An exemplary structural schematic diagram of a memory DDR DRAM in the prior art is shown. Refer to Figure 1 As shown, the DDR DRAM includes four BGs for storing data: BG0, BG1, BG2, and BG3. Among them, BG0 and BG1 are arranged side by side in a row, BG2 and BG3 are arranged side by side in another row, and the row where BG0 and BG1 are located is parallel to the row where BG2 and BG3 are located.

[0043] In addition, there is a central area 100 between the above two columns. The circuit in the central area 100 is used to control writing stored data into each BG and reading stored data from each BG. There are four circuits in the central area 100: a writing circuit 101, a writing circuit 103, a reading circuit 102, and a reading circuit 104.

[0044] Among them, the writing circuit 101 is used to write the stored data in the writing bus 106 into BG0 and BG1, the writing circuit 103 is used to write the stored data in the writing bus 106 into BG2 and BG3, the reading circuit 102 is used to send the stored data read from BG0 and BG1 to the reading bus 105, and the reading circuit 104 is used to send the stored data read from BG2 and BG3 to the reading bus 105.

[0045] The stored data in the above-mentioned writing bus 106 is the stored data obtained from the DQ (data queue).

[0046] For the above-mentioned write circuit 101, it includes a write input buffer circuit 1013 and a write input buffer circuit 1016, a write control circuit 1012 and a write control circuit 1015, a write output buffer circuit 1011 and a write output buffer circuit 1014.

[0047] It can be seen that the write input buffer circuit 1013, the write control circuit 1012, and the write output buffer circuit 1011 are used to write stored data into BG0, and the write input buffer circuit 1016, the write control circuit 1015, and the write output buffer circuit 1014 are used to write stored data into BG1.

[0048] Among them, one end of the write input buffer circuit 1013 is connected to the write bus 106, and the other end is connected to the write control circuit 1012, and it is used to send the stored data obtained from the write bus 106 to the write control circuit 1012.

[0049] One end of the write control circuit 1012 is connected to the above-mentioned write input buffer circuit 1013, and the other end is connected to the write output buffer circuit 1011, and it is used to send the stored data received from the write input buffer circuit 1013 to the write output buffer circuit 1011.

[0050] One end of the write output buffer circuit 1011 is connected to the above-mentioned write control circuit 1012, and the other end is connected to BG0, and it is used to send the stored data received from the write control circuit 1012 to BG0.

[0051] Similarly, one end of the write input buffer circuit 1016 is connected to the write bus 106, and the other end is connected to the write control circuit 1015, and it is used to send the stored data received from the write bus 106 to the write control circuit 1015.

[0052] One end of the write control circuit 1015 is connected to the above-mentioned write input buffer circuit 1016, and the other end is connected to the write output buffer circuit 1014, and it is used to send the stored data received from the write input buffer circuit 1016 to the write output buffer circuit 1014.

[0053] One end of the write output buffer circuit 1014 is connected to the above-mentioned write control circuit 1015, and the other end is connected to BG1, and it is used to send the stored data received from the write control circuit 1015 to BG1.

[0054] It can be understood that for the write circuit 103, its structure is the same as that of the write circuit 101, the difference is that the two write output buffer circuits in the write circuit 103 are respectively connected to BG2 and BG3, and are used to write the stored data into BG2 and BG3.

[0055] For the above-mentioned reading circuit 102, it includes a reading output buffer circuit 1023 and a reading output buffer circuit 1026, a reading control circuit 1022 and a reading control circuit 1025, a reading input buffer circuit 1021 and a reading input buffer circuit 1024.

[0056] It can be seen that the reading input buffer circuit 1021, the reading control circuit 1022, and the reading output buffer circuit 1023 are used to read the stored data from BG0, and the reading input buffer circuit 1024, the reading control circuit 1025, and the reading output buffer circuit 1026 are used to read the stored data from BG1.

[0057] Among them, one end of the reading input buffer circuit 1021 is connected to BG0, and the other end is connected to the reading control circuit 1022, and is used to send the stored data read from BG0 to the reading control circuit 1022.

[0058] One end of the reading control circuit 1022 is connected to the above-mentioned reading input buffer circuit 1021, and the other end is connected to the reading output buffer circuit 1023, and is used to send the stored data received from the reading input buffer circuit 1021 to the reading output buffer circuit 1023.

[0059] One end of the reading output buffer circuit 1023 is connected to the above-mentioned reading control circuit 1022, and the other end is connected to the reading bus 105, and is used to send the stored data received from the reading control circuit 1022 to the reading bus 105.

[0060] Similarly, one end of the reading input buffer circuit 1024 is connected to BG1, and the other end is connected to the reading control circuit 1025, and is used to send the stored data read from BG1 to the reading control circuit 1025.

[0061] One end of the reading control circuit 1025 is connected to the above-mentioned reading input buffer circuit 1024, and the other end is connected to the reading output buffer circuit 1026, and is used to send the stored data received from the reading input buffer circuit 1024 to the reading output buffer circuit 1026.

[0062] One end of the reading output buffer circuit 1026 is connected to the above-mentioned reading control circuit 1025, and the other end is connected to the reading bus 105, and is used to send the stored data received from the reading control circuit 1025 to the reading bus 105.

[0063] It can be understood that for the reading circuit 104, its structure is the same as that of the reading circuit 102, the difference is that the two reading input buffer circuits in the reading circuit 104 are respectively connected to BG2 and BG3, and are used to send the stored data in BG2 and BG3 to the reading bus 105.

[0064] However, the circuit size of the central region 100 of the above-mentioned memory is relatively large.

[0065] To solve the above problems, after studying the above circuits, the applicant found that the process of writing stored data into BG0 and BG1 is carried out alternately, and their writing times are different, so there is no writing conflict between them. In addition, the process of reading stored data from BG0 and BG1 is also carried out alternately, and their reading times are different, so there is no reading conflict between them. Similarly, there are no writing conflicts and reading conflicts between BG2 and BG3.

[0066] Based on the above findings, the embodiments of the present application can perform at least one of the following circuit merges: the merge of the write input buffer circuits corresponding to BG0 and BG1, the merge of the write control circuits corresponding to BG0 and BG1, the merge of the read output buffer circuits corresponding to BG0 and BG1, the merge of the read control circuits corresponding to BG0 and BG1, the merge of the write input buffer circuits corresponding to BG2 and BG3, the merge of the write control circuits corresponding to BG2 and BG3, the merge of the read output buffer circuits corresponding to BG2 and BG3, and the merge of the read control circuits corresponding to BG2 and BG3. In this way, the circuit size of the merged central region can be reduced.

[0067] The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in some embodiments. The embodiments of the present application will be described below with reference to the drawings.

[0068] Figure 2 and Figure 3 Exemplarily shows the structural schematic diagrams of two data processing circuits provided by the embodiments of the present application. Referring to Figure 2 and Figure 3 as shown, the above data processing circuit mainly includes:

[0069] A first storage group 201 and a second storage group 202; a write circuit 203, the write circuit 203 includes a write input buffer circuit 2031, the write circuit 203 receives stored data from the write bus 206 through the write input buffer circuit 2031, the write circuit 203 writes the stored data into the first storage group 201 through the first read / write bus 207, and the write circuit 203 writes the stored data into the second storage group 202 through the second read / write bus 208; a read circuit 204, the read circuit 204 includes a read output buffer circuit 2041, the read circuit 204 reads the stored data from the first storage group 201 through the first read / write bus 207, the read circuit 204 reads the stored data from the second storage group 202 through the second read / write bus 208, and the read circuit 204 sends the stored data to the read bus 205 through the read output buffer circuit 2041.

[0070] Among them, the data reading and writing times of the first storage group 201 and the second storage group 202 are different. The above-mentioned first storage group 201 and second storage group 202 are two storage groups that store data alternately. At the same time, they are also two storage groups that write and store data alternately, that is, store data is alternately written into the first storage group 201 and the second storage group 202, and stored data is alternately read from the first storage group 201 and the second storage group 202. In addition, the data reading and writing logics of the first storage group 201 and the second storage group 202 are the same, so that the writing circuits of the first storage group 201 and the second storage group 202 can be combined, and the reading circuits of the first storage group 201 and the second storage group 202 can be combined. For example, when the above-mentioned first storage group 201 is Figure 1 BG0 in Figure 1 , the second storage group 202 is BG1; when the above-mentioned first storage group 201 is

[0071] From Figure 2 it can be seen that the above-mentioned writing circuit 203 includes: a writing input buffer circuit 2031, a first writing control circuit 2032, a second writing control circuit 2034, a first writing output buffer circuit 2033, and a second writing output buffer circuit 2035.

[0072] Among them, the writing input buffer circuit 2031 is respectively connected to the writing bus 206, the first writing control circuit 2032, and the second writing control circuit 2034, and is used to send the stored data obtained from the writing bus 206 to the first writing control circuit 2032 and the second writing control circuit 2034.

[0073] The first writing control circuit 2032 is respectively connected to the writing input buffer circuit 2031 and the first writing output buffer circuit 2033, and is used to send the stored data sent by the writing input buffer circuit 2031 to the first writing output buffer circuit 2033.

[0074] The second writing control circuit 2034 is respectively connected to the writing input buffer circuit 2031 and the second writing output buffer circuit 2035, and is used to send the stored data sent by the writing input buffer circuit 2031 to the second writing output buffer circuit 2035. The first writing output buffer circuit 2033 is respectively connected to the first writing control circuit 2032 and the first storage group 201, and sends the stored data sent by the first writing control circuit 2032 to the first storage group 201.

[0075] The second writing output buffer circuit 2035 is respectively connected to the second writing control circuit 2034 and the second storage group 202, and sends the stored data sent by the second writing control circuit 2034 to the second storage group 202.

[0076] Among them, the first write-output buffer circuit 2033 is connected to the first storage group 201 through the first read-write bus 207, and the second write-output buffer circuit 2035 is connected to the second storage group 202 through the second read-write bus 208. In the embodiments of the present application, the storage data in the write bus 206 can be written into the first storage group 201 through the write-input buffer circuit 2031, the first write control circuit 2032, and the first write-output buffer circuit 2033, and the storage data in the write bus 206 can be written into the second storage group 202 through the write-input buffer circuit 2031, the second write control circuit 2034, and the second write-output buffer circuit 2035. Figure 2 As can be seen from [reference], the above-mentioned reading circuit 204 includes: a read-output buffer circuit 2041, a first read control circuit 2042, a second read control circuit 2044, a first read-input buffer circuit 2043, and a second read-input buffer circuit 2045.

[0077] From Figure 2 As can be seen from [reference], the above-mentioned reading circuit 204 includes: a read-output buffer circuit 2041, a first read control circuit 2042, a second read control circuit 2044, a first read-input buffer circuit 2043, and a second read-input buffer circuit 2045.

[0078] Among them, the first read-input buffer circuit 2043 is respectively connected to the first storage group 201 and the first read control circuit 2042, and is used to send the storage data obtained from the first storage group 201 to the first read control circuit 2042.

[0079] The second read-input buffer circuit 2045 is respectively connected to the second storage group 202 and the second read control circuit 2044, and is used to send the storage data obtained from the second storage group 202 to the second read control circuit 2044.

[0080] The first read control circuit 2042 is respectively connected to the first read-input buffer circuit 2043 and the read-output buffer circuit 2041, and is used to send the storage data obtained from the first read-input buffer circuit 2043 to the read-output buffer circuit 2041.

[0081] The second read control circuit 2044 is respectively connected to the second read-input buffer circuit 2045 and the read-output buffer circuit 2041, and is used to send the storage data obtained from the second read-input buffer circuit 2045 to the read-output buffer circuit 2041.

[0082] The read-output buffer circuit 2041 is respectively connected to the first read control circuit 2042, the second read control circuit 2044, and the read bus 205, and is used to send the storage data obtained from the first read control circuit 2042 and the second read control circuit 2044 to the read bus 205.

[0083] Among them, the first read input buffer circuit 2043 and the first memory bank 201 are connected through the first read / write bus 207, and the second read input buffer circuit 2045 and the second memory bank 202 are connected through the second read / write bus 208. In the embodiments of the present application, through Figure 2 the first read input buffer circuit 2043, the first read control circuit 2042, and the read output buffer circuit 2041 in

[0084] the stored data in the first memory bank 201 can be read onto the read bus 205. Through the second read input buffer circuit 2045, the second read control circuit 2044, and the read output buffer circuit 2041, the stored data in the second memory bank 202 can be read onto the read bus 205. Figure 3 As can be seen from

[0085] the write circuit 203 includes a write input buffer circuit 2031, a write control circuit 2036, a first write output buffer circuit 2033, and a second write output buffer circuit 2035.

[0086] The write input buffer circuit 2031 is respectively connected to the write bus 206 and the write control circuit 2036, and is used to send the stored data obtained from the write bus 206 to the write control circuit 2036.

[0087] The write control circuit 2036 is respectively connected to the write input buffer circuit 2031, the first write output buffer circuit 2033, and the second write output buffer circuit 2035, and is used to send the stored data sent by the write input buffer circuit 2031 to the first write output buffer circuit 2033 or the second write output buffer circuit 2035.

[0088] The first write output buffer circuit 2033 is connected to the first memory bank 201, and sends the stored data sent by the write control circuit 2036 to the first memory bank 201.

[0089] In the embodiments of the present application, through Figure 3 the write input buffer circuit 2031, the write control circuit 2036, and the first write output buffer circuit 2033 in Figure 2The write input buffer circuit 2031 in 2 or 3 receives stored data through a first control signal, and the frequency of the first control signal is the same as the clock frequency for writing the stored data.

[0090] During the process of receiving stored data from the write bus 206, the above write input buffer circuit 2031 needs to rely on the frequency of the first control signal, and the frequency of the first control signal is the frequency at which the first control signal receives the stored data. For example, the first control signal can be a clock signal, and the stored data on the write bus 206 is transferred to the write input buffer circuit 2031 at the rising edge or falling edge of each clock signal.

[0091] It can be understood that when the frequency of the first control signal is greater than the clock frequency for writing the stored data, the write input buffer circuit 2031 has no stored data to receive at some moments, wasting the resources of the write input buffer circuit 2031; when the frequency of the first control signal is less than the clock frequency for writing the stored data, the write input buffer circuit 2031 will miss some stored data that needs to be written. The embodiments of the present application can make the frequency of the first control signal the same as the clock frequency for writing the stored data, which can not only save resources but also avoid missing the stored data that needs to be written.

[0092] Optionally, Figure 2 The first write output buffer circuit 2033 in 2 or 3 writes the stored data into the first storage group 201 through a second control signal, and the second write output buffer circuit 2035 writes the stored data into the second storage group 202 through a third control signal. The frequencies of the second control signal and the third control signal are half of the frequency of the first control signal, and the falling edges of the second control signal and the third control signal appear alternately.

[0093] It can be understood that the write circuit 203 is used to alternately write the stored data into the first storage group 201 and the second storage group 202, so that the falling edges of the second control signal and the third control signal appear alternately. For Figure 2 the write circuit 203 shown, when the falling edge of the second control signal appears, the first write output buffer circuit 2033 writes the stored data obtained from the first write control circuit 2032 into the first storage group 201. When the falling edge of the third control signal appears, the second write output buffer circuit 2035 writes the stored data obtained from the second write control circuit 2034 into the second storage group 202. It should be noted that the falling edge drive of the control signal does not constitute a limitation on the drive method. In some embodiments, the rising edge drive or the level drive can also be used.

[0094] For Figure 3The writing circuit 203 shown writes the stored data obtained from the writing control circuit 2036 into the first storage group 201 by the first writing output buffer circuit 2033 when the falling edge of the second control signal appears, and writes the stored data obtained from the writing control circuit 2036 into the second storage group 202 by the second writing output buffer circuit 2035 when the falling edge of the third control signal appears.

[0095] In addition, the arrival frequency of the falling edges of the second control signal and the third control signal is half of the frequency of the first control signal, that is, half of the clock frequency for writing the stored data. In this way, the stored data on the writing bus 206 can be evenly and alternately written into the first storage group 201 and the second storage group 202. For example, the stored data is written into the first storage group 201 and the second storage group 202 in the following order: the first storage group 201 - the second storage group 202 - the first storage group 201 - the second storage group 202 - … - the first storage group 201 - the second storage group 202, and so on in a cycle.

[0096] From Figure 3 it can be seen that the above reading circuit 204 includes: a reading output buffer circuit 2041, a reading control circuit 2046, a first reading input buffer circuit 2043, and a second reading input buffer circuit 2045.

[0097] Among them, the first reading input buffer circuit 2043 is connected to the first storage group 201 and is used to read the stored data from the first storage group 201.

[0098] The second reading input buffer circuit 2045 is connected to the second storage group 202 and is used to read the stored data from the second storage group 202.

[0099] The reading control circuit 2046 is respectively connected to the first reading input buffer circuit 2043 and the second reading input buffer circuit 2045, and is used to send the stored data sent by the first reading input buffer circuit 2043 or the second reading input buffer circuit 2045 to the reading output buffer circuit 2041.

[0100] The reading output buffer circuit 2041 is respectively connected to the reading control circuit 2046 and the reading bus 205, and is used to send the stored data obtained from the reading control circuit 2046 to the reading bus 205.

[0101] Among them, the first read input buffer circuit 2043 and the first memory bank 201 are connected through the first read / write bus 207, and the second read input buffer circuit 2045 and the second memory bank 202 are connected through the second read / write bus 208. In the embodiment of the present application, the storage data can be read from the first memory bank 201 to the read bus 205 through the read output buffer circuit 2041, the read control circuit 2046, and the first read input buffer circuit 2043 in the read circuit 204, and the storage data can be read from the second memory bank 202 to the read bus 205 through the read output buffer circuit 2041, the read control circuit 2046, and the second read input buffer circuit 2045 in the read circuit 204.

[0102] It should be noted that Figure 1 the time intervals of the data in the write control circuit 1012, the write control circuit 1015, the read control circuit 1022, and the read control circuit 1025 are the same. For example, it can be 5 nanoseconds. Figure 3 the data intervals in the write control circuit 2036 and the read control circuit 2046 are both Figure 1 half of that of the write control circuit 1012 in

[0103] The above Figure 3 The bit numbers of the read bus 205, the write bus 206, the first read / write bus 207, and the second read / write bus 208 in Figure 14 can be selected according to the actual application scenario. Figure 14 Exemplarily shows the specific structural schematic diagram of a data processing circuit provided by the embodiment of the present application. It can be seen from Figure 14 that when the read bus 205 and the write bus 206 are both 36 (i.e., [35:0]) bits, the first read / write bus 207 and the second read / write bus 208 can be 72 (i.e., [71:0]) bits. In this way, for the same memory bank, writing and reading can be performed simultaneously. For example, while writing data to the first memory bank 201 through the [35:0] bits of the write bus 206 and the first read / write bus 207, data can also be read from the first memory bank 201 through the [71:36] bits of the read bus 205 and the first read / write bus 207. It should be noted that Figure 14 the data processing circuit in Figure 14 can be composed of multiple sub-circuits. For example, it is composed of 9 sub-circuits. The structure of each sub-circuit is the same as that of the circuit structure in Figure 14 However, the write bus 206 and the read bus 205 of each sub-circuit are both 4 (i.e., [3:0]) bits, the first read / write bus 207 and the second read / write bus 208 are both 8 (i.e., [7:0]) bits, and the first memory banks in all sub-circuits are the same, and the second memory banks in all sub-circuits are the same.

[0104] Optionally,Figure 2 The first read input buffer circuit 2043 in 2 or 3 reads the stored data through the fourth control signal, and the second read input buffer circuit 2045 reads the stored data through the fifth control signal. The frequencies of the fourth control signal and the fifth control signal are the same, and the falling edges in the fourth control signal and the fifth control signal appear alternately.

[0105] It can be understood that the read circuit 204 is used to alternately read the stored data from the first storage group 201 and the second storage group 202, so that the falling edges of the fourth control signal and the fifth control signal appear alternately. When the falling edge of the fourth control signal appears, the first read input buffer circuit 2043 reads the stored data from the first storage group 201. When the falling edge of the fifth control signal appears, the second read input buffer circuit 2045 reads the stored data from the second storage group 202.

[0106] In addition, the arrival frequencies of the falling edges of the fourth control signal and the fifth control signal are the same. In this way, the stored data can be read evenly and alternately from the first storage group 201 and the second storage group 202. For example, the stored data is read from the first storage group 201 and the second storage group 202 in the following order: the first storage group 201 - the second storage group 202 - the first storage group 201 - the second storage group 202 -... - the first storage group 201 - the second storage group 202, and so on in a cycle.

[0107] Optionally, Figure 2 The read output buffer circuit 2041 in 2 or 3 sends the stored data to the read bus 205 through the sixth control signal, and the frequency of the sixth control signal is twice the frequency of the fourth control signal.

[0108] Among them, the frequency of the sixth control signal is the arrival frequency of the falling edge in the sixth control signal. When the falling edge of the sixth control signal arrives, the read output buffer circuit 2041 sends the stored data to the read bus 205. Since the read output buffer circuit 2041 not only needs to send the stored data read by the first read input buffer circuit 2043 from the first storage group 201 to the read bus 205, but also needs to send the stored data read by the second read input buffer circuit 2045 from the second storage group 202 to the read bus 205, the frequency of the sixth control signal is twice the frequency of the fourth control signal.

[0109] When the falling edges of the fourth control signal and the fifth control signal alternate, the read output buffer circuit 2041 can alternately send the stored data in the first storage group 201 and the stored data in the second storage group 202 to the read bus 205.

[0110] Optionally, the first read / write bus 207 and the second read / write bus 208 are arranged in a cross pattern. The first read / write bus 207 includes a first sub-bus with multiple bits, and the second read / write bus 208 includes a second sub-bus with multiple bits. After the first sub-bus and the second sub-bus corresponding to the same bit extend to the same height, they are respectively connected to the first storage group 201 and the second storage group 202.

[0111] In practical applications, the first sub-bus with multiple bits can achieve multi-bit parallel reading or multi-bit parallel writing to the first storage group 201, and the second sub-bus with multiple bits can achieve multi-bit parallel reading or multi-bit parallel writing to the second storage group 202. Figure 4 Exemplarily shown is a schematic diagram of the arrangement of the first read / write bus and the second read / write bus provided in the embodiment of the present application. As Figure 4 shown, the first read / write bus 207 includes a first sub-bus with 5 bits: b11, b12, b13, b14, and b15, and the second read / write bus includes a second sub-bus with 5 bits: b21, b22, b23, b24, and b25. Among them, b11 and b21 are the same bit, b12 and b22 are the same bit, b13 and b23 are the same bit, b14 and b24 are the same bit, and b15 and b25 are the same bit. It can be seen that after b11 and b21 extend to the same height, b11 is connected to the first storage group 201, and b12 is connected to the second storage group 202, and so on.

[0112] From Figure 4 it can be seen that the first sub-bus included in the above first read / write bus 207 and the second sub-bus included in the second read / write bus 208 are arranged in a cross pattern.

[0113] Through the above arrangement of the read / write buses, the embodiment of the present application can enable the first sub-bus and the second sub-bus of the same bit to share a horizontal lane, which helps to reduce the number of lanes and further reduces the size of the data processing circuit.

[0114] Optionally, the write circuit 203 and the read circuit 204 are arranged side by side on a first straight line, the first storage group 201 and the second storage group 202 are arranged side by side on a second straight line, and the first straight line and the second straight line are parallel.

[0115] It should be noted that the first straight line and the second straight line are parallel to each other but do not coincide. In this way, it is convenient for the circuit connection between the write circuit 203 and the first storage group 201, the circuit connection between the write circuit 203 and the second storage group 202, the circuit connection between the read circuit 204 and the first storage group 201, and the circuit connection between the read circuit 204 and the second storage group 202.

[0116] Optionally, a first region where the writing circuit 203 and the reading circuit 204 are located, and a second region where the first storage group 201 and the second storage group 202 are located are arranged side by side on a third straight line, and the third straight line is perpendicular to the first straight line.

[0117] It can be understood that when the third straight line is perpendicular to the first straight line and the first straight line is parallel to the second straight line, the writing circuit, the reading circuit, the first storage group, and the second storage group can form an approximate rectangle, which helps to minimize the size of the circuit as much as possible.

[0118] The principle of writing data to the first storage group and the second storage group by one writing circuit during the writing process is described in detail above. Next, the principle of writing data to the first storage group and the second storage group by two writing circuits will be described in detail.

[0119] Figure 5 Or Figure 6 An exemplary structural schematic diagram of a third data processing circuit provided by an embodiment of the present application is shown. Refer to Figure 5 Or Figure 6 As shown, the data processing circuit mainly includes:

[0120] A first storage group 301 and a second storage group 302; two writing circuits 303 and 304. The writing circuit 303 includes a writing input buffer circuit 3031, and the writing circuit 304 includes a writing input buffer circuit 3041. The writing circuits 303 and 304 respectively receive stored data from the same writing bus 306 through the writing input buffer circuits 3031 and 3041, write the stored data to the first storage group 301 through the first read-write bus 307, and write the stored data to the second storage group 302 through the second read-write bus 308; the control signals adopted by the two writing input buffer circuits 3031 and 3041 have a frequency that is half of the clock frequency of writing the stored data on the writing bus 306, and the falling edges appear alternately.

[0121] Among them, for the detailed description of the first storage group 301 and the second storage group 302, reference can be made to the detailed description of the first storage group 201 and the second storage group 202, which will not be elaborated here.

[0122] From Figure 5 it can be seen that the above-mentioned writing circuit 303 includes: a writing input buffer circuit 3031, a first writing control circuit 3032, a second writing control circuit 3034, a first writing output buffer circuit 3033, and a second writing output buffer circuit 3035.

[0123] Among them, the write input buffer circuit 3031 is respectively connected to the write bus 306, the first write control circuit 3032, and the second write control circuit 3034, and is used to send the stored data obtained from the write bus 306 to the first write control circuit 3032 and the second write control circuit 3034.

[0124] The first write control circuit 3032 is respectively connected to the write input buffer circuit 3031 and the first write output buffer circuit 3033, and is used to send the stored data sent by the write input buffer circuit 3031 to the first write output buffer circuit 3033.

[0125] The second write control circuit 3034 is respectively connected to the write input buffer circuit 3031 and the second write output buffer circuit 3035, and is used to send the stored data sent by the write input buffer circuit 3031 to the second write output buffer circuit 3035.

[0126] The first write output buffer circuit 3033 is respectively connected to the first write control circuit 3032 and the first storage group 301, and sends the stored data sent by the first write control circuit 3032 to the first storage group 301.

[0127] The second write output buffer circuit 3035 is respectively connected to the second write control circuit 3034 and the second storage group 302, and sends the stored data sent by the second write control circuit 3034 to the second storage group 302.

[0128] Among them, the first write output buffer circuit 3033 is connected to the first storage group 301 through the first read / write bus 307, and the second write output buffer circuit 3035 is connected to the second storage group 302 through the second read / write bus 308. Embodiments of the present application can pass Figure 5 the write input buffer circuit 3031, the first write control circuit 3032, and the first write output buffer circuit 3033 in, write the stored data in the write bus 306 into the first storage group 301, and pass the write input buffer circuit 3031, the second write control circuit 3034, and the second write output buffer circuit 3035 in the write circuit 303 to write the stored data in the write bus 306 into the second storage group 302.

[0129] The structure of the write circuit 304 is the same as that of 303, and will not be described in detail here.

[0130] Embodiments of the present application can pass Figure 5The first branch in it (the circuit composed of the write input buffer circuit 3031, the first write control circuit 3032, and the first write output buffer circuit 3033), and the second branch (the circuit composed of the write input buffer circuit 3041, the first write control circuit 3042, and the first write output buffer circuit 3043) parallelly write the stored data in the write bus 306 into the first storage group 301. Through Figure 5 The third branch in it (the circuit composed of the write input buffer circuit 3031, the second write control circuit 3034, and the second write output buffer circuit 3035), and the fourth branch (the circuit composed of the write input buffer circuit 3041, the second write control circuit 3044, and the second write output buffer circuit 3045) parallelly write the stored data in the write bus 306 into the second storage group 302.

[0131] Such as Figure 5 As shown, a total of two branches, namely the first branch and the second branch, perform parallel writing. In some embodiments, there can also be four branches or eight branches for parallel writing. The number of write branches can be determined according to the number of bits of the write bus 306, and there is no limitation here.

[0132] From Figure 6 it can be seen that the write circuit 303 includes: the write input buffer circuit 3031, the write control circuit 3036, the first write output buffer circuit 3033, and the second write output buffer circuit 3035.

[0133] The write input buffer circuit 3031 is respectively connected to the write bus 306 and the write control circuit 3036, and is used to send the stored data obtained from the write bus 306 to the write control circuit 3036.

[0134] The write control circuit 3036 is connected to the write input buffer circuit 3031 in its own write circuit 303, the first write output buffer circuit 3033 in its own write circuit 303, and the second write output buffer circuit 3035 in its own write circuit 303, and is used to send the stored data sent by the write input buffer circuit 3031 to the first write output buffer circuit 3033 or the second write output buffer circuit 3035.

[0135] The first write output buffer circuit 3033 is connected to the first storage group 301, and is used to send the stored data sent by the write control circuit 3036 to the first storage group 301.

[0136] The second write output buffer circuit 3035 is connected to the second storage group 302, and is used to send the stored data sent by the write control circuit 3036 to the second storage group 302.

[0137] Similarly, the structure of the writing circuit 304 is the same as that of the writing circuit 303, and will not be elaborated here.

[0138] The embodiment of the present application can pass Figure 6 in the first branch (the circuit composed of the write input buffer circuit 3031, the write control circuit 3036, and the first write output buffer circuit 3033), and, the second branch (the circuit composed of the write input buffer circuit 3041, the write control circuit 3046, and the first write output buffer circuit 3043), parallelly write the stored data in the write bus 306 into the first storage group 301, and pass Figure 6 in the third branch (the circuit composed of the write input buffer circuit 3031, the write control circuit 3036, and the second write output buffer circuit 3035), and, the fourth branch (the circuit composed of the write input buffer circuit 3041, the write control circuit 3046, and the second write output buffer circuit 3045), parallelly write the stored data in the write bus 306 into the second storage group 302.

[0139] As Figure 6 shown, a total of two branches, namely the first branch and the second branch, perform parallel writing. In some embodiments, there can also be four branches or eight branches for parallel writing. The number of writing branches can be determined according to the number of bits of the write bus 306, and there is no limitation here.

[0140] It should be noted that Figure 1 the time intervals of the data in the write control circuit 1012, the write control circuit 1015, the read control circuit 1022, and the read control circuit 1025 in Figure 6 are all the same. For example, it can be 5 nanoseconds. The data intervals in the write control circuits 3036 and 3046 in Figure 1 are both half of the data interval of the write control circuit 1012 in

[0141] For example, it is 2.5 milliseconds. Figure 6 The number of bits (i.e., the number of digits) of the write bus 306, the first read-write bus 307, and the second read-write bus 308 in the above Figure 15 can be selected according to the actual application scenario. Figure 15It can be seen that when the write bus 306 is 4 (i.e., [3:0]) bits, the first read / write bus 307 and the second read / write bus 308 can be 8 (i.e., [7:0]) bits. In this way, two consecutive 4-bit data on the write bus 306 can be simultaneously written into the first storage group 201 through the [3:0] bits and [7:4] bits of the first read / write bus 307 respectively, or two consecutive 4-bit data on the write bus 306 can be simultaneously written into the second storage group 202 through the [3:0] bits and [7:4] bits of the second read / write bus 308 respectively.

[0142] It can also be seen from Figure 15 that for the first storage group 201, the write circuit 303 can be used to write 4 (i.e., [3:0]) bits into the first storage group 201, and the write circuit 304 can be used to write 4 (i.e., [7:4]) bits into the first storage group 201. Similarly, for the second storage group 202, the write circuit 303 can be used to write 4 (i.e., [3:0]) bits into the second storage group 202, and the write circuit 304 can be used to write 4 (i.e., [7:4]) bits into the second storage group 202.

[0143] Figure 15 includes two write circuits. In practical applications, the data processing circuit may also include more than two write circuits, and their connection methods are the same as Figure 15 shown. For example, when the write bus 306 is 36 (i.e., [35:0]) bits, the first read / write bus 307 and the second read / write bus can be 72 (i.e., [71:0]) bits, so the write circuits included therein are 18, that is, it includes 9 groups of Figure 15 the data processing circuits shown.

[0144] Optionally, Figure 5 or Figure 6 the first write output buffer circuits 3033 and 3043 in the two write circuits 303 and 304 in

[0145] Figure 7 adopt the same second control signal, and the second write output buffer circuits 3035 and 3045 in the two write circuits 303 and 304 adopt the same third control signal. The frequencies of the second control signal and the third control signal are both one-fourth of the clock frequency of the written storage data, and the falling edges of the second control signal and the third control signal appear alternately. Figure 7 is Figure 6 the timing diagram corresponding to the data processing circuit. It can be seen from Figure 7It can be seen that the frequencies of the control signals adopted by the write input buffer circuits 3031 and 3041 of the two write circuits 303 and 304 are both half of the clock frequency at which the write bus 306 writes stored data, that is: the occurrence frequency of the falling edge of the write input buffer circuit 3031 and the occurrence frequency of the falling edge of the write input buffer circuit 3041 are half of the frequency of writing stored data. In addition, it can also be seen that the falling edge of the write input buffer circuit 3031 and the falling edge of the write input buffer circuit 3041 appear alternately.

[0146] At time t1, since a falling edge of the control signal of the write input buffer circuit 3031 arrives, the write control circuit 3036 outputs the currently received stored data d1. At time t2, since a falling edge of the control signal of the write input buffer circuit 3041 arrives, the write control circuit 3046 outputs the currently received stored data d2. At the same time, at time t2, since a falling edge of the control signal of the first write output buffer circuit 3033 arrives, the first write output buffer circuit 3033 writes the stored data d1 output by the write control circuit 3036 into the first storage group 301. At the same time, at time t2, since a falling edge of the control signal of the first write output buffer circuit 3043 arrives, the first write output buffer circuit 3043 writes the stored data d2 output by the write control circuit 3046 into the second storage group 302. It can be seen that through the above process, the stored data d1 and d2 at different times are written into the first storage group 301 at the same time t2.

[0147] Similarly, at time t3, since a falling edge of the control signal of the write input buffer circuit 3031 arrives, the write control circuit 3036 outputs the currently received stored data d3. At time t4, since a falling edge of the control signal of the write input buffer circuit 3041 arrives, the write control circuit 3046 outputs the currently received stored data d4. At the same time, at time t4, since a falling edge of the control signal of the second write output buffer circuit 3035 arrives, the second write output buffer circuit 3035 writes the stored data d3 output by the write control circuit 3036 into the second storage group 302. At the same time, at time t4, since a falling edge of the control signal of the second write output buffer circuit 3045 arrives, the second write output buffer circuit 3045 writes the stored data d4 output by the write control circuit 3046 into the second storage group 302. It can be seen that through the above process, the stored data d3 and d4 at different times are written into the second storage group 302 at the same time t4.

[0148] When Figure 6 the write bus in Figure 7The stored data d1, d2, d3, and d4 therein can all be 4 bits. d1 is the [3:0] bits written to the first storage group 301, d2 is the [7:4] bits written to the first storage group 301, d3 is the [3:0] bits written to the second storage group 302, and d4 is the [7:4] bits written to the second storage group 302.

[0149] Optionally, referring to Figure 6 In [reference], the frequencies of the control signals adopted by the write control circuits 3036 and 3046 in the two write circuits 303 and 304 are the same as the frequencies of the control signals adopted by the write input buffer circuits 3031 and 3041. In this way, the stored data sent by the write input buffer circuits 3031 and 3041 can be received synchronously, avoiding the loss of stored data.

[0150] Optionally, both the first write output buffer circuit and the second write output buffer circuit in one write circuit adopt full latches, and both the first write output buffer circuit and the second write output buffer circuit in the other write circuit adopt half latches. The write control circuit in the write circuit controls data writing with the time delay between column address strobes, and the time delay between column address strobes includes four clock cycles.

[0151] Among them, a latch is a memory cell circuit sensitive to pulse levels or rising edges or falling edges, and is used for data caching. In the embodiments of the present application, the write input buffer circuit, the first write output buffer circuit, the second write output buffer circuit, the first read input buffer circuit, the second read input buffer circuit, and the read output buffer circuit are all latches.

[0152] In the embodiments of the present disclosure, for the write circuit, the stored data in the write bus 306 is serial in time. In order to implement writing the serial stored data into the first storage group 301 or into the second storage group 302 simultaneously, the write circuit that receives the stored data first needs to wait for the write circuit that receives the stored data later. Thus, the first write output buffer circuit and the second write output buffer circuit in the write circuit that receives the stored data first can adopt full latches, and the first write output buffer circuit and the second write output buffer circuit in the write circuit that receives the stored data later can adopt half latches. Since the caching duration of the full latch for the stored data is longer than that of the half latch for the stored data, the two write circuits that receive the stored data at different times can write the stored data simultaneously, realizing the serial-to-parallel data writing process.

[0153] Figure 12 、 Figure 13 Exemplarily shows the circuit structure diagrams of the half latch and the full latch provided by the embodiments of the present application. As Figure 12 and13 As shown, the full latch is obtained by connecting two half latches in series. D is the data input port, CK and CKB are complementary clock ports, and Q and QB are data output ports.

[0154] Optionally, the first read / write bus and the second read / write bus are arranged in a cross pattern.

[0155] Optionally, the first read / write bus includes a first sub-bus with multiple bits, and the second read / write bus includes a second sub-bus with multiple bits. After the first sub-bus and the second sub-bus corresponding to the same bit extend to the same height, they are respectively connected to the first storage group and the second storage group.

[0156] Optionally, the two write circuits are arranged side by side on a first straight line, the first storage group and the second storage group are arranged side by side on a second straight line, and the first straight line and the second straight line are parallel.

[0157] It should be noted that the first straight line and the second straight line are parallel to each other but do not coincide. In this way, it is convenient for the circuit connection between the write circuit and the first storage group, and the circuit connection between the write circuit and the second storage group.

[0158] Optionally, the first region where the two write circuits are located, and the second region where the first storage group and the second storage group are located are arranged side by side on a third straight line, and the third straight line is perpendicular to the first straight line.

[0159] Optionally, the data writing times of the first storage group and the second storage group are different, and the data writing logics of the first storage group and the second storage group are the same. In this way, when there is no writing conflict, the write circuits for writing data with the same logic to the first storage group and the second storage group can be combined.

[0160] Figures 8 to 11 Exemplarily shows the structural schematic diagrams of four memories provided by the embodiments of the present application. Refer to Figures 8 to 11 As shown, each write circuit in the two data processing circuits is connected to the same write bus. For the two data processing circuits with read circuits, each read circuit in the two data processing circuits is connected to the same read bus.

[0161] Refer to Figure 8 As shown in Figure 9 As shown, one data processing circuit 401 includes: a first storage group BG0, a second storage group BG1, a write circuit 203, and a read circuit 204. Another data processing circuit 402 includes: a first storage group BG2, a second storage group BG3, a write circuit 209, and a read circuit 210. Figure 8 The two data processing circuits 401 and 402 in Figure 2The structures of the data processing circuits shown are the same. Figure 9 The two data processing circuits 401 and 402 in Figure 3 have the same structure as the data processing circuit shown.

[0162] Of course, Figure 2 the data processing circuit in Figure 3 and the data processing circuit in Figure 2 can form a memory, that is, the memory includes a Figure 3 data processing circuit shown and a

[0163] Referring to Figure 10 shown or Figure 11 shown, a data processing circuit 401 includes: a first storage group BG0, a second storage group BG1, a writing circuit 303, and a writing circuit 304. Another data processing circuit 402 includes: a first storage group BG2, a second storage group BG3, a writing circuit 309, and a writing circuit 310. Figure 10 The two data processing circuits 401 and 402 in Figure 5 have the same structure as the data processing circuit shown. Figure 11 The two data processing circuits 401 and 402 in Figure 6 have the same structure as the data processing circuit shown.

[0164] Of course, Figure 5 the data processing circuit in Figure 6 and the data processing circuit in Figure 5 can form a memory, that is, the memory includes a Figure 6 data processing circuit shown and a

[0165] Optionally, the above-mentioned memory is a double data rate dynamic random access memory DDR DRAM.

[0166] Optionally, the writing circuits in the two data processing circuits are located in the central area. The first storage group and the second storage group in one of the data processing circuits are located on one side of the central area, and the first storage group and the second storage group in the other data processing circuit are located on the other side of the central area.

[0167] Similarly, the reading circuits in the two data processing circuits are located in the central area. The first storage group and the second storage group in one of the data processing circuits are located on one side of the central area, and the first storage group and the second storage group in the other data processing circuit are located on the other side of the central area.

[0168] As Figure 8As shown in FIGS. 9 or 10, the writing circuits 203, 209, the reading circuits 204, 210 are located in the central region 200. The first memory bank BG0 and the second memory bank BG1 in the data processing circuit 401 are located on the upper side of the central region 200, and the first memory bank BG2 and the second memory bank BG3 in the data processing circuit 402 are located on the lower side of the central region 200.

[0169] As Figure 10 As shown in FIGS. 11 or 12, the writing circuits 303, 304, 309, 310 are located in the central region 300. The first memory bank BG0 and the second memory bank BG1 in the data processing circuit 401 are located on the upper side of the central region 300, and the first memory bank BG2 and the second memory bank BG3 in the data processing circuit 402 are located on the lower side of the central region 300. In this way, it is convenient for the wiring connections between the memory banks and the reading and writing circuits.

[0170] In an embodiment of the present application, an electronic device including the above-mentioned memory is further provided.

[0171] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

[0172] For the sake of convenience of explanation, the above description has been made in conjunction with specific embodiments. However, the above exemplary discussion is not intended to be exhaustive or to limit the embodiments to the specific forms disclosed above. According to the above teachings, various modifications and variations can be obtained. The selection and description of the above embodiments are for the purpose of better explaining the principles and practical applications, so that those skilled in the art can better use the embodiments and various different modified embodiments suitable for specific use considerations.

Claims

1. A data processing circuit, characterized in that, it includes: a first storage group and a second storage group; two writing circuits, each of the writing circuits includes a writing input buffer circuit, the two writing circuits respectively receive storage data from the same writing bus through the writing input buffer circuit, write the storage data to the first storage group through a first read-write bus, and write the storage data to the second storage group through a second read-write bus; the frequencies of the control signals adopted by the two writing input buffer circuits are both half of the clock frequency of writing storage data on the writing bus, and the falling edges appear alternately; each of the writing circuits further includes: a writing control circuit, which is respectively connected to the writing input buffer circuit, the first writing output buffer circuit, and the second writing output buffer circuit in its own writing circuit, and sends the storage data sent by the writing input buffer circuit to the first writing output buffer circuit or the second writing output buffer circuit; a first writing output buffer circuit, connected to the first storage group, and sends the storage data sent by the writing control circuit to the first storage group; a second writing output buffer circuit, connected to the second storage group, and sends the storage data sent by the writing control circuit to the second storage group; the first writing output buffer circuits in the two writing circuits adopt the same second control signal, the second writing output buffer circuits in the two writing circuits adopt the same third control signal, the frequencies of the second control signal and the third control signal are both one-fourth of the clock frequency of writing storage data, and the falling edges of the second control signal and the third control signal appear alternately.

2. The data processing circuit according to claim 1, characterized in that, the frequency of the control signal adopted by the writing control circuit in the two writing circuits is the same as the frequency of the control signal adopted by the writing input buffer circuit.

3. The data processing circuit according to any one of claims 1 to 2, characterized in that, the first writing output buffer circuit and the second writing output buffer circuit in one of the writing circuits both adopt full latches, and the first writing output buffer circuit and the second writing output buffer circuit in the other writing circuit both adopt half latches.

4. The data processing circuit according to any one of claims 1 to 2, characterized in that, the first read-write bus and the second read-write bus are arranged crosswise.

5. The data processing circuit according to claim 4, characterized in that, the first read-write bus includes a first sub-bus with multiple bits, the second read-write bus includes a second sub-bus with multiple bits, after the first sub-bus and the second sub-bus corresponding to the same bit extend to the same height, they are respectively connected to the first storage group and the second storage group.

6. The data processing circuit according to any one of claims 1 to 2, characterized in that, The two writing circuits are arranged side by side on a first straight line, the first storage group and the second storage group are arranged side by side on a second straight line, and the first straight line and the second straight line are parallel.

7. The data processing circuit according to claim 6, wherein, a first area where the two writing circuits are located, and a second area where the first storage group and the second storage group are located are arranged side by side on a third straight line, and the third straight line is perpendicular to the first straight line.

8. The data processing circuit according to any one of claims 1 to 2, wherein, the data writing times of the first storage group and the second storage group are different, and the data writing logics of the first storage group and the second storage group are the same.

9. The data processing circuit according to any one of claims 1 to 2, wherein, the writing control circuit controls data writing with a time delay between column address strobes, and the time delay between column address strobes includes four clock cycles.

10. A memory, wherein, it includes the data processing circuit according to any one of claims 1 to 9, and the writing circuits in the two data processing circuits are connected to the same writing bus.

11. The memory according to claim 10, wherein, the memory is a double data rate dynamic random access memory DDR DRAM.

12. The memory according to claim 10, wherein, the writing circuits in the two data processing circuits are located in a central area, the first storage group and the second storage group in one of the data processing circuits are located on one side of the central area, and the first storage group and the second storage group in the other data processing circuit are located on the other side of the central area.

13. An electronic device, wherein, it includes the memory according to any one of claims 10 to 12.

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