Memory chip and electronic device

Abstract

The embodiment of the present application provides a memory chip and an electronic device, which can store data according to resistance value states. The memory chip comprises at least one sub-storage circuit, each sub-storage circuit comprising a P-type MOS tube, an N-type MOS tube, a first memristor and a second memristor, and a control circuit is used for increasing the resistance values of the first memristor and the second memristor when the current directions through the first memristor and the second memristor are respectively controlled to be from the positive end to the negative end, increasing to the maximum value when the resistance values are greater than a preset rising resistance value, decreasing the resistance values of the first memristor and the second memristor when the current directions through the first memristor and the second memristor are controlled to be from the negative end to the positive end, and decreasing to the minimum value when the resistance values are less than a preset falling resistance value; and each sub-storage circuit stores data when the first memristor and the second memristor are kept at the maximum value and the minimum value respectively.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of storage, and in particular, to a memory chip and an electronic device. BACKGROUND

[0002] With the rapid growth of data, the requirements for storage chips are also increasing.

[0003] The existing storage chip generally stores data by using transistors. Because of the on-off characteristics of the transistor, the state of the transistor can be used to store data. For example, when the MOS transistor is turned on, logic 1 is stored, and when the MOS transistor is turned off, logic 0 is stored. SUMMARY

[0004] The embodiments of the present application provide a memory chip and an electronic device, which can store data according to the resistance state.

[0005] A memory chip includes at least one sub-storage circuit, each of the sub-storage circuits includes a P-type MOS transistor, an N-type MOS transistor, a first memristor, and a second memristor, the first and second memristors each include a positive terminal and a negative terminal, the P-type MOS transistor and the N-type MOS transistor each include a first terminal, a second terminal, and a control terminal, the first terminal of the P-type MOS transistor is connected to the first terminal of the N-type MOS transistor, and the connection is connected to a first input signal as a first terminal of the memory chip, the second terminal of the P-type MOS transistor is connected to the positive terminal of the first memristor, the second terminal of the N-type MOS transistor is connected to the negative terminal of the second memristor, the control terminals of the P-type MOS transistor and the N-type MOS transistor are connected to control signals, and the negative terminal of the first memristor and the negative terminal of the second memristor are connected together as a second terminal of the memory chip and connected to a second input signal.

[0006] The memory chip further includes a control circuit connected to the first terminal and the second terminal of each of the sub-storage circuits, and connected to the control terminal of the P-type MOS transistor and the control terminal of the N-type MOS transistor in each of the sub-storage circuits, for generating corresponding first input signals, second input signals, and control signals according to data to be stored, and loading the signals to the first terminal, the second terminal, the control terminal of the P-type MOS transistor, and the control terminal of the N-type MOS transistor in each of the sub-storage circuits, so that the memory chip stores the data to be stored.

[0007] The control circuit is configured to increase the resistance values of the first and second memristors when the current directions through the first and second memristors are positive terminal to negative terminal, and the resistance values reach maximum values when the resistance values are greater than preset rising resistance values, and the control circuit is configured to turn off the P-type MOS tube and the N-type MOS tube respectively, and the resistance values are kept as the maximum values; the control circuit is configured to decrease the resistance values of the first and second memristors when the current directions through the first and second memristors are negative terminal to positive terminal, and the resistance values reach minimum values when the resistance values are less than preset falling resistance values, and the control circuit is configured to turn off the P-type MOS tube and the N-type MOS tube respectively, and the resistance values are kept as the minimum values.

[0008] Each sub-storage circuit stores data when the first and second memristors are kept as the maximum and minimum values respectively.

[0009] In some embodiments, the voltage at the second terminal of each sub-storage circuit is greater than the voltage at the first terminal, and the current through the first memristor flows from the positive terminal to the negative terminal, or vice versa.

[0010] The voltage at the first terminal of each sub-storage circuit is greater than the voltage at the second terminal, and the current through the second memristor flows from the positive terminal to the negative terminal, or vice versa.

[0011] In some embodiments, each sub-storage circuit is configured to store logic 11, logic 10, logic 01 or logic 00; the first and second memristors represent storage of logic 1 when the resistance values are kept as the maximum values, and represent storage of logic 0 when the resistance values are kept as the minimum values.

[0012] Each sub-storage circuit includes the following control logic, and the control circuit is configured to store the control logic.

[0013] When each sub-storage circuit stores logic 11, the P-type MOS tube is controlled to be in a conductive state, the N-type MOS tube is controlled to be in a cut-off state, the current direction is controlled to flow from the positive terminal to the negative terminal of the first memristor, the P-type MOS tube is controlled to be in a cut-off state when the resistance value of the first memristor reaches the maximum value, the N-type MOS tube is controlled to be in a conductive state, the current direction of the second memristor is controlled to flow from the positive terminal to the negative terminal, the N-type MOS tube is controlled to be in a cut-off state when the resistance value of the second memristor reaches the maximum value, and thus the sub-storage circuit stores logic 11.

[0014] When each sub-storage circuit stores logic 00, the P-type MOS transistor is first controlled to be in an on state, the N-type MOS transistor is controlled to be in an off state, and the current direction is controlled to flow from the negative terminal to the positive terminal of the first memristor; when the resistance of the first memristor reaches a minimum value, the P-type MOS transistor is controlled to be in an off state so that the resistance of the first memristor is maintained at the minimum value, and the N-type MOS transistor is controlled to be in an on state, and the current of the second memristor is controlled to flow from the negative terminal to the positive terminal; when the resistance of the second memristor reaches a minimum value, the N-type MOS transistor is controlled to be in an off state, thereby realizing that the sub-storage circuit stores logic 00.

[0015] When each sub-storage circuit stores logic 10, the P-type MOS transistor and the N-type MOS transistor are first controlled to be in an on state, and the current is controlled to flow from the positive terminal to the negative terminal of the first memristor and from the negative terminal to the positive terminal of the second memristor; when the resistance of the first memristor reaches a maximum value and the resistance of the second memristor reaches a minimum value, the P-type MOS transistor and the N-type MOS transistor are controlled to be in an off state, thereby maintaining the resistance states of the first memristor and the second memristor, thereby realizing that the sub-storage circuit stores logic 10.

[0016] When each sub-storage circuit stores logic 01, the P-type MOS transistor and the N-type MOS transistor are first controlled to be in an on state, and the current is controlled to flow from the negative terminal to the positive terminal of the first memristor and from the positive terminal to the negative terminal of the second memristor; when the resistance of the first memristor reaches a maximum value and the resistance of the second memristor reaches a minimum value, the P-type MOS transistor and the N-type MOS transistor are controlled to be in an off state, thereby maintaining the resistance states of the first memristor and the second memristor, thereby realizing that the sub-storage circuit stores logic 01.

[0017] In some embodiments, a decoding circuit and an operation circuit are further included, and the decoding circuit and the operation circuit are connected with the control circuit;

[0018] The decoding circuit is used for decoding the data to be stored, and determining the number of sub-storage circuits to be used and the logic data to be stored by each sub-storage circuit according to the decoded data;

[0019] The control circuit is used for obtaining corresponding control logic according to the number of sub-storage circuits, and the logic data to be stored by each sub-storage circuit;

[0020] The operation circuit is used for inputting the required power consumption of the branch where the first memristor and the second memristor are located and the logic data to be stored into an acceleration model, and the time required for the acceleration model to output an extreme value is defined as an extreme value time;

[0021] The control circuit is used for controlling the sub-storage circuit to store the logic data to be stored according to the corresponding control logic, and when the extreme time is reached, the corresponding MOS tube is controlled to be turned off, or when the operation of the stored logic data is needed, the instruction of the operation of the stored data is received, and when the extreme time is reached, the operation is performed, and after the operation is ended, the corresponding MOS tube is controlled to be turned off.

[0022] In some embodiments, the memory chip further comprises a first voltage conversion circuit, a second voltage conversion circuit, and a selection switch, the number of the first voltage conversion circuit and the second voltage conversion circuit is the same as the number of the sub-storage circuit, the number of the selection switch is twice the number of the sub-storage circuit, the selection switch in one group is defined as a first selection switch and is connected to the first end of the corresponding sub-storage circuit, the selection switch in the other group is defined as a second selection switch and is connected to the second end of the corresponding sub-storage circuit, each selection switch comprises three ends, which are a selection end, a first conduction end, and a second conduction end, the first voltage conversion circuit outputs a first voltage, and the second voltage conversion circuit outputs a second voltage, the first voltage is higher than the second voltage;

[0023] Each first voltage conversion circuit and each second voltage conversion circuit are connected to the control circuit, the first end of each sub-storage circuit is connected to the selection end of the corresponding first selection switch, the first conduction end of each first selection switch is connected to the corresponding first voltage conversion circuit, and the second conduction end is connected to the corresponding second voltage conversion circuit, when the selection end of the first selection switch is connected to the first conduction end, the first end of the sub-storage circuit is connected to the first voltage, and when the second conduction end is connected, the second end of the sub-storage circuit is connected to the second voltage; the second end of each sub-storage circuit is connected to the selection end of the corresponding second selection switch, the first conduction end of the second selection switch is connected to the first voltage conversion circuit, and the second conduction end is connected to the second voltage conversion circuit, when the selection end of the second selection switch is connected to the first conduction end, the first end of the sub-storage circuit is connected to the first voltage, and when the second conduction end is connected, the second end of the sub-storage circuit is connected to the second voltage.

[0024] In some embodiments, the acceleration model adopts a lightweight convolutional neural network model, and the lightweight convolutional neural network model comprises an input layer, a first point-to-point convolutional layer, a deep convolutional layer, an activation function convolutional layer, a second point-to-point convolutional layer, and an output layer.

[0025] The input layer is configured to normalize input data, the first point-to-point convolutional layer is configured to perform 1*1 point convolution operation on the data output by the input layer, the deep convolutional layer is configured to perform K*K convolution on the convolution output result after the 1*1 point convolution operation, K is the size of the convolution kernel of the deep convolutional layer, the number of output channels is changed according to the expansion rate to control the dimension of the output, the activation function convolutional layer is configured to activate the convolution output result of the deep convolutional layer and multiply the convolution output result by the activation probability, the second point-to-point convolutional layer is configured to perform 1*1 point convolution operation on the output result of the activation function convolutional layer, and the output layer is configured to perform full connection operation on the convolution result of the second point-to-point convolutional layer and output target data, the target data is the time required for the first memristor and the second memristor to store logical 0 and logical 1 respectively.

[0026] In some embodiments, the training process of the acceleration model comprises:

[0027] The training data set is input into the lightweight convolutional neural network model, the training data set includes the logical data stored by the first memristor and the corresponding required power consumption, the logical data stored by the second memristor and the corresponding required power consumption, and is labeled with the time required to reach the maximum resistance value and the minimum resistance value respectively;

[0028] The lightweight convolutional neural network model is trained until the model converges, wherein, in the training process of the lightweight convolutional neural network model structure, for the first memristor, the difference of the time characteristics of storing the same logical data is reduced, while the difference of the time characteristics of storing different logical data is expanded, the difference of the time characteristics of the same logical data with the same power consumption is reduced, while the difference of the time characteristics of the same logical data with different power consumption is expanded, for the second memristor, the difference of the time characteristics of storing the same logical data is reduced, while the difference of the time characteristics of storing different logical data is expanded, the difference of the time characteristics of the same logical data with the same power consumption is reduced, while the difference of the time characteristics of the same logical data with different power consumption is expanded.

[0029] An electronic device comprising the memory chip according to any one of the preceding embodiments.

[0030] The memory chip according to the embodiments of the present application can store data in the first memristor and the second memristor by controlling the current direction and the operating state of the P-type MOS tube and the N-type MOS tube, and store data when the first memristor and the second memristor respectively maintain the maximum value and the minimum value. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, not all embodiments.

[0032] Figure 1 A partial structure diagram of a memory chip in one embodiment;

[0033] Figure 2 A partial structure diagram of a memory chip in another embodiment;

[0034] Figure 3 A structure diagram of a lightweight neural network model in one embodiment. DETAILED DESCRIPTION

[0035] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0036] It should be noted that the first device mentioned in the present application is coupled / connected / electrically connected to the second device, which means that the first device can be directly electrically / structurally connected to the second device, or indirectly electrically / structurally connected to the second device through other devices or connection means.

[0037] The term "and / or" used in the present application includes any and all combinations of one or more related listed items.

[0038] The terms "first", "second" used in the present application are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise explicitly and specifically limited. In the description of the present application, the meaning of "several" is at least one, such as one, two, etc., unless otherwise explicitly and specifically limited.

[0039] The present application proposes a memory chip, which can store data according to resistance state.

[0040] Figure 1 A partial structure diagram of a memory chip in one embodiment. Please refer to Figure 1The memory chip of the present application comprises at least one sub-memory circuit, each of which comprises a P-type MOS transistor, an N-type MOS transistor, a first memristor and a second memristor, the first and second memristors each comprising a positive terminal and a negative terminal, the P-type MOS transistor and the N-type MOS transistor each comprising a first terminal, a second terminal and a control terminal, the first terminal of the P-type MOS transistor being connected to the first terminal of the N-type MOS transistor, and the connection serving as a first terminal of the sub-memory circuit and being connected to a first input signal, the second terminal of the P-type MOS transistor being connected to the positive terminal of the first memristor, the second terminal of the N-type MOS transistor being connected to the negative terminal of the second memristor, the control terminals of the P-type MOS transistor and the N-type MOS transistor being connected to control signals, and the negative terminal of the first memristor and the negative terminal of the second memristor being connected together to serve as a second terminal of the sub-memory circuit and being connected to a second input signal. It should be noted that Figure 1 Terminals with the same reference numerals in the figures represent corresponding terminals connected together. Figure 1 Four sub-memory circuits are exemplarily shown, and the specific number of sub-memory circuits depends on actual requirements. Figure 1 The memory chip comprises four first memristors R11, R12, R13 and R14, four second memristors R21, R22, R23 and R24, four P-type MOS transistors MP1, MP2, MP3 and MP4, and four N-type MOS transistors MN1, MN2, MN3 and MN4.

[0041] The memory chip further comprises a control circuit U1 connected to the first terminals and the second terminals of the sub-memory circuits, and connected to the control terminals of the P-type MOS transistors and the control terminals of the N-type MOS transistors in the sub-memory circuits, for generating corresponding first input signals, second input signals and control signals according to the data to be stored, and loading the signals to the first terminals, the second terminals, the control terminals of the P-type MOS transistors and the control terminals of the N-type MOS transistors in the sub-memory circuits, so that the memory chip stores the data to be stored.

[0042] The control circuit U1 is used to increase the resistance values of the first and second memristors when the current directions through the first and second memristors are positive end to negative end, and the resistance values reach maximum values when the resistance values are greater than preset rising resistance values, and then the control circuit U1 turns off the P-type MOS tube and the N-type MOS tube respectively to keep the resistance values as the maximum values. The control circuit U1 is also used to decrease the resistance values of the first and second memristors when the current directions through the first and second memristors are negative end to positive end, and the resistance values reach minimum values when the resistance values are less than preset falling resistance values, and then the control circuit U1 turns off the P-type MOS tube and the N-type MOS tube respectively to keep the resistance values as the minimum values. Each sub storage circuit stores data when the first and second memristors keep as the maximum and minimum values, for example, stores logic 0 or logic 1. For example, the first and second memristors keep as the maximum values to store logic 1, and keep as the minimum values to store logic 0.

[0043] In conclusion, the memory chip of the embodiment of the application can store data into the first and second memristors by controlling the current directions and the operating states of the P-type MOS tube and the N-type MOS tube, that is, stores data when the first and second memristors keep as the maximum and minimum values.

[0044] The first input signal, the second input signal and the control signal mentioned above can be current or voltage signals. Taking the voltage signal as an example, the current direction through the first memristor is determined by the positive end voltage and the negative end voltage of the first memristor, the voltage of the negative end of the first memristor is determined by the input voltage connected to the first end of the sub storage circuit, and the voltage of the positive end is determined by the input voltage connected to the second end of the sub storage circuit. When the voltage of the positive end of the first memristor is greater than the voltage of the negative end, that is, the voltage of the second end of the sub storage circuit is greater than the voltage of the first end, the current flows from the positive end to the negative end, and vice versa. Similarly, the current direction through the second memristor is determined by the positive end voltage and the negative end voltage of the second memristor, the voltage of the positive end of the second memristor is determined by the voltage of the first end of the sub storage circuit, and the voltage of the negative end is determined by the voltage of the second end of the sub storage circuit. When the voltage of the positive end of the second memristor is greater than the voltage of the negative end, that is, the voltage of the first end of the sub storage circuit is greater than the voltage of the second end, the current flows from the positive end to the negative end, and vice versa. The control end voltage of the P-type MOS tube and the N-type MOS tube determines whether the two are turned on or turned off. When the control end voltage of the P-type MOS tube is greater than the threshold voltage, the P-type MOS tube is turned on, and when the control end voltage is less than the threshold voltage, the P-type MOS tube is turned off. When the control end voltage of the N-type MOS tube is less than the threshold voltage, the N-type MOS tube is turned on, and when the control end voltage is greater than the threshold voltage, the N-type MOS tube is turned off.

[0045] In some embodiments, each of the sub-memory circuits is used to store logic 11, logic 10, logic 01 or logic 00; the first and second memristors represent storage of logic 1 when the resistance value is kept at the maximum, and storage of logic 0 when the resistance value is kept at the minimum; each of the sub-memory circuits comprises a control logic, and the control circuit is used to store the control logic.

[0046] The following is an example of the first sub-memory circuit in the dashed box in FIG. 1. Figure 1 When each of the sub-memory circuits stores logic 11, the P-type MOS transistor MP1 is first controlled to be in the on state, the N-type MOS transistor MN1 is controlled to be in the off state, and the current direction is controlled to flow from the positive terminal to the negative terminal of the first memristor R11. When the resistance value of the first memristor R11 reaches the maximum, the P-type MOS transistor MP1 is controlled to be in the off state to keep the resistance value of the first memristor R11 at the maximum, i.e., to realize storage of logic 1 by the first memristor R11. At the same time, the N-type MOS transistor MN1 is controlled to be in the on state, and the current of the second memristor R21 is controlled to flow from the positive terminal to the negative terminal. When the resistance value of the second memristor R21 reaches the maximum, the N-type MOS transistor MN1 is controlled to be in the off state to realize storage of logic 1 by the second memristor R21. Similarly, to store logic 00, only the current direction of the first and second memristors R11 and R21 needs to be changed from the negative terminal to the positive terminal, and the remaining control operations remain unchanged and will not be described again.

[0047] When each of the sub-memory circuits stores logic 10, the P-type MOS transistor MP1 and the N-type MOS transistor MN1 are first controlled to be in the on state, and the voltage at the first terminal of the first sub-memory circuit is controlled to be higher than the voltage at the second terminal. In this way, the current direction can be controlled to flow from the positive terminal to the negative terminal of the first memristor R11 and from the negative terminal to the positive terminal of the second memristor R21. When the resistance value of the first memristor reaches the maximum and the resistance value of the second memristor reaches the minimum, the P-type MOS transistor MP1 and the N-type MOS transistor MN1 can be controlled to be in the off state, so as to keep the resistance values of the first and second memristors R11 and R21, thereby realizing storage of logic 10. Similarly, to store logic 01, only the voltage at the second terminal of the first sub-memory circuit needs to be controlled to be higher than the voltage at the first terminal, so as to control the current direction to flow from the negative terminal to the positive terminal of the first memristor R11 and from the positive terminal to the negative terminal of the second memristor R21, and the remaining control operations remain unchanged and will not be described again.

[0048] When subsequent reading of the data stored in the memory chip is required, the resistance values of the memristors can be read by using the reading circuit.

[0049] In some embodiments, the different sub-storage circuits, each first memristor and second memristor in the branch store the same data. To accelerate the data writing, each first memristor in the branch storing the same data can be simultaneously controlled to write the same data, and / or each second memristor in the branch storing the same data can be simultaneously controlled to write the same data.

[0050] In a specific implementation, the control circuit is further configured to obtain information about each first memristor in the branch storing the same data, and control each first memristor in the branch storing the same data to write the same data when controlling each sub-storage circuit to store the logical data to be stored according to the corresponding control logic.

[0051] In a specific implementation, the control circuit is further configured to obtain information about each second memristor in the branch storing the same data, and control each second memristor in the branch storing the same data to write the same data when controlling each sub-storage circuit to store the logical data to be stored according to the corresponding control logic.

[0052] Preferably, each sub-storage circuit uses the same first memristor and the same second memristor. The aforementioned "same" includes the same model, size, material, and other parameters of the memristor, which provides a hardware basis for better synchronization control.

[0053] Considering that the number of sub-storage circuits needed to be used simultaneously may be different when storing different data, the circuit power consumption is different, the control logic is different, and the time required for the first memristor and the second memristor to reach the extreme resistance state is also different. In order to accelerate the data storage process of the memory chip, in some embodiments, an acceleration model is used to output corresponding control signals. Here, the aforementioned extreme resistance state is defined as the minimum resistance value and the maximum resistance value.

[0054] In these embodiments, please refer to Figure 2 In addition to the control circuit U1, the memory chip further includes a decoding circuit U2 and an operation circuit U3, both of which are connected to the control circuit U1. The decoding circuit U2 is configured to decode the data to be stored, determine the number of sub-storage circuits to be used according to the number of bits of the decoded data, and determine the logical data to be stored by each sub-storage circuit, for example, the data to be stored is 11100110, which has a total of 8 bits, and 4 sub-storage circuits can be used for the low bits, and the logical data to be stored by each sub-storage circuit is 11, 10, 01, and 10.

[0055] The control circuit U1 is configured to obtain the corresponding control logic according to the number of sub-storage circuits and the logical data to be stored by each sub-storage circuit.

[0056] The operation circuit U3 is used for inputting the power consumption required by the branch where the first and second memristors are located and the logic data to be stored into an acceleration model, and outputting the time required to reach the extreme value by the acceleration model, which is defined as the extreme value time;

[0057] The control circuit U1 is used for controlling the MOS tube to be turned off when the extreme value time is reached when the sub-storage circuit stores data according to the control logic, or performing the operation when the extreme value time is reached when the instruction of operating the stored data is received, such as addition, subtraction, multiplication, division or Boolean operation, and then controlling the corresponding MOS tube to be turned off after the operation is completed.

[0058] Through the above scheme, the MOS tube is controlled to be turned off when the extreme value time is reached, which can save the power consumption of the circuit.

[0059] In order to accelerate the storage of data, the extreme value time required by the first and second memristors to reach the corresponding extreme value can be calculated by the operation circuit U3, and the extreme value time can be pre-calculated and saved in the control circuit U1 when the memory chip is obtained, so that the control circuit U1 can be directly called when the control circuit U1 is used to control the sub-storage circuit to store the corresponding logic data according to the control logic.

[0060] Specifically, please refer to Figure 2 The memory chip further includes a first voltage conversion circuit U5, a second voltage conversion circuit U6 and selection switches, the number of the first voltage conversion circuit U5 and the second voltage conversion circuit U6 is the same as the number of the sub-storage circuit, and the number of the selection switches is twice the number of the sub-storage circuit. The selection switches in one group are defined as first selection switches and are used to be connected to the first end of the corresponding sub-storage circuit, and the selection switches in the other group are defined as second selection switches and are used to be connected to the second end of the corresponding sub-storage circuit. Each selection switch includes three ends, which are a selection end, a first conduction end and a second conduction end. The first voltage conversion circuit U5 outputs a first voltage, the second voltage conversion circuit U6 outputs a second voltage, and the first voltage is higher than the second voltage. Taking Figure 2 for example, the first selection switch includes four, which are K11, K12, K13 and K14, and the second selection switch includes K21, K22, K23 and K24.

[0061] Each first voltage conversion circuit U5 and each second voltage conversion circuit U6 are connected to the control circuit U1, so that Figure 2The first end of the sub-storage circuit is connected with the selection end of the corresponding first selection switch, the first conduction end of each first selection switch is connected with the corresponding first voltage conversion circuit U5, and the second conduction end is connected with the corresponding second voltage conversion circuit U6. When the selection end of the first selection switch is connected with the first conduction end, the first end of the sub-storage circuit is connected with the first voltage, and when the second conduction end is connected, the second end of the sub-storage circuit is connected with the second voltage. Similarly, the second end of each sub-storage circuit is connected with the selection end of the corresponding second selection switch, the first conduction end of the second selection switch is connected with the first voltage conversion circuit U5, and the second conduction end is connected with the second voltage conversion circuit U6. When the selection end of the second selection switch is connected with the first conduction end, the first end of the sub-storage circuit is connected with the first voltage, and when the second conduction end is connected, the second end of the sub-storage circuit is connected with the second voltage. As a preferred embodiment, the first selection switch and the second selection switch connected with the same sub-storage circuit share the same first voltage conversion circuit U5 and the second voltage conversion circuit U6, which can reduce the area overhead.

[0062] In the embodiments, when the first end of each sub-storage circuit is connected with the first voltage and the second end is connected with the second voltage, the current of the corresponding first memristor flows from the negative end to the positive end, and the current of the corresponding second memristor flows from the positive end to the negative end; when the second end of the sub-storage circuit is connected with the first voltage and the first end is connected with the second voltage, the current of the first memristor flows from the positive end to the negative end, and the current of the second memristor flows from the negative end to the positive end.

[0063] The operation circuit U3 is used for inputting the power consumption of the branch where the first memristor and the second memristor are located, the use time of the memory chip, and the data to be stored into the acceleration model. The time required for the acceleration model to reach the extreme value is defined as the extreme value time.

[0064] The power consumption of the branch where the first memristor and the second memristor are located can be obtained according to the memristor parameters and the MOS tube parameters.

[0065] The acceleration model adopts a lightweight convolutional neural network model, such as Figure 3 As shown in the figure, the lightweight convolutional neural network model includes an input layer 310, a first point-to-point convolutional layer 320, a deep convolutional layer 330, an activation function convolutional layer 340, a second point-to-point convolutional layer 350, and an output layer 360.

[0066] The input layer 310 is configured to normalize the input data, such as power consumption of the branch where the first and second memristors are located, memory chip usage time, and data to be stored. The first point-to-point convolution layer 320 is configured to perform 1*1 point convolution operation on the data output by the input layer. The deep convolution layer 330 is configured to perform K*K convolution on the convolution output result after the 1*1 point convolution operation, where K is the size of the convolution kernel of the deep convolution layer, and the output channel number is changed according to the inflation rate to control the dimension of the output. The activation function convolution layer 340 is configured to activate the convolution output result of the deep convolution layer and multiply the convolution output result by the activation probability. The second point-to-point convolution layer 350 is configured to perform 1*1 point convolution operation on the output result of the activation function convolution layer. The output layer 360 is configured to perform full connection operation on the convolution result of the second point-to-point convolution layer and output target data. The target data is the time required for the first and second memristors to store logical 0 and logical 1, respectively, that is, the time to reach the maximum resistance and the minimum resistance, respectively.

[0067] Figure 3 The first point-to-point convolution layer, the deep convolution layer, the activation function convolution layer, and the second point-to-point convolution layer in the convolutional neural network include three dimensions, where the height of the model represents one of the two dimensions of the input data, the width of the model represents the other dimension of the two-dimensional input data, and the length of the model represents the number of channels. The length of the deep convolution layer is determined by the inflation rate, which is greater than 0 and less than 1.

[0068] In some embodiments, the acceleration model used is a lightweight convolutional neural network model, which can reduce the computational load of the memory chip and reduce power consumption.

[0069] The training process of the acceleration model includes:

[0070] The training data set is input into the lightweight convolutional neural network model, and the training data set includes logical data stored by the first memristor and corresponding required power consumption, logical data stored by the second memristor and corresponding required power consumption, and is labeled with the time required to reach the maximum resistance value and the minimum resistance value, respectively.

[0071] The lightweight convolutional neural network model is trained until the model converges, wherein, due to the difference in MOS tubes and connection modes of the first and second memristors in the training process of the lightweight convolutional neural network model structure, there is a certain difference in power consumption of branches where the first and second memristors are located, for the first memristor, the difference in time characteristics of the same logical data is reduced, and the difference in time characteristics of different logical data is expanded, then, the difference in time characteristics of the same logical data with the same power consumption is further reduced, and the difference in time characteristics of the same logical data with different power consumption is expanded, for the second memristor, the difference in time characteristics of the same logical data is reduced, and the difference in time characteristics of different logical data is expanded, then, the difference in time characteristics of the same logical data with the same power consumption is further reduced, and the difference in time characteristics of the same logical data with different power consumption is expanded.

[0072] For the training data set, the required power consumption of the branch where the first and second memristors are located can be obtained according to the memristor parameters and the MOS tube parameters of the branch, or tested and obtained.

[0073] The application also provides an electronic device comprising the memory chip as described in any one of the above embodiments.

[0074] The above embodiments only express several implementation manners of the application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be pointed out that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the application, and these all belong to the protection scope of the application. Therefore, the patent protection scope of the application should be subject to the appended claims.

Claims

1. A memory chip, characterized in that, The device includes at least one sub-memory circuit. Each sub-memory circuit includes a P-type MOSFET, an N-type MOSFET, a first memristor, and a second memristor. The first and second memristors each have a positive terminal and a negative terminal. The P-type MOSFET and the N-type MOSFET each have a first terminal, a second terminal, and a control terminal. The first terminal of the P-type MOSFET and the first terminal of the N-type MOSFET are connected, and the connection point serves as the first terminal of the corresponding sub-memory circuit, which is connected to a first input signal. The second terminal of the P-type MOSFET is connected to the positive terminal of the first memristor, and the second terminal of the N-type MOSFET is connected to the negative terminal of the second memristor. The control terminals of the P-type MOSFET and the N-type MOSFET are respectively connected to control signals. The negative terminals of the first and second memristors are connected together as the second terminal of the corresponding sub-memory circuit, which is connected to a second input signal. The memory chip also includes a control circuit, which is connected to the first and second ends of each sub-memory circuit, and also connected to the control ends of the P-type MOS transistors and N-type MOS transistors in each sub-memory circuit. The control circuit generates corresponding first input signals, second input signals, and control signals based on the data to be stored and loads them onto the first and second ends of each sub-memory circuit, the control ends of the P-type MOS transistors and the control ends of the N-type MOS transistors in each sub-memory circuit, so that the memory chip stores the data to be stored. The control circuit is used to increase the resistance values ​​of the first and second memristors when the current flowing through the first and second memristors is controlled to flow from the positive terminal to the negative terminal, respectively. The resistance values ​​increase to a maximum value when they exceed a preset rising resistance value. The control circuit then turns off the P-type MOSFET and the N-type MOSFET respectively to keep the resistance values ​​at their maximum values. The control circuit is also used to decrease the resistance values ​​of the first and second memristors when the current flowing through the first and second memristors is controlled to flow from the negative terminal to the positive terminal, respectively. The resistance values ​​decrease to a minimum value when they exceed a preset falling resistance value. The control circuit then turns off the P-type MOSFET and the N-type MOSFET respectively to keep the resistance values ​​at their minimum values. Each of the sub-storage circuits stores data when the first memristor and the second memristor are at their maximum and minimum values, respectively.

2. The memory chip according to claim 1, characterized in that, If the voltage at the second terminal of each of the sub-memory circuits is greater than the voltage at the first terminal, then the current through the first memristor flows from the positive terminal to the negative terminal, and vice versa. If the voltage at the first terminal of each of the sub-storage circuits is greater than the voltage at the second terminal, then the current through the second memristor flows from the positive terminal to the negative terminal, and vice versa.

3. The memory chip according to claim 2, characterized in that, Each of the sub-memory circuits is used to store logic 11, logic 10, logic 01 or logic 00; the first memristor and the second memristor represent storing logic 1 when the resistance value is kept at its maximum, and storing logic 0 when the resistance value is kept at its minimum; Each of the sub-storage circuits includes the following control logic, and the control circuit is used to store the control logic: When storing logic 11 in each of the sub-memory circuits, the P-type MOS transistor is first controlled to be in the on state while the N-type MOS transistor is controlled to be in the off state, and the current direction is controlled to flow from the positive terminal to the negative terminal of the first memristor. When the resistance of the first memristor reaches its maximum value, the P-type MOS transistor is controlled to be in the off state so that the resistance of the first memristor remains at its maximum value. At the same time, the N-type MOS transistor is controlled to be in the on state, and the current of the second memristor is controlled to flow from the positive terminal to the negative terminal. When the resistance of the second memristor reaches its maximum value, the N-type MOS transistor is controlled to be in the off state, thereby realizing the storage logic 11 of the sub-memory circuit. When each of the sub-memory circuits stores logic 00, the P-type MOS transistor is first controlled to be in the on state while the N-type MOS transistor is controlled to be in the off state. The current direction is controlled to flow from the negative terminal to the positive terminal of the first memristor. When the resistance of the first memristor reaches its minimum value, the P-type MOS transistor is controlled to be in the off state so that the resistance of the first memristor remains at its minimum value. At the same time, the N-type MOS transistor is controlled to be in the on state, and the current of the second memristor is controlled to flow from the negative terminal to the positive terminal. When the resistance of the second memristor reaches its minimum value, the N-type MOS transistor is controlled to be in the off state, thereby realizing the storage of logic 00 by the sub-memory circuit. When each of the sub-memory circuits stores logic 10, it first controls both the P-type MOS transistor and the N-type MOS transistor to be in the on state, and controls the current to flow from the positive terminal of the first memristor to the negative terminal and from the negative terminal of the second memristor to the positive terminal. When the resistance of the first memristor reaches its maximum value and the resistance of the second memristor reaches its minimum value, it controls the P-type MOS transistor and the N-type MOS transistor to enter the off state, thereby maintaining the resistance state of the first memristor and the second memristor, thereby realizing the storage logic 10 of the sub-memory circuit. When each of the sub-memory circuits stores logic 01, it first controls both the P-type MOS transistor and the N-type MOS transistor to be in the on state, and controls the current to flow from the negative terminal of the first memristor to the positive terminal and from the positive terminal of the second memristor to the negative terminal. When the resistance of the first memristor reaches its maximum value and the resistance of the second memristor reaches its minimum value, it controls the P-type MOS transistor and the N-type MOS transistor to enter the off state, thereby maintaining the resistance state of the first memristor and the second memristor, thus realizing the storage of logic 01 by the sub-memory circuit.

4. The memory chip according to claim 3, characterized in that, It also includes a decoding circuit and an arithmetic circuit, both of which are connected to the control circuit. The decoding circuit is used to decode the data to be stored, and determines the number of sub-storage circuits needed and the logical data to be stored in each sub-storage circuit based on the decoded data. The control circuit is used to obtain the corresponding control logic based on the number of sub-storage circuits and the logic data to be stored in each sub-storage circuit; The arithmetic circuit is used to input the power consumption required by the branch where the first memristor and the second memristor are located, and the logic data to be stored into the acceleration model. The acceleration model outputs the time required to reach the extreme value, which is defined as the extreme value time. The control circuit is used to control the sub-storage circuit to store the logic data to be stored according to the corresponding control logic. When the extreme value time is reached, the corresponding MOS transistor is turned off. Alternatively, when the stored logic data needs to be processed, and an instruction to process the stored data is received, the operation is performed when the extreme value time is reached. After the operation is completed, the corresponding MOS transistor is turned off.

5. The memory chip according to claim 4, characterized in that, The memory chip further includes a first voltage conversion circuit, a second voltage conversion circuit, and selection switches. The number of the first voltage conversion circuit and the second voltage conversion circuit is the same as the number of sub-storage circuits. The number of selection switches is twice that of the sub-storage circuits. The selection switches are divided into two groups. The selection switches in one group are all defined as first selection switches and are used to connect to the first terminal of the corresponding sub-storage circuit. The selection switches in the other group are all defined as second selection switches and are used to connect to the second terminal of the corresponding sub-storage circuit. Each selection switch includes three terminals: a selection terminal, a first conduction terminal, and a second conduction terminal. The first voltage conversion circuit outputs a first voltage, and the second voltage conversion circuit outputs a second voltage. The first voltage is higher than the second voltage. Each of the first voltage conversion circuits and each of the second voltage conversion circuits is connected to the control circuit. The first terminal of each sub-storage circuit is connected to the selection terminal of the corresponding first selection switch. The first conducting terminal of each first selection switch is connected to the corresponding first voltage conversion circuit, and the second conducting terminal is connected to the corresponding second voltage conversion circuit. When the selection terminal of the first selection switch is connected to the first conducting terminal, the first terminal of the sub-storage circuit is connected to the first voltage; when it is connected to the second conducting terminal, the second terminal of the sub-storage circuit is connected to the second voltage. The second terminal of each sub-storage circuit is connected to the selection terminal of the corresponding second selection switch. The first conducting terminal of the second selection switch is connected to the first voltage conversion circuit, and the second conducting terminal is connected to the second voltage conversion circuit. When the selection terminal of the second selection switch is connected to the first conducting terminal, the first terminal of the sub-storage circuit is connected to the first voltage; when it is connected to the second conducting terminal, the second terminal of the sub-storage circuit is connected to the second voltage.

6. The memory chip according to claim 4, characterized in that, The acceleration model adopts a lightweight convolutional neural network model, which includes an input layer, a first point-to-point convolutional layer, a depthwise convolutional layer, an activation function convolutional layer, a second point-to-point convolutional layer, and an output layer. The input layer is used to normalize the input data. The first point-to-point convolutional layer is used to perform a 1×1 point convolution operation on the data output from the input layer. The depthwise convolutional layer is used to perform a K*K convolution on the convolution output after the 1×1 point convolution operation, where K is the kernel size of the depthwise convolutional layer. The number of output channels is changed according to the dilation rate to control the output dimension. The activation function convolutional layer is used to activate the convolution output of the depthwise convolutional layer and multiply the convolution output by the activation probability. The second point-to-point convolutional layer is used to perform a 1×1 point convolution operation on the output of the activation function convolutional layer. The output layer is used to perform a fully connected operation on the convolution result of the second point-to-point convolutional layer and output the target data. The target data is the time required for the first memristor and the second memristor to store logic 0 and logic 1, respectively.

7. The memory chip according to claim 6, characterized in that, The training process of the accelerated model includes: The training dataset is input into a lightweight convolutional neural network model. The training dataset includes the logic data stored in the first memristor and the corresponding required power consumption, the logic data stored in the second memristor and the corresponding required power consumption, and is labeled with the time required to reach the maximum resistance value and the minimum resistance value, respectively. The lightweight convolutional neural network model is trained until it converges. During the training process of the lightweight convolutional neural network model structure, for the first memristor, the time feature differences in storing the same logical data are reduced, while the time feature differences in storing different logical data are increased; the time feature differences in the same logical data with the same power consumption are reduced, while the time feature differences in the same logical data with different power consumption are increased. For the second memristor, the time feature differences in storing the same logical data are reduced, while the time feature differences in storing different logical data are increased; the time feature differences in the same logical data with the same power consumption are reduced, while the time feature differences in the same logical data with different power consumption are increased.

8. The memory chip according to claim 6, characterized in that, The control circuit is also used to obtain the branch information of each first memristor storing the same data, and when controlling each sub-storage circuit to store the logic data to be stored according to the corresponding control logic, control the branch of each first memristor storing the same data to write the same data. And / or, the control circuit is also used to obtain the branch information of each second memristor storing the same data, and when controlling each sub-storage circuit to store the logic data to be stored according to the corresponding control logic, control the branches of each second memristor storing the same data to write the same data.

9. The memory chip according to claim 8, characterized in that, The first memristor used in each sub-memory circuit is the same, and the second memristor used in each sub-memory circuit is the same.

10. An electronic device, characterized in that, Including the memory chip as described in any one of claims 1-9.

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