Masking and precharging circuit for content addressable memory

Abstract

A shielding circuit for a content addressable memory includes a shielding control circuit and a level control circuit. The shielding control circuit generates a shielding signal based on a word line signal and a write enable signal. When the two signals correspond to a first level, the shielding signal is a first shielding signal. When the two signals correspond to different levels, the shielding signal is a second shielding signal. The two shielding signals are different. The level control circuit generates a level control signal based on the shielding signal to determine whether to pull a voltage level of an output terminal to a predetermined level. The output terminal is coupled to a match line of the content addressable memory. When the shielding signal is the first shielding signal, the level control circuit pulls the voltage level of the output terminal to the predetermined level. When the shielding signal is the second shielding signal, the level control circuit does not affect the voltage level of the output terminal.

Description

Technical Field

[0001] This invention relates to a shielding circuit and a pre-charge circuit, and more particularly to a shielding circuit and a pre-charge circuit suitable for a content addressable memory (CAM). Background Technology

[0002] Figure 1 This illustrates a conventional Content Addressable Memory (CAM) basic unit 100, including a storage element 110 and a comparison element 120. The storage element 110 stores a written content, and the comparison element 120 compares the written content with an input content to output a comparison result to a matching line for use by backend circuitry. The storage of the written content is achieved by controlling a word line and a bit line; the provision of the input content is achieved by controlling a search bit line. Figure 1 In this context, the bit line includes a positive endpoint bit line (BLP) and a negative endpoint bit line (BLN), and the search bit line includes a positive endpoint search bit line (SBLP) and a negative endpoint search bit line (SBLN).

[0003] Figure 2 This displays a conventional CAM array basic architecture 200, including multiple CAM basic cells 210, multiple precharge circuits 220, and a search data register / search bit line driver 230, wherein each CAM basic cell 210 is... Figure 1 The CAM basic unit 100 shown; each column of basic units 210 is equipped with a precharge circuit 220; the precharge circuits 220 charge or discharge a matching line of each column of basic units 210 according to a Matching Line Precharge Signal (MLPR); the search data register / search bit line driver 230 controls the search bit line of each row of CAM basic units 210 to provide an input content. When the CAM array basic architecture 200 is operating, a precharge circuit 220 first charges the matching line of the selected CAM basic unit 210, bringing its level to a high level (logic 1). After the search data register / search bit line driver 230 provides an input, the CAM basic unit 210 compares its stored content with the input content to generate a comparison result. When the comparison result indicates that the stored content is different from the input content, the precharge circuit 220 discharges the matching line, bringing its level down to a low level (logic 0). When the comparison result indicates that the stored content is the same as the input content, the precharge circuit 220 does not perform any action on the matching line, keeping it at the high level. Figure 2The connection architecture of the cascaded CAM basic unit 210 is usually called the NOR Type Match Line architecture. It is worth noting that... Figure 2 Each column of basic unit 210 is connected to a word line driver (not shown) to receive a word line signal (WL).

[0004] Please see Figure 1 and Figure 2 For a traditional CAM array, the storage element of a basic CAM unit (e.g.: Figure 1 The storage element 110) and the comparison element (e.g.: Figure 1 The operation of the comparison element 120 is independently controlled; basically, the read operation of the CAM array can be performed simultaneously with the comparison operation, but the write operation of the CAM array will affect the comparison operation. More specifically, when the CAM basic unit is performing a write operation, the result of the comparison operation performed on the CAM basic unit may be misjudged.

[0005] Generally speaking, in order to avoid misjudgment caused by write operations, a complex judgment circuit must be added to the back end of a traditional CAM array, which leads to an increase in design and manufacturing costs. Summary of the Invention

[0006] One of the objectives of this invention is to provide a shielding circuit and a pre-charging circuit to avoid the problems of the prior art.

[0007] One embodiment of the shielding circuit of the present invention is applicable to a content-addressable memory (CAM). This embodiment includes a shielding control circuit and a level control circuit. The shielding control circuit generates a shielding signal based on a first signal and a second signal. When the first signal and the second signal correspond to a first level, the shielding signal is a first shielding signal; when the first signal and the second signal correspond to different levels, the shielding signal is a second shielding signal. The first shielding signal is different from the second shielding signal. The level control circuit generates a level control signal based on the shielding signal to determine whether to pull the level of an output terminal to a predetermined level. The output terminal is coupled to a matching line of the CAM. When the shielding signal is the first shielding signal, the level control circuit pulls the level of the output terminal to the predetermined level; when the shielding signal is the second shielding signal, the level control circuit does not affect the level of the output terminal.

[0008] An embodiment of the pre-charge circuit of the present invention is applicable to a content-addressable memory. This embodiment includes a shielding control circuit, a charging control circuit, and a discharging control circuit. The shielding control circuit generates a shielding signal based on a word line signal and a write-enabled signal. When the word line signal and the write-enabled signal correspond to a first level, the shielding signal is a first shielding signal; when the word line signal and the write-enabled signal correspond to different levels, the shielding signal is a second shielding signal. The first shielding signal is different from the second shielding signal. The charging control circuit generates a charging control signal based on a matching line pre-charge signal and the shielding signal to determine whether to charge a matching line. When the shielding signal is the first shielding signal, the shielding signal blocks changes in the matching line pre-charge signal, so the charging control signal does not change with the matching line pre-charge signal. When the shielding signal is the second shielding signal, the shielding signal does not block changes in the matching line pre-charge signal, so the charging control signal changes with the matching line pre-charge signal. The discharge control circuit is used to generate a discharge control signal based on the shielding signal to determine whether to discharge the matching line. When the shielding signal shields the change of the pre-charge signal of the matching line, the discharge control signal discharges the matching line.

[0009] Another embodiment of the pre-charge circuit of the present invention includes a shielding control circuit, a charging control circuit, and a discharging control circuit. The shielding control circuit is used to couple or decouple a charging terminal from the charging control circuit based on a word line signal and a write-allow signal. Specifically, when either the word line signal or the write-allow signal corresponds to a first level, the shielding control circuit couples the charging terminal to the charging control circuit; when neither the word line signal nor the write-allow signal corresponds to the first level, the shielding control circuit decouples the charging terminal from the charging control circuit. The charging control circuit is used to determine whether to charge a matching line based on a matching line pre-charge signal. Specifically, when the matching line pre-charge signal corresponds to a second level, the charging control circuit decides to charge the matching line; when the matching line pre-charge signal corresponds to the first level, the charging control circuit decides not to charge the matching line. The discharge control circuit is used to determine whether to discharge the matching line based on the word line signal and the write-allow signal. When both the word line signal and the write-allow signal correspond to the second level, the discharge control circuit decides to discharge the matching line. When neither the word line signal nor the write-allow signal corresponds to the second level, the discharge control circuit decides not to discharge the matching line.

[0010] The features, implementation, and effects of the present invention will be described in detail below with reference to the accompanying drawings, focusing on preferred embodiments. Attached Figure Description

[0011] Figure 1 This displays a basic unit of a traditional content-addressable memory;

[0012] Figure 2 This illustrates the basic architecture of a traditional content-addressable memory array;

[0013] Figure 3 An embodiment of the pre-charging circuit of the present invention is shown;

[0014] Figure 4 show Figure 3 An embodiment of the shielding control circuit, charging control circuit and discharging control circuit;

[0015] Figure 5 Another embodiment of the pre-charging circuit of the present invention is shown;

[0016] Figure 6 show Figure 5 An embodiment of the shielding control circuit, charging control circuit and discharging control circuit;

[0017] Figure 7 A schematic diagram showing the signal relationships during a write operation; and

[0018] Figure 8 Another schematic diagram showing signal relationships during a write operation. Detailed Implementation

[0019] This invention proposes a pre-charge circuit and a shielding circuit that can determine whether to shield the comparison result of a content addressable memory (CAM) basic unit, thereby reducing the complexity of CAM circuit design. The pre-charge circuit and shielding circuit of this invention are applicable to CAMs with NOR type-match line architectures; more specifically, the pre-charge circuit of this invention can replace... Figure 2 Each of the precharge circuits 220 of the present invention receives a word line signal and a write enable signal, and operates accordingly. Additionally, the precharge circuit of the present invention may receive a system clock generated by a timing controller and operate accordingly. The generation and control of the aforementioned word line signal, write enable signal, and system clock are implemented based on known or self-developed techniques and are not within the scope of this invention; therefore, their details are omitted in this specification.

[0020] Figure 3 This invention illustrates an embodiment of the pre-charging circuit. Figure 3The pre-charge circuit 300 includes a shielding control circuit 310, a charging control circuit 320, and a discharging control circuit 330, which are described below.

[0021] Please see Figure 3 The shielding control circuit 310 generates a shielding signal MS based on a word line signal WL and a write-enabled signal WE. When both the word line signal WL and the write-enabled signal WE correspond to a first level (e.g., the level of logic 1, such as a high level), the shielding signal MS is a first shielding signal; when the word line signal WL and the write-enabled signal WE correspond to different levels, the shielding signal MS is a second shielding signal, and the first shielding signal is different from the second shielding signal. It is worth noting that when both the word line signal WL and the write-enabled signal WE correspond to a second level (e.g., the level of logic 0, such as a low level), the shielding signal MS is the second shielding signal.

[0022] Please see Figure 3 The charging control circuit 320 is used to generate a charging control signal (e.g., based on a matching line precharge signal MLPR and the shielding signal MS) Figure 4 The charging control signal "CG" is used to determine whether to charge a matching line. When the shielding signal MS is the first shielding signal, the shielding signal MS shields the changes in the matching line pre-charge signal MLPR, so the charging control signal will not change with the matching line pre-charge signal MLPR; when the shielding signal MS is the second shielding signal, the shielding signal MS does not shield the changes in the matching line pre-charge signal MLPR, so the charging control signal will change with the matching line pre-charge signal MLPR.

[0023] Please see Figure 3 The discharge control circuit 330 is used to generate a discharge control signal based on the shielding signal MS (e.g.: Figure 4 The discharge control signal "DCG" is used to determine whether to discharge the matching line. When the shielding signal MS shields the change of the matching line precharge signal MLPR, the discharge control signal discharges the matching line.

[0024] Figure 4 show Figure 3An embodiment of a shielding control circuit 310, a charging control circuit 320, and a discharging control circuit 330. The shielding control circuit 310 includes a first NAND gate 312, which generates the shielding signal MS based on the word line signal WL and the write-enabled signal WE. The charging control circuit 320 includes a second NAND gate 322, which generates a charging control signal CG based on the matching line precharge signal MLPR and the shielding signal MS. The charging control circuit 320 further includes a first switch 324 (e.g., a P-type semiconductor), which couples or decouples a charging terminal (e.g., a power supply terminal VDD) from the matching line based on the charging control signal CG. The discharging control circuit 330 includes an inverter 332, which generates a discharging control signal DCG based on the shielding signal MS. The discharge control circuit 330 further includes a second switch 334 (e.g., an N-type semiconductor) for coupling or decoupling the matching line from a discharge terminal (e.g., ground terminal GND) based on the discharge control signal DCG.

[0025] It is worth noting that, Figure 4 The combination of the first NAND gate 312, the second NAND gate 322, and the inverter 332 can be replaced by combinations of other logic elements; in other words... Figure 4 The embodiments described herein are not intended to limit the implementation of the invention. Since those skilled in the art, based on the teachings of this invention and common knowledge in the art, can replace the combinations of the above-described logic elements, redundant descriptions are omitted here.

[0026] It is also worth noting that, Figure 3 The charging control circuit 320 can be selectively omitted depending on implementation requirements. When the charging control circuit 320 is omitted, Figure 3The circuit, acting as a shielding circuit, includes a shielding control circuit 310 and a discharge control circuit 330. In this case, the shielding circuit can disregard whether the aforementioned matching line is charged. More specifically, when the shielding circuit discharges the matching line, even if the matching line is simultaneously charged according to the aforementioned matching line pre-charge signal MLPR, the leakage path between the charging end and the discharging end will not substantially affect the operation of the shielding circuit. To avoid this leakage path, those skilled in the art can use any known or self-developed method to prevent the matching line from being simultaneously pre-charged and discharged. For example, by controlling the timing of the write-enabled signal WE and / or the matching line pre-charge signal MLPR, the following effect can be achieved: during the data writing to CAM phase, when the shielding signal MS is the first shielding signal (i.e., the write-enabled signal WE is at the first level) to discharge the matching line, the matching line pre-charge signal MLPR is at the second level, and the matching line is not pre-charged. Where feasible, the word line signal WL and the write-enabled signal WE can be replaced by other signals; the discharge control circuit 330 can be replaced by a level control circuit, in which case the discharge terminal is replaced by a predetermined level terminal, the level of which is a predetermined level, wherein one embodiment of the level control circuit is the discharge control circuit 330.

[0027] Figure 5 This illustrates another embodiment of the pre-charging circuit of the present invention. Figure 5 The pre-charge circuit 500 includes a shielding control circuit 510, a charging control circuit 520, and a discharging control circuit 530. These circuits are described below.

[0028] Please see Figure 5 The shielding control circuit 510 is used to couple or decouple a charging terminal (e.g., based on a word line signal WL and a write-enabled signal WE) Figure 6 The power supply terminal (VDD) is connected to the charging control circuit 520. When either the word line signal WL or the write-enabled signal WE corresponds to a first level (e.g., the level of logic 0, such as a low level), the shielding control circuit 510 couples the charging terminal to the charging control circuit 520; when neither the word line signal WL nor the write-enabled signal WE corresponds to the first level, the shielding control circuit 510 decouples the charging terminal from the charging control circuit 520. For example, when both the word line signal WL and the write-enabled signal WE correspond to a second level (e.g., the level of logic 1, such as a high level), the shielding control circuit 510 decouples the charging terminal from the charging control circuit 520.

[0029] Please see Figure 5The charging control circuit 520 is used to determine whether to charge a matching line (ML) based on a matching line precharge signal MLPR. When the matching line precharge signal MLPR corresponds to the second level (e.g., high level), the charging control circuit 520 decides to charge the matching line; when the matching line precharge signal MLPR corresponds to the first level (e.g., low level), the charging control circuit 520 decides not to charge the matching line.

[0030] Please see Figure 5 The discharge control circuit 530 determines whether to discharge the matched line based on the word line signal WL and the write-allow signal EN. When both the word line signal WL and the write-allow signal EN correspond to the second level (e.g., a high level), the discharge control circuit 530 decides to discharge the matched line; when neither the word line signal WL nor the write-allow signal EN corresponds to the second level (e.g., at least one is not high), the discharge control circuit 530 decides not to discharge the matched line. For example, when either the word line signal WL or the write-allow signal EN corresponds to the first level, the discharge control circuit 530 decides not to discharge the matched line.

[0031] Figure 6 show Figure 5An embodiment of the shielding control circuit 510, charging control circuit 520, and discharging control circuit 530. The shielding control circuit 510 includes a first switch 512 (e.g., a PMOS transistor) and a second switch 514 (e.g., a PMOS transistor). The first switch 512 is coupled between a charging terminal VDD and the charging control circuit 520, and is used to couple or decouple the charging terminal VDD and the charging control circuit 520 according to the write enable signal WE. The second switch 514 is coupled between the charging terminal VDD and the charging control circuit 520, and is used to couple or decouple the charging terminal VDD and the charging control circuit 520 according to the word line signal WL. The charging control circuit 520 includes an inverter 522 and a third switch 524 (e.g., a PMOS transistor). Inverter 522 generates an inverse matching line precharge signal based on the matching line precharge signal MLPR to determine whether to charge a matching line. Inverter 522 and third switch 524 can be replaced by a single switch (e.g., an NMOS transistor) whose control logic is opposite to that of third switch 524. Third switch 524 is used to couple or decouple shielding control circuit 510 from the matching line based on the inverse matching line precharge signal. Discharge control circuit 530 includes a fourth switch 532 and a fifth switch 534 (e.g., an NMOS transistor). Fourth switch 532 is coupled between the matching line and fifth switch 534 and is used to couple or decouple the matching line from the fifth switch 534 based on word line signal WL. Fifth switch 534 is coupled between fourth switch 532 and a discharge terminal (e.g., ground GND) and is used to couple or decouple fourth switch 532 from the discharge terminal based on write enable signal WE. In an alternative embodiment, the fourth switch 532 is turned on or off according to the write enable signal WE, while the fifth switch 534 is turned on or off according to the word line signal WL.

[0032] It is worth noting that each of the aforementioned matching lines can be coupled to a back-end circuit (not shown) via a sense amplifier (not shown). This sense amplifier samples the signal on the matching line during latch-active operation and outputs the level of the sampled signal (logic 1 or logic 0) as a matchout to the back-end circuit. Since the configuration and operation of the aforementioned sense amplifier and back-end circuit can be implemented according to implementation requirements using known or self-developed technologies, and are not within the scope of this invention, their details are omitted here.

[0033] Figure 7An exemplary schematic diagram showing the system clock (SCLK, not shown in the previous diagram), the match line precharge signal MLPR, the word line signal WL and write enable signal WE, the signal on the match line (ML, not shown in the previous diagram), the sense amplifier latch active signal (SA Latch Active, not shown in the previous diagram), and the match output (MO, not shown in the previous diagram) during a write operation. Figure 7 As shown, within each system clock cycle, the matching line precharge signal MLPR first enters an evaluation phase for comparison, and then enters a pre-charge phase. When the word line signal WL and the write-enabled signal WE are high, the aforementioned discharge control circuit 330 / 530 discharges the matching line, thereby lowering the signal level on the matching line (corresponding to the interval marked "discharging the matching line" on the signal ML in the figure), so that the level of the matching output is logic 0 (corresponding to the interval marked "logic 0" on the signal MO in the figure). Figure 8 This is another exemplary schematic diagram showing the system clock, the match line precharge signal MLPR, the word line signal WL and the write enable signal WE, the signals on the match line, the signals of the sense amplifier, and the match output during a write operation; compared to Figure 7 , Figure 8 Within each system clock cycle, the matched line precharge signal MLPR first enters a precharge phase, and then enters an operation phase.

[0034] It is worth noting that, Figure 2 Each column of CAM basic unit 210 can be integrated into a known hierarchical architecture that shares a global match line. Figure 3 The pre-charge circuit 300 / 500 of the / 5 can still selectively shield the changes in the pre-charge signal MLPR of the matching line, as described above, to control the signal level of the overall matching line. In short, Figure 3 The 300 / 500 precharge circuit of the / 5 is applicable to a variety of CAM architectures, especially CAMs with NOR-N matching line architectures.

[0035] Please note that, where feasible, those skilled in the art may selectively implement some or all of the technical features in any of the foregoing embodiments, or selectively implement a combination of some or all of the technical features in the foregoing multiple embodiments, thereby increasing the selectivity of implementation of the present invention.

[0036] In summary, this invention can determine whether to shield the comparison results of CAM basic units, which helps to reduce the complexity of CAM circuit design and thus reduce the design and manufacturing costs of CAM.

[0037] While the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention. All such changes fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined according to the claims of this specification.

[0038] Explanation of reference numerals in the attached figures:

[0039] 100: Traditional basic unit of content-addressable memory

[0040] 110: Storage element

[0041] 120: Contrast element

[0042] BLP: Positive Endpoint Line

[0043] BLN: Negative bit line

[0044] SBLP: Positive End Search Bitline

[0045] SBLN: Negative End Search Bitline

[0046] 200: Basic Architecture of Traditional Content-Addressable Memory Arrays

[0047] 210: Basic unit of content-addressable memory

[0048] 220: Pre-charge circuit

[0049] 230: Search data register / search bit line driver

[0050] MLPR: Matching Line Precharge Signal

[0051] WL: Word line signal

[0052] 300: Pre-charge circuit

[0053] 310: Shielding control circuit

[0054] 320: Charging control circuit

[0055] 330: Discharge control circuit

[0056] WL: Word line signal

[0057] WE: Write Enable Signal

[0058] MS: Shielded signal

[0059] MLPR: Matching Line Precharge Signal

[0060] 312: First NAND Gate

[0061] 322: Second NAND gate

[0062] 324: First Switch

[0063] 332: Inverter

[0064] 334: Second Switch

[0065] CG: Charging control signal

[0066] DCG: Discharge control signal

[0067] VDD: Power supply terminal

[0068] 500: Pre-charge circuit

[0069] 510: Shielding control circuit

[0070] 520: Charging control circuit

[0071] 530: Discharge control circuit

[0072] 512: First Switch

[0073] 514: Second Switch

[0074] 522: Inverter

[0075] 524: The Third Switch

[0076] 532: Fourth Switch

[0077] 534: The Fifth Switch

[0078] SCLK: System Clock

[0079] ML: Matching signal on the line

[0080] SA Latch Active: Lock-on actuation signal for the sense amplifier

[0081] MO: Matching Output

Claims

1. A masking circuit adapted for a content addressable memory, the masking circuit comprising: a masking control circuit for generating a masking signal in response to a first signal and a second signal, wherein the masking signal is a first masking signal when the first signal and the second signal correspond to a first level, and the masking signal is a second masking signal when the first signal and the second signal correspond to different levels, the first masking signal being different from the second masking signal; and a level control circuit for generating a level control signal in response to the masking signal to determine whether to pull a voltage level of an output terminal to a predetermined level, wherein the output terminal is coupled to a match line of the content addressable memory; the level control circuit pulls the voltage level of the output terminal to the predetermined level when the masking signal is the first masking signal, and the level control circuit does not affect the voltage level of the output terminal when the masking signal is the second masking signal, wherein the first signal is a word line signal for the content addressable memory, and the second signal is a write enable signal for the content addressable memory. a match line precharge signal is at a second level when the masking signal is the first masking signal, the match line precharge signal being used to determine whether to precharge the match line, the match line precharge signal determining not to precharge the match line when the match line precharge signal is the second level; and the match line precharge signal determining to precharge the match line when the match line precharge signal is the first level.

2. The shielding circuit of claim 1, wherein the masking control circuit comprises a NAND gate for generating the masking signal in response to the first signal and the second signal. the level control circuit comprises:

3. The shielding circuit of claim 1, wherein, an inverter for generating the level control signal in response to the masking signal; and 4. The shielding circuit of claim 1, wherein, a switch coupled between the output terminal and a predetermined level terminal, the switch being used to couple or decouple the output terminal and the predetermined level terminal in response to the level control signal, the predetermined level terminal being at the predetermined level.

5. A precharge circuit adapted for a content addressable memory, the precharge circuit comprising: a masking control circuit for generating a masking signal in response to a word line signal and a write enable signal, wherein the masking signal is a first masking signal when the word line signal and the write enable signal correspond to a first level, and the masking signal is a second masking signal when the word line signal and the write enable signal correspond to different levels, the first masking signal being different from the second masking signal; and a level control circuit for generating a level control signal in response to the masking signal to determine whether to pull a voltage level of an output terminal to a predetermined level, wherein the output terminal is coupled to a match line of the content addressable memory; the level control circuit pulls the voltage level of the output terminal to the predetermined level when the masking signal is the first masking signal, and the level control circuit does not affect the voltage level of the output terminal when the masking signal is the second masking signal, wherein the first signal is a word line signal for the content addressable memory, and the second signal is a write enable signal for the content addressable memory. a charge control circuit for generating a charge control signal according to a match line precharge signal and the shield signal to determine whether to charge a match line, wherein when the shield signal is the first shield signal, the shield signal masks a change of the match line precharge signal, so that the charge control signal does not change with the match line precharge signal, and when the shield signal is the second shield signal, the shield signal does not mask the change of the match line precharge signal, so that the charge control signal changes with the match line precharge signal; and a discharge control circuit for generating a discharge control signal according to the shield signal to determine whether to discharge the match line, wherein when the shield signal masks the change of the match line precharge signal, the discharge control signal discharges the match line.

6. A precharge circuit adapted for a content addressable memory, the precharge circuit comprising a shield control circuit, a charge control circuit and a discharge control circuit, wherein: the shield control circuit is for coupling or decoupling a charge terminal and the charge control circuit according to a word line signal and a write enable signal, wherein when either of the word line signal and the write enable signal corresponds to a first level, the shield control circuit couples the charge terminal and the charge control circuit, and when neither of the word line signal and the write enable signal corresponds to the first level, the shield control circuit decouples the charge terminal and the charge control circuit; the charge control circuit is for determining whether to charge a match line according to a match line precharge signal, wherein when the match line precharge signal corresponds to a second level, the charge control circuit determines to charge the match line, and when the match line precharge signal corresponds to the first level, the charge control circuit determines not to charge the match line; and the discharge control circuit is for determining whether to discharge the match line according to the word line signal and the write enable signal, wherein when both of the word line signal and the write enable signal correspond to the second level, the discharge control circuit determines to discharge the match line, and when either of the word line signal and the write enable signal does not correspond to the second level, the discharge control circuit determines not to discharge the match line.

7. The pre-charge circuit of claim 6, wherein, the shield control circuit comprises: a first switch coupled between the charge terminal and the charge control circuit for coupling or decoupling the charge terminal and the charge control circuit according to the write enable signal; and a second switch coupled between the charge terminal and the charge control circuit for coupling or decoupling the charge terminal and the charge control circuit according to the word line signal.

8. The pre-charge circuit of claim 7, wherein, the charge control circuit comprises: an inverter for generating an inverted match line precharge signal according to the match line precharge signal to determine whether to charge the match line; and a third switch for coupling or decoupling the shield control circuit and the match line according to the inverted match line precharge signal.

9. The pre-charge circuit of claim 8, wherein, the discharge control circuit comprises: a fourth switch coupled between the match line and a fifth switch for coupling or decoupling the match line and the fifth switch according to a first signal, the first signal being one of the word line signal and the allow write signal; and a fifth switch coupled between the fourth switch and a discharge terminal for coupling or decoupling the fourth switch and the discharge terminal according to a second signal, the second signal being one of the word line signal and the allow write signal, and the second signal being different from the first signal.

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