Memory system and method of operating the same

Abstract

Various embodiments generally relate to a memory system and an operating method thereof. According to an embodiment of the present disclosure, the memory system sets a status check memory block for a first memory die included in a plurality of memory dies, the status check memory block being used to check the status of data stored in a memory block included in the first memory die, and the memory system manages a status check page and a programming memory block list for each of a plurality of predetermined temperature intervals, the status check page corresponding to the temperature interval and included in the status check memory block, and the programming memory block list indicating information about a specific memory block programmed when the temperature of the memory system falls within the temperature interval.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2021-0035251, filed on March 18, 2021, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the disclosed technology generally relate to a memory system and a method of operating the same. Background Art

[0004] Memory systems include data storage devices that store data based on requests from a host such as a computer, server, smart phone, tablet PC or other electronic device. Examples of memory systems range from traditional disk-based hard disk drives (HDDs) to semiconductor-based data storage devices such as solid-state drives (SSDs), universal flash memory devices (UFS) or embedded MMC (eMMC) devices.

[0005] The memory system may further include a memory controller for controlling the memory device. The memory controller may receive a command from the host, and based on the received command, may execute a command or control a read operation / write operation / erase operation on the memory device in the memory system. The memory controller may be used to execute firmware operations to perform logic operations for controlling these operations.

[0006] Since data is stored in the memory device, the possibility of an error in the data stored in the memory device increases with the passage of time. Therefore, the memory system needs to check whether an error occurs in the data stored in the memory device by checking the state of the corresponding data. Summary of the invention

[0007] Various embodiments of the disclosed technology relate to a memory system and an operating method thereof that can quickly detect whether an error occurs in stored data under various temperature environments.

[0008] Various embodiments of the disclosed technology relate to a memory system and an operating method thereof capable of preventing problems caused by reliability degradation due to temperature variation by checking in advance whether an error occurs in data programmed under a specific temperature condition.

[0009] In one aspect, an embodiment of the disclosed technology may provide a memory system comprising: a memory device including a plurality of memory dies, each memory die including a plurality of memory blocks configured to store data; and a memory controller coupled to communicate with the memory device and configured to control the memory device.

[0010] The memory controller may set a status check memory block for a first memory die included in the plurality of memory dies, the status check memory block being used to check a status of data stored in a memory block included in the first memory die.

[0011] The memory controller may manage, for each of a plurality of predetermined temperature periods, (1) a status check page corresponding to the temperature period and included in a status check memory block, and (2) a programming memory block list indicating information about specific memory blocks to be programmed when the temperature of the memory system falls within the temperature period.

[0012] The memory controller may program data in the status check page in response to determining that the temperature of the memory system has entered the temperature interval for the first time, such that there are no memory cells in the status check page that are in an erased state.

[0013] In another aspect, embodiments of the disclosed technology may provide a method for operating a memory system including a memory device.

[0014] A method of operating a memory system may include setting a status check memory block for checking a status of data stored in a memory block included in the first memory die, for a first memory die that is one of a plurality of memory dies included in a memory device.

[0015] In addition, a method for operating a memory system may include managing, for each of a plurality of predetermined temperature intervals, (1) a status check page corresponding to the temperature interval and included in a status check memory block, and (2) a programming memory block list indicating information about a specific memory block to be programmed when the temperature of the memory system falls within the temperature interval.

[0016] The management may include: determining whether the temperature of the memory system has entered the temperature interval for the first time; and programming data in a status check page so that there are no memory cells in an erased state in the status check page.

[0017] According to an embodiment of the disclosed technology, it is possible to quickly detect whether an error occurs in stored data under various temperature environments and to check in advance whether an error occurs in data programmed under specific temperature conditions, thereby preventing problems caused by reduced reliability due to temperature changes. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram showing the configuration of a memory system based on an embodiment of the disclosed technology.

[0019] Figure 2 is a block diagram schematically illustrating a memory device according to an embodiment of the disclosed technology.

[0020] Figure 3 is a diagram showing the structure of word lines and bit lines of a memory device based on an embodiment of the disclosed technology.

[0021] Figure 4 is a diagram showing a schematic structure of a memory system based on an embodiment of the disclosed technology.

[0022] Figure 5 is a diagram illustrating a status check memory block of a first memory die based on an embodiment of the disclosed technology.

[0023] Figure 6 is a diagram illustrating an operation of managing a status check page and a program memory block list for each of a plurality of temperature intervals based on an embodiment of the disclosed technology.

[0024] Figure 7 is a diagram illustrating operations performed by a memory system when the temperature of the memory system has initially entered a first temperature interval based on an embodiment of the disclosed technology.

[0025] Figure 8 is a diagram illustrating an example of an operation of programming data to a reference page based on an embodiment of the disclosed technology.

[0026] Fig. 9 is a diagram illustrating an operation of determining whether the temperature of a memory system has entered a first temperature interval for the first time based on an embodiment of the disclosed technology.

[0027] Fig.10 is a diagram illustrating an example of an operation of determining a location of a reference page based on an embodiment of the disclosed technology.

[0028] Fig.11 and Fig.12 is a diagram illustrating an example of an operation of managing a first program memory block list based on an embodiment of the disclosed technology.

[0029] Fig.13 is a diagram illustrating an example of an operation of reading data stored in a reference page based on an embodiment of the disclosed technology.

[0030] Fig.14 is a flowchart illustrating an example of an operation of determining whether to check a state of data stored in a memory block based on an embodiment of the disclosed technology.

[0031] Fig.15is a flowchart illustrating an example of an operation of determining whether to reprogram data stored in a memory block based on an embodiment of the disclosed technology.

[0032] Fig.16 is a diagram illustrating a method of operating a memory system based on an embodiment of the disclosed technology.

[0033] Fig.17 is a diagram illustrating an example of an operation of managing a status check page and programming a memory block list for each of a plurality of temperature intervals.

[0034] Fig.18 is a diagram showing the configuration of a computing system based on some embodiments of the disclosed technology. DETAILED DESCRIPTION

[0035] Hereinafter, examples of embodiments of the disclosed technology are described in detail with reference to the accompanying drawings.

[0036] Figure 1 is a diagram showing a schematic configuration of a memory system 100 based on an embodiment of the disclosed technology.

[0037] In some embodiments, the memory system 100 may include a memory device 110 configured to store data, and a memory controller 120 configured to control the memory device 110 .

[0038] The memory device 110 may include a plurality of memory blocks, each memory block including a plurality of memory cells for storing data. The memory device 110 may be configured to operate in response to a control signal received from the memory controller 120. The operation of the memory device 110 may include, for example, a read operation, a program operation (also referred to as a "write operation"), an erase operation, etc.

[0039] The memory cells in the memory device 110 are used to store data and can be arranged in a memory cell array. The memory cell array can be divided into storage blocks of memory cells, and each block includes different pages of memory cells. In a typical embodiment of a NAND flash memory device, a page of memory cells is the smallest memory unit that can be programmed or written, and data stored in the memory cells can be erased in units of blocks.

[0040] In some embodiments, the memory device 110 can be implemented as various types such as: double data rate synchronous dynamic random access memory (DDR SDRAM), fourth generation low power double data rate (LPDDR4) SDRAM, graphic double data rate (GDDR) SDRAM, low power DDR (LPDDR), Rambus dynamic random access memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), or spin transfer torque random access memory (STT-RAM).

[0041] The memory device 110 may be implemented in a three-dimensional array structure. Some embodiments of the disclosed technology may be applied to any type of flash memory device having a charge storage layer. In an embodiment, the charge storage layer may be formed of a conductive material, and such a charge storage layer may be referred to as a floating gate. In another embodiment, the charge storage layer may be formed of an insulating material, and such a flash memory device may be referred to as a charge trap flash memory (CTF).

[0042] The memory device 110 may be configured to receive a command and an address from the memory controller 120 to access a region of the memory cell array selected using the address. That is, the memory device 110 may perform an operation corresponding to the received command on a memory region of the memory device having a physical address corresponding to the address received from the memory controller 120.

[0043] In some embodiments, the memory device 110 may perform a programming operation, a read operation, an erase operation, etc. During a programming operation, the memory device 110 may write data to an area selected by an address. During a read operation, the memory device 110 may read data from a memory area selected by an address. During an erase operation, the memory device 110 may erase data stored in a memory area selected by an address.

[0044] The memory controller 120 may control write (program) operations, read operations, erase operations, and background operations performed on the memory device 110. The background operations may include, for example, operations implemented to optimize the overall performance of the memory device 110, such as garbage collection (GC) operations, wear leveling (WL) operations, and bad block management (BBM) operations.

[0045] The memory controller 120 may control the operation of the memory device 110 at the request of the host. Alternatively, when the memory controller 120 performs such background operation of the memory device, the memory controller 120 may control the operation of the memory device 110 even without a request from the host.

[0046] The memory controller 120 and the host may be separate devices. In some embodiments, the memory controller 120 and the host may be integrated and implemented as a single device. In the following description, as an example, the memory controller 120 and the host will be discussed as separate devices.

[0047] Reference Figure 1 , the memory controller 120 may include a memory interface 122 , a control circuit 123 , and a host interface 121 .

[0048] The host interface 121 may be configured to provide an interface for communicating with a host.

[0049] When receiving a command from the host HOST, the control circuit 123 may receive the command through the host interface 121 and may perform an operation of processing the received command.

[0050] The memory interface 122 may be directly or indirectly connected to the memory device 110 to provide an interface for communicating with the memory device 110. That is, the memory interface 122 may be configured to provide an interface to the memory device 110 and the memory controller 120 for the memory controller 120 to perform memory operations on the memory device 110 based on control signals and instructions from the control circuit 123.

[0051] The control circuit 123 may be configured to control the operation of the memory device 110 through the memory controller 120. For example, the control circuit 123 may include a processor 124 and a working memory 125. The control circuit 123 may further include an error detection / correction circuit (ECC circuit) 126 and the like.

[0052] The processor 124 may control the overall operation of the memory controller 120 . The processor 124 may perform logic operations. The processor 124 may communicate with the host HOST through the host interface 121 . The processor 124 may communicate with the memory device 110 through the memory interface 122 .

[0053] The processor 124 may be used to perform operations associated with a flash translation layer (FTL) to effectively manage memory operations on the memory system 100. The processor 124 may convert a logical block address (LBA) provided by the host into a physical block address (PBA) through the FTL. The FTL may receive the LBA and convert the LBA into the PBA by using a mapping table.

[0054] Based on the mapping unit, FTL can adopt a variety of address mapping methods. Typical address mapping methods may include page mapping method, block mapping method and hybrid mapping method.

[0055] The processor 124 may be configured to randomize the data received from the host to write the randomized data to the memory cell array. For example, the processor 124 may randomize the data received from the host by using a randomization seed. The randomized data is provided to the memory device 110 and written to the memory cell array.

[0056] The processor 124 may be configured to derandomize data received from the memory device 110 during a read operation. For example, the processor 124 may derandomize the data received from the memory device 110 by using a derandomization seed. The derandomized data may be output to the host HOST.

[0057] The processor 124 may execute firmware (FW) to control the operation of the memory controller 120. In other words, the processor 124 may control the overall operation of the memory controller 120, and may execute (drive) the firmware loaded into the working memory 125 during booting in order to perform logical operations.

[0058] Firmware refers to a program or software stored on some non-volatile memory and executed inside the memory system 100 .

[0059] In some embodiments, the firmware may include various functional layers. For example, the firmware may include at least one of a flash translation layer (FTL), a host interface layer (HIL), and a flash interface layer (FIL), wherein the flash translation layer (FTL) is configured to convert a logical address in a host HOST request into a physical address of the memory device 110, the host interface layer (HIL) is configured to interpret a command issued by the host HOST to a data storage device such as the memory system 100 and pass the command to the FTL, and the flash interface layer (FIL) is configured to pass the command issued by the FTL to the memory device 110.

[0060] For example, the firmware may be stored in the memory device 110 and then loaded into the working memory 125 .

[0061] The working memory 125 may store firmware, program code, commands, or pieces of data necessary to operate the memory controller 120. The working memory 125 may include, for example, at least one of static RAM (SRAM), dynamic RAM (DRAM), and synchronous RAM (SDRAM) as volatile memories.

[0062] Error detection / correction circuit 126 may be configured to detect and correct one or more erroneous bits in the data by using an error detection and correction code. In some embodiments, the data subject to error detection and correction may include data stored in working memory 125 and data retrieved from memory device 110.

[0063] The error detection / correction circuit 126 can be implemented to decode the data by using an error correction code. The error detection / correction circuit 126 can be implemented by using various decoding schemes. For example, a decoder that performs non-systematic code decoding or a decoder that performs systematic code decoding can be used.

[0064] In some embodiments, the error detection / correction circuit 126 can detect one or more error bits based on sectors. That is, each read data can include multiple sectors. In this patent document, a sector can refer to a data unit that is smaller than a read unit (e.g., a page) of a flash memory. The sectors that constitute each read data can be mapped based on addresses.

[0065] In some embodiments, the error detection / correction circuit 126 can calculate the bit error rate (BER) on a sector-by-sector basis and determine whether the number of error bits in the data is within the error correction capability. For example, if the BER is higher than a reference value, the error detection / correction circuit 126 can determine that the error bits in the corresponding sector are uncorrectable, and the corresponding sector is marked as "failed". If the BER is lower than or equal to the reference value, the error detection / correction circuit 126 can determine that the corresponding sector is correctable, or the corresponding sector can be marked as "passed".

[0066] The error detection / correction circuit 126 may sequentially perform error detection and correction operations on all read data. When a sector included in the read data is correctable, the error detection / correction circuit 126 may proceed to the next sector to check whether an error correction operation is required for the next sector. After completing the error detection and correction operations on all read data in this manner, the error detection / correction circuit 126 may obtain information about which sector in the read data is considered uncorrectable. The error detection / correction circuit 126 may provide such information (e.g., the address of the uncorrectable bit) to the processor 124.

[0067] The memory system 100 may further include a bus 127 to provide a channel between constituent elements 121, 122, 124, 125, and 126 of the memory controller 120. The bus 127 may include, for example, a control bus for transferring various types of control signals and commands and a data bus for transferring various types of data.

[0068] By way of example, Figure 1 The above-mentioned constituent elements 121, 122, 124, 125, and 126 of the memory controller 120 are shown. Note that some of the constituent elements shown in the drawings may be omitted, or some of the above-mentioned constituent elements 121, 122, 124, 125, and 126 of the memory controller 120 may be integrated into a single element. In addition, in some embodiments, one or more other constituent elements may be added to the above-mentioned constituent elements of the memory controller 120.

[0069] Figure 2 is a block diagram schematically illustrating a memory device 110 according to an embodiment of the disclosed technology.

[0070] In some implementations, a memory device 110 based on an embodiment of the disclosed technology may include a memory cell array 210 , an address decoder 220 , a read / write circuit 230 , a control logic 240 , and a voltage generation circuit 250 .

[0071] The memory cell array 210 may include a plurality of memory blocks BLK1 to BLKz, where z is a natural number equal to or greater than 2.

[0072] In the plurality of memory blocks BLK1 to BLKz, a plurality of word lines WL and a plurality of bit lines BL may be arranged in rows and columns, and a plurality of memory cells MC may be disposed.

[0073] The plurality of memory blocks BLK1 to BLKz may be connected to the address decoder 220 through a plurality of word lines WL. The plurality of memory blocks BLK1 to BLKz may be connected to the read / write circuit 230 through a plurality of bit lines BL.

[0074] Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. For example, the plurality of memory cells are nonvolatile memory cells. In some embodiments, such nonvolatile memory cells may be arranged in a vertical channel structure.

[0075] The memory cell array 210 may be configured as a memory cell array having a two-dimensional structure. In some embodiments, the memory cell array 210 may be arranged in a three-dimensional structure.

[0076] Each of the plurality of memory cells included in the memory cell array 210 may store at least one bit of data. For example, each of the plurality of memory cells included in the memory cell array 210 may be a single-level cell (SLC) configured to store one bit of data. For another example, each of the plurality of memory cells included in the memory cell array 210 may be a multi-level cell (MLC) configured to store two bits of data per memory cell. For another example, each of the plurality of memory cells included in the memory cell array 210 may be a triple-level cell (TLC) configured to store three bits of data per memory cell. For another example, each of the plurality of memory cells included in the memory cell array 210 may be a quad-level cell (QLC) configured to store four bits of data per memory cell. For another example, the memory cell array 210 may include a plurality of memory cells, and each of the plurality of memory cells may be configured to store at least five bits of data per memory cell.

[0077] Reference Figure 2 , the address decoder 220 , the read / write circuit 230 , the control logic 240 , and the voltage generating circuit 250 may operate as a peripheral circuit configured to drive the memory cell array 210 .

[0078] The address decoder 220 may be connected to the memory cell array 210 through a plurality of word lines WL.

[0079] The address decoder 220 may be configured to operate in response to commands and control signals from the control logic 240 .

[0080] The address decoder 220 may receive an address through an input / output buffer inside the memory device 110. The address decoder 220 may be configured to decode a block address among the received addresses. The address decoder 220 may select at least one memory block based on the decoded block address.

[0081] The address decoder 220 may receive a read voltage Vread and a pass voltage Vpass from the voltage generating circuit 250 .

[0082] During a read operation, the address decoder 220 may apply a read voltage Vread to a selected word line WL within a selected memory block, and may apply a pass voltage Vpass to the remaining unselected word lines WL.

[0083] During a program verification operation, the address decoder 220 may apply a verification voltage generated by the voltage generation circuit 250 to a selected word line WL within a selected memory block, and may apply a pass voltage Vpass to remaining unselected word lines WL.

[0084] The address decoder 220 may be configured to decode a column address among the received addresses. The address decoder 220 may transmit the decoded column address to the read / write circuit 230.

[0085] The memory device 110 may perform a read operation and a program operation on a page-by-page basis. An address received when requesting a read operation and a program operation may include at least one of a block address, a row address, and a column address.

[0086] The address decoder 220 may select a memory block and a word line based on the block address and the row address. The column address may be decoded by the address decoder 220 and provided to the read / write circuit 230.

[0087] The address decoder 220 may include at least one of a block decoder, a row decoder, a column decoder, and an address buffer.

[0088] The read / write circuit 230 may include a plurality of page buffers PB. When the memory cell array 210 performs a read operation, the read / write circuit 230 may operate as a “read circuit”, and when the memory cell array 210 performs a write operation, the read / write circuit 230 may operate as a “write circuit”.

[0089] The above-mentioned read / write circuit 230 is also called a page buffer circuit or a data register circuit, and the page buffer circuit includes a plurality of page buffers PB. The read / write circuit 230 may include a data buffer participating in a data processing function, and in some embodiments, may further include a cache buffer for data caching.

[0090] A plurality of page buffers PB may be connected to the memory cell array 210 through a plurality of bit lines BL. In order to detect or sense a threshold voltage Vth of a memory cell during a read operation and a program verification operation, the plurality of page buffers PB may continuously supply a sensing current to the bit lines BL connected to the memory cell to detect a change proportional to a current amount at a sensing node, wherein the current amount varies according to a programming state of the corresponding memory cell, and may hold or latch a corresponding voltage as sensing data.

[0091] The read / write circuit 230 may operate in response to a page buffer control signal output from the control logic 240 .

[0092] During a read operation, the read / write circuit 230 senses a voltage value of a memory cell and reads the voltage value as data. The read / write circuit 230 temporarily stores the retrieved data and outputs the data DATA to an input / output buffer of the memory device 110. In an embodiment, the read / write circuit 230 may further include a column selection circuit in addition to the page buffer PB or the page register.

[0093] The control logic 240 may be connected to the address decoder 220, the read / write circuit 230, and the voltage generating circuit 250. The control logic 240 may receive the command CMD and the control signal CTRL through the input / output buffer of the memory device 110.

[0094] The control logic 240 may be configured to control the overall operation of the memory device 110 in response to the control signal CTRL. The control logic 240 may output a control signal for adjusting the voltage level of the sensing nodes of the plurality of page buffers PB to a precharge voltage level.

[0095] The control logic 240 may control the read / write circuit 230 to perform a read operation in the memory cell array 210. The voltage generation circuit 250 may generate a read voltage Vread and a pass voltage Vpass used during a read operation in response to a voltage generation circuit control signal output from the control logic 240.

[0096] The memory block BLK included in the memory device 110 may include a plurality of pages PG. In some embodiments, a plurality of memory cells arranged in columns form a memory cell string, and a plurality of memory cells arranged in rows form a memory block. Each of the plurality of pages PG is connected to a word line WL, and each of the memory cell strings STR is connected to a bit line BL.

[0097] In the memory block BLK, a plurality of word lines WL and a plurality of bit lines BL may be arranged in rows and columns. For example, each of the plurality of word lines WL may be arranged in a row direction, and each of the plurality of bit lines BL may be arranged in a column direction. For another example, each of the plurality of word lines WL may be arranged in a column direction, and each of the plurality of bit lines BL may be arranged in a row direction.

[0098] In some embodiments, a plurality of word lines WL and a plurality of bit lines BL may intersect each other to address a single memory cell in an array of a plurality of memory cells MC. In some embodiments, each memory cell MC may include a transistor TR including a material layer that may hold a charge.

[0099] For example, the transistor TR arranged in each memory cell MC may include a drain, a source, and a gate. The drain (or source) of the transistor TR may be connected to the corresponding bit line BL directly or via another transistor TR. The source (or drain) of the transistor TR may be connected to a source line (which may be ground) directly or via another transistor TR. The gate of the transistor TR may include a floating gate (FG) surrounded by an insulator and a control gate (CG) to which a gate voltage is applied from a word line WL.

[0100] In each of the multiple storage blocks BLK1 to BLKz, a first selection line (also called a source selection line or a drain selection line) may be additionally arranged on the outside of a first outermost word line among the two outermost word lines that is closer to the read / write circuit 230, and a second selection line (also called a drain selection line or a source selection line) may be additionally arranged on the outside of the other second outermost word line.

[0101] In some embodiments, at least one dummy word line may be additionally disposed between the first outermost word line and the first selection line. In addition, at least one dummy word line may be additionally disposed between the second outermost word line and the second selection line.

[0102] A read operation and a program operation (write operation) of a memory block may be performed page by page, and an erase operation may be performed memory block by memory block.

[0103] Figure 3 is a diagram showing the structure of word lines WL and bit lines BL of a memory device 110 based on an embodiment of the disclosed technology.

[0104] Reference Figure 3 , the memory device 110 has a core region where memory cells MC are arranged and an auxiliary region (the remaining region except the core region) including a circuit for performing an operation of the memory cell array 210 .

[0105] In the core region, a certain number of memory cells arranged in one direction may be referred to as a “page” PG, and a certain number of memory cells connected in series may be referred to as a “memory cell string” STR.

[0106] The word lines WL1 to WL9 may be connected to the row decoder 310. The bit lines BL may be connected to the column decoder 320. Figure 2 A data register 330 corresponding to the read / write circuit 230 may exist between the plurality of bit lines BL and the column decoder 320 .

[0107] The plurality of word lines WL1 to WL9 may correspond to a plurality of pages PG.

[0108] For example, Figure 3As shown, each of the plurality of word lines WL1 to WL9 may correspond to one page PG. When each of the plurality of word lines WL1 to WL9 has a large size, each of the plurality of word lines WL1 to WL9 may correspond to at least two (e.g., two or four) page PGs. Each page PG is the minimum unit in a programming operation and a reading operation, and when performing a programming operation and a reading operation, all memory cells MC within the same page PG may perform the operation simultaneously.

[0109] The plurality of bit lines BL may be connected to the column decoder 320 . In some embodiments, the plurality of bit lines BL may be divided into odd-numbered bit lines BL and even-numbered bit lines BL such that a pair of odd-numbered bit lines and even-numbered bit lines are commonly coupled to the column decoder 320 .

[0110] When accessing the memory cell MC, the row decoder 310 and the column decoder 320 are used to locate a desired memory cell based on an address.

[0111] In some embodiments, the data register 330 plays an important role because all data processing performed by the memory device 110, including programming operations and read operations, occurs via the data register 330. If the data processing performed by the data register 330 is delayed, all other areas need to wait until the data register 330 completes the data processing, which reduces the overall performance of the memory device 110.

[0112] Reference Figure 3 In the example shown, in one memory cell string STR, a plurality of transistors TR1 to TR9 may be connected to a plurality of word lines WL1 to WL9, respectively. In some embodiments, the plurality of transistors TR1 to TR9 correspond to memory cells MC. In this example, the plurality of transistors TR1 to TR9 include a control gate CG and a floating gate FG.

[0113] The plurality of word lines WL1 to WL9 include two outermost word lines WL1 and WL9. A first selection line DSL may be additionally disposed outside the first outermost word line WL1, which is closer to the data register 330 and has a shorter signal path than the other outermost word line WL9. A second selection line SSL may be additionally disposed outside the other outermost word line WL9.

[0114] The first selection transistor D-TR controlled to be turned on / off by the first selection line DSL has a gate electrode connected to the first selection line DSL but does not include a floating gate FG. The second selection transistor S-TR controlled to be turned on / off by the second selection line SSL has a gate electrode connected to the second selection line SSL but also does not include a floating gate FG.

[0115] The first selection transistor D-TR is used as a switch circuit that connects the corresponding memory cell string STR to the data register 330. The second selection transistor S-TR is used as a switch circuit that connects the corresponding memory cell string STR to the source line SL. That is, the first selection transistor D-TR and the second selection transistor S-TR can be used to enable or disable the corresponding memory cell string STR.

[0116] In some embodiments, the memory system 100 applies a predetermined turn-on voltage Vcc to the gate electrode of the first selection transistor D-TR, thereby turning on the first selection transistor D-TR, and applies a predetermined turn-off voltage (e.g., 0V) to the gate electrode of the second selection transistor S-TR, thereby turning off the second selection transistor S-TR.

[0117] During a read operation or a verification operation, the memory system 100 turns on both the first selection transistor D-TR and the second selection transistor S-TR. Therefore, during a read operation or a verification operation, a current may flow through the corresponding memory cell string STR and to the source line SL corresponding to the ground, so that the voltage level of the bit line BL can be measured. However, during a read operation, there may be a time difference in the turn-on / off timing between the first selection transistor D-TR and the second selection transistor S-TR.

[0118] During the erase operation, the memory system 100 may apply a predetermined voltage (e.g., +20V) to the substrate through the source line SL. During the erase operation, the memory system 100 applies a specific voltage to allow both the first selection transistor D-TR and the second selection transistor S-TR to float. Thus, the applied erase voltage may remove charge from the floating gate FG of the selected memory cell.

[0119] Figure 4 is a diagram showing a schematic structure of a memory system 100 based on an embodiment of the disclosed technology.

[0120] Reference Figure 4 , the memory system 100 may include a memory device 110 and a memory controller 120. The memory device 110 of the memory system 100 may include a plurality of memory dies DIE. Each of the plurality of memory dies DIE may include a plurality of memory blocks BLK.

[0121] The memory controller 120 of the memory system 100 may request the memory device 110 to program data to a memory block BLK included in any one of a plurality of memory dies DIE included in the memory device 110 .

[0122] The first memory die DIE_1 as one example of the plurality of memory dies DIE will be described in more detail.

[0123] Figure 5 is a diagram illustrating a status check memory block SC_BLK of a first memory die DIE_1 based on an embodiment of the disclosed technology.

[0124] Reference Figure 5 , the memory controller 120 of the memory system 100 may select or set the status check memory block SC_BLK for the first memory die DIE_1 among the plurality of memory dies DIE included in the memory device 110 .

[0125] The status check memory block SC_BLK is a memory block for checking the status of data stored in the memory block BLK included in the first memory die DIE_1. For example, the status check memory block SC_BLK can check whether an error occurs in the data stored in the memory block BLK included in the first memory die DIE_1. The memory controller 120 can select the status check memory block SC_BLK as one of the memory blocks BLK included in the first memory die DIE_1.

[0126] The following section describes the reason why the memory controller 120 of the memory system 100 checks the status of data stored in the memory block BLK included in the first memory die DIE_1 using the separate status check memory block SC_BLK.

[0127] The retention time that the memory system 100 retains data without error may be determined by various factors, such as environmental and other factors (e.g., temperature, power-on time, etc.). During operation of the memory system, one or more of these factors may change. For example, the memory system 100 may not always be in a powered-on state or the temperature of the memory system 100 may change over time. It may be difficult for the memory system 100 to capture and reflect such changes in real time.

[0128] Therefore, the memory system 100 can determine the state of the data stored in the memory device 110 by actually reading the data stored in the memory device. In this case, the memory system 100 may need to determine from which memory block BLK among the memory blocks included in the memory device 110 the data is to be read. The memory system 100 can check the possibility of an error occurring in the data stored in each memory block in the memory device 110, and select a memory block with a higher possibility of an error occurring among the memory blocks BLK included in the memory device 110. Determining the state of the data stored in the memory device 110 by using a memory block with a higher possibility of an error occurring can allow the memory system 100 to detect the occurrence of an error more quickly.

[0129] In order to check the state of data included in the first memory die DIE_1 of the memory device 110 , the memory system 100 may first determine from which memory block BLK data is to be read by using the state check memory block SC_BLK.

[0130] In some embodiments, the memory controller 120 may use the status check memory block SC_BLK included in the first memory die DIE_1 for other memory dies in the memory device 110. In some other embodiments, the memory controller 120 may set a separate status check memory block for each memory die DIE of the memory dies in the memory device 110.

[0131] In some embodiments, when a specific condition is met, the memory controller 120 may change the status check memory block SC_BLK to another memory block included in the first memory die DIE_1 for the first memory die DIE_1. For example, when the erase / program count of the current status check memory block SC_BLK increases to be equal to or greater than a predetermined threshold count value, the memory controller 120 may change the status check memory block SC_BLK to another memory block included in the first memory die DIE_1. The memory controller 120 may avoid or reduce degradation of the status check memory block SC_BLK that occurs due to repeated erase operations / program operations.

[0132] Hereinafter, an example of a detailed method is described to explain how the memory system 100 checks the state of data stored in the first memory die DIE_1 based on the state check storage block SC_BLK and the additional data structure of the first memory die DIE_1.

[0133] Figure 6 is a diagram illustrating an operation of the memory system 100 based on an embodiment of the disclosed technology to manage a status check page SC_PG and a program memory block list PGM_BLK_LIST for each of a plurality of temperature zones TP.

[0134] Reference Figure 6 , the memory controller 120 of the memory system 100 may check which temperature interval TP the temperature of the memory system 100 falls into among the set multiple temperature intervals TP. Information about the multiple temperature intervals TP may be set in advance during the manufacturing process of the memory system 100 or stored as separate setting information. The number of the multiple temperature intervals TP and the range of each temperature interval TP may be arbitrarily determined.

[0135] In some embodiments, the temperature of memory system 100 may be determined as an average of temperatures measured at a plurality of memory die DIEs, respectively. In some other embodiments, the temperature of memory system 100 may be determined as a temperature of a specific module or region included in memory system 100.

[0136] In some embodiments, memory system 100 can use at least one temperature sensor to measure the temperature of memory system 100 .

[0137] For each of a plurality of temperature sections TP set in advance, the memory controller 120 may manage a status check page SC_PG corresponding to the temperature section TP. The status check page SC_PG may be included in the above referenced Figure 5 The status check described is stored in the SC_BLK block. Figure 6 The status checking memory block SC_BLK includes a plurality of status checking pages SC_PG corresponding to the temperature intervals TP, respectively. The status checking pages SC_PG may be used to check the status of data stored in the first memory die DIE_1 in the temperature interval TP corresponding to the corresponding status checking page SC_PG.

[0138] In some embodiments, for each of a plurality of temperature intervals TP set in advance, the memory controller 120 may manage a program memory block list PGM_BLK_LIST indicating information on memory blocks programmed with data when the temperature of the memory system 100 falls within the corresponding temperature interval TP.

[0139] The program memory block list PGM_BLK_LIST may indicate which memory blocks data is programmed into among the memory blocks included in the first memory die DIE_1 when the temperature of the memory system 100 falls within the temperature interval TP corresponding to the corresponding program memory block list PGM_BLK_LIST. The memory controller 120 may sequentially access information about the memory blocks stored in the program memory block list PGM_BLK_LIST according to the arrangement order of the information.

[0140] In some embodiments, the program memory block list PGM_BLK_LIST may be implemented by various data structures such as: a linked list, a circular list, an array, and the like.

[0141] Figure 7 TP1 is a diagram illustrating an example of an operation performed by the memory system 100 when the temperature of the memory system 100 has initially entered the first temperature interval TP1 according to an embodiment of the disclosed technology.

[0142] Reference Figure 7When it is determined that the temperature of the memory system 100 has initially entered the first temperature interval TP1 among multiple temperature intervals TP, the memory controller 120 of the memory system 100 can program data to a reference page REF_PG, which is a status check page corresponding to the first temperature interval TP1 and is included in the status check storage block SC_BLK of the first memory die DIE_1.

[0143] The reference page REF_PG is a status check page for determining the status of a memory block programmed with data when the temperature of the memory system 100 falls within the first temperature interval TP1.

[0144] Hereinafter, a detailed method in which the memory system 100 programs data to the above-mentioned reference page REF_PG will be described.

[0145] Figure 8 is a diagram illustrating an example of an operation of programming data to a reference page REF_PG based on an embodiment of the disclosed technology.

[0146] Reference Figure 8 When programming data to the reference page REF_PG, the memory controller 120 of the memory system 100 may program data to the reference page REF_PG so that there are no memory cells in the erased state among the memory cells corresponding to the reference page REF_PG. Therefore, when no error occurs in the memory cells of the reference page REF_PG, the number of memory cells in the erased state is zero.

[0147] The status check memory block SC_BLK includes a plurality of memory cells, and some of the plurality of memory cells may correspond to the reference page REF_PG. Depending on the type of memory cells included in the status check memory block SC_BLK, the number of memory cells corresponding to the reference page REF_PG may vary. For example, when the storage capacity of the reference page REF_PG is 4KB and the type of each memory cell included in the status check memory block SC_BLK is SLC, the number of memory cells corresponding to the reference page REF_PG may be 4K*8 / 1=32K. In another example, when the storage capacity of the reference page REF_PG is 4KB and the type of each memory cell included in the status check memory block SC_BLK is QLC, the number of memory cells corresponding to the reference page REF_PG may be 4K*8 / 4=8K.

[0148] Before the memory controller 120 programs data to the reference page REF_PG, all memory cells corresponding to the reference page REF_PG are in an erased state. When programming data to the reference page REF_PG, in order to ensure that there are no memory cells in an erased state among the memory cells corresponding to the reference page REF_PG, the memory controller 120 may set the data to be programmed to the reference page REF_PG so that the data to be stored in each memory cell has a specific value (e.g., 110 or 010) other than a value indicating an erased state (e.g., 111).

[0149] Programming data to memory cells corresponding to the reference page REF_PG may be implemented in other ways.In some implementations, the memory controller 120 may program data having the same value to all memory cells corresponding to the reference page REF_PG.

[0150] Hereinafter, a method for determining whether the temperature of the memory system 100 has initially entered the first temperature interval TP1 will be described.

[0151] Fig. 9 is a diagram illustrating an operation of determining whether the temperature of the memory system 100 has initially entered the first temperature interval TP1 based on some embodiments of the disclosed technology.

[0152] Reference Fig. 9 , the memory controller 120 of the memory system 100 may determine whether the temperature of the memory system 100 has initially entered the first temperature interval TP1 based on the value of the bit indicating whether the reference page REF_PG has been generated.

[0153] exist Fig. 9 In the embodiment, for each temperature interval TP, the memory controller 120 can manage a corresponding bit indicating whether the temperature of the memory system 100 has ever entered each temperature interval TP. When the corresponding bit has a first value (e.g., 0), the corresponding bit indicates that the temperature of the memory system 100 has never entered the specific temperature interval TP corresponding to the corresponding bit. When the corresponding bit has a second value (e.g., 1), the corresponding bit indicates that the temperature of the memory system 100 has entered the temperature interval TP corresponding to the corresponding bit.

[0154] In this case, when the temperature of the memory system 100 enters the first temperature interval TP1, if the bit corresponding to the first temperature interval TP1 has a first value, the memory controller 120 determines that the temperature of the memory system 100 has initially entered the first temperature interval TP1. If the bit corresponding to the first temperature interval TP1 has a second value, the memory controller 120 determines that the temperature of the memory system 100 has previously entered the first temperature interval TP1.

[0155] When the temperature of the memory system 100 enters a specific temperature interval TP among the multiple temperature intervals TP, the memory controller 120 may change the value of the corresponding bit of the specific temperature interval TP from the first value to the second value. The change of the bit corresponding to the specific temperature interval TP from the first value to the second value may be used as a record that the temperature of the memory system 100 has entered the corresponding temperature interval TP for the first time. As described above, upon determining that the temperature of the memory system 100 has entered the specific temperature interval for the first time, the memory system 100 programs data to the memory cells included in the status check page corresponding to the specific temperature interval.

[0156] Next, a method in which the memory system 100 determines the location of the reference page REF_PG in the status check memory block SC_BLK will be described.

[0157] Fig.10 is a diagram illustrating an example of an operation of the memory system 100 determining a location of a reference page REF_PG based on an embodiment of the disclosed technology.

[0158] Reference Fig.10 , the memory controller 120 of the memory system 100 can determine the reference page REF_PG based on the information indicating the position of the status check page to be assigned to any one of the multiple temperature intervals TP in the status check memory block SC_BLK. For example, the memory controller 120 can obtain the information by searching for a page that has not been assigned to any one of the multiple temperature intervals TP in the status check memory block SC_BLK. For another example, the memory controller 120 can obtain the information by searching for a page that 1) has not been assigned to any one of the multiple temperature intervals TP and 2) is adjacent to the status check page corresponding to the temperature interval to which the temperature of the memory system 100 currently belongs.

[0159] Each of the status check pages included in the status check memory block SC_BLK may be a status check page that has been assigned to any one of the multiple temperature intervals TP or a status check page that has not been assigned to any one of the multiple temperature intervals TP. When the temperature of the memory system 100 first enters the first temperature interval TP1, the memory controller 120 may select a status check page to be assigned to the first temperature interval TP1 from among each status check page that has not been assigned to any one of the multiple temperature intervals TP.

[0160] To this end, the memory controller 120 can determine the position of the reference page REF_PG based on the information indicating the position of the status check page included in the status check memory block SC_BLK and to be allocated to any one of the multiple temperature intervals TP next, and can determine the reference page REF_PG at the corresponding position. Therefore, the reference page REF_PG located at the corresponding position becomes the status check page corresponding to the first temperature interval TP1.

[0161] Because the reference page REF_PG has been allocated to the first temperature zone TP1, the memory controller 120 may update information indicating the location of the status check page to be allocated next to any one of the plurality of temperature zones TP. The updated information indicates one or more status check pages that have not yet been allocated to any one of the plurality of temperature zones TP.

[0162] Hereinabove, the reference page REF_PG as the status check page corresponding to the first temperature zone TP1 has been described.

[0163] Hereinafter, a method of managing the first program memory block list PGM_BLK_LIST1 will be explained. The first program memory block list PGM_BLK_LIST1 refers to Figure 6 The program memory block list PGM_BLK_LIST shown in FIG. 1 and corresponding to the first temperature zone TP1 is a program memory block list PGM_BLK_LIST.

[0164] Fig.11 and Fig.12 is a diagram illustrating an example of an operation of managing a first program memory block list PGM_BLK_LIST1 which is a program memory block list PGM_BLK_LIST corresponding to a first temperature zone TP1 based on an embodiment of the disclosed technology.

[0165] Reference Fig.11 , when the temperature of the memory system 100 falls within the first temperature interval TP1, the first program memory block list PGM_BLK_LIST1 includes information on the memory blocks BLK programmed with data.

[0166] When the temperature of the memory system 100 falls within the first temperature interval TP1, among the memory blocks BLK programmed with data, there may be memory blocks storing valid data, and there may be memory blocks not storing valid data. For example, if valid data is programmed into any memory block when the temperature of the memory system 100 falls within the first temperature interval TP1, and then an erase operation or a garbage collection operation is performed on the corresponding memory block, then valid data may no longer exist in the corresponding memory block.

[0167] The memory controller 120 of the memory system 100 may remove information about a memory block that does not store valid data from the first program memory block list PGM_BLK_LIST1 because there is no need to correct an error occurring in invalid data.

[0168] Reference Fig.12 , when the temperature of the memory system 100 falls within the first temperature interval TP1, the first program memory block list PGM_BLK_LIST1 includes information on the memory blocks BLK programmed with valid data among the memory blocks BLK programmed with data.

[0169] The memory controller 120 of the memory system 100 may rearrange the information on the memory blocks BLK included in the first program memory block list PGM_BLK_LIST1 according to the value of the erase / program count EW_CNT of each memory block BLK. Fig.12 , as an example, an operation of the memory controller 120 to rearrange the information on the memory blocks BLK included in the first program memory block list PGM_BLK_LIST1 in descending order relative to the value of the erase / program count EW_CNT will be described. The erase / program count corresponds to the number of times an erase operation or a program operation is performed on a memory block.

[0170] For example, assume that the first program memory block list PGM_BLK_LIST1 includes information on memory blocks having erase / program counts EW_CNT of 10, 30, 20, and 15, respectively.

[0171] The memory controller 120 can rearrange the information about the memory block BLK included in the first programming memory block list PGM_BLK_LIST1 so that the information about the memory block BLK whose erase / program count EW_CNT is a maximum value of 30 is located first, the information about the memory block BLK whose erase / program count EW_CNT value is 20 is located second, the information about the memory block BLK whose erase / program count EW_CNT value is 15 is located third, and the information about the memory block BLK whose erase / program count EW_CNT value is 10 is located last.

[0172] Hereinafter, the memory controller 120 may check the state of the memory block BLK indicated by the first programming memory block list PGM_BLK_LIST1 according to the arrangement order of the plurality of pieces of information about the memory block BLK. The memory controller 120 may first check the state of the memory block BLK whose erase / program count EW_CNT is a maximum value of 30, then check the state of the memory block BLK whose erase / program count EW_CNT value is 20, then check the state of the memory block BLK whose erase / program count EW_CNT value is 15, and then check the state of the memory block BLK whose erase / program count EW_CNT value is 10.

[0173] In some embodiments, as described above Fig.12 Unlike the rearrangement method described, the memory controller 120 rearranges the information on the memory blocks BLK included in the first program memory block list PGM_BLK_LIST1 in ascending order with respect to the value of the erase / program count EW_CNT.

[0174] Hereinabove, the method of managing the reference page REF_PG and the first program memory block list PGM_BLK_LIST1 has been described.

[0175] Hereinafter, a method of checking a state of data stored in a memory block BLK included in the first memory die DIE_1 when the temperature of the memory system 100 falls within the first temperature interval TP1 will be described.

[0176] Fig.13 is a diagram illustrating an example of an operation of the memory system 10 reading data stored in the reference page REF_PG based on an embodiment of the disclosed technology.

[0177] Reference Fig.13 When the temperature of the memory system 100 falls within the first temperature interval TP1, in order to check the state of data stored in the memory block included in the first memory die DIE_1, the memory controller 120 of the memory system 100 can read the data stored in the reference page REF_PG included in the status check memory block SC_BLK.

[0178] As described above, the data stored in the reference page REF_PG is the data programmed when the temperature of the memory system 100 first enters the first temperature interval TP1. In some embodiments, based on the state of the data stored in the reference page REF_PG, when the temperature of the memory system 100 is in the first temperature interval TP1, the memory controller 120 can predict the overall state of the data programmed to the first memory die DIE_1.

[0179] Fig.14is a flowchart illustrating an example of an operation of determining whether to check a state of data stored in a memory block based on an embodiment of the disclosed technology.

[0180] Reference Fig.14 , the memory controller 120 of the memory system 100 may read data stored in the reference page REF_PG ( S1410 ).

[0181] In operation S1410, data stored in the reference page REF_PG is read. Based on the result of reading the data stored in the reference page REF_PG in operation S1410, the memory controller 120 determines the number of memory cells in the erased state and corresponding to the reference page REF_PG (S1420). For example, by dividing the data read in operation S1410 into data units corresponding to the memory cells, and then counting the number of data units each having a value corresponding to the erased state among the data units, the memory controller 120 can determine the number of memory cells in the erased state.

[0182] The memory controller 120 determines whether the number of memory cells in the erase state is equal to or greater than a preset threshold count (S1430).

[0183] When the number of memory cells in the erased state is equal to or greater than the preset threshold count (S1430-Y), the memory controller 120 may check the state of data stored in the memory block indicated by the first program memory block list PGM_BLK_LIST1 which is the program memory block list PGM_BLK_LIST corresponding to the first temperature zone TP1 (S1440). The fact that the memory block is indicated by the first program memory block list PGM_BLK_LIST1 means that information indicating the corresponding memory block is included in the first program memory block list PGM_BLK_LIST1.

[0184] On the other hand, when the number of memory cells in the erased state is less than the preset threshold count (S1430-N), the memory controller 120 may not perform an operation of checking the state of data stored in a memory block whose information is indicated by the first program memory block list PGM_BLK_LIST1.

[0185] When the temperature of the memory system 100 is in the first temperature interval TP1, the memory controller 120 programs data to the reference page REF_PG so that there is no memory cell in an erased state among the memory cells corresponding to the reference page REF_PG. Therefore, the fact that a memory cell in an erased state is detected among the memory cells corresponding to the reference page REF_PG indicates that an error occurs in the data programmed to the first memory die DIE_1 in the first temperature interval TP1.

[0186] If the number of memory cells in the erased state among the memory cells corresponding to the reference page REF_PG is equal to or greater than the threshold count, it can also be considered that the possibility of error in the data programmed to the first memory die DIE_1 is high when the temperature of the memory system 100 falls within the first temperature interval TP1. Therefore, by checking the state of the data programmed to the first memory die DIE_1, when the temperature of the memory system 100 falls within the first temperature interval TP1, the memory controller 120 can prevent the problem of reduced reliability of the data programmed to the first memory die DIE_1 due to a change in the temperature of the memory system 100.

[0187] Fig.15 is a flowchart illustrating an example of an operation of determining whether to reprogram data stored in a memory block based on an embodiment of the disclosed technology.

[0188] Reference Fig.15 , the memory controller 120 of the memory system 100 reads data stored in a memory block indicated by the first program memory block list PGM_BLK_LIST1 which is a program memory block list PGM_BLK_LIST corresponding to the first temperature zone TP1 ( S1510 ).

[0189] Based on the data read in operation S1510, the memory controller 120 determines whether the number of error bits detected in the memory block indicated by the first program memory block list PGM_BLK_LIST1 corresponding to the first temperature zone TP1 is equal to or greater than a preset threshold error bit number (S1520). The number of error bits of the UECC may also be included in the number of error bits detected.

[0190] When the number of detected error bits is equal to or greater than the preset threshold error bit number (S1520-Yes), the memory controller 120 may reprogram the data programmed to the memory block indicated by the first program memory block list PGM_BLK_LIST1 (S1530). For example, in order to execute the reprogramming operation, the memory controller 120 may execute garbage collection on the memory block indicated by the first program memory block list PGM_BLK_LIST1 corresponding to the first temperature zone TP1.

[0191] On the other hand, when the number of detected error bits is less than the preset threshold error bit number ( S1520 -N), the memory controller 120 may omit the operation of reprogramming data programmed to the memory block indicated by the first program memory block list PGM_BLK_LIST1.

[0192] Fig.16 is a diagram illustrating a method of operating a memory system 100 based on an embodiment of the disclosed technology.

[0193] Reference Fig.16 , for a first memory die DIE_1 among a plurality of memory die DIE included in a memory device 110, an operating method of a memory system 100 may include operation S1610: setting a status check memory block SC_BLK among a plurality of memory blocks BLK included in the first memory die DIE_1 as a memory block for checking a status of data stored in a memory block BLK included in the first memory die DIE_1.

[0194] In addition, the operating method of the memory system 100 may include operation S1620: for each of the set multiple temperature intervals TP, managing the status check page SC_PG corresponding to each temperature interval TP in the status check storage block SC_BLK and the programming storage block list PGM_BLK_LIST, the programming storage block list PGM_BLK_LIST indicating information about the storage block BLK programmed with data when the temperature of the memory system 100 falls within each temperature interval TP.

[0195] Fig.17 is a diagram illustrating an example of operation S1620 of managing a status check page and programming a memory block list for each of a plurality of temperature intervals.

[0196] Reference Fig.17 Operation S1620 of managing a status check page and a program memory block list for each of a plurality of temperature intervals may include operation S1710 of determining whether the temperature of the memory system 100 has initially entered a first temperature interval TP1 among the plurality of temperature intervals TP.

[0197] Moreover, the operation S1620 of managing the status check page and the program memory block list for each of the plurality of temperature intervals may include an operation S1720 of programming the data in a reference page REF_PG as a status check page corresponding to the first temperature interval TP1 in the status check memory block SC_BLK in order to check the status of the memory block programmed with the data when the temperature of the memory system 100 falls within the first temperature interval TP1. At this time, the data is programmed so that there is no memory cell in an erased state among the memory cells corresponding to the reference page REF_PG.

[0198] Operation S1710 of determining whether the temperature of the memory system 100 has initially entered the first temperature interval TP1 among the plurality of temperature intervals TP may determine whether the temperature of the memory system 100 has initially entered the first temperature interval TP1 , for example, based on the value of a bit indicating whether the reference page REF_PG has been generated.

[0199] For example, the reference page REF_PG in the status checking memory block SC_BLK may be determined based on information indicating a location of a status checking page to be allocated next to any one of the plurality of temperature zones TP in the status checking memory block SC_BLK.

[0200] In addition to operations S1710 and S1720, operation S1620 of managing the status check page and the program memory block list for each of the plurality of temperature intervals may further include the following operation: removing information about the memory blocks that do not store valid data from the first program memory block list PGM_BLK_LIST1 that is the program memory block list PGM_BLK_LIST corresponding to the first temperature interval TP1. In this case, operation S1620 may further include the following operation: rearranging the information about the memory blocks included in the first program memory block list PGM_BLK_LIST1 according to the value of the erase / program count of each memory block.

[0201] In some embodiments, operation S1620 of managing a status check page and a programming storage block list for each of a plurality of temperature intervals may further include the following operations: when the temperature of the memory system 100 falls within the first temperature interval TP1, in order to check the status of the data stored in the storage block included in the first memory die DIE_1, the data stored in the reference page REF_PG in the status check storage block SC_BLK is read.

[0202] Operation S1620 may further include the following operation: when it is determined that the number of memory cells in the erased state among the memory cells corresponding to the reference page REF_PG is equal to or greater than the preset threshold count, checking the state of data stored in the memory block indicated by the first programming memory block list PGM_BLK_LIST1 which is the programming memory block list PGM_BLK_LIST corresponding to the first temperature interval TP1.

[0203] Operation S1620 may further include an operation of reprogramming data programmed into a memory block indicated by the first program memory block list PGM_BLK_LIST1 when the number of error bits detected in the memory block indicated by the first program memory block list PGM_BLK_LIST1 is equal to or greater than a threshold error bit number.

[0204] Fig.18 is a diagram showing a configuration of a computing system 1800 based on an embodiment of the disclosed technology.

[0205] Reference Fig.18 , a computing system 1800 based on an embodiment of the disclosed technology may include: a memory system 100, electrically connected to a system bus 1860; a CPU 1810, configured to control the overall operation of the computing system 1800; a RAM 1820, configured to store data and information related to the operation of the computing system 1800; a user interface / user experience (UI / UX) module 1830, configured to provide a user environment to a user; a communication module 1840, configured to communicate with an external device in a wired and / or wireless type; and a power management module 1850, configured to manage the power used by the computing system 1800.

[0206] The computing system 1800 may be a personal computer (PC) or may include a mobile terminal such as a smart phone, a tablet computer, or various electronic devices.

[0207] The computing system 1800 may further include a battery for supplying an operating voltage, and may further include an application chipset, a graphics-related module, a camera image processor, and a DRAM. Other elements will be apparent to those skilled in the art.

[0208] The memory system 100 may include not only a device configured to store data in a disk, such as a hard disk drive (HDD), but also a device configured to store data in a non-volatile memory, such as a solid state drive (SSD), a universal flash memory device, or an embedded MMC (eMMC) device. The non-volatile memory may include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc. In addition, the memory system 100 may be implemented as various types of storage devices and installed inside various electronic devices.

[0209] Based on the embodiments of the disclosed technology, the operation delay time of the memory system can be advantageously reduced or minimized. In addition, based on the embodiments of the disclosed technology, the overhead caused in the process of calling a specific function can be advantageously reduced or minimized.

[0210] Although various embodiments of the disclosed technology have been described with specific details and variations for illustrative purposes, various modifications, additions, and substitutions to the disclosed embodiments and other embodiments are possible based on what is disclosed or shown in this patent document.

Claims

1. A memory system, comprising: A memory device including a plurality of memory dies, each memory die including a plurality of memory blocks storing data; as well as a memory controller coupled to communicate with the memory device, control the memory device, and check which temperature interval the memory system falls into among a plurality of temperature intervals, the plurality of temperature intervals being predetermined and including a first temperature interval and a second temperature interval, wherein the memory controller selects a status check memory block for a first memory die included in the plurality of memory dies based on a probability of an error occurring in data stored in a memory block included in the first memory die, the status check memory block having a greater probability of an error occurring than other memory blocks in the first memory die, the status check memory block including a status check page, the status check page including a first status check page and a second status check page corresponding to the first temperature interval and the second temperature interval, respectively, wherein the memory controller further determines that the memory system falls within the first temperature interval, and in response to the determination, programs second data into the first status check page corresponding to the first temperature interval among the plurality of temperature intervals, wherein the memory controller accesses information about memory blocks stored in a programming memory block list, the programming memory block list being a linked list indicating which memory blocks among memory blocks included in the first memory die the data is to be programmed into when the temperature of the memory system falls within the first temperature interval, and The memory controller sequentially accesses information on the memory blocks arranged in the programming memory block list according to the order in which the information is arranged.

2. The memory system of claim 1 , wherein the determining determines that the temperature of the memory system has initially entered the first temperature interval, and the second data is programmed in the first status check page, and there are no memory cells in an erased state in the first status check page. 3 . The memory system of claim 2 , wherein the memory controller further determines whether the temperature of the memory system has entered the first temperature interval based on a value of a bit indicating whether the first status check page has been generated. 4 . The memory system of claim 2 , wherein the memory controller further determines the status check page included in the status check memory block based on information indicating a location of another status check page to be allocated to another temperature interval among the plurality of temperature intervals. 5 . The memory system of claim 2 , wherein the memory controller further removes information about memory blocks that do not store valid data from the program memory block list. 6 . The memory system of claim 5 , wherein the memory controller further rearranges the information on the specific memory block included in the program memory block list according to a count value that an erase operation or a program operation has been performed on each memory block.

7. The memory system according to claim 2, wherein the memory controller further reads the second data stored in the first status check page in the status check storage block to determine the status of the specific storage block when the temperature of the memory system falls within the first temperature range.

8. The memory system of claim 7, wherein the memory controller further checks data stored in the specific memory block indicated by the programming memory block list if the status check memory block includes a number of memory cells in an erased state equal to or greater than a preset threshold count.

9. The memory system of claim 8, wherein the memory controller further reprograms data programmed into the specific memory block indicated by the programmed memory block list when the number of error bits detected in the specific memory block is equal to or greater than a threshold number.

10. A method of operating a memory system, the memory system comprising a memory device, the method comprising: Based on the probability of an error occurring in data stored in a memory block included in a first memory die that is one of a plurality of memory dies included in the memory device, selecting a status check memory block for the first memory die, the status check memory block having a greater probability of an error occurring than other memory blocks in the first memory die, the status check memory block including status check pages corresponding to a plurality of temperature intervals, the status check pages including a first status check page and a second status check page corresponding to a first temperature interval and a second temperature interval included in the plurality of temperature intervals, respectively, each memory die including a plurality of memory blocks storing the data; determining that the memory system falls within the first temperature interval, and in response to the determination, programming second data into the first status check page corresponding to the first temperature interval among the plurality of temperature intervals, and accessing information about memory blocks stored in a programming memory block list, the programming memory block list being a linked list indicating which memory blocks among memory blocks included in the first memory die the data is to be programmed into when the temperature of the memory system falls within the first temperature interval, The information on the memory blocks arranged in the programming memory block list is sequentially accessed according to the order in which the information is arranged.

11. The method according to claim 10, wherein the determining determines whether the temperature of the memory system has initially entered the first temperature interval, and the second data is programmed in the first status check page, and there is no memory cell in an erased state in the first status check page. 12 . The method of claim 11 , wherein the determining is performed based on a value of a bit indicating whether the first status check page has been generated. 13 . The method according to claim 11 , wherein the first status check page is determined based on information indicating a position of another status check page to be allocated to another temperature interval among the plurality of temperature intervals.

14. The method according to claim 11, further comprising: Information on memory blocks that do not store valid data is removed from the program memory block list.

15. The method according to claim 14, further comprising: The information on the specific memory block included in the program memory block list is rearranged according to a count of how many erase operations or program operations have been performed on each memory block.

16. The method according to claim 11, further comprising: When the temperature of the memory system falls within the temperature interval, the second data stored in the status check page in the status check memory block is read to determine the status of the specific memory block.

17. The method according to claim 16, further comprising: In a case where the state-checking memory block includes a number of memory cells in an erased state equal to or greater than a preset threshold count, data stored in the specific memory block indicated by the program memory block list is checked.

18. The method according to claim 17, further comprising: In a case where the number of error bits detected in the specific memory block is equal to or greater than a threshold number, data programmed into the specific memory block indicated by the program memory block list is reprogrammed.

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