Chip interconnection component and preparation method thereof

Abstract

The present invention provides a chip interconnection component and a preparation method thereof. The interconnection component includes: a first conductive structure, arranged between a first conductive column and a first interconnection conductive pad, for welding the first conductive column and the first interconnection conductive pad to each other, and forming a first conductive height after welding; a second conductive structure, arranged between a second conductive column and the second interconnection conductive pad, for welding the second conductive column and the second interconnection conductive pad to each other, and forming a second conductive height after welding; wherein the first conductive height is the same as the second conductive height; the interconnection component solves the problem of poor interconnection between reflow solder balls with smaller diameters and conductive pads when I / O pins of different sizes on the same chip are interconnected with conductive pads on an interconnection carrier in the prior art, thereby ensuring the electrical stability of the chip package.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a component suitable for chip interconnection and a preparation method thereof. Background Art

[0002] In the prior art, I / O pins of different sizes are provided on the same chip. When preparing conductive pillars and solder bumps on the said I / O pins, the same sputtering metal nucleation layer process and electroplating conductive pillar process are usually adopted, resulting in the corresponding conductive pillars, solder bumps and interconnecting conductive pads on the I / O pins having the same overall height. However, in the subsequent high-temperature reflow soldering process, solder bumps of the same height form spheres under the action of surface tension, resulting in the shrinkage of the solder balls in height; the larger the diameter of the solder bump, the smaller the shrinkage of the formed sphere in the vertical direction, resulting in poor conductivity between the solder balls formed by the solder bumps with smaller diameters and the interconnecting conductive pads. In addition, the greater the difference in the horizontal cross-sectional area of the chip I / O pins, the more serious the degree of poor conductivity between the solder balls and the interconnecting conductive pads.

[0003] It can be seen that in the prior art, when I / O pins of different sizes on the same chip are interconnected with conductive pads on an interconnect carrier, there is a problem of poor interconnection between reflow solder balls with smaller diameters and the interconnect conductive pads. Summary of the Invention

[0004] In response to the deficiencies in the prior art, the present invention provides a chip interconnection component and a method for preparing the same, which solves the problem in the prior art of poor interconnection between reflow solder balls with smaller diameters and conductive pads when I / O pins of different sizes on the same chip are interconnected with conductive pads on an interconnection carrier.

[0005] In a first aspect, the present invention provides a chip interconnect component for use in welding a chip interconnect base and an interconnect carrier, wherein the chip interconnect base includes a first stacked metal layer and a second stacked metal layer, a first conductive pillar and a second conductive pillar, and the interconnect carrier includes a first interconnect conductive pad corresponding to the first conductive pillar and a second interconnect conductive pad corresponding to the second conductive pillar, wherein the cross-sectional area of the first conductive pillar is greater than the cross-sectional area of the second conductive pillar. The chip interconnect component includes: a first conductive structure, disposed between the first conductive pillar and the first interconnect conductive pad, configured to provide a conductive connection between the first conductive pillar and the first interconnect conductive pad, and to form a first conductive height after welding; and a second conductive structure, disposed between the second conductive pillar and the second interconnect conductive pad, configured to provide a conductive connection between the second conductive pillar and the second interconnect conductive pad, and to form a second conductive height after welding; wherein the second conductive structure includes a compensation metal pillar, configured to compensate for the conductive height between the chip interconnect base and the second interconnect conductive pad, so that the first conductive height and the second conductive height are the same.

[0006] Optionally, the compensation metal column is arranged on the second conductive column.

[0007] Optionally, the second conductive structure further includes: a first welding body, disposed on the compensation metal column, and configured to weld the second conductive column to the second interconnected conductive pad via the compensation metal column.

[0008] Optionally, the compensation metal column is provided on the second interconnection conductive pad.

[0009] Optionally, the second conductive structure further includes: a second welding body, disposed on the compensation metal column, and configured to weld the second conductive column to the second interconnected conductive pad via the compensation metal column.

[0010] Optionally, the material of the first conductive pillar includes copper; or / and the material of the second conductive pillar includes copper.

[0011] Optionally, the first conductive structure includes a solder ball structure; or / and the second conductive structure includes a solder ball structure.

[0012] Optionally, the solder ball structure is prepared by depositing tin-based alloy solder and performing a high-temperature reflow process.

[0013] In a second aspect, the present invention provides a method for preparing a chip interconnection component, the method comprising: providing a chip interconnection substrate, coating photoresist on first conductive pillars and second conductive pillars of the chip interconnection substrate to obtain a first interconnection photoresist layer; exposing and developing the first interconnection photoresist layer to obtain a first interconnection mask layer having a first interconnection opening, wherein the first interconnection opening corresponds to the second conductive pillar; preparing a compensation metal pillar at the first interconnection opening; coating photoresist on the compensation metal pillar to obtain a second interconnection photoresist layer, exposing and developing the second interconnection photoresist layer to obtain a second interconnection mask layer having an interconnection opening array, wherein the interconnection opening array includes a second interconnection opening corresponding to the first conductive pillar and a third interconnection opening corresponding to the compensation metal pillar; depositing solder at the second interconnection opening and the third interconnection opening to form a first conductive structure on the first conductive pillar and a first welding body on the compensation metal pillar to obtain a chip interconnection component.

[0014] Optionally, a chip interconnect substrate is provided, comprising: providing a carrier and a silicon wafer comprising a plurality of chips, the carrier being bonded to the passive surface of the silicon wafer by a bonding adhesive, wherein the chip comprises a first built-in conductive pad and a second built-in conductive pad, and the cross-sectional area of the first built-in conductive pad is larger than the cross-sectional area of the second built-in conductive pad; applying photoresist on the active surface of the silicon wafer to obtain a first chip photoresist layer, exposing and developing the first chip photoresist layer to obtain a first chip mask layer having a first opening array, wherein the first opening array comprises a first chip opening corresponding to the first built-in conductive pad and a second chip opening corresponding to the first built-in conductive pad. A second chip opening corresponding to the second built-in conductive pad; preparing a laminated metal layer on the first chip mask layer; applying photoresist on the laminated metal layer to obtain a second chip photoresist layer, and exposing and developing the second chip photoresist layer to obtain a second chip mask layer having a second opening array, wherein the second opening array includes a third chip opening corresponding to the first chip opening and a fourth chip opening corresponding to the second chip opening; electroplating copper at the third chip opening and the fourth chip opening to prepare a first conductive column and a second conductive column, thereby obtaining the chip interconnection substrate.

[0015] Optionally, copper is electroplated at the third chip opening and the fourth chip opening to prepare the first conductive pillar and the second conductive pillar, and then the chip interconnection matrix is obtained, including: after copper is electroplated at the third chip opening and the fourth chip opening to prepare the first conductive pillar and the second conductive pillar, the second chip mask layer, the laminated metal layer and the first chip mask layer are cleaned and removed to obtain the chip interconnection matrix; or, after copper is electroplated at the third chip opening and the fourth chip opening to prepare the first conductive pillar and the second conductive pillar, the second chip mask layer, the laminated metal layer and the first chip mask layer are retained to obtain the chip interconnection matrix.

[0016] In a third aspect, the present invention provides a method for preparing a chip interconnection component, the method comprising: providing an interconnection carrier, coating photoresist on a first interconnection conductive pad and a second interconnection conductive pad of the interconnection carrier to obtain a first interconnection carrier photoresist layer; exposing and developing the first interconnection carrier photoresist layer to obtain a first interconnection carrier mask layer having a first interconnection carrier opening, wherein the first interconnection carrier opening corresponds to the second interconnection conductive pad; preparing a compensation metal pillar at the first interconnection carrier opening; coating photoresist on the compensation metal pillar to obtain a second interconnection carrier photoresist layer, exposing and developing the second interconnection carrier photoresist layer to obtain a second interconnection carrier mask layer having an interconnection carrier opening array, wherein the interconnection carrier opening array includes a second interconnection carrier opening corresponding to the first interconnection conductive pad and a third interconnection carrier opening corresponding to the compensation metal pillar; depositing solder at the second interconnection carrier opening and the third interconnection carrier opening to form a first conductive structure on the first interconnection conductive pad, a compensation metal pillar and a second solder body on the compensation metal pillar, and cleaning and removing the first interconnection carrier photoresist layer and the first interconnection carrier mask layer to obtain the chip interconnection component.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] The present invention uses the first conductive structure and the second conductive structure to form a first conductive height after the conductive pillars with a larger cross-sectional area on the chip interconnect substrate are connected to the interconnect conductive pads on the interconnect carrier, and to form a second conductive height after the conductive pillars with a smaller cross-sectional area on the chip interconnect substrate are connected to the conductive pads on the interconnect carrier, and the first conductive height and the second conductive height are made the same, thereby solving the problem of poor interconnection between reflow solder balls with a smaller diameter and the interconnect conductive pads when I / O pins of different sizes on the same chip are connected to the interconnect conductive pads in the prior art, and ensuring the electrical reliability of the chip package. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 The figure shows a schematic diagram of poor soldering between I / O pins of different sizes on the same chip and conductive pads on an interconnect carrier in the prior art;

[0020] Figure 2 FIG2 is a schematic structural diagram of a first chip interconnection component provided by an embodiment of the present invention;

[0021] Figure 3 FIG2 is a schematic diagram of an application scenario of the first chip interconnection component provided by an embodiment of the present invention;

[0022] Figure 4 FIG2 is a flow chart of a method for preparing a chip interconnect substrate provided by an embodiment of the present invention;

[0023] Figure 5 FIG2 is a schematic diagram of bonding a carrier board and a chip according to an embodiment of the present invention;

[0024] Figure 6 FIG2 is a schematic diagram of preparing a first chip mask layer according to an embodiment of the present invention;

[0025] Figure 7 FIG2 is a schematic diagram of preparing a laminated metal layer according to an embodiment of the present invention;

[0026] Figure 8 FIG2 is a schematic diagram of preparing a second chip mask layer according to an embodiment of the present invention;

[0027] Figure 9 FIG2 is a schematic diagram of preparing a first conductive column and a second conductive column according to an embodiment of the present invention;

[0028] Figure 10 FIG2 is a schematic structural diagram of a chip interconnection substrate provided by an embodiment of the present invention;

[0029] Figure 11 FIG2 is a schematic structural diagram of a second chip interconnection component provided by an embodiment of the present invention;

[0030] Figure 12 FIG2 is a schematic diagram of an application scenario of the second chip interconnection component provided by an embodiment of the present invention;

[0031] Figure 13 FIG2 is a schematic flow chart of a method for preparing a first chip interconnection component provided by an embodiment of the present invention;

[0032] Figure 14 FIG2 is a schematic diagram of preparing a first interconnect photoresist layer on a chip interconnect substrate according to an embodiment of the present invention;

[0033] Figure 15 FIG2 is a schematic diagram of preparing a first interconnect mask layer according to an embodiment of the present invention;

[0034] Figure 16 FIG2 is a schematic diagram of a method for preparing a compensating metal column according to an embodiment of the present invention;

[0035] Figure 17 FIG2 is a schematic diagram of preparing a second interconnect mask layer according to an embodiment of the present invention;

[0036] Figure 18 FIG2 is a schematic diagram of preparing a first conductive structure and a second solder block according to an embodiment of the present invention;

[0037] Figure 19FIG2 is a flow chart of a second method for preparing a chip interconnection component provided by an embodiment of the present invention;

[0038] Figure 20 FIG2 is a schematic diagram of preparing a first interconnect carrier photoresist layer according to an embodiment of the present invention;

[0039] Figure 21 FIG2 is a schematic diagram of preparing a first interconnection carrier mask layer according to an embodiment of the present invention;

[0040] Figure 22 FIG2 is a schematic diagram of another method for preparing a compensating metal column according to an embodiment of the present invention;

[0041] Figure 23 Shown is a schematic diagram of preparing a second interconnect carrier mask layer provided by an embodiment of the present invention.

[0042] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0043] Before describing this embodiment, it is necessary to elaborate on the problems mentioned in the background technology: In the prior art, due to the special circuit design built into the chip, it is usually necessary to realize the transmission of different current densities and / or different signal strengths on the same chip, so there will be I / O pins of different sizes on the same chip, such as Figure 1 a and Figure 1 As shown in b, the conductive pillar 11 in the chip 100 is electrically connected to the built-in conductive pad 10 thereof, and the solder block 12 arranged on the conductive pillar 11, and the interconnection conductive pad 13 is arranged on the interconnection carrier 1, wherein the interconnection conductive pad 13 can be designed as an interconnection conductive pad 13a corresponding to the larger solder block 12a on the chip 100, or an interconnection conductive pad 13b corresponding to the smaller solder block 12b on the chip 100, or all the interconnection conductive pads on the interconnection carrier 1 can be designed as the interconnection conductive pad 13a corresponding to the larger solder block 12a on the chip 100. After the solder block 12 on the chip 100 corresponds one-to-one with the interconnection conductive pad 13 on the interconnection carrier 1, the solder block is melted by a high-temperature reflow process, and the solder block forms a solder ball under the action of surface tension, forming an alloy interconnection structure between the conductive pillar 11 and the interconnection conductive pad 13. However, if there are conductive pillars 11 and solder blocks 12 of different sizes in the same chip, the use of conventional interconnection structure and preparation process will result in the following Figure 2The poor soldering phenomenon shown is caused by the fact that, when preparing conductive pillars 11 and solder bumps 12 for I / O pins of different sizes on a chip, the chip is typically uniformly subjected to photolithography openings, deposition of stacked metal layers, and copper electroplating. Since the copper electroplating process takes the same time, the heights of the conductive pillars 11 and solder bumps 12 prepared at corresponding locations on I / O pins of different sizes are the same. During high-temperature reflow soldering, the solder bumps 12 form spheres under the action of surface tension. The diameter or height of the reflow solder bumps is positively correlated with the horizontal cross-sectional area of the solder bumps. Therefore, the reflow solder bumps with larger diameters can form good electrical connections with the interconnecting conductive pads, while the reflow solder bumps with smaller diameters cannot form good interconnections with the interconnecting conductive pads, significantly increasing the interconnection resistance between the smaller diameter solder bumps and the interconnecting conductive pads. If the cross-sectional areas corresponding to different I / O pins on the same chip differ significantly, the smaller diameter reflow solder bumps may even lose connectivity with the interconnecting conductive pads.

[0044] The interconnection carrier includes but is not limited to: a packaging substrate, a metal wiring layer structure (RDL), a silicon carrier with TSV conductive vias, a bridge chip with TSV conductive vias, a chip package with an electrical connection layer, a glass carrier with conductive vias, and a ceramic carrier with conductive vias.

[0045] In a first aspect, in order to solve the above-mentioned problems, the present invention provides a chip interconnection component, which specifically includes the following embodiments:

[0046] Example 1

[0047] Figure 2 FIG. 1 is a schematic structural diagram of a first chip interconnection component provided by an embodiment of the present invention; Figure 2 As shown, the chip interconnection component is used in the welding of the chip interconnection base and the interconnection carrier, wherein the chip interconnection base includes a first stacked metal layer 22a, a first conductive pillar 24a, and a second stacked metal layer 22b, a second conductive pillar 24b. The interconnection carrier includes a first interconnection conductive pad corresponding to the first conductive pillar 24a and a second interconnection conductive pad corresponding to the second conductive pillar 24b. The cross-sectional area of the first conductive pillar 24a is larger than the cross-sectional area of the second conductive pillar 24b. The chip interconnection component includes:

[0048] A first conductive structure is provided between the first conductive column 24a and the first interconnected conductive pad, and is used to interconnect and weld the first conductive column 24a and the first interconnected conductive pad, and form a first conductive height after welding;

[0049] A second conductive structure is provided between the second conductive column 24b and the second interconnected conductive pad, and is used to interconnect and weld the second conductive column 24b and the second interconnected conductive pad, and form a second conductive height after welding;

[0050] The first conductive height is the same as the second conductive height.

[0051] In a first implementation of this embodiment, the second conductive structure includes: a compensation metal column 32, which is arranged on the second conductive column 24b and is used to compensate for the conductive height between the chip interconnection base and the interconnection carrier; a second welding body 35b, which is arranged on the compensation metal column 32 and is used to weld the second conductive column 24b to the second interconnection conductive pad through the compensation metal column 32.

[0052] Compared with the prior art, the beneficial effects of this embodiment are:

[0053] In this embodiment, if Figure 3 As shown, by preparing a compensation metal column 32 with a certain height on the second conductive column 24b with a smaller diameter, a good conductive interconnection structure is formed between the second interconnection solder ball 36b formed by the first welding body 35b corresponding to the compensation metal column 32 after high-temperature reflow and the second conductive column 24b and the second interconnection conductive pad 13b; and by preparing the first conductive structure on the first conductive column 24a with a larger diameter, a good conductive interconnection structure is formed between the first interconnection solder ball 36a formed after high-temperature reflow and the first conductive column 24a and the first interconnection conductive pad 13a, so that the welding height formed after the first conductive column and the first interconnection conductive pad are welded to each other is the same as the welding height formed after the second conductive column and the second interconnection conductive pad are welded to each other, thereby solving the problem of poor interconnection between the reflow solder ball with a smaller diameter and the conductive pad when I / O pins of different sizes on the same chip are interconnected with the conductive pad on the interconnection carrier.

[0054] In a second aspect, this embodiment provides a method for preparing a chip interconnect substrate, and the specific process steps are as follows:

[0055] Figure 4 FIG. 1 is a flow chart of a method for preparing a chip interconnect substrate according to an embodiment of the present invention; FIG. Figure 4 As shown, the method for preparing the chip interconnect substrate specifically includes the following steps:

[0056] Step S101 : providing a carrier board and a silicon wafer including a plurality of chips, wherein the carrier board is bonded to the passive surface of the silicon wafer by bonding adhesive.

[0057] In this embodiment, if Figure 5As shown, silicon wafer S1 includes multiple chips 100. The active surface of chip 100 includes a first internal conductive pad 10a and a second internal conductive pad 10b, with the cross-sectional area of the first internal conductive pad 10a being larger than that of the second internal conductive pad 10b. The active surface corresponds to the passive surface of the silicon wafer. A carrier C1 is connected to the passive surface of silicon wafer S1 via bonding adhesive F1. The silicon wafer is thinned before being bonded to the bonding adhesive.

[0058] In step S102 , a photoresist is applied on the active surface of the silicon wafer to obtain a first chip photoresist layer, and the first chip photoresist layer is exposed and developed to obtain a first chip mask layer having a first opening array.

[0059] It should be noted that if Figure 6 As shown in FIG. a, a layer of photoresist is coated on the active surface of the silicon wafer S1 to obtain a first chip photoresist layer 20a; wherein, a dielectric film with a UV photosensitive agent can also be used as a mask layer by hot pressing. Figure 6 As shown in FIG. 2 , the first chip photoresist layer 20a is exposed and developed by a photolithography process to obtain a first chip mask layer 20b having a first opening array, wherein the first opening array includes a first chip opening 211 corresponding to the first built-in conductive pad 10a and a second chip opening 212 corresponding to the second built-in conductive pad 10b.

[0060] Step S103: preparing a laminated metal layer on the first chip mask layer.

[0061] In this embodiment, if Figure 7 As shown, several layers of stacked metal layers 22 are sputtered on the first chip mask layer 20b. In a specific stacked metal layer structure, the stacked metal layer includes a sputtered metal barrier layer and a copper seed layer; the metal barrier layer includes Ti, Ni, Cu, Pd, Pt or Ti-W, and its function is to prevent copper atoms from diffusing to the chip substrate.

[0062] Step S104 , coating photoresist on the stacked metal layer to obtain a second chip photoresist layer, and exposing and developing the second chip photoresist layer to obtain a second chip mask layer having a second opening array.

[0063] It should be noted that if Figure 8 As shown in a, a photoresist layer is coated on the laminated metal layer to obtain a second chip photoresist layer 23a;

[0064] like Figure 8As shown in FIG. 2 , the second chip photoresist layer 23a is exposed and developed by a photolithography process to obtain a second chip mask layer 23b having a second opening array, wherein the second opening array includes a third chip opening 221 corresponding to the first chip opening 211 and a fourth chip opening 222 corresponding to the second chip opening 212.

[0065] Furthermore, the stacked metal layer 22 includes a stacked metal layer on the first opening array and a mask stacked metal layer outside the first opening array.

[0066] Step S105 , electroplating copper at the third chip opening and the fourth chip opening to prepare first conductive pillars and second conductive pillars, and then obtaining the chip interconnection substrate.

[0067] In this embodiment, copper is electroplated at the third chip opening and the fourth chip opening to prepare the first conductive pillar and the second conductive pillar, and then the chip interconnection matrix is obtained, including: after copper is electroplated at the third chip opening and the fourth chip opening to prepare the first conductive pillar and the second conductive pillar, the second chip mask layer, the laminated metal layer and the first chip mask layer are cleaned and removed to obtain the chip interconnection matrix.

[0068] Optionally, copper is electroplated at the third chip opening and the fourth chip opening to prepare the first conductive pillar and the second conductive pillar, and then the chip interconnection matrix is obtained, including: after copper is electroplated at the third chip opening and the fourth chip opening to prepare the first conductive pillar and the second conductive pillar, the second chip mask layer, the stacked metal layer and the first chip mask layer are retained to obtain the chip interconnection matrix.

[0069] In this embodiment, if Figures 8-9 As shown, a copper electroplating process is performed on the stacked metal layers corresponding to the third chip opening 221 and the fourth chip opening 222 to prepare first conductive pillars 24a and second conductive pillars 24b. The height of the conductive pillars can be greater than, less than, or equal to the height of the second chip mask layer 23b.

[0070] In the first embodiment of the obtained chip interconnection matrix, as shown in FIG. Figure 10 As shown in a, the second chip mask layer 23b, the mask stacked metal layer outside the first opening array, and the first chip mask layer 20b are cleaned and removed in sequence to prepare a chip interconnect substrate P1 connected to the chip built-in conductive pad on the chip active surface, wherein the chip interconnect substrate P1 includes a stacked metal layer, a first conductive column 24a and a second conductive column 24b.

[0071] In the second embodiment of the obtained chip interconnect matrix, Figure 10As shown in b, copper is electroplated at the third chip opening and the fourth chip opening to prepare the first conductive pillar and the second conductive pillar. Different from the first method mentioned above, the chip interconnection substrate P1' here does not need to remove the second chip mask layer, the mask stacked metal layer outside the first opening array and the first chip mask layer, that is, the photoresist mask layer and the stacked metal layer jointly surround the first conductive pillar and the second conductive pillar.

[0072] In a second aspect, this embodiment provides a method for preparing a chip interconnect component, and the specific process steps are as follows:

[0073] Figure 11 FIG. 1 is a flow chart of a method for preparing a first chip interconnection component according to an embodiment of the present invention; FIG. Figure 11 As shown, the method for preparing the chip interconnection component specifically includes the following steps:

[0074] Step S201 : providing a chip interconnect substrate P1 , and coating photoresist on first conductive pillars and second conductive pillars of the chip interconnect substrate to obtain a first interconnect photoresist layer.

[0075] It should be noted that if Figure 12 As shown, photoresist is coated on the first conductive pillars 24a and the second conductive pillars 24b of the chip interconnect substrate to obtain a first interconnect photoresist layer 30a; wherein, a dielectric film with ultraviolet photosensitizer that is hot-pressed can also be used as a mask layer to replace the first interconnect photoresist layer 30a.

[0076] This process step can also refer to Figure 10 As shown in b, photoresist is directly coated on the chip interconnect substrate P1' to save photoresist materials and simplify the process flow.

[0077] Step S202 : exposing and developing the first interconnect photoresist layer to obtain a first interconnect mask layer having a first interconnect opening, wherein the first interconnect opening corresponds to the second conductive pillar.

[0078] like Figure 13 As shown, the first interconnect photoresist layer 30a is exposed and developed to obtain a first interconnect mask layer 30b having a first interconnect opening 31, wherein the first interconnect opening 31 corresponds to the second conductive pillar 24b.

[0079] Step S203 , preparing a compensation metal column at the first interconnect opening.

[0080] like Figure 14 As shown, a copper electroplating process is performed at the first interconnection opening 31 to obtain a compensation metal pillar 32 .

[0081] Step S204 , coating photoresist on the compensation metal pillar to obtain a second interconnect photoresist layer, exposing and developing the second interconnect photoresist layer to obtain a second interconnect mask layer having an interconnect opening array.

[0082] like Figure 15 As shown in a, a photoresist is coated on the compensation metal pillar 32 to obtain a second interconnect photoresist layer 33a;

[0083] like Figure 15 As shown in FIG. 2 , the second interconnect photoresist layer 33a is exposed and developed to obtain a second interconnect mask layer 33b having an interconnect opening array; wherein the interconnect opening array includes a second interconnect opening 341 corresponding to the first conductive column 24a and a third interconnect opening 342 corresponding to the compensation metal column 32.

[0084] Step S205 , depositing solder at the second interconnect opening and the third interconnect opening to form a first conductive structure on the first conductive pillar and a first solder body on the compensation metal pillar, thereby obtaining a chip interconnection component.

[0085] like Figure 16 As shown, solder is deposited at the second interconnect opening 341 and the third interconnect opening 342 to form a first conductive structure 35a on the first conductive pillar 24a and a first solder body 35b on the compensation metal pillar 32; after cleaning and removing the second interconnect mask layer 33b and the first interconnect mask layer 30b, the following is obtained. Figure 2 The chip interconnection component shown in FIG. wherein the solder comprises tin-based alloy solder.

[0086] In this embodiment, after the chip interconnection component is prepared on the chip interconnection substrate P1 and interconnected with the interconnection carrier, the following steps are further included:

[0087] like Figures 2-3 As shown, the first conductive structure and first solder body on the chip interconnect component are aligned one-to-one with the interconnect conductive pads on the interconnect carrier. The larger-diameter first conductive structure 35a corresponds to the first interconnect conductive pad 13a, and the smaller-diameter first solder bump 35b corresponds to the second interconnect conductive pad 13b. A high-temperature reflow process melts the first conductive structure 35a and the first solder body 35b, producing first interconnect solder balls 36a and second interconnect solder balls 36b under the action of surface tension. This ensures that the soldered heights formed by the compensation metal pillars 32 and the second interconnect solder balls 36b are the same as the soldered heights of the first interconnect solder balls 36a.

[0088] Example 2

[0089] Figure 17FIG. 1 is a schematic structural diagram of a second chip interconnection component provided by an embodiment of the present invention; Figure 17 As shown, the second conductive structure includes: a compensation metal column 42, which is arranged on the second interconnect conductive pad 13b and is used to compensate for the second conductive height; a second welding body 43b, which is arranged on the compensation metal column 42 and is used to achieve a welding connection between the second conductive column and the compensation metal column.

[0090] Compared with the prior art, the beneficial effects of this embodiment are:

[0091] In this embodiment, it should be noted that Figure 18 As shown in Figures 18a and 18b, a compensation metal pillar 42 having a certain height is prepared on the second interconnect conductive pad 13b with a smaller diameter in the interconnect carrier, so that a good conductive interconnection structure is formed between the second interconnect solder ball 44b formed by the second solder block 43b corresponding to the compensation metal pillar 42 after high-temperature reflow and the second stacked metal layer 22b, the second conductive pillar 24b, the compensation metal pillar 42, and the second interconnect conductive pad 13b; and a good conductive interconnection structure is formed between the first interconnect solder ball 44a formed after high-temperature reflow on the first interconnect conductive pad 13a with a larger diameter, and the first stacked metal layer 22a, the first conductive pillar 24a, and the first interconnect conductive pad 13a. As a result, the welding height formed by the first conductive pillar 24a and the first interconnect conductive pad 13a after welding is the same as the welding height formed by the second conductive pillar 24b and the second interconnect conductive pad 13b after welding, thereby solving the problem of poor interconnection between the reflow solder ball with a smaller diameter and the conductive pad when I / O pins of different sizes on the same chip are interconnected with the conductive pad on the interconnect carrier.

[0092] In a second aspect, this embodiment provides a method for preparing a chip interconnect component, and the specific process steps are as follows:

[0093] Figure 19 FIG. 1 is a flow chart of a second method for preparing a chip interconnection component according to an embodiment of the present invention; FIG. Figure 19 As shown, the method for preparing the chip interconnection component specifically includes the following steps:

[0094] Step S301, providing an interconnect carrier, coating a photoresist on a first interconnect conductive pad and a second interconnect conductive pad of the interconnect carrier to obtain a first interconnect carrier photoresist layer;

[0095] like Figure 20 As shown, a layer of photoresist is coated on the base surface corresponding to the interconnection conductive pad on the interconnection carrier to obtain a first interconnection carrier photoresist layer 40a; wherein the interconnection conductive pad includes a first interconnection conductive pad 13a with a larger cross-sectional area and a second interconnection conductive pad 13b with a smaller cross-sectional area.

[0096] Step S302, exposing and developing the first interconnection carrier photoresist layer to obtain a first interconnection carrier mask layer having a first interconnection carrier opening, wherein the first interconnection carrier opening corresponds to the second interconnection conductive pad;

[0097] like Figure 21 As shown, the first interconnection carrier photoresist layer 40a is exposed and developed to form a first interconnection carrier mask layer 40b having a first interconnection carrier opening 41b; wherein the first interconnection carrier opening 41b corresponds to the second interconnection conductive pad 13b;

[0098] Step S303, preparing a compensation metal column at the opening of the first interconnection carrier;

[0099] like Figure 22 As shown, conductive metal is filled in the first interconnect carrier opening 41 b to prepare a compensation metal column 42 .

[0100] Step S304: coating photoresist on the compensation metal pillar to obtain a second interconnection carrier photoresist layer, exposing and developing the second interconnection carrier photoresist layer to obtain a second interconnection carrier mask layer having an interconnection carrier opening array, wherein the interconnection carrier opening array includes a second interconnection carrier opening corresponding to the first interconnection conductive pad and a third interconnection carrier opening corresponding to the compensation metal pillar;

[0101] like Figure 23 As shown in a, a photoresist is applied on the compensation metal pillar 42 to obtain a second interconnection carrier photoresist layer 40c. Figure 23 As shown in step b, exposure and development are performed on the second interconnection carrier photoresist layer 40c to obtain a second interconnection carrier mask layer 40d having an interconnection carrier opening array, wherein the interconnection carrier opening array includes a second interconnection carrier opening corresponding to the first interconnection conductive pad and a third interconnection carrier opening corresponding to the compensation metal column.

[0102] Step S305 , depositing solder at the second interconnect carrier opening and the third interconnect carrier opening to form a first conductive structure on the first interconnect conductive pad, and forming a compensation metal column and a second solder body on the compensation metal column, and cleaning and removing the second interconnect carrier mask layer and the first interconnect carrier mask layer to obtain a chip interconnect component.

[0103] In this embodiment, if Figure 23As shown in FIG. 2 , solder is deposited at the openings of the second interconnection carrier and the third interconnection carrier to form a first conductive structure 43 a on the first interconnection conductive pad 13 a and a second solder body 43 b on the compensation metal column 42. After cleaning and removing the mask layer of the second interconnection carrier and the mask layer of the first interconnection carrier, the following is obtained: Figure 17 The chip interconnect components shown.

[0104] For the chip interconnect substrate P1', the second interconnect carrier mask layer, the first interconnect carrier mask layer, the second chip mask layer, the mask stack metal layer in the non-conductive pillar region and the first chip mask layer need to be cleaned and removed respectively.

[0105] In this embodiment, after the chip interconnection component is prepared on the interconnection carrier and interconnected with the chip interconnection substrate P1, the following steps are further included:

[0106] like Figure 18 As shown in FIG. 1 , the first conductive pillars 24a on the chip interconnection substrate P1 correspond one-to-one with the first conductive structures 43a on the chip interconnection component, and the second conductive pillars 24b on the chip interconnection substrate P1 correspond one-to-one with the first solder bumps 43b on the chip interconnection component.

[0107] like Figure 18 As shown in FIG. 2 , the high-temperature reflow process melts the first conductive structure 43a and the second solder body 43b, and prepares the first interconnect solder ball 44a and the second interconnect solder ball 44b respectively under the action of surface tension, so that the welding height formed by the compensation metal column 42 and the second interconnect solder ball 44b is the same as the welding height of the first interconnect solder ball 44a.

[0108] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

Claims

1. A chip interconnection component, characterized in that: The invention is applied to the welding of a chip interconnection base and an interconnection carrier, wherein the chip interconnection base includes a first stacked metal layer and a second stacked metal layer, a first conductive column and a second conductive column, the interconnection carrier includes a first interconnection conductive pad corresponding to the first conductive column and a second interconnection conductive pad corresponding to the second conductive column, the cross-sectional area of the first conductive column is larger than the cross-sectional area of the second conductive column, and the chip interconnection component includes: a first conductive structure disposed between the first conductive pillar and the first interconnected conductive pad, configured to provide a conductive connection between the first conductive pillar and the first interconnected conductive pad, wherein after welding, a height formed between the first conductive structure, the first conductive pillar, and the first interconnected conductive pad is a first conductive height; a second conductive structure disposed between the second conductive pillar and the second interconnected conductive pad, configured to provide conductive connection between the second conductive pillar and the second interconnected conductive pad, wherein after welding, a height formed between the second conductive structure, the second conductive pillar, and the second interconnected conductive pad is a second conductive height; The second conductive structure includes a compensation metal column for compensating the conductive height between the chip interconnect substrate and the second interconnect conductive pad, so that the first conductive height is the same as the second conductive height.

2. The chip interconnection component according to claim 1, wherein: The compensation metal column is arranged on the second conductive column.

3. The chip interconnection component according to claim 2, wherein: The second conductive structure further includes: The first welding body is disposed on the compensation metal column and is used to weld the second conductive column and the second interconnected conductive pad to each other through the compensation metal column.

4. The chip interconnection component according to claim 1, wherein: The compensation metal column is arranged on the second interconnection conductive pad.

5. The chip interconnection component according to claim 4, wherein: The second conductive structure further includes: The second welding body is arranged on the compensation metal column and is used to weld the second conductive column and the second interconnected conductive pad to each other through the compensation metal column.

6. The chip interconnection component according to claim 1, wherein: The material of the first conductive pillar includes copper; or / and the material of the second conductive pillar includes copper.

7. The chip interconnection component according to claim 1, wherein: The first conductive structure includes a solder ball structure; or / and the second conductive structure includes a solder ball structure.

8. The chip interconnection component according to claim 7, wherein: The solder ball structure is prepared by depositing tin-based alloy solder and performing a high-temperature reflow process.

9. A method for preparing a chip interconnection component, characterized in that: The method comprises: Providing a chip interconnect substrate, coating a photoresist on a first conductive pillar and a second conductive pillar of the chip interconnect substrate to obtain a first interconnect photoresist layer, wherein the cross-sectional area of the first conductive pillar is greater than the cross-sectional area of the second conductive pillar; exposing and developing the first interconnect photoresist layer to obtain a first interconnect mask layer having a first interconnect opening, wherein the first interconnect opening corresponds to the second conductive pillar; preparing a compensation metal column at the first interconnect opening; Applying photoresist on the compensation metal pillar to obtain a second interconnect photoresist layer, exposing and developing the second interconnect photoresist layer to obtain a second interconnect mask layer having an interconnect opening array, wherein the interconnect opening array includes a second interconnect opening corresponding to the first conductive pillar and a third interconnect opening corresponding to the compensation metal pillar; Depositing solder at the second interconnect opening and the third interconnect opening to form a first conductive structure on the first conductive pillar and a first solder body on the compensation metal pillar to obtain a chip interconnection component; Among them, after the first conductive structure and the first welding body are both welded, the height formed between the first conductive column, the first conductive structure, and the first interconnected conductive pad is the first conductive height, and the height formed between the second conductive column, the compensation metal column, the first welding body, and the second interconnected conductive pad is the second conductive height, and the first conductive height is the same as the second conductive height.

10. The method for preparing a chip interconnection component according to claim 9, wherein: A chip interconnect substrate is provided, comprising: A carrier board and a silicon wafer including a plurality of chips are provided, wherein the carrier board is bonded to the passive surface of the silicon wafer by bonding adhesive, wherein the chip includes a first built-in conductive pad and a second built-in conductive pad, and the cross-sectional area of the first built-in conductive pad is greater than the cross-sectional area of the second built-in conductive pad; Applying photoresist on the active surface of the silicon wafer to obtain a first chip photoresist layer, exposing and developing the first chip photoresist layer to obtain a first chip mask layer having a first opening array, wherein the first opening array includes a first chip opening corresponding to the first built-in conductive pad and a second chip opening corresponding to the second built-in conductive pad; preparing a laminated metal layer on the first chip mask layer; Applying photoresist on the laminated metal layer to obtain a second chip photoresist layer, and exposing and developing the second chip photoresist layer to obtain a second chip mask layer having a second opening array, wherein the second opening array includes a third chip opening corresponding to the first chip opening and a fourth chip opening corresponding to the second chip opening; The chip interconnection substrate is obtained by electroplating copper at the third chip opening and the fourth chip opening to prepare the first conductive pillar and the second conductive pillar.

11. The method for preparing a chip interconnection component according to claim 10, wherein: The chip interconnection substrate is obtained by electroplating copper at the third chip opening and the fourth chip opening to prepare first conductive pillars and second conductive pillars, comprising: Electroplating copper at the third chip opening and the fourth chip opening to prepare a first conductive pillar and a second conductive pillar, and then cleaning and removing the second chip mask layer, the laminated metal layer and the first chip mask layer to obtain the chip interconnection substrate; Alternatively, after copper is electroplated at the third chip opening and the fourth chip opening to prepare the first conductive pillar and the second conductive pillar, the second chip mask layer, the stacked metal layer and the first chip mask layer are retained to obtain the chip interconnection substrate.

12. A method for preparing a chip interconnection component, characterized in that: The method comprises: Providing an interconnect carrier, coating a photoresist on a first interconnect conductive pad and a second interconnect conductive pad of the interconnect carrier to obtain a first interconnect carrier photoresist layer, wherein a cross-sectional area of the first interconnect conductive pad is greater than a cross-sectional area of the second interconnect conductive pad; exposing and developing the first interconnection carrier photoresist layer to obtain a first interconnection carrier mask layer having a first interconnection carrier opening, wherein the first interconnection carrier opening corresponds to the second interconnection conductive pad; preparing a compensation metal column at the opening of the first interconnection carrier; Applying photoresist on the compensation metal pillar to obtain a second interconnection carrier photoresist layer, exposing and developing the second interconnection carrier photoresist layer to obtain a second interconnection carrier mask layer having an interconnection carrier opening array, wherein the interconnection carrier opening array includes a second interconnection carrier opening corresponding to the first interconnection conductive pad and a third interconnection carrier opening corresponding to the compensation metal pillar; Depositing solder at the second interconnection carrier opening and the third interconnection carrier opening to form a first conductive structure on the first interconnection conductive pad and a second solder body on the compensation metal column, and cleaning and removing the second interconnection carrier mask layer and the first interconnection carrier mask layer to obtain a chip interconnection component; Among them, after the first conductive structure and the second welding body are both welded, the high column formed between the first interconnected conductive pad, the first conductive structure, and the first conductive column is the first conductive height, and the height formed between the second interconnected conductive pad, the compensation metal column, the second welding body, and the second conductive column is the second conductive height, and the first conductive height is the same as the second conductive height.

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