A low on-resistance SiC-based MOSFET device and its preparation method

Abstract

The present invention discloses a low on-resistance SiC-based MOSFET device and a method for manufacturing the same. The device comprises a drift layer comprising an nx first drift layer and an n-second drift layer disposed above the nx first drift layer, wherein the nx first drift layer has a higher doping concentration than the n-second drift layer. The SiC-based MOSFET device, with a segmented doped epitaxial structure, utilizes a highly doped drift layer away from the main junction region to reduce the device's series resistance. Furthermore, the device utilizes a low-doped layer in the main junction region to enhance the protective effect of the p-type shielding layer, reducing the device's Miller charge and thereby improving the switching capability of the SiC-based MOSFET.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a SiC-based MOSFET device with low on-resistance and a preparation method thereof. Background Art

[0002] The third-generation semiconductor silicon carbide (SiC) material has shown great application potential in power electronics, semiconductor lighting, detectors, and lasers. Its critical breakdown electric field is nearly 10 times higher than that of Si, which allows SiC power devices to have a very thin drift region thickness and high doping at the same voltage, thereby greatly reducing the on-state resistance. Secondly, SiC has a bandgap width and thermal conductivity three times that of Si, so the excitation temperature of intrinsic carriers is higher, allowing the former to operate in high-temperature, high-irradiation environments. Thirdly, high thermal conductivity greatly improves the integration of power systems. Therefore, electronic devices based on wide-bandgap SiC materials can give full play to the important advantages of energy conservation and emission reduction in power electronics fields such as high temperature, high power, high frequency, and high radiation, and will occupy an important position in technology updates and product promotion.

[0003] SiC metal-oxide-semiconductor field-effect transistor (MOSFET) power devices are making continuous progress in the commercialization process. Currently, planar gate MOSFETs (DMOSFETs) and trench gate MOSFETs (UMOSFETs) are the leading devices on the market. As field-controlled devices, SiC-based MOSFETs feature ease of drive, high operating frequency, and high power density, and are being strongly driven by the current demand for industrial and automotive-grade products. Despite this, the power loss of SiC-based MOSFET devices remains a focus of attention, and significant challenges exist in reducing device on-resistance and improving chip wafer yield. The resistance of SiC-based MOSFETs includes source-drain contact resistance, channel resistance, JFET resistance, drift layer resistance, and substrate resistance. Drift layer resistance is the primary parameter for measuring device on-state performance, but due to the large number of interface states between the SiO2 layer and the SiC substrate, channel resistance accounts for a significant portion after drift layer resistance. In recent years, while continuous advancements in SiC-based MOS gate dielectric technology have reduced channel resistance, drift layer resistance has become the largest component of resistance in high-voltage applications. Optimizing drift layer resistance is one of the primary approaches to addressing the conduction issues of SiC-based MOSFETs. Therefore, a new design and manufacturing method for SiC-based MOSFETs with low on-resistance is needed. Summary of the Invention

[0004] The purpose of the present invention is to provide an epitaxial structure design scheme and preparation method for SiC-based MOSFET devices to address the problem of high on-resistance of current high-voltage SiC-based MOSFET devices, which is mainly used to reduce the drift layer resistance of SiC-based MOSFET devices, thereby improving the capacity and Baliga figure of merit of the high-voltage SiC-based MOSFET.

[0005] The technical solution of the present invention is to consider the on-resistance of the drift layer of the SiC-based MOSFET device and propose a SiC-based MOSFET device with a segmented doped epitaxial structure. The device series resistance is reduced by using a highly doped drift layer away from the main junction region, and the protective effect of the p-type shielding layer is enhanced by using a low-doped layer in the main junction region, thereby reducing the Miller charge of the device and improving the switching conversion capability of the SiC-based MOSFET device.

[0006] The present invention describes a method for fabricating a SiC-based MOSFET device with both low on-resistance and high breakdown voltage. This method utilizes epitaxial growth technology, deep submicron self-aligned implantation, high-temperature activation and annealing, gate oxide technology, and polysilicon gate electrode technology to fabricate the epitaxial structure, active region doping, and electrodes. This method improves the on-state capability and high-voltage breakdown capability of the SiC-based MOSFET device, enhancing both its static on-state characteristics and its dynamic switching characteristics.

[0007] In order to achieve the above objectives, the technical solution of the present invention is:

[0008] A low on-resistance SiC-based MOSFET device comprises, from bottom to top, a drain electrode contact, an n++-type SiC substrate, and a SiC epitaxial layer, and further comprises a gate dielectric, a gate electrode contact, an inner insulating material, a source electrode contact, and a source pad metal layer disposed above the SiC epitaxial layer; the SiC epitaxial layer comprises, from bottom to top, an n+-type buffer layer and a drift layer, the drift layer comprising an nx-first drift layer disposed on the n+-type buffer layer and an n--second drift layer disposed on the nx-first drift layer, a p-well region disposed within the n--second drift layer, and an n+-type doped region and a p+-type doped region disposed within the p-well region; wherein,

[0009] The nx first drift layer and the n-second drift layer are made of the same material. The doping concentration of the nx first drift layer is higher than that of the n-second drift layer, and the thickness of the n-second drift layer accounts for 20%-50% of the total drift layer thickness. The distance between the bottom of the p well region and the bottom of the n-second drift layer is 80%-90% of the thickness of the n-second drift layer.

[0010] The homogeneous materials mentioned here refer to materials with the same impurities doped into them.

[0011] Optionally, the nx first drift layer includes at least two stacked doping layers, and the doping concentrations of the doping layers decrease in a step-wise manner from bottom to top.

[0012] Optionally, the nx first drift layer is gradually doped from bottom to top, and the doping concentration gradually decreases.

[0013] Optionally, the doping concentration of the nx first drift layer is between 1×10 15 cm -3 ~1×10 17 cm -3 between.

[0014] Optionally, the doping concentration of the n- second drift layer is in the range of 1×10 14 cm -3 ~1×10 16 cm -3 , thickness range is 2-5μm.

[0015] Optionally, the p well region is located on both sides of the upper part of the n-second drift layer, the gate dielectric and the gate electrode contact are stacked in sequence in the middle of the surface of the n-second drift layer, the source electrode contact is located above the p+ type doped region, the source electrode contact is connected to the source pad metal layer, and the internal insulating material separates the gate electrode contact from the source electrode contact and the source pad metal layer.

[0016] A method for preparing the above-mentioned low on-resistance SiC-based MOSFET device comprises the following steps:

[0017] 1) growing an n+ type buffer layer on an n++ type SiC substrate;

[0018] 2) growing an nx first drift layer with a higher doping concentration on the n+ type buffer layer, and growing an n- second drift layer with a lower doping concentration on the nx first drift layer;

[0019] 3) Doping the active region to form a p-well region, an n+ type doping region, and a p+ type doping region on the upper portion of the n- second drift layer;

[0020] 4) forming a gate dielectric on the n-second drift layer;

[0021] 5) forming a gate electrode contact on the gate dielectric;

[0022] 6) making an inner insulating material covering the gate electrode contact;

[0023] 7) Fabricating ohmic contacts, including a drain electrode contact located on the bottom surface of the n++ type SiC substrate 10 and a source electrode contact located outside the inner insulating material;

[0024] 8) Fabricate a source pad metal layer that contacts the source electrode.

[0025] Optionally, in step 2), the drift layer is grown using a chemical vapor deposition process, the growth temperature is 1500-1700° C., the doping source is NH 3 , and the doping concentration is controlled by controlling the doping source flow rate.

[0026] Optionally, during the growth of the nx first drift layer, the flow rate of the doping source is fixed, reduced in stages, or reduced gradually.

[0027] The beneficial effects of the present invention are:

[0028] (1) Based on the partially highly doped drift layer, the drift layer resistance of SiC-based MOSFET is greatly reduced. This advantage is particularly evident in the high-voltage field;

[0029] (2) By adopting a segmented doping epitaxial structure, the low-doping layer in the main junction region can still enhance the protection of the p-type shielding layer and improve the blocking capability of SiC-based MOSFET devices;

[0030] (3) By adopting a segmented doping epitaxial structure, the thickness of the high-doping layer away from the main junction area can be appropriately reduced, further reducing the epitaxial cost of high-voltage SiC-based MOSFET devices;

[0031] (4) The SiC-based MOSFET device of the present invention has a smaller size than conventional MOSFET devices, thereby improving wafer manufacturing capabilities;

[0032] (5) Compared with conventional MOSFET devices, the SiC-based MOSFET device of the present invention has lower on-resistance, higher Baliga figure of merit, and larger high-frequency switching figure of merit. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 1 is a flow chart for preparing a SiC-based MOSFET device according to an embodiment;

[0034] Figure 2 is a structural diagram of the SiC epitaxial material substrate of Example 1;

[0035] Figure 3 is a structural diagram of the nx first drift layer 31 of Example 1;

[0036] Figure 4 is a structural diagram of the n-second drift layer 30 of Example 1;

[0037] Figure 5 This is a structural diagram of the active region doping in Example 1;

[0038] Figure 6is a structural diagram of a gate dielectric 70 manufactured in the first embodiment;

[0039] Figure 7 is a structural diagram of a gate electrode contact 80 in Example 1;

[0040] Figure 8 This is a structural diagram of the inner insulating material 90 according to the first embodiment;

[0041] Figure 9 1 is a structural diagram of a source electrode contact 100 and a drain electrode contact 110 according to the first embodiment;

[0042] Figure 10 is a structural diagram of the pad metal layer 120 of the first embodiment;

[0043] Figure 11 is a structural diagram of the nx first drift layer 31 of Example 2;

[0044] Figure 12 3 is a structural diagram of a SiC-based MOSFET device with low on-resistance manufactured in Example 2.

[0045] Figure 13 is a structural diagram of the nx first drift layer 31 of Example 3;

[0046] Figure 14 1 is a structural diagram of a SiC-based MOSFET device with low on-resistance manufactured in Example 3;

[0047] Figure 15 This is an embodiment one Comparison effect diagram of the low on-resistance SiC-based MOSFET device and comparative example 1. DETAILED DESCRIPTION

[0048] The present invention is further explained below with reference to the accompanying drawings and specific embodiments. The drawings are provided for illustrative purposes only to facilitate understanding of the present invention, and their specific proportions may be adjusted according to design requirements. Those skilled in the art will understand that the vertical relationships between components and the definitions of front and back in the figures described herein refer to the relative positions of components. Therefore, they can be flipped to present the same components, and all such representations are within the scope of this specification.

[0049] The device of the present invention utilizes a segmented doped epitaxial structure to significantly reduce the drift layer resistance of the SiC-based MOSFET. Simultaneously, the coupling effect between the low-doped drift layer and the p-well region ensures the device's blocking characteristics, avoiding the low breakdown voltage disadvantage of the highly doped drift layer. During forward conduction, electrons enter the low-doped drift layer along the short-channel inversion layer and then enter the highly doped drift layer along the JFET region. During reverse blocking, the shielding effect of the adjacent p-well and low-doped drift layer effectively protects the gate dielectric, significantly reducing the device's gate dielectric electric field and causing avalanche to occur at the PN junction in the device body. The resulting SiC-based MOSFET device exhibits low forward on-resistance and high reverse blocking capability, while also improving both static and dynamic operational reliability.

[0050] Example 1

[0051] Figure 1 The present invention is a flow chart of a method for preparing a SiC-based MOSFET device having both low on-resistance and high breakdown voltage, comprising the following steps:

[0052] S1. Cleaning SiC material substrate;

[0053] S2. Growth buffer layer;

[0054] S3. Growth drift layer;

[0055] S4. Making active area doping;

[0056] S5. Making a gate dielectric;

[0057] S6. Making gate electrode contacts;

[0058] S7. Fabricating a passivation layer;

[0059] S8. Making source electrode contacts and drain electrode contacts;

[0060] S9. Make a pad metal layer.

[0061] in,

[0062] Step S1: Cleaning the SiC epitaxial material substrate. The SiC epitaxial material substrate comprises an n++ type SiC substrate substrate 10. The substrate sample is subjected to standard cleaning, specifically:

[0063] a. Ultrasonic clean the surface with acetone and ethanol three times, then rinse with deionized water.

[0064] b. Place the organic ultrasonicated SiC epitaxial material substrate in concentrated sulfuric acid and hydrogen peroxide solution and boil for at least 10 minutes.

[0065] c. Boil the SiC epitaxial substrate, which has been boiled in concentrated sulfuric acid, in Solution 1 and Solution 2, sequentially for 15 minutes. Rinse with deionized water and blow dry with nitrogen. Solution 1 is a mixture of ammonia, hydrogen peroxide, and deionized water (with a volume ratio of ammonia: hydrogen peroxide: deionized water of 1:2:5). Solution 2 is a mixture of hydrochloric acid, hydrogen peroxide, and deionized water (with a volume ratio of hydrochloric acid: hydrogen peroxide: deionized water of 1:2:5).

[0066] d. Soak the rinsed SiC epitaxial material substrate in diluted hydrofluoric acid (hydrogen fluoride: deionized water = 1:3 by volume) for 1 minute to remove surface oxides, then rinse with deionized water and dry.

[0067] Step S2: growing a buffer layer. Figure 2 As shown, the n+ type buffer layer 20 is made of homogeneous materials, specifically including: Figure 2 As shown, it is obtained by physical or chemical vapor deposition, specifically: using chemical vapor deposition or physical vapor deposition methods to grow a homogeneous material n+ type buffer layer 20 onto the n++ type SiC substrate substrate 10 of the cleaned SiC material substrate, the growth source is SiH4 and C2H4, or other Si source and C source gases, the thickness of the n+ type buffer layer 20 is 0.5-5μm, the growth temperature of the n+ type buffer layer 20 is 1500-1700℃, and the doping source is NH3. For example, the doping concentration of the n+ type buffer layer 20 is 1×10 18 cm -3 -5×10 18 cm -3 , thickness is 0.5-2μm.

[0068] Step S3: growing a drift layer. Figure 3 and Figure 4 As shown, the drift layer includes an nx first drift layer 31 and an n- second drift layer 30. The nx first drift layer 31 and the n- second drift layer 30 are made of the same material, specifically including:

[0069] a. Figure 3 As shown, it is obtained by physical or chemical vapor deposition, specifically: using chemical vapor deposition or physical vapor deposition methods to grow a homogeneous material nx first drift layer 31 on the n+ type buffer layer 20, the growth source is SiH4 and C2H4, or other Si source and C source gases, the thickness of the nx first drift layer 31 accounts for 50-80% of the thickness of the entire drift layer, the growth temperature of the nx first drift layer 31 is 1500-1700℃, and the doping source is NH3. For example, the doping concentration of the nx first drift layer 31 is 1×10 16 cm -3, with a thickness of 5-8μm.

[0070] b. Figure 4 As shown, it is obtained by physical or chemical vapor deposition, specifically: using chemical vapor deposition or physical vapor deposition methods to grow the homogeneous material n-second drift layer 30 on the nx first drift layer 31, the growth source is SiH4 and C2H4, or other Si source and C source gases, the thickness of the n-second drift layer 30 accounts for 20-50% of the thickness of the entire drift layer, the growth temperature of the n-second drift layer 30 is 1500-1700℃, and the doping source is NH3. For example, the doping concentration of the n-second drift layer 30 is 5×10 15 cm -3 , with a thickness of 2-5μm.

[0071] Step S4: Make active area doping. Figure 5 As shown, the active area doping includes a p-well region 40, which is periodically arranged within the n-second drift layer 30. The bottom of the p-well region 40 does not exceed the bottom of the n-second drift layer 30, that is, it maintains a certain distance from the top of the nx first drift layer 31; a p+ type doping region 60, which is located within the p-well region 40; and an n+ type doping region 50, which is formed by self-aligned implantation and is located within the p-well region 40. Specifically, it includes:

[0072] Sub-step S4-1: Forming the p-well region 40. A mask layer is deposited on the n-second drift layer 300 using chemical vapor deposition or physical vapor deposition. The mask layer can be SiO2, Si3N4, polysilicon, or a metal. A photoresist A is used to perform photolithographic patterning to form an implantation mask layer. Ion implantation or other doping methods are then used to form the p-well region 40 in the n-second drift layer 30. The p-well region 40 is periodically arranged within the n-second drift layer 30. The bottom of the p-well region 40 does not exceed the bottom of the n-second drift layer 30, i.e., it maintains a certain distance from the top of the nx first drift layer 31. The p-well region 40 has a high doping concentration at the bottom and a low doping concentration at the surface. The doping concentration ranges from the surface to the bottom, and is 1×10 16 cm -3 ~2×10 18 cm -3 , with a depth of 0.7-1μm.

[0073] Sub-step S4-2: Make an n+ type doped region 50. Based on the injection mask layer formed by the photoresist A in step S4-1, a secondary mask is deposited by chemical vapor deposition or physical vapor deposition. The secondary mask can be SiO2 or Si3N4 or polysilicon. The secondary mask is etched to form a sidewall mask. The sidewall mask can also be obtained by other polysilicon oxidation methods. For details, please refer to the existing technology. Based on the sidewall mask, a doping method such as thermal diffusion or ion implantation is used to dope the p well area 40 to form an n+ type doped region 50. The doping element of the n+ type doped region 50 can be a donor-type element such as N, P or As. The doping concentration of the n+ type doped region 50 is 1×10 20 cm -3 ~1×10 21 cm -3 .

[0074] Sub-step S4-3: Forming the p+ doping region 60. Deposit a mask layer by chemical vapor deposition or physical vapor deposition. The mask layer may be SiO2, Si3N4, or polysilicon. Photolithography and etching are performed on the mask layer to form a base doping mask layer. The n+ doping region 50 is doped by thermal diffusion or ion implantation to form a p+ doping region 60. The doping element of the p+ doping region 60 may be an acceptor element such as B, Al, Ga, or Nb. The doping concentration of the p+ doping region 60 is 2×10 19 cm -3 ~1×10 21 cm -3 .

[0075] Step S5. Make a gate dielectric, such as Figure 6 As shown, specifically including:

[0076] Step S5-1: After high-temperature activation of the active area doping, sacrificial oxygen treatment is performed and the SiC surface is cleaned in a standard manner.

[0077] Step S5-2: Using thermal oxidation and post-oxidation annealing methods, dry oxygen oxidation is performed at 600°C to 1300°C for about half an hour, and annealing is performed at 600°C to 1300°C in a NO atmosphere for 1 to 3 hours. The annealing atmosphere is not limited to NO, but can also be POCl3, H2, N2O, P2O5, Sb+NO, etc., to finally obtain a gate dielectric 70. The gate dielectric 70 can also be obtained by physical or chemical vapor deposition or atomic layer deposition, and the gate dielectric 70 can also be other insulating materials such as Si x N y (x, y is the element ratio) and high-k dielectric materials such as Al2O3, AlN, AlON, HfO2 and their combinations.

[0078] Step S6. Make gate electrode contact 80, such as Figure 7 As shown, specifically including:

[0079] Sub-step S6 - 1 : using a thin film deposition technique such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., to deposit highly doped polysilicon on the surface where the gate dielectric 70 has been formed.

[0080] Sub-step S6-2: Then use the photolithography mask and physical, chemical etching methods, such as reactive ion etching (RIE) or inductively coupled plasma (ICP), to dry-etch the deposited highly doped polysilicon, and finally form a gate electrode contact 80 on the surface of the gate dielectric 70. The left and right ends of the gate electrode contact 80 are at a certain distance from the boundary of the n+ type doped region 50, and the distance is 0.5-3μm. The gate electrode contact 80 does not exist above the p+ type doped region 60.

[0081] Step S7. Make a passivation layer, such as Figure 8 As shown, specifically including:

[0082] a. Using physical vapor deposition, chemical vapor deposition, atomic layer deposition and other thin film deposition techniques, an inner insulating material 90 is deposited on the SiC substrate on which the gate electrode contact 80 has been formed. The inner insulating material 90 has a platform surface.

[0083] b. Utilize photolithographic patterning and dry-etch the inner insulating material 90 by physical or chemical etching methods, such as reactive ion etching (RIE) or inductively coupled plasma (ICP). The etching gas used for the dry etching can be a gas combination of SF6 / O2, NF3 / Ar, CF4, CHF3 / O2, C4F8 / O2, etc., so that holes are opened in the inner insulating material 90, and the opening positions expose the surfaces of the n+ doped region 50 and the p+ doped region 60.

[0084] Step S8. Make an ohmic contact, the ohmic contact includes a source electrode contact 100 and a drain electrode contact 110, such as Figure 9 As shown, specifically including:

[0085] Sub-step S8-1: Photolithography patterning, using a thin film deposition method such as electron beam evaporation or sputtering to sequentially deposit multiple layers of metals such as Ni, Ti, and Al, and then peeling them off to form a source electrode contact 100, which is located on the upper surfaces of the n++-type doped region 100 and the p++-type doped region 110.

[0086] Sub-step S8-2: The front side of the SiC substrate is coated with photoresist for protection. The oxide layer on the back side of the n++-type SiC substrate 10 is removed using diluted HF. A metal layer is deposited on the back side using a thin film deposition method such as electron beam evaporation or sputtering. The metal layer can be made of a metal such as AlTi, Ni, TiW, AlTi, or a combination thereof to form the drain electrode contact 110. The front side photoresist is then removed. Sub-step S8-3: The source electrode contact 100 and the drain electrode contact 110 are annealed in nitrogen or argon at a temperature range of 900°C to 1100°C to form ohmic contacts.

[0087] Step S9. Make the pad metal layer 120, such as Figure 10 As shown, a thick metal layer is deposited on the front of the SiC substrate using thin film deposition methods such as electron beam evaporation or sputtering to interconnect the source electrode contact 100 and form a pad metal layer 120. This completes the preparation of a SiC-based MOSFET device with both low on-resistance and high breakdown voltage.

[0088] refer to Figure 10 The SiC-based MOSFET device is manufactured, comprising an n++-type SiC substrate substrate 10; an n+-type buffer layer 20 grown on the n++-type SiC substrate substrate 10; an nx first drift layer 31 grown on the n+-type buffer layer 20; an n-second drift layer 30 grown on the nx first drift layer 31; a p-well region 40 periodically arranged within the n-second drift layer 30, wherein the bottom of the p-well region 40 does not exceed the bottom of the n-second drift layer 30, i.e., maintains a certain distance from the top of the nx first drift layer 31; a p+-type doped region 60 located within the p-well region 40; an n+-type doped region 50 formed by self-aligned implantation and located within the p-well region 40; and a gate dielectric 70 located between the n+-type doped region 50, the p-well region 40, and the n-type doped region 50. The well region 40 and the upper surface of the n-second drift layer 30; the gate electrode contact 80, located on the upper surface of the gate dielectric 70; the inner insulating material 90, completely covering the gate electrode contact 80 and the gate dielectric 70; the source electrode contact 100, located on the upper surface of the n++ type doped region 100 and the p++ type doped region 110; the drain electrode contact 110, located on the back side of the n++ type SiC substrate substrate 10; and the pad metal layer 120, located on the front side of the SiC substrate, interconnecting the source electrode contact 100.

[0089] Example 2

[0090] Steps S1-S2 and steps S4-S9 of the method for preparing a SiC-based MOSFET device in the second embodiment are the same as those in the first embodiment, except that:

[0091] Step S3: growing a drift layer. Figure 11 and Figure 12As shown, the drift layer includes an nx first drift layer 31 and an n- second drift layer 30. The nx first drift layer 31 and the n- second drift layer 30 are made of the same material, specifically including:

[0092] a. Figure 11 As shown, it is obtained by physical or chemical vapor deposition, specifically: using chemical vapor deposition or physical vapor deposition methods to grow a homogeneous material nx first drift layer 31 onto the n+ type buffer layer 20, the growth source is SiH4 and C2H4, or other Si source and C source gases, the growth temperature is 1500-1700℃, and the doping source is NH3. The nx first drift layer 31 includes a multi-layer structure from bottom to top. As an example, the nx first drift layer includes a three-layer structure of nx1, nx2 and nx3. By regulating the flow rate of the doping source to reduce in stages, the doping concentrations of nx1, nx2 and nx3 are reduced in sequence, but the doping concentrations of nx1, nx2 and nx3 are all higher than the n- second drift layer 30 grown later. For example, the doping concentration of the nx1 layer is 5×10 16 cm -3 , with a thickness of 1-2 μm; the doping concentration of the nx2 layer is 3×10 16 cm -3 , with a thickness of 2-3 μm; the doping concentration of the nx3 layer is 1×10 16 cm -3 , with a thickness of 2-3μm.

[0093] b. Figure 12 As shown, it is obtained by physical or chemical vapor deposition, specifically: using chemical vapor deposition or physical vapor deposition methods to grow the homogeneous material n- second drift layer 30 on the nx first drift layer 31, the growth source is SiH4 and C2H4, or other Si source and C source gases, the growth temperature is 1500-1700℃, and the doping source is NH3. The thickness of the n- second drift layer 30 is 2-5μm, and the doping concentration is 5×10 15 cm -3 .

[0094] Finally, after steps S4-S9, a SiC-based MOSFET device with both low on-resistance and high breakdown voltage is prepared, such as Figure 12 shown.

[0095] In this embodiment, the nx first drift layer has a step-wise change in doping concentration, wherein the lower doping concentration nx3 layer can improve the blocking characteristics of the device, and the high doping concentration nx1 layer can improve the conduction capability of the device. At the same time, the high doping concentration nx1 layer can also improve the turn-off capability of the device when the body diode is turned on, so that the MOSFET can have a higher switching speed when used in the field of high-frequency circuits.

[0096] Example 3

[0097] Steps S1-S2 and steps S4-S9 of the method for preparing a SiC-based MOSFET device in the third embodiment are the same as those in the first embodiment, except that:

[0098] Step S3: growing a drift layer. Figure 13 and Figure 14 As shown, the drift layer includes an nx first drift layer 31 and an n- second drift layer 30. The nx first drift layer 31 and the n- second drift layer 30 are made of the same material, specifically including:

[0099] a. Figure 13 As shown, it is obtained by physical or chemical vapor deposition, specifically: a homogeneous material nx first drift layer 31 is grown on the n+ type buffer layer 20 by chemical vapor deposition or physical vapor deposition, the growth source is SiH4 and C2H4, or other Si source and C source gases, the growth temperature is 1500-1700℃, and the doping source is NH3. By controlling the flow rate of the doping source to gradually decrease, a gradient doping structure is formed from bottom to top in the nx first drift layer 31. The doping concentration of the nx first drift layer 31 decreases from bottom to top, but the doping concentration of the nx first drift layer 31 is higher than that of the n- second drift layer 30 grown later. The thickness of the nx first drift layer 31 accounts for 50-80% of the thickness of the entire drift layer. For example, the thickness is 5-8μm, and the doping concentration is from 1×10 17 cm -3 The doping concentration of the second drift layer 30d is uniformly changed to n-, for example, 5×10 15 cm -3 .

[0100] b. Figure 14 As shown, it is obtained by physical or chemical vapor deposition, specifically: using chemical vapor deposition or physical vapor deposition methods to grow the homogeneous material n- second drift layer 30 onto the nx first drift layer 31, the growth source is SiH4 and C2H4, or other Si source and C source gas, the growth temperature is 1500-1700℃, and the doping source is NH3.

[0101] Finally, after steps S4-S6, a SiC-based MOSFET device with both low on-resistance and high breakdown voltage is prepared, such as Figure 14 shown.

[0102] In this embodiment, the blocking characteristics of the device can be further improved without sacrificing the conduction characteristics by using the nx first drift layer with a gradually varying doping concentration. In particular, the concentration of the initial nx first drift layer is closer to that of the n+ type buffer layer 10, thereby reducing interface-related defects and improving the reliability of the device under electrical stress.

[0103] The substrate materials used in the specific embodiments described above are not limited to SiC materials and may also include power electronic semiconductor materials such as silicon, gallium nitride, gallium oxide, and diamond. When other semiconductor materials are used as substrates, the resulting DMOSFET devices and preparation methods that have both high on-state capability and low Miller charge are also included within the scope of protection of this disclosure.

[0104] Typically, increasing the drift layer doping as much as possible actually reduces blocking characteristics. To achieve both high blocking voltage and low on-resistance, design optimization requires that the thickness of the low-doped n-second drift layer account for 20%-50% of the total drift layer thickness, while the thickness of the highly-doped nx first drift layer accounts for 50%-80% of the total drift layer thickness. The distance between the bottom of the p-well region and the bottom of the n-second drift layer is 80%-90% of the thickness of the n-second drift layer. If this distance is too small, it can easily lead to high electric field focusing in the PN junction region of the device, causing premature device breakdown.

[0105] Comparative Example 1

[0106] The present invention is extended to high voltage devices. The difference between the comparative example 1 and the embodiment 1 is that the drift layer adopts a uniform doping concentration of 1.2×10 15 cm -3 , with a thickness of 60μm.

[0107] refer to Figure 15 It can be seen that when the nx first drift layer of Example 1 is 1.7×10 15 cm -3 and n-second drift layer 1.2×10 15 cm -3 After segmented doping, the on-current is significantly improved.

[0108] The above embodiments are only used to further illustrate a low on-resistance SiC-based MOSFET device and a preparation method thereof of the present invention, but the present invention is not limited to the embodiments. Any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention fall within the scope of protection of the technical solution of the present invention.

Claims

1. A low on-resistance SiC-based MOSFET device, characterized by: From bottom to top, it includes a drain electrode contact, an n++ type SiC substrate and a SiC epitaxial layer, and also includes a gate dielectric, a gate electrode contact, an internal insulating material, a source electrode contact and a source pad metal layer arranged above the SiC epitaxial layer; the SiC epitaxial layer includes an n+ type buffer layer and a drift layer from bottom to top, the drift layer includes an nx first drift layer arranged on the n+ type buffer layer and an n- second drift layer arranged on the nx first drift layer, a p well region is provided in the n- second drift layer, and an n+ type doped region and a p+ type doped region are provided in the p well region; wherein, The nx first drift layer and the n- second drift layer are made of the same material and doped with the same impurities. The doping concentration of the nx first drift layer is higher than that of the n- second drift layer, and the thickness of the n- second drift layer accounts for 20%-50% of the total drift layer thickness. The distance between the bottom of the p well region and the bottom of the n- second drift layer is 80%-90% of the thickness of the n- second drift layer.

2. The low on-resistance SiC-based MOSFET device according to claim 1, characterized in that: The nx first drift layer includes at least two stacked doping layers, and the doping concentration of the doping layers decreases stepwise from bottom to top.

3. The low on-resistance SiC-based MOSFET device according to claim 1, characterized in that: The nx first drift layer is gradually doped from bottom to top, and the doping concentration gradually decreases.

4. The low on-resistance SiC-based MOSFET device according to claim 2 or 3, characterized in that: The doping concentration of the nx first drift layer is between 1×10 15 cm -3 ~1×10 17 cm -3 between.

5. The low on-resistance SiC-based MOSFET device according to claim 1, characterized in that: The doping concentration of the n-second drift layer is in the range of 1×10 14 cm -3 ~1×10 16 cm -3 , thickness range is 2-5μm.

6. The low on-resistance SiC-based MOSFET device according to claim 1, characterized in that: The p well region is located on both sides of the upper part of the n-second drift layer, the gate dielectric and the gate electrode contact are sequentially stacked in the middle of the surface of the n-second drift layer, the source electrode contact is located on the p+ doped region, the source electrode contact is connected to the source pad metal layer, and the internal insulating material separates the gate electrode contact from the source electrode contact and the source pad metal layer.

7. A method for preparing a low on-resistance SiC-based MOSFET device according to any one of claims 1 to 6, characterized in that: The following steps are involved: 1) Growing an n+ type buffer layer on an n++ type SiC substrate; 2) growing an nx first drift layer with a higher doping concentration on the n+ type buffer layer, and growing an n- second drift layer with a lower doping concentration on the nx first drift layer; 3) Doping the active region to form a p-well region, an n+ type doping region, and a p+ type doping region on the upper part of the n- second drift layer; 4) forming a gate dielectric on the n-second drift layer; 5) Making gate electrode contacts on the gate dielectric; 6) Making an inner insulating material covering the gate electrode contact; 7) Fabricating ohmic contacts, including a drain electrode contact located on the bottom surface of the n++ type SiC substrate and a source electrode contact located outside the inner insulating material; 8) Make a source pad metal layer that contacts the source electrode.

8. The preparation method according to claim 7, characterized in that: In the step 2), the drift layer is grown by chemical vapor deposition process, the growth temperature is 1500-1700° C., the doping source is NH 3, and the doping concentration is controlled by controlling the doping source flow rate.

9. The preparation method according to claim 8, characterized in that: During the growth of the nx first drift layer, the flow rate of the doping source is fixed, reduced in stages, or reduced gradually.

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