A GaN-based HFETs device and a method for controlling strain under the gate thereof

Abstract

The present invention discloses a GaN-based HFET device, comprising a SiC substrate, an AlN nucleation layer, and a GaN channel layer stacked sequentially from bottom to top. A source and drain are symmetrically arranged above the GaN channel layer, with an AlN intercalation layer, a barrier layer, and a gate disposed between the source and drain. A gate dielectric is disposed in the center portion above the barrier layer, and the gate is fixed to the upper surface of the gate dielectric. The gate dielectric comprises a multilayer composite of multiple gate dielectric blocks, with any two adjacent gate dielectric blocks having different dielectric constants. Al2O3 passivation layers are formed on both sides of the gate dielectric by atomic layer deposition. The above-described technical solution further adjusts the electrical characteristics of the GaN-based HFET device by disposing multiple gate dielectrics with different dielectric constants below the gate. This novel adjustment method, combined with existing control methods, can effectively improve the transport characteristics of the GaN-based HFET device, enabling its application in high-power and power electronics fields.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic components, and in particular to a GaN-based HFETs device and a method for controlling strain under the gate thereof. Background Art

[0002] GaN-based heterojunction field-effect transistors (HFETs) have broad application prospects in high-power and power electronics due to their high two-dimensional electron gas (2DEG) concentration and high breakdown field strength. GaN-based materials exhibit strong spontaneous and piezoelectric polarization effects, allowing a high concentration of two-dimensional electron gas (2DEG) to form in the channel of GaN-based HFETs even when the gate voltage is zero. The transport properties of the 2DEG are a key concern in GaN-based HFET device research.

[0003] In order to improve the transport characteristics of 2DEG in GaN-based HFETs, researchers at home and abroad have made great efforts in materials, structures, processes, etc. and have made great progress. At present, there are two main aspects to adjust the transport characteristics. On the one hand, the gate bias V GS By controlling the concentration of 2DEG, the on-off of the transport channel is determined, thereby controlling the lateral leakage current I DS However, the above-mentioned adjustment method has certain limitations and cannot meet the application requirements of GaN-based HFETs in high-power and power electronics fields.

[0004] On the other hand, in GaN-based HFETs, polarized Coulomb field scattering, which is related to the strain distribution in the barrier layer below the gate, is another important factor affecting the transport properties of the 2DEG. Therefore, the study of the strain below the gate in GaN-based HFETs is of great significance. Therefore, it is necessary to propose a GaN-based HFET device and a method for regulating the strain below the gate. Summary of the Invention

[0005] In view of the deficiencies of the existing technology, the present invention proposes a GaN-based HFETs device and a method for controlling the strain under the gate thereof. This method provides a new direction for regulating the electrical characteristics of GaN-based HFETs devices and further improves the transport characteristics of GaN-based HFETs devices.

[0006] In order to solve the above technical problems, the technical solution of the present invention is:

[0007] A GaN-based HFET device comprises a SiC substrate, an AlN nucleation layer, and a GaN channel layer stacked in sequence from bottom to top; a source and a drain are symmetrically arranged above the GaN channel layer; an AlN intercalation layer, a barrier layer, and a gate are arranged between the source and drain; a gate dielectric is provided in the middle portion above the barrier layer; the gate is fixed to the upper surface of the gate dielectric; the gate dielectric comprises a multilayer composite of several gate dielectric blocks; the dielectric constants of any two adjacent gate dielectric blocks are different; and an Al2O3 passivation layer is formed on both sides of the gate dielectric by atomic layer deposition.

[0008] Preferably, the gate dielectric includes five gate dielectric blocks, and the five gate dielectric blocks are SiO2 / Al2O3 / HfO2 / Al2O3 / AlN from the source side to the drain side.

[0009] Preferably, the sum of the lengths of all the dielectric blocks under the gate is the same as the length of the gate.

[0010] Preferably, the gate is formed by a double layer of Ni and Au, wherein the thickness of Ni and Au are 60 nm and 160 nm respectively.

[0011] Preferably, the barrier layer is made of Al 0.21 Ga 0.79 N, and its thickness is 23nm.

[0012] Preferably, both ends of the barrier layer are connected to the source and the drain respectively through an ohmic contact process, and the ohmic contact metal at both ends of the barrier layer connected to the source and the drain respectively is a four-layer composite metal of Ti, Al, Ni, and Au.

[0013] Preferably, there is a two-dimensional electron gas at the interface between the GaN channel layer and the AlN intercalation layer and on the side of the GaN channel layer.

[0014] The present invention also provides a method for regulating the under-gate strain of a GaN-based HFETs device, characterized in that a under-gate dielectric composed of a plurality of under-gate dielectric blocks with different dielectric constants is arranged under the gate, and the under-gate strain is regulated by adjusting the number of under-gate dielectric blocks and the length and thickness of the under-gate dielectric.

[0015] The present invention has the following characteristics and beneficial effects:

[0016] The above technical solution, by disposing multiple gate dielectrics with different dielectric constants below the gate, ensures that when a gate voltage is applied to the device, the voltage drops across the gate dielectrics with different dielectric constants are different. This obviously results in different voltage drops across the AlGaN barrier layer under the gate corresponding to the gate dielectrics with different dielectric constants. Furthermore, due to the inverse piezoelectric effect, the strain of the AlGaN barrier layer under the gate will also vary along the channel from the gate near the source end to the gate near the drain end, thereby enabling the regulation of the strain of the gate barrier layer. Changes in strain will lead to changes in strain-related polarization Coulomb field scattering under the gate, which has a significant impact on the device's electrical properties. This helps further regulate the electrical properties of GaN-based HFETs. This new regulation method, combined with existing regulation methods, can effectively improve the transport characteristics of GaN-based HFETs, enabling their application in high-power and power electronics fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 2 is a structural diagram of an embodiment of the present invention.

[0019] In the figure, 1-SiC substrate, 2-AlN nucleation layer, 3-GaN channel layer, 4-two-dimensional electron gas, 5-AlN intercalation layer, 6-barrier layer, 7-source, 8-gate, 9-drain, 10-Al2O3 passivation layer, 11-under-gate dielectric block. DETAILED DESCRIPTION

[0020] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0021] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0022] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0023] The present invention provides a GaN-based HFETs device, such as Figure 1 As shown, the device comprises a SiC substrate 1, an AlN nucleation layer 2, and a GaN channel layer 3 stacked sequentially from bottom to top. A source 7 and a drain 9 are symmetrically arranged above the GaN channel layer 3. An AlN intercalation layer 5, a barrier layer 6, and a gate 8 are positioned between the source 7 and drain 9. A gate dielectric is positioned above and in the middle of the barrier layer 6. The gate 8 is fixed to the upper surface of the gate dielectric. The gate dielectric comprises a multilayer composite of multiple gate dielectric blocks 11. Any two adjacent gate dielectric blocks have different dielectric constants. Al2O3 passivation layers 10 are formed on both sides of the gate dielectric by atomic layer deposition. A two-dimensional electron gas 4 is present at the interface between the GaN channel layer 3 and the AlN intercalation layer 5, and on the GaN channel layer 3 side.

[0024] In the above technical solution, the gate dielectric is improved so that it is composed of a plurality of gate dielectric blocks 11. By arranging a plurality of gate dielectrics with different dielectric constants under the gate, when a gate voltage is applied to the device, the voltage drops on the gate dielectrics with different dielectric constants are different. This obviously makes the voltage drops on the gate AlGaN barrier layer under the gate corresponding to the gate dielectrics with different dielectric constants different. Due to the inverse piezoelectric effect, the strain of the gate AlGaN barrier layer will also be different along the channel from the gate near the source end to the gate near the drain end, thereby realizing the regulation of the strain of the gate barrier layer, and further effectively adjusting the gate strain of the GaN-based HFETs device.

[0025] The gate 8 is fabricated using a Schottky process and is composed of a double-layer Ni and Au composite, where the lengths of the Ni and Au layers are 60 nm and 160 nm, respectively. Specifically, in this embodiment, the under-gate dielectric includes five under-gate dielectric blocks 11. The five under-gate dielectric blocks 11 are composed of SiO2 / Al2O3 / HfO2 / Al2O3 / AlN, in the order from the source 7 to the drain 9. The sum of the lengths of all under-gate dielectric blocks 11 is the same as the length of the gate 8.

[0026] Furthermore, the barrier layer 6 is made of Al 0.21 Ga 0.79 The two ends of the barrier layer 6 are connected to the source 7 and the drain 9 respectively through the ohmic contact process, and the ohmic contact metal connecting the two ends of the barrier layer 6 with the source 7 and the drain 9 respectively is a four-layer composite metal of Ti, Al, Ni and Au.

[0027] The present invention also provides a method for regulating the under-gate strain of a GaN-based HFETs device, wherein a under-gate dielectric composed of a plurality of under-gate dielectric blocks 11 with different dielectric constants is arranged under the gate 8. The under-gate strain is regulated by adjusting the number of under-gate dielectric blocks 11 and the length and thickness of the under-gate dielectric.

[0028] It can be understood that by arranging a plurality of gate dielectrics with different dielectric constants under the gate, when the gate voltage is applied to the device, the voltage drop on the gate dielectrics with different dielectric constants is different, which obviously makes the voltage drop on the gate AlGaN barrier layer under the gate corresponding to the gate dielectrics with different dielectric constants different; and due to the inverse piezoelectric effect, the strain of the gate AlGaN barrier layer will also be different along the channel from the gate near the source end to the gate near the drain end, thereby realizing the regulation of the strain of the gate barrier layer, and then effectively adjusting the gate strain of the GaN-based HFETs device.

[0029] Finally, it should be noted that the embodiments in this specification are intended only to illustrate the specific technical solutions of the present invention and are not intended to be limiting. It should be understood that the gate dielectrics described above with multiple dielectric constants under the gate can include N materials with different dielectric constants; and that there are multiple combinations of these N materials with different dielectric constants from the gate near the source to the gate near the drain, ensuring that the dielectric constants of adjacent portions are different. Therefore, modifications or improvements made by those skilled in the art based on the present invention also fall within the scope of protection claimed by the present invention.

[0030] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. It will be apparent to those skilled in the art that various changes, modifications, substitutions, and variations of these embodiments, including components, without departing from the principles and spirit of the present invention are still within the scope of protection of the present invention.

Claims

1. A GaN-based HFETs device, comprising a SiC substrate (1), an AlN nucleation layer (2), and a GaN channel layer (3) stacked in sequence from bottom to top, wherein a source electrode (7) and a drain electrode (9) are symmetrically arranged above the GaN channel layer (3), and an AlN intercalation layer (5), a barrier layer (6), and a gate electrode (8) are arranged between the source electrode (7) and the drain electrode (9), characterized in that: A gate dielectric is provided in the middle portion above the barrier layer (6), the gate (8) is fixed on the upper surface of the gate dielectric, the gate dielectric comprises a plurality of gate dielectric blocks (11) formed by multilayer composite, the dielectric constants of any two adjacent gate dielectric blocks are different, an Al2O3 passivation layer (10) is formed on both sides of the gate dielectric by atomic layer deposition, the gate dielectric comprises five gate dielectric blocks (11), the five gate dielectric blocks (11) are SiO2 / Al2O3 / HfO2 / Al2O3 / AlN from the side near the source (7) to the side near the drain (9), and a two-dimensional electron gas (4) is present at the interface between the GaN channel layer (3) and the AlN intercalation layer (5) and on the side of the GaN channel layer (3).

2. The GaN-based HFETs device according to claim 1, characterized in that: The sum of the lengths of all the dielectric blocks (11) under the gate is the same as the length of the gate (8).

3. The GaN-based HFETs device according to claim 1, characterized in that: The gate (8) is composed of a double layer of Ni and Au, wherein the thicknesses of Ni and Au are 60 nm and 160 nm respectively.

4. The GaN-based HFETs device according to claim 1, characterized in that: The barrier layer (6) is made of Al 0.21 Ga 0.79 N, and its thickness is 23nm.

5. The GaN-based HFETs device according to claim 1, characterized in that: The two ends of the barrier layer (6) are respectively connected to the source electrode (7) and the drain electrode (9) through an ohmic contact process, and the ohmic contact metal for respectively connecting the two ends of the barrier layer (6) to the source electrode (7) and the drain electrode (9) is a four-layer composite metal of Ti, Al, Ni, and Au.

6. A method for controlling the under-gate strain of a GaN-based HFET device according to claim 1, characterized in that: A sub-gate dielectric composed of a plurality of sub-gate dielectric blocks (11) with different dielectric constants is provided below the gate (8), and the sub-gate strain is regulated by adjusting the number of sub-gate dielectric blocks (11) and the length and thickness of the sub-gate dielectric.

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