A level shifting circuit

Abstract

The application discloses a level shift circuit, and the application adds resistors between the D pole of a PMOS tube Mp1 and a node n1 and between the D pole of a PMOS tube Mp2 and a node n2, so that all competition risks in the level conversion process are eliminated; on the basis of the added resistors, a speed-up auxiliary circuit is added, the switching speed of the overall circuit is improved through the auxiliary circuit, and a steady-state high-speed level shift circuit is realized.

Description

Technical Field

[0001] This invention relates to a level shifting circuit, belonging to the field of semiconductor device technology. Background Technology

[0002] In next-generation electronic circuit design, with the application of different voltage logic, input-output logic level mismatches frequently occur in the system, as well as signal voltage transmission voltage mismatches arising from different modules operating at different voltages in integrated circuits. This necessitates the introduction of level conversion, using level-shifter circuits to convert low voltages to high voltages to meet the operational requirements between inputs / outputs and between modules. To ensure the overall circuit performance, level-shifter circuits must possess low power consumption characteristics.

[0003] Existing level shifting circuits such as Figure 1 As shown, the circuit includes inverters inv1 and inv2, NMOS transistors Mn1 and Mn2, PMOS transistors Mp1 and Mp2. The output of inverter inv1 is connected to the gate (G) of NMOS transistor Mn1 and the input of inverter inv1. The output of inverter inv2 is connected to the gate (G) of NMOS transistor Mn2. The source (S) of NMOS transistors Mn1 and Mn2 is connected to VSS (ground). The drain (D) of NMOS transistor Mn1 is connected to the drain (D) of PMOS transistor Mp1 and the gate (G) of PMOS transistor Mp2. The drain (D) of NMOS transistor Mn2 is connected to the gate (G) of PMOS transistor Mp1 and the drain (D) of PMOS transistor Mp2. The source (S) of PMOS transistors Mp1 and Mp2 is connected to VDD (high voltage power supply voltage signal). The common connection point of the drain of NMOS transistor Mn1, the drain of PMOS transistor Mp1, and the gate of PMOS transistor Mp2 is node n1. The common connection point of the drain of NMOS transistor Mn2, the gate of PMOS transistor Mp1, and the drain of PMOS transistor Mp2 is node n2. Nodes n1 and n2 can be used as the two output terminals Vout1 and Vout2 of the circuit, respectively.

[0004] Figure 1The circuit in the whole is a cross-coupling structure, which can accelerate the conversion of control signals. Vin is a logic signal inputted into the input end of the inverter inv1, VDD1 is a power voltage of a low-voltage control signal, the low-voltage control signal is first amplified through the inverter inv1, and then a pair of complementary logic control signals are formed at the G poles of the NMOS tubes Mn1 and Mn2 through the inverter inv2. The working principle of the circuit is as follows: when Vin is VSS, the NMOS tube Mn1 is opened, the NMOS tube Mn2 is turned off, the NMOS tube Mn1 discharges the n1 point, the n1 potential is lowered, the PMOS tube Mp2 is gradually opened, the n2 point potential is pulled up, the PMOS tube Mp1 is gradually turned off, and the n1 potential is locked at VSS, which contains a positive feedback loop. When the input signal Vin is VDD1, the level logic is opposite to the above.

[0005] The existing level shift circuit has the following disadvantages: there is a risk of competition in the level conversion process. For example: when Vin is VSS, the NMOS tube Mn1 competes with the PMOS tube Mp1, the condition for forming a positive feedback is that the node n1 potential is pulled to VSS, before being pulled down, the NMOS tube Mn1 and the PMOS tube Mp1 will exist in a state of being opened, the node n1 potential will exist in a competitive relationship, and a large competitive current will be generated. With the decrease of VDD1, the down-pulling ability of the NMOS tubes Mn1 and Mn2 becomes weaker, and the competition ability with the PMOS tubes Mp1 and Mp2 becomes weaker, and the overall conversion becomes difficult. SUMMARY

[0006] The present application provides a level shift circuit, which solves the problem of competition risk in the level conversion process of the existing circuit.

[0007] In order to solve the above technical problems, the technical scheme adopted by the present application is:

[0008] The level shift circuit comprises an inverter inv1, an inverter inv2, an NMOS transistor Mn1, an NMOS transistor Mn2, a PMOS transistor Mp1 and a PMOS transistor Mp2, the output end of the inverter inv1 is connected to the G electrode of the NMOS transistor Mn1 and the input end of the inverter inv1, the output end of the inverter inv2 is connected to the G electrode of the NMOS transistor Mn2, the D electrode of the NMOS transistor Mn1 is connected to the D electrode of the PMOS transistor Mp1 and the G electrode of the PMOS transistor Mp2, the D electrode of the NMOS transistor Mn2 is connected to the G electrode of the PMOS transistor Mp1 and the D electrode of the PMOS transistor Mp2, the D electrode of the NMOS transistor Mn1, the D electrode of the PMOS transistor Mp1 and the G electrode of the PMOS transistor Mp2 are jointly connected to a node n1, the D electrode of the NMOS transistor Mn2, the G electrode of the PMOS transistor Mp1 and the D electrode of the PMOS transistor Mp2 are jointly connected to a node n2, and the level shift circuit further comprises resistors R1 and R2, the resistor R1 is connected in series between the D electrode of the PMOS transistor Mp1 and the node n1, and the resistor R2 is connected in series between the D electrode of the PMOS transistor Mp2 and the node n2.

[0009] The level shift circuit further comprises a first speed-up circuit and a second speed-up circuit, the first speed-up circuit and the second speed-up circuit are arranged between the node n1 and the node n2, and the first speed-up circuit and the second speed-up circuit are used to improve the switching speed of the voltage rise of the node n1 and the node n2.

[0010] The first speed-up circuit comprises a PMOS transistor Mp3, a resistor R3 and a capacitor C1, the S electrode of the PMOS transistor Mp3 is connected to a high-voltage power supply voltage signal VDD, the D electrode of the PMOS transistor Mp3 is connected to the node n1, one end of the resistor R3 is connected to the high-voltage power supply voltage signal VDD, the other end of the resistor R3 is connected to the G electrode of the PMOS transistor Mp3 and one end of the capacitor C1 respectively, and the other end of the capacitor C1 is connected to the node n2.

[0011] The resistor R3 is further connected to a first voltage protection device, and the first voltage protection device is used to protect the voltage at a node n3; wherein the node n3 is a common connection of the PMOS transistor Mp3, the resistor R3 and the capacitor C1.

[0012] The first voltage protection device is a diode D1, an NMOS transistor Mn3 or a PMOS transistor Mp7.

[0013] If the first voltage protection device is the diode D1, the negative electrode of the diode D1 is connected to the high-voltage power supply voltage signal VDD, and the positive electrode of the diode D1 is connected to the node n3.

[0014] If the first voltage protection device is the NMOS transistor Mn3, the S electrode of the NMOS transistor Mn3 is connected to the high-voltage power supply voltage signal VDD, and the G electrode, the D electrode and the B electrode of the NMOS transistor Mn3 are all connected to the node n3.

[0015] If the first voltage protection device is the PMOS tube Mp7, the S pole of the PMOS tube Mp7 is connected to the node n3, and the G pole, the D pole and the B pole of the PMOS tube Mp7 are all connected to the high-voltage power supply voltage signal VDD.

[0016] The second speed-up circuit comprises the PMOS tube Mp4, the resistor R4 and the capacitor C2, the S pole of the PMOS tube Mp4 is connected to the high-voltage power supply voltage signal VDD, the D pole of the PMOS tube Mp4 is connected to the node n2, one end of the resistor R4 is connected to the high-voltage power supply voltage signal VDD, the other end of the resistor R4 is respectively connected to the G pole of the PMOS tube Mp4 and one end of the capacitor C2, and the other end of the capacitor C2 is connected to the node n1.

[0017] The resistor R4 is also connected to the second voltage protection device at both ends, and the second voltage protection device is used to protect the voltage at the node n4; wherein the node n4 is the common connection of the PMOS tube Mp4, the resistor R4 and the capacitor C2.

[0018] The second voltage protection device is the diode D2, the NMOS tube Mn4 or the PMOS tube Mp8;

[0019] If the second voltage protection device is the diode D2, the negative pole of the diode D2 is connected to the high-voltage power supply voltage signal VDD, and the positive pole of the diode D2 is connected to the node n4;

[0020] If the second voltage protection device is the NMOS tube Mn4, the S pole of the NMOS tube Mn4 is connected to the high-voltage power supply voltage signal VDD, and the G pole, the D pole and the B pole of the NMOS tube Mn4 are all connected to the node n4;

[0021] If the second voltage protection device is the PMOS tube Mp8, the S pole of the PMOS tube Mp8 is connected to the node n4, and the G pole, the D pole and the B pole of the PMOS tube Mp8 are all connected to the high-voltage power supply voltage signal VDD.

[0022] The first output circuit and the second output circuit are further included;

[0023] The first output circuit comprises the NMOS tube Mn5 and the PMOS tube Mp5, the S pole of the NMOS tube Mn5 is connected to the ground, the G pole of the NMOS tube Mn5 is connected to the output end of the inverter inv1, the D pole of the NMOS tube Mn5 is connected to the D pole of the PMOS tube Mp5, the S pole of the PMOS tube Mp5 is connected to the high-voltage power supply voltage signal VDD, the G pole of the PMOS tube Mp5 is connected to the G pole of the PMOS tube Mp1, and the midpoint between the NMOS tube Mn5 and the PMOS tube Mp5 is replaced by the node n1 as a new output end Vout1;

[0024] The second output circuit comprises an NMOS transistor Mn6 and a PMOS transistor Mp6, the S pole of the NMOS transistor Mn6 is connected to the ground, the G pole of the NMOS transistor Mn6 is connected to the output end of the inverter inv2, the D pole of the NMOS transistor Mn6 is connected to the D pole of the PMOS transistor Mp6, the S pole of the PMOS transistor Mp6 is connected to the high-voltage power supply voltage signal VDD, the G pole of the PMOS transistor Mp6 is connected to the G pole of the PMOS transistor Mp2, and the midpoint between the NMOS transistor Mn6 and the PMOS transistor Mp6 is replaced by a node n2 as a new output end Vout2.

[0025] The present application has the following advantages: 1. The present application adds resistors between the D pole of the PMOS transistor Mp1 and the node n1 and between the D pole of the PMOS transistor Mp2 and the node n2, which eliminates all the risks of competition in the level conversion process; 2. The present application adds a speed-up circuit on the basis of adding resistors, which improves the switching speed through the speed-up circuit and realizes a steady-state high-speed level shift circuit; 3. The present application also adds a one-stage output circuit, which isolates the influence of the output load connected to Vout1 and Vout2 on the nodes n1 and n2, makes the switching speed of the voltage of the nodes n1 and n2 faster, improves the switching speed of the overall circuit, and also improves the driving capability of Vout1 and Vout2. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 It is a circuit diagram of a traditional level shift circuit;

[0027] Figure 2 It is a circuit diagram after adding resistors on the basis of Figure 1 ;

[0028] Figure 3 It is a circuit diagram after adding a speed-up circuit on the basis of Figure 2 ;

[0029] Figure 4 It is a circuit diagram using an NMOS transistor as a voltage protection device;

[0030] Figure 5 It is a circuit diagram using a PMOS transistor as a voltage protection device;

[0031] Figure 6 It is a circuit diagram after adding a one-stage output on the basis of Figure 3 ;

[0032] Figure 7 It is a simulation comparison diagram of the two circuits. DETAILED DESCRIPTION

[0033] The present application will be further described below in conjunction with the drawings. The following examples are only used to more clearly illustrate the technical solutions of the present application, and cannot be used to limit the protection scope of the present application.

[0034] like Figure 2 As shown, in Figure 1 Based on this, resistors R1 and R2 are added. Resistor R1 is connected in series between the drain of PMOS transistor Mp1 and node n1, and resistor R2 is connected in series between the drain of PMOS transistor Mp2 and node n2. In this circuit, node n1 and node n2 can be used as two output terminals Vout1 and Vout2, respectively.

[0035] Figure 2 The overall structure is also a cross-coupled structure. When Vin switches from high level to low level, node S1 becomes high level, NMOS transistor Mn1 turns on and NMOS transistor Mn2 turns off, node n1 becomes low, PMOS transistor Mp2 turns on, the voltage of node n2 becomes high level, and PMOS transistor Mp1 turns off. Among them, node S1 is the common connection point of the output terminal of inverter inv1, the gate of NMOS transistor Mn1 and the input terminal of inverter inv2.

[0036] The entire circuit has a positive feedback structure. The voltage at node n2 is pulled up by the voltage at node n1 first, which causes the PMOS transistor Mp2 to turn on, and then the PMOS transistor Mp1 turns off. There is a sequential logic, so the PMOS transistor Mp1 turns off slower than the NMOS transistor Mn1 turns on.

[0037] Without resistors R1 and R2, the potential of node n1 will compete between NMOS transistor Mn1 and PMOS transistor Mp1. The potential switching speed of node n1 also determines the magnitude of the competing current. After adding resistors R1 and R2, the impedance increases when looking from nodes n1 and n2 to VDD. This is mainly because the resistance of PMOS transistors Mp1 and Mp2 is too small when they are turned on. R1 and R2 compensate for the resistance from nodes n1 and n2 to VDD at this time. When the Vin voltage switches, the potential of node n1 or node n2 will drop faster than in the traditional structure. When NMOS transistor Mn1 is turned on, PMOS transistor Mp1 cannot be completely turned off. At this time, there will be a large current in resistor R1, which will also limit the current. The value of resistor R1 is large enough to be greater than the impedance of NMOS transistor Mn1 when it is turned on. Even if PMOS transistor Mp1 is fully turned on or the switching speed of PMOS transistor Mp1 is much smaller than that of NMOS transistor Mn1, the potential of node n1 can still be pulled low, and then the positive feedback logic is completed.

[0038] The entire circuit structure is symmetrical from left to right, and the logic for turning on NMOS transistor Mn2 is the same as the logic for turning on NMOS transistor Mn1.

[0039] Therefore, it can be seen that by adding resistors R1 and R2, all competition risks in the level conversion process are eliminated.

[0040] The addition of resistors R1 and R2 does not affect the ability of the voltage at node n1 and node n2 to drop, but the switching speed of the voltage at node n1 and node n2 to rise is reduced. In order to further improve the situation, a first speed-up circuit and a second speed-up circuit are added on the basis of Figure 2 , wherein the first speed-up circuit is the part enclosed by the dashed box A1, the second speed-up circuit is the part enclosed by the dashed box A2, and the first speed-up circuit and the second speed-up circuit are both arranged between node n1 and node n2, i.e. between Vout1 and Vout2.

[0041] As can be seen from the figure, the structures of the two speed-up circuits are consistent, but the logic functions of the two are opposite when the overall circuit is running.

[0042] As shown in Figure 3 and 4 , the first speed-up circuit specifically includes a PMOS transistor Mp3, a resistor R3, a capacitor C1, and a first voltage protection device. The S pole of the PMOS transistor Mp3 is connected to a high-voltage power supply voltage signal VDD, the D pole of the PMOS transistor Mp3 is connected to node n1, one end of the resistor R3 is connected to the high-voltage power supply voltage signal VDD, the other end of the resistor R3 is connected to the G pole of the PMOS transistor Mp3 and one end of the capacitor C1 respectively, the other end of the capacitor C1 is connected to node n2, and the first voltage protection device is connected across the resistor R3.

[0043] The second speed-up circuit specifically includes a PMOS transistor Mp4, a resistor R4, a capacitor C2, and a second voltage protection device. The S pole of the PMOS transistor Mp4 is connected to the high-voltage power supply voltage signal VDD, the D pole of the PMOS transistor Mp4 is connected to node n2, one end of the resistor R4 is connected to the high-voltage power supply voltage signal VDD, the other end of the resistor R4 is connected to the G pole of the PMOS transistor Mp4 and one end of the capacitor C2 respectively, the other end of the capacitor C2 is connected to node n1, and the second voltage protection device is connected across the resistor R4.

[0044] The first voltage protection device is mainly used to protect the voltage at node n3, so as to ensure that the voltage of the circuit cannot be too high; wherein node n3 is the common connection of the PMOS transistor Mp3, the resistor R3, and the capacitor C1.

[0045] The first voltage protection device can be a diode D1, as shown in Figure 3 , the negative electrode of the diode D1 is connected to the high-voltage power supply voltage signal VDD, and the positive electrode of the diode D1 is connected to node n3. The first voltage protection device can also be an NMOS transistor Mn3, as shown in Figure 4 , the S pole of the NMOS transistor Mn3 is connected to the high-voltage power supply voltage signal VDD, and the G pole, the D pole, and the B pole of the NMOS transistor Mn3 are all connected to node n3. The first voltage protection device can also be a PMOS transistor Mp7, as shown in Figure 5The source (S) of PMOS transistor Mp7 is connected to node n3, and the gate (G), drain (D), and base (B) of PMOS transistor Mp7 are all connected to the high-voltage power supply signal VDD.

[0046] Similarly, the second voltage protection device is used to protect the voltage at node n4 to ensure that the circuit voltage is not too high; where node n4 is the common connection point of PMOS transistor Mp4, resistor R4 and capacitor C2.

[0047] The second voltage protection device can be diode D2, see... Figure 3 The cathode of diode D2 is connected to the high-voltage power supply signal VDD, and the anode of diode D2 is connected to node n4. The second voltage protection device can be an NMOS transistor Mn4, see [link to relevant documentation]. Figure 4 The source (S) of NMOS transistor Mn4 is connected to the high-voltage power supply signal VDD, and the gate (G), drain (D), and base (B) of NMOS transistor Mn4 are all connected to node n4. The second voltage protection device can also be a PMOS transistor Mp8, see [link to relevant documentation]. Figure 5 The source (S) of PMOS transistor Mp8 is connected to node n4, and the gate (G), drain (D), and base (B) of PMOS transistor Mp8 are all connected to the high-voltage power supply signal VDD.

[0048] right Figure 3 Analysis: When NMOS transistor Mn1 is turned on, the voltage drop capability of node n1 is not hindered, and the voltage of node n1 drops rapidly from VDD. The lower plate of capacitor C2 is connected to node n1, and the voltage of the upper plate of capacitor C2 drops synchronously from VDD. At this time, PMOS transistor Mp4 is turned on. PMOS transistor Mp4 is directly connected between VDD and node n2, and node n2 rises rapidly. PMOS transistor Mp1 is turned off. After switching, capacitor C2 needs to be recharged. After each switching, resistor R4 sets the upper plate potential of capacitor C2 at VDD, while PMOS transistor Mp4 turns off (Mp4 only turns on when the voltage at node n1 switches from VDD to VSS; it remains off during the switching process from VSS to VDD). At this time, the voltage at node n2 switches from VDD to VSS. Because PMOS transistor Mp4 remains off and there is resistor R2 between PMOS transistor Mp2 and node n2, the potential drop at node n2 is smooth, and the crosstalk current from VDD to node n2 is very small. During the rise of the potential at node n1, the upper plate potential of capacitor C2 will exceed VDD. Resistor R4 has a limited discharge rate. To protect PMOS transistor Mp4, diode D2 is connected between node n4 and VDD to limit the voltage at node n4 from becoming too high. After the switching is complete, some transistors are off, and there is no path from VSS to VDD, logically achieving a static zero-power structure.

[0049] Figure 4 and Figure 3Similarly, Vin is amplified by inverter inv1, then inverted by inverter inv2. When NMOS transistors Mn1 or Mn2 are turned on, their internal resistance is relatively low. Therefore, resistors R1 and R2 do not need to be too large to allow smooth switching in the cross-coupled main circuit (excluding the speed-up circuit). The values ​​of capacitors C1 and C2 are determined by the size of the PMOS transistors and the switching frequency of the circuit, allowing PMOS transistors Mp3 and Mp4 to turn on quickly. Resistors R3 and R4 serve two purposes: first, to replenish the charge of capacitors C1 and C2; and second, to determine the turn-on time of PMOS transistors Mp3 and Mp4 during switching. At lower frequencies, resistors R3 and R4 can be larger, with NMOS transistors Mn3 and Mn4 replacing them. Figure 3 The diodes in the middle can also achieve the function.

[0050] The circuit described above achieves a steady-state high-speed level shifting circuit by adding a speed-increasing circuit to the existing resistor, thereby increasing the switching speed.

[0051] like Figure 6 As shown, in Figure 3 Based on this, an additional output stage is added, namely, a first output circuit and a second output circuit.

[0052] The first output circuit includes an NMOS transistor Mn5 and a PMOS transistor Mp5. The source (S) of the NMOS transistor Mn5 is grounded, the gate (G) of the NMOS transistor Mn5 is connected to the output terminal of the inverter inv1, the drain (D) of the NMOS transistor Mn5 is connected to the drain (D) of the PMOS transistor Mp5, the source (S) of the PMOS transistor Mp5 is connected to the high-voltage power supply signal VDD, and the gate (G) of the PMOS transistor Mp5 is connected to the gate (G) of the PMOS transistor Mp1. The midpoint between the NMOS transistor Mn5 and the PMOS transistor Mp5 replaces node n1 as the new output terminal Vout1.

[0053] The second output circuit includes an NMOS transistor Mn6 and a PMOS transistor Mp6. The source (S) of the NMOS transistor Mn6 is grounded, the gate (G) of the NMOS transistor Mn6 is connected to the output of the inverter inv2, the drain (D) of the NMOS transistor Mn6 is connected to the drain of the PMOS transistor Mp6, the source (S) of the PMOS transistor Mp6 is connected to the high-voltage power supply signal VDD, and the gate (G) of the PMOS transistor Mp6 is connected to the gate (G) of the PMOS transistor Mp2. The midpoint between the NMOS transistor Mn6 and the PMOS transistor Mp6 replaces node n2 as the new output terminal Vout2.

[0054] Compared to Figure 3 and 4 , Figure 6The circuit in the application can isolate the influence of the output load connected with Vout1 and Vout2 on the nodes n1 and n2, make the switching speed of the voltage of the nodes n1 and n2 faster, improve the switching speed of the overall circuit, improve the driving capability of Vout1 and Vout2, and do not affect the stability of the switching of the circuit.

[0055] In the case that VDD is 3V and VDD1 is 2V, simulation comparison is carried out on Figure 1 and Figure 3 The simulation comparison is shown in Figure 7 The upper two curves are Figure 1 transient simulation waveforms, and the lower two curves are Figure 3 simulation waveforms. The upper two curves are not only slower than the lower two curves in switching speed, but also asymmetric left and right. The real line drops in a winding manner, which is caused by the voltage competition in the switching. The lower two curves are stable in switching speed. Therefore, it can be seen that the application realizes the stable and high-speed level shift circuit.

[0056] The above description is only the preferred embodiment of the application, and it should be pointed out that, for those skilled in the art, some improvements and modifications can be made without departing from the technical principles of the application, and these improvements and modifications should also be considered as the protection scope of the application.

Claims

1. A level shifting circuit comprising an inverter invl, an inverter inv2, an NMOS transistor Mn1, an NMOS transistor Mn2, a PMOS transistor Mpl and a PMOS transistor Mp2, an output terminal of the inverter invl is connected to a G terminal of the NMOS transistor Mn1 and an input terminal of the inverter invl, an output terminal of the inverter inv2 is connected to a G terminal of the NMOS transistor Mn2, a D terminal of the NMOS transistor Mn1 is connected to a D terminal of the PMOS transistor Mpl and a G terminal of the PMOS transistor Mp2, a D terminal of the NMOS transistor Mn2 is connected to a G terminal of the PMOS transistor Mpl and a D terminal of the PMOS transistor Mp2, a D terminal of the NMOS transistor Mn1, a D terminal of the PMOS transistor Mpl and a G terminal of the PMOS transistor Mp2 are commonly connected at a node nl, a D terminal of the NMOS transistor Mn2, a G terminal of the PMOS transistor Mpl and a D terminal of the PMOS transistor Mp2 are commonly connected at a node n2, characterized in that, The resistor R1 is connected in series between the D pole of the PMOS tube Mp1 and the node n1, and the resistor R2 is connected in series between the D pole of the PMOS tube Mp2 and the node n2. The first speed-up circuit and the second speed-up circuit are arranged between the node n1 and the node n2, and are used to improve the switching speed of the voltage rise of the node n1 and the node n2. The first speed-up circuit comprises the PMOS tube Mp3, the resistor R3 and the capacitor C1, the S pole of the PMOS tube Mp3 is connected to the high-voltage power supply voltage signal VDD, the D pole of the PMOS tube Mp3 is connected to the node n1, one end of the resistor R3 is connected to the high-voltage power supply voltage signal VDD, the other end of the resistor R3 is connected to the G pole of the PMOS tube Mp3 and one end of the capacitor C1 respectively, and the other end of the capacitor C1 is connected to the node n2. The resistor R3 is further connected to the first voltage protection device, and the first voltage protection device is used to protect the voltage at the node n3; wherein the node n3 is the common connection of the PMOS tube Mp3, the resistor R3 and the capacitor C1.

2. A level shifting circuit according to claim 1, characterized in that The first voltage protection device is a diode D1, an NMOS tube Mn3 or a PMOS tube Mp7. If the first voltage protection device is the diode D1, the negative pole of the diode D1 is connected to the high-voltage power supply voltage signal VDD, and the positive pole of the diode D1 is connected to the node n3. If the first voltage protection device is the NMOS tube Mn3, the S pole of the NMOS tube Mn3 is connected to the high-voltage power supply voltage signal VDD, and the G pole, the D pole and the B pole of the NMOS tube Mn3 are all connected to the node n3. If the first voltage protection device is the PMOS tube Mp7, the S pole of the PMOS tube Mp7 is connected to the node n3, and the G pole, the D pole and the B pole of the PMOS tube Mp7 are all connected to the high-voltage power supply voltage signal VDD.

3. A level shifting circuit according to claim 1, characterized in that The second speed-up circuit comprises the PMOS tube Mp4, the resistor R4 and the capacitor C2, the S pole of the PMOS tube Mp4 is connected to the high-voltage power supply voltage signal VDD, the D pole of the PMOS tube Mp4 is connected to the node n2, one end of the resistor R4 is connected to the high-voltage power supply voltage signal VDD, the other end of the resistor R4 is connected to the G pole of the PMOS tube Mp4 and one end of the capacitor C2 respectively, and the other end of the capacitor C2 is connected to the node n1.

4. A level shifting circuit as claimed in claim 3, characterized in that The resistor R4 is further connected to the second voltage protection device, and the second voltage protection device is used to protect the voltage at the node n2; wherein the node n4 is the common connection of the PMOS tube Mp4, the resistor R4 and the capacitor C2.

5. A level shifting circuit as claimed in claim 4, characterized in that The second voltage protection device is a diode D2, an NMOS tube Mn4 or a PMOS tube Mp8. If the second voltage protection device is the diode D2, the negative pole of the diode D2 is connected to the high-voltage power supply voltage signal VDD, and the positive pole of the diode D2 is connected to the node n4. If the second voltage protection device is the NMOS tube Mn4, the S pole of the NMOS tube Mn4 is connected to the high-voltage power supply voltage signal VDD, and the G pole, the D pole and the B pole of the NMOS tube Mn4 are all connected to the node n4. If the second voltage protection device is the PMOS tube Mp8, the S pole of the PMOS tube Mp8 is connected to the node n4, and the G pole, the D pole and the B pole of the PMOS tube Mp8 are all connected to the high-voltage power supply voltage signal VDD. If the second voltage protection device is the PMOS tube Mp8, the S pole of the PMOS tube Mp8 is connected to the node n4, and the G pole, the D pole and the B pole of the PMOS tube Mp8 are all connected to the high-voltage power supply voltage signal VDD.

6. A level shifting circuit as claimed in claim 1, characterized in that The first output circuit and the second output circuit are further included. The first output circuit includes the NMOS tube Mn5 and the PMOS tube Mp5, the S pole of the NMOS tube Mn5 is grounded, the G pole of the NMOS tube Mn5 is connected to the output end of the inverter inv1, the D pole of the NMOS tube Mn5 is connected to the D pole of the PMOS tube Mp5, the S pole of the PMOS tube Mp5 is connected to the high-voltage power supply voltage signal VDD, the G pole of the PMOS tube Mp5 is connected to the G pole of the PMOS tube Mp1, and the midpoint between the NMOS tube Mn5 and the PMOS tube Mp5 is replaced by the node n1 as a new output end Vout1. The second output circuit includes the NMOS tube Mn6 and the PMOS tube Mp6, the S pole of the NMOS tube Mn6 is grounded, the G pole of the NMOS tube Mn6 is connected to the output end of the inverter inv2, the D pole of the NMOS tube Mn6 is connected to the D pole of the PMOS tube Mp6, the S pole of the PMOS tube Mp6 is connected to the high-voltage power supply voltage signal VDD, the G pole of the PMOS tube Mp6 is connected to the G pole of the PMOS tube Mp2, and the midpoint between the NMOS tube Mn6 and the PMOS tube Mp6 is replaced by the node n2 as a new output end Vout2.

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