System and method for multi-core parallel testing of a single object under test

Abstract

The present invention provides a system and method for multi-core parallel testing of a single DUT. The method for multi-core parallel testing of a single DUT includes the following steps: calculating the test quantity of the DUT; evenly distributing the test quantity of the DUT to multiple test cores to control the time for the multiple test cores to parallelly test the DUT, thereby improving the efficiency of the factory production line.

Description

Technical Field

[0001] The present invention relates to a test system and method, and more particularly to a system and method for multi-core parallel testing of a single device under test. Background Art

[0002] A device under test (DUT), also known as an equipment under test (EUT) or unit under test (UUT), is a manufactured product that undergoes functional testing and calibration checks either during its first manufacture or at a later stage in its life cycle. This can include testing after repair to determine whether the product performs according to the original product specifications. In the electronics industry, the device under test can be any electronic component being tested. However, the current test time of test machines is still not short enough.

[0003] To solve the above-mentioned problem of test time, the related art has spared no effort to seek solutions, but no applicable method has been developed for a long time. Therefore, how to test the device under test more efficiently is one of the important current research topics and also an urgent improvement goal in the current related fields. Summary of the Invention

[0004] The present invention provides a system and method for multi-core parallel testing of a single device under test to improve the problems of the prior art.

[0005] In an embodiment of the present invention, the system for multi-core parallel testing of a single device under test proposed by the present invention includes a computer device and a plurality of test cores, and the plurality of test cores are connected to the computer device. The computer device evenly distributes the test volume of the device under test to the plurality of test cores to control the time for the plurality of test cores to parallelly test the device under test.

[0006] In an embodiment of the present invention, the computer device calculates the total capacitance values of a plurality of test networks of the device under test, classifies and sorts the plurality of total capacitance values, and accordingly allocates the plurality of test networks to the plurality of test cores, so as to balance the sum of the total capacitance values to be tested by each of the plurality of test cores.

[0007] In an embodiment of the present invention, the computer device classifies the plurality of test networks into a plurality of test networks to be allocated and the remaining test networks. Each of the total capacitance values of the plurality of test networks to be allocated is greater than a preset capacitance value. The computer device arranges the plurality of total capacitance values from largest to smallest to correspondingly sort the plurality of test networks to be allocated, so as to allocate the plurality of test networks to be allocated to the plurality of test cores.

[0008] In an embodiment of the present invention, the plurality of test cores are the first to the Nth test cores, and the computer device allocates the sorted plurality of test networks to be allocated to the first to the Nth test cores in a round-robin allocation, odd-even allocation, or random average allocation manner.

[0009] In an embodiment of the present invention, the total capacitance values of the remaining test networks are all less than or equal to a preset capacitance value, and the computer device randomly selects any one of a plurality of test cores to test the remaining test networks.

[0010] In an embodiment of the present invention, the computer device calculates the total quantity of each parameter to be measured of the object to be measured, so as to evenly distribute the quantity of each parameter to be measured that each of the plurality of test cores needs to test.

[0011] In an embodiment of the present invention, each parameter to be measured is a non-capacitive parameter.

[0012] In an embodiment of the present invention, the non-capacitive parameters are resistance value, inductance value, voltage value, charge measurement parameter, electrical parameter of a pin of an integrated circuit, and voltage parameter of a clamping diode.

[0013] In an embodiment of the present invention, the method for multi-core parallel testing of a single object to be measured proposed by the present invention includes the following steps: calculating the test quantity of the object to be measured; evenly distributing the test quantity of the object to be measured to a plurality of test cores to control the time for the plurality of test cores to parallelly test the object to be measured.

[0014] In an embodiment of the present invention, the method further includes: calculating the total capacitance values of a plurality of test networks of the object to be measured, classifying and sorting the plurality of total capacitance values, and accordingly allocating the plurality of test networks to a plurality of test cores, so as to balance the sum of the total capacitance values that each of the plurality of test cores needs to test.

[0015] In an embodiment of the present invention, the method further includes: classifying the plurality of test networks into a plurality of test networks to be allocated and the remaining test networks, each of the total capacitance values of the plurality of test networks to be allocated is greater than a preset capacitance value, and the computer device arranges the plurality of total capacitance values from large to small to correspondingly sort the plurality of test networks to be allocated, so as to allocate the plurality of test networks to be allocated to a plurality of test cores.

[0016] In an embodiment of the present invention, the plurality of test cores are the first to the Nth test cores, and the method further includes: allocating the sorted plurality of test networks to be allocated to the first to the Nth test cores in a way of round-robin allocation, odd-even allocation or random average allocation.

[0017] In an embodiment of the present invention, the total capacitance values of the remaining test networks are all less than or equal to a preset capacitance value, and the method further includes: randomly selecting any one of the plurality of test cores to test the remaining test networks.

[0018] In an embodiment of the present invention, the method further includes: calculating the total quantity of each parameter to be measured of the object to be measured, so as to evenly distribute the quantity of each parameter to be measured that each of the plurality of test cores needs to test.

[0019] In one embodiment of the present invention, each of the above parameters to be measured is a non-capacitive parameter.

[0020] In one embodiment of the present invention, the non-capacitive parameters are resistance value, inductance value, voltage value, upper power measurement parameter, electrical parameter of the pin of an integrated circuit, and voltage parameter of a clamping diode.

[0021] In summary, the technical solution of the present invention has obvious advantages and beneficial effects compared with the prior art. Through the technical solution of the present invention, the system and method for multi-core parallel testing of a single object under test can save testing time, thereby shortening the production time of products and improving the efficiency of the factory production line.

[0022] The following will describe the above description in detail by way of embodiments, and provide a further explanation of the technical solution of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] To make the above and other objects, features, advantages and embodiments of the present invention more obvious and understandable, the description of the accompanying drawings is as follows:

[0024] Figure 1 is a block diagram of a system for multi-core parallel testing of a single object under test according to an embodiment of the present invention; and

[0025] Figure 2 is a flowchart of a method for multi-core parallel testing of a single object under test according to an embodiment of the present invention.

[0026]

REFERENCE SIGNS

[0027] To make the above and other objects, features, advantages and embodiments of the present invention more obvious and understandable, the description of the accompanying reference signs is as follows:

[0028] 100: System for multi-core parallel testing of a single object under test

[0029] 110: Computer device

[0030] 120: Testing machine

[0031] 120A, 120B, 120C, 120D: Testing cores

[0032] 190: Object under test

[0033] 200: Method for multi-core parallel testing of a single object under test

[0034] S201, S202: Steps DETAILED DESCRIPTION OF THE EMBODIMENTS

[0035] To make the description of the present invention more detailed and complete, reference may be made to the accompanying drawings and each of the following embodiments. The same numbers in the drawings represent the same or similar elements. On the other hand, well-known elements and steps are not described in the embodiments to avoid unnecessary limitations to the present invention.

[0036] Please refer to Figure 1 , the technical aspect of the present invention is a system 100 for multi-core parallel testing of a single DUT 190, which can be applied to a testing machine or widely used in related technical processes. The system 100 for multi-core parallel testing of a single DUT 190 proposed by the present invention can effectively save testing time, thereby shortening the production time of products and improving the efficiency of factory production lines. Therefore, the system 100 for multi-core parallel testing of a single DUT of this technical aspect can achieve considerable technological progress and has wide industrial utilization value. The following will be described in conjunction with Figure 1 、 2 to illustrate the specific implementation manners of the system 100.

[0037] It should be understood that various implementation manners of the system 100 for multi-core parallel testing of a single DUT are described in conjunction with Figure 1 . In the following description, for the sake of explanation, many specific details are further set to provide a comprehensive elaboration of one or more implementation manners. However, the present technology can be implemented without these specific details. In other examples, in order to effectively describe these implementation manners, known structures and devices are shown in block diagram form. The term "for example" used herein means "as an example, instance or illustration". Any embodiment described herein as "for example" need not be construed as better or superior to other embodiments.

[0038] Figure 1 is a block diagram of a system 100 for multi-core parallel testing of a single DUT 190 according to an embodiment of the present invention. As Figure 1 shown, the system 100 for multi-core parallel testing of a single DUT 190 may include a computer device 110 and multiple test cores 120A, 120B, 120C, and 120D (such as: automatic test core devices). It should be noted that in this article, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0039] For example, the computer device 110 may be a computer host, a processor, or a server. Taking the computer device 110 being a server as an example, many technologies that have been developed or are in the process of being developed can manage the operation of computer servers, generally providing accessibility, consistency, and efficiency. Remote management allows for the removal of input / output interfaces for servers and the need for network administrator entities to access each server. For example, large data centers with many computer servers generally use a variety of remote management tools to manage, configure, monitor, and debug server hardware and software.

[0040] Taking the computer device 110 being a computer host as an example, the functions and steps of the present invention can be implemented through software, hardware, and / or firmware. For example, if execution speed and accuracy are the primary considerations, then hardware and / or firmware can basically be selected as the main components; if design flexibility is the primary consideration, then these units can basically be selected with software as the main component; or, software, hardware, and firmware can be used in cooperation simultaneously. It should be understood that there is no distinction between superiority and inferiority among these examples given above, nor are they used to limit the present invention. Those skilled in the art should flexibly select specific implementation manners according to the needs at that time.

[0041] Taking the computer device 110 being a processor as an example, the processor can be an integrated circuit chip with the ability to process signals. In practice, the various functions of a computer can be completed through the integrated logic circuits of the hardware in the processor or instructions in software form. The above-mentioned processor can be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The functions and steps disclosed in combination with the embodiments of the present invention can be executed by a hardware processor or through a combination of hardware and software modules in the processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, or electrically erasable programmable memory, registers, and other well-known storage media in the art. This storage media is located in the memory, and the processor reads the information in the memory and combines its hardware to execute.

[0042] Architecturally, multiple test cores 120A, 120B, 120C, and 120D are electrically connected to a computer device 110. These test cores 120A, 120B, 120C, and 120D may be installed in a test machine 120. The test machine 120 may include a switchboard (not shown) that switches paths between the multiple test cores 120A, 120B, 120C, and 120D. Each test core in the test machine 120 (e.g., an automated test core circuit) may have independent testing capabilities. It should be understood that in the embodiments and claims, the term "electrically connected" may generally refer to an indirect electrical coupling of one component to another component through another component, or a direct electrical connection of one component to another component without requiring another component. For example, the computer device 110 may be a built-in processor directly electrically connected to the multiple test cores 120A, 120B, 120C, and 120D, or the computer device 110 may be an external computer host indirectly electrically coupled to the multiple test cores 120A, 120B, 120C, and 120D through a switchboard of the test machine 120.

[0043] For example, the object under test 190 may be an object having active and / or passive components (e.g., a printed circuit board), but the present invention is not limited thereto. During use, the computer device 110 evenly distributes the test quantity of the object under test 190 (e.g., the total capacitance of the object under test 190, the number of various non-capacitive parameters, etc.) to the multiple test cores 120A, 120B, 120C, and 120D to control the time during which the multiple test cores 120A, 120B, 120C, and 120D test the object under test 190 in parallel. Thus, compared to a machine using a single test core, the system 100 proposed by the present invention for multi-core parallel testing of a single object under test 190 can effectively save testing time, thereby shortening product production time and improving factory production line efficiency.

[0044] In practice, the device under test 190 has one or more test networks. Each test network can be a measurement point or a set of multiple associated measurement points, or can be a connection point or a set of multiple associated connection points. The larger the capacitance of the device under test 190, the slower its discharge speed. In a control experiment, a single test core is used to discharge the capacitors on the test network one by one through a resistor placed inside the test core, so the discharge time is relatively long. In order to accelerate the discharge and measurement of large capacitors, in an embodiment of the present invention, the computer device 110 calculates the total capacitance values of multiple test networks of the device under test 190, classifies and sorts the total capacitance values, and accordingly assigns the multiple test networks to multiple test cores 120A, 120B, 120C, 120D, so as to balance the sum of the total capacitance values to be tested by each of the multiple test cores 120A, 120B, 120C, 120D. Thereby, the sum of the total capacitance values to be tested by each of the multiple test cores 120A, 120B, 120C, 120D is approximately close. Compared with the control experiment using a single test core, the discharge time can be significantly shortened.

[0045] It should be understood that although Figure 1 only four test cores 120A, 120B, 120C, 120D are shown, this does not limit the number of test cores of the present invention. The multiple test cores can be the first to the Nth test cores, where N is a positive integer greater than 1. Compared with the control experiment using a single test core, the discharge time in this embodiment can ideally be shortened by about 1 / N of the time.

[0046] It should be noted that the terms "about", "approximately" or "substantially" used herein are used to modify any quantity that can vary slightly, but such slight variations do not change its essence. In the embodiments, unless otherwise specified, it means that the error range of the value modified by "about", "approximately" or "substantially" is generally allowed to be within twenty percent, preferably within ten percent, and more preferably within five percent.

[0047] Specifically, in an embodiment of the present invention, the computer device 110 classifies multiple test networks of the object to be tested 190 into multiple test networks to be allocated and the remaining test networks. Each of the total capacitance values of the multiple test networks to be allocated is greater than a preset capacitance value (e.g., 100 uF). It should be understood that the aforementioned "preset capacitance value" can be flexibly adjusted in size by the system administrator or other personnel according to actual applications. In practice, the total capacitance value of a large capacitor is greater than the preset capacitance value, and its discharge time is longer. Without reasonable allocation to each test core 120A, 120B, 120C, 120D, it will cause delays in testing. Therefore, the computer device arranges the multiple total capacitance values greater than the preset capacitance value from largest to smallest to correspondingly sort the multiple test networks to be allocated, so as to allocate the multiple test networks to be allocated to multiple test cores.

[0048] In an embodiment of the present invention, the multiple test cores are the first to the Nth test cores, and the computer device 110 allocates the sorted multiple test networks to be allocated back and forth from the first to the Nth test cores and then from the Nth to the first test cores. For example, Figure 1Among them, multiple test cores 120A, 120B, 120C, and 120D can be the first test core 120A, the second test core 120B, the third test core 120C, and the fourth test core 120D. The computer device 110 will distribute the sorted multiple test networks to be allocated back and forth from the first, second, third to the fourth test cores 120A, 120B, 120C, 120D and then from the fourth, third, second to the first test cores 120D, 120C, 120B, 120A. Experimentally, the test networks to be allocated corresponding to the total capacitance values arranged from large to small in the aforementioned back-and-forth distribution manner can make the sum of the total capacitance values to be tested for each of the multiple test cores 120A, 120B, 120C, and 120D the closest. Then, according to the test networks allocated by the computer device 110, the multiple test cores 120A, 120B, 120C, and 120D test the object under test 190 in parallel. According to the experimental application of capacitor discharge in large-capacitance measurement, approximately 70% of the test time can be saved through calculation. In addition to the aforementioned back-and-forth distribution manner, in other embodiments, odd-even distribution, random average distribution, or other distribution manners can also be adopted. Those skilled in the art can flexibly select according to the needs at that time. For example, the odd-even distribution can be to first allocate the test networks to be allocated corresponding to the total capacitance values arranged from large to small to the first and third test cores 120A and 120C, then allocate them to the second and fourth test cores 120B and 120D and repeat this, or first allocate them to the second and fourth test cores 120B and 120D, then allocate them to the first and third test cores 120A and 120C and repeat this. The random average distribution can be to allocate the test networks to be allocated corresponding to the total capacitance values arranged from large to small to the test cores arranged in a random order (such as: the second, third, first, fourth test cores 120B, 120C, 120D, 120A) and repeat this.

[0049] In an embodiment of the present invention, except for the above-mentioned test network to be allocated, the total capacitance values of the remaining test networks of the object under test 190 are all less than or equal to a preset capacitance value. In practice, the discharge time required for a capacitor with a capacitance less than the preset capacitance value is short, and the proportion of the overall test time is negligible. Therefore, the computer device 110 randomly selects any one of the multiple test cores 120A, 120B, 120C, 120D (such as: test core 120C) to test the remaining test networks. Alternatively, in other embodiments, it is not necessary to use the preset capacitance value to distinguish the test network to be allocated from the remaining test networks. The computer device 110 directly adopts the above-mentioned repeated allocation method, odd-number allocation, random allocation or other allocation methods to evenly allocate all the multiple test networks on the object under test 190 to the multiple test cores 120A, 120B, 120C, 120D, so that the sum of the total capacitance values to be tested by each of the multiple test cores 120A, 120B, 120C, 120D is approximately close.

[0050] As described above, the test cores 120A, 120B, 120C, 120D, etc. The specific implementation methods can be test cores of the same specification to increase the parallel test efficiency, but they can also be test cores of different specifications. And those skilled in the art should understand that Figure 1 It is only to make the technology of this case more obvious and easy to understand, and does not limit the number of test cores and the functions performed. Combining multiple test cores into a combined test core for parallel testing with the remaining test cores, or replacing the function of one test core to be executed in another test core, still belongs to the implementation mode of the present invention.

[0051] In practice, multi-core parallel testing of a single object under test 190 can be applied to a Manufacturing Defects Analyzer (MDA). In the manufacturing defect analyzer test, discharging and measuring large capacitors are accelerated under the architecture of multiple test cores. Similarly, multi-core parallel testing of a single object under test 190 can be applied to an In-Circuit Tester (ICT) or any test machine.

[0052] In addition to the total capacitance value of each test network, in practice, the system 100 for multi-core parallel testing of a single DUT 190 can test each parameter to be measured (e.g., non-capacitive parameters) of the DUT 190. Since there is no obvious phenomenon of inconsistent test hysteresis for non-capacitive parameters, in an embodiment of the present invention, the computer device 110 calculates the total number of each parameter to be measured (e.g., non-capacitive parameters) of the DUT 190 to evenly distribute the number of each parameter to be measured required for each of the multiple test cores 120A, 120B, 120C, and 120D. Thereby, the number of measurements required for each of the multiple test cores 120A, 120B, 120C, and 120D is approximately close. Compared with the control experiment using a single test core, the test time can be significantly shortened.

[0053] In an embodiment of the present invention, the non-capacitive parameter may be a resistance value, an inductance value, a voltage value, an upper charge measurement parameter, an electrical parameter of a pin of an integrated circuit, a voltage parameter of a clamping diode, and / or other parameters. In practice, for example, the electrical parameter (e.g., voltage parameter) of a pin of an integrated circuit can be sensed by Testjet or other similar technologies to determine whether the pin is abnormal (e.g., open circuit); the voltage parameter of the clamping diode can be measured by sending a small current into the input / output pins of the clamping diode and measuring the voltage difference between the voltage source (Vcc) connected to the circuit and the input / output pins to determine whether there is an open circuit in the voltage source or the input / output pins, or by measuring the voltage difference between the ground terminal and the input / output pins to determine whether there is an open circuit in the ground terminal or the input / output pins. It should be understood that the above-mentioned measurement technologies for Testjet and the voltage parameter of the clamping diode are well-known technologies to those of ordinary skill in the art and are not within the scope of the present invention, so they will not be elaborated here.

[0054] To further elaborate on the method run by the system 100 for multi-core parallel testing of a single DUT 190, please also refer to Figure 1 、 2 , Figure 2 is a flowchart of a method 200 for multi-core parallel testing of a single DUT 190 according to an embodiment of the present invention. As Figure 2 shown, the method 200 for multi-core parallel testing of a single DUT 190 includes steps S201 and S202 (it should be understood that the steps mentioned in this embodiment, except for those specifically stating their order, can be adjusted in their front-back order according to actual needs, and even can be executed simultaneously or partially simultaneously). As for the hardware devices for implementing these steps, since they have been specifically disclosed in the above embodiments, they will not be repeated here.

[0055] The method 200 for multi-core parallel testing of a single object under test 190 as described above can be implemented via a computer, such as the aforementioned computer device 110. Part of its functions can also be implemented as a computer program and stored in a non-transitory computer-readable recording medium. After a computer reads this recording medium, a computer system is made to execute the method 200 for multi-core parallel testing of a single object under test 190.

[0056] For example, the method 200 for multi-core parallel testing of a single object under test 190 can be in the form of a computer program product on a non-transitory computer-readable recording medium. This computer-readable recording medium has a plurality of computer-readable instructions contained in the medium. Suitable recording media can include any of the following: non-volatile memories, such as read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM); volatile memories, such as static random access memory (SRAM), dynamic random access memory (SRAM), double data rate random access memory (DDR-RAM); optical storage devices, such as compact disc read-only memory (CD-ROM), digital versatile disc read-only memory (DVD-ROM); magnetic storage devices, such as hard disk drives, floppy disk drives.

[0057] In an embodiment of the present invention, in step S201, the test quantity of the object under test 190 is calculated; in step S202, the test quantity of the object under test 190 is evenly distributed among a plurality of test cores 120A, 120B, 120C, 120D to control the time for the plurality of test cores 120A, 120B, 120C, 120D to parallel test the object under test 190. Thus, compared with a machine using a single test core, the method 200 for multi-core parallel testing of a single object under test 190 proposed by the present invention can effectively save the test time, thereby shortening the production time of the product and improving the efficiency of the factory production line.

[0058] In an embodiment of the present invention, in the method 200 for multi-core parallel testing of a single object under test 190, the total capacitance values of a plurality of test networks of the object under test 190 are calculated, classified and sorted, and accordingly, the plurality of test networks are assigned to the plurality of test cores 120A, 120B, 120C, 120D, so as to balance the total capacitance values to be tested by each of the plurality of test cores 120A, 120B, 120C, 120D. Thereby, the total capacitance values to be tested by each of the plurality of test cores 120A, 120B, 120C, 120D are approximately close, and the discharge time can be greatly shortened.

[0059] In an embodiment of the present invention, in a method 200 for multi-core parallel testing of a single DUT 190, a plurality of test networks are classified into a plurality of test networks to be allocated and the remaining test networks. Each of the total capacitance values of the plurality of test networks to be allocated is greater than a preset capacitance value. The plurality of total capacitance values are arranged from largest to smallest to correspondingly sort the plurality of test networks to be allocated, so as to allocate the plurality of test networks to be allocated to a plurality of test cores 120A, 120B, 120C, and 120D.

[0060] In an embodiment of the present invention, the plurality of test cores 120A, 120B, 120C, and 120D are the first to the Nth test cores. In the method 200 for multi-core parallel testing of a single DUT 190, the sorted plurality of test networks to be allocated are first allocated back and forth from the first to the Nth test cores and then from the Nth to the first test cores, where N is a positive integer greater than 1 (e.g., 4). Experimentally, allocating the test networks to be allocated corresponding to the total capacitance values arranged from largest to smallest to the first to the Nth test cores in a back-and-forth allocation, odd-even allocation, random average allocation, or other allocation methods can make the sum of the total capacitance values to be tested by each of the plurality of test cores 120A, 120B, 120C, and 120D closest. Then, according to the above-allocated test networks, the plurality of test cores 120A, 120B, 120C, and 120D perform parallel testing on the DUT 190. According to the experimental application of capacitor discharge in large-capacitance measurement, approximately 70% of the test time can be saved through calculation.

[0061] In an embodiment of the present invention, in addition to the above test networks to be allocated, the total capacitance values of the remaining test networks of the DUT 190 are all less than or equal to the preset capacitance value. In practice, the discharge time required for a capacitor with a capacitance less than the preset capacitance value is short, and the proportion of the overall test time is negligible. Therefore, in the method 200 for multi-core parallel testing of a single DUT 190, any one of the plurality of test cores is randomly selected to test the remaining test networks.

[0062] In addition to the total capacitance values of each test network, in practice, the system 100 for multi-core parallel testing of a single DUT 190 can test each parameter to be measured of the DUT 190 (e.g., non-capacitive parameters). Therefore, in an embodiment of the present invention, in the method 200 for multi-core parallel testing of a single DUT 190, the total number of each parameter to be measured of the DUT (e.g., non-capacitive parameters) is calculated to evenly distribute the number of each parameter to be measured that each of the plurality of test cores needs to test.

[0063] In an embodiment of the present invention, the above non-capacitive parameters may be resistance values, inductance values, voltage values, charge measurement parameters, electrical parameters of pins of integrated circuits, voltage parameters of clamping diodes, and / or other parameters.

[0064] In summary, the technical solution of the present invention has obvious advantages and beneficial effects compared with the prior art. Through the technical solution of the present invention, the system 100 and method 200 for multi-core parallel testing of a single object to be tested can save testing time, thereby shortening the production time of products and improving the efficiency of the factory production line.

[0065] Although the present invention has been disclosed above in the form of embodiments, it is not intended to limit the present invention. Any person skilled in this art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the appended claims.

Claims

1. A system for multi-core parallel testing of a single object under test, characterized in that, The system includes: a computer device; and a plurality of test cores, electrically connected to the computer device, and the computer device evenly distributes the test quantity of the object under test to the plurality of test cores to control the time for the plurality of test cores to concurrently test the object under test; The computer device calculates the total quantity of each parameter to be measured of the object under test to evenly distribute the quantity of each parameter to be measured that each of the plurality of test cores needs to test.

2. The system according to claim 1, wherein The test quantity of the object under test includes the total capacitance values of a plurality of test networks of the object under test, and the computer device calculates the total capacitance values to classify and sort the total capacitance values, and accordingly distributes the plurality of test networks to the plurality of test cores, so as to balance the sum of the total capacitance values that each of the plurality of test cores needs to test. The plurality of test networks are a set of measurement points or a set of connection points.

3. The system according to claim 2, wherein The computer device classifies the plurality of test networks into a plurality of test networks to be allocated and the remaining test networks. Each of the total capacitance values of the plurality of test networks to be allocated is greater than a preset capacitance value. The computer device arranges the total capacitance values from largest to smallest to correspondingly sort the plurality of test networks to be allocated, so as to allocate the plurality of test networks to be allocated to the plurality of test cores.

4. The system according to claim 3, wherein The plurality of test cores are the first to the Nth test cores, and the computer device distributes the sorted plurality of test networks to be allocated to the first to the Nth test cores in a one-way allocation, an odd-even allocation, or a random average allocation manner.

5. The system according to claim 3, wherein The total capacitance values of the remaining test networks are all less than or equal to the preset capacitance value, and the computer device randomly selects any one of the plurality of test cores to test the remaining test networks.

6. The system according to claim 1, wherein Each parameter to be measured is a non-capacitive parameter.

7. The system according to claim 6, wherein The non-capacitive parameter is a resistance value, an inductance value, a voltage value, an on-quantity measurement parameter, an electrical parameter of a pin of an integrated circuit, and a voltage parameter of a clamping diode.

8. A method for multi-core parallel testing of a single object to be tested, characterized in that, The method includes the following steps: calculating the test quantity of the object under test; evenly distributing the test quantity of the object under test to a plurality of test cores to control the time for the plurality of test cores to concurrently test the object under test; and calculating the total quantity of each parameter to be measured of the object under test to evenly distribute the quantity of each parameter to be measured that each of the plurality of test cores needs to test.

9. The method according to claim 8, wherein It further includes: The test quantity of the object under test includes the total capacitance values of a plurality of test networks of the object under test. Calculate the total capacitance values to classify and sort the total capacitance values, and accordingly distribute the plurality of test networks to the plurality of test cores, so as to balance the sum of the total capacitance values that each of the plurality of test cores needs to test. The plurality of test networks are a set of measurement points or a set of connection points.

10. The method according to claim 9, wherein It further includes: classifying the plurality of test networks into a plurality of test networks to be allocated and the remaining test networks. Each of the total capacitance values of the plurality of test networks to be allocated is greater than a preset capacitance value. Arranging the total capacitance values from largest to smallest to correspondingly sort the plurality of test networks to be allocated, so as to allocate the plurality of test networks to be allocated to the plurality of test cores.

11. The method according to claim 10, wherein The multiple test cores are the first to the Nth test cores, and the method further includes: Allocating the sorted multiple test networks to be allocated one by one in a back-and-forth allocation, an odd-even allocation, or a random average allocation manner to the first to the Nth test cores.

12. The method according to claim 10, characterized in that, The total capacitance values of the remaining test networks are all less than or equal to the preset capacitance value, and the method further includes: Randomly selecting any one of the multiple test cores to test the remaining test networks.

13. The method according to claim 8, characterized in that, Each type of parameter to be measured is a non-capacitive parameter.

14. The method according to claim 13, wherein The non-capacitive parameters are resistance value, inductance value, voltage value, charge measurement parameter, electrical parameter of a pin of an integrated circuit, and voltage parameter of a clamping diode.

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