Power consumption control method and device, board card, electronic equipment and storage medium

Abstract

The application relates to a power consumption control method and device, a board card, electronic equipment and a storage medium, wherein the method is applied to a board card with a dynamic random access memory, and the method comprises the following steps: acquiring a data stream of the board card; and controlling an active bandwidth of the dynamic random access memory according to the data stream. By acquiring the data stream of the board card and controlling the active bandwidth of the dynamic random access memory according to the data stream, the active bandwidth of the dynamic random access memory can be in a non-constant state, that is, the bandwidth of the dynamic random access memory is not all activated, but is in a change. Therefore, when the bandwidth is not all activated, certain energy consumption is saved; since the specific active bandwidth is controlled according to the data stream of the board card, the bandwidth can meet the demand of the data stream, and certain energy consumption is also saved when the bandwidth is not all activated.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of board card power consumption, and particularly relates to a power consumption control method and device, a board card, electronic equipment and a storage medium. BACKGROUND

[0002] A board card is a printed circuit board, referred to as a PCB board, which can be used as a mainboard of a computer or inserted into a slot of the mainboard through a reserved pin core to control the running of hardware, such as a display, a capture card and the like, and after installation of a driver program, corresponding hardware functions can be realized. The board card generates certain power consumption in the process of processing and transmitting data, and in the related art, due to lack of effective control of the power consumption of the board card, certain energy consumption is wasted. SUMMARY

[0003] The present application provides a power consumption control method and device, a board card, electronic equipment and a storage medium to solve the problems in the related art.

[0004] According to a first aspect of an embodiment of the present application, a power consumption control method is provided, applied to a board card, the board card having a dynamic random access memory, comprising:

[0005] obtaining a data stream of the board card;

[0006] controlling an activation bandwidth of the dynamic random access memory according to the data stream.

[0007] In one embodiment, the board card further has a write controller, a read controller and a cache controller;

[0008] The obtaining of the data stream of the board card comprises:

[0009] obtaining a write data stream from a transmission channel between the write controller and the cache controller;

[0010] obtaining a read data stream from a transmission channel between the read controller and the cache controller;

[0011] determining the data stream according to the write data stream and the read data stream.

[0012] In one embodiment, the board card further has a read-write bus arbitrator;

[0013] The obtaining of the write data stream from the transmission channel between the write controller and the cache controller comprises:

[0014] determining a target write controller from a plurality of write controllers according to an arbitration result of the read-write bus arbitrator;

[0015] obtaining the write data stream from a transmission channel between the target write controller and the cache controller.

[0016] the read data stream is obtained from a transmission channel between the read controller and the cache controller, including:

[0017] a target read controller is determined from the read controllers according to an arbitration result of the read-write bus arbiter;

[0018] the read data stream is obtained from a transmission channel between the target read controller and the cache controller.

[0019] In one embodiment, the data stream of the board card is obtained, including:

[0020] a bandwidth of the data stream is obtained.

[0021] In one embodiment, the board card further has a power supply controller of a flash memory and a dynamic random memory, and the dynamic random memory includes a plurality of dynamic random sub-memories.

[0022] the activation bandwidth of the dynamic random memory is controlled according to the data stream, including:

[0023] an activation number of the dynamic random sub-memories is determined according to the bandwidth of the data stream and the bandwidth of each dynamic random sub-memory;

[0024] in response to the activation number being greater than the number of the activated dynamic random sub-memories, at least one of the activated dynamic random sub-memories is determined as a to-be-idle sub-memory, a configuration file in each to-be-idle sub-memory is copied to the flash memory, and the power supply of each to-be-idle sub-memory is cut off by the power supply controller;

[0025] in response to the activation number being less than the number of the activated dynamic random sub-memories, at least one of the unactivated dynamic random sub-memories is determined as a to-be-activated sub-memory, a configuration file of each to-be-activated sub-memory is read from the flash memory and copied to the corresponding to-be-activated sub-memory, and the power supply of each to-be-activated sub-memory is restored by the power supply controller.

[0026] According to a second aspect of the embodiment of the present application, a power consumption control device is provided, which is applied to a board card having a dynamic random memory, and includes:

[0027] an obtaining module, configured to obtain a data stream of the board card;

[0028] a control module, configured to control an activation bandwidth of the dynamic random memory according to the data stream.

[0029] In one embodiment, the board card further has a write controller, a read controller and a cache controller;

[0030] The acquisition module comprises:

[0031] A write data stream acquisition unit, configured to acquire a write data stream from a transmission channel between the write controller and the cache controller;

[0032] A read data stream acquisition unit, configured to acquire a read data stream from a transmission channel between the read controller and the cache controller;

[0033] A data stream summarization unit, configured to determine a data stream according to the write data stream and the read data stream.

[0034] In one embodiment, the board card further has a read-write bus arbitrator;

[0035] The write data stream acquisition unit is specifically configured to:

[0036] determine a target write controller from a plurality of write controllers according to an arbitration result of the read-write bus arbitrator;

[0037] acquire a write data stream from a transmission channel between the target write controller and the cache controller;

[0038] The read data stream acquisition unit is specifically configured to:

[0039] determine a target read controller from a plurality of read controllers according to an arbitration result of the read-write bus arbitrator;

[0040] acquire a read data stream from a transmission channel between the target read controller and the cache controller.

[0041] In one embodiment, when the acquisition module is used to acquire a data stream of the board card, it is specifically configured to:

[0042] acquire a bandwidth of the data stream.

[0043] In one embodiment, the board card further has a power supply controller of a flash memory and a dynamic random memory, and the dynamic random memory comprises a plurality of dynamic random sub-memories;

[0044] The control module is specifically configured to:

[0045] determine an activation number of the dynamic random sub-memories according to the bandwidth of the data stream and a bandwidth of each dynamic random sub-memory;

[0046] in response to the activated number being greater than the number of activated dynamic random sub-memories, determining at least one of the activated dynamic random sub-memories as a to-be-idle sub-memory, transferring a configuration file in each of the to-be-idle sub-memories to the flash memory, and cutting off power supply of each of the to-be-idle sub-memories by the power supply controller;

[0047] in response to the activated number being less than the number of activated dynamic random sub-memories, determining at least one of the unactivated dynamic random sub-memories as a to-be-activated sub-memory, reading a configuration file of each of the to-be-activated sub-memories from the flash memory, transferring the configuration file to the corresponding to-be-activated sub-memory, and restoring power supply of each of the to-be-activated sub-memories by the power supply controller.

[0048] According to a third aspect of the embodiments of the present application, a board card is provided, comprising a processor, a data input interface, a data output interface, a dynamic random memory, a flash memory, a power supply and a power supply controller of the dynamic random memory, which are connected with the processor respectively;

[0049] The processor is provided with a write controller, a read controller, a read-write bus arbitrator and a cache controller, and the cache controller is connected with the dynamic random memory.

[0050] The dynamic random memory comprises a plurality of dynamic random sub-memories, and the power supply controller is used for controlling power supply of each of the dynamic random sub-memories.

[0051] According to a fourth aspect of the embodiments of the present application, an electronic device is provided, comprising a memory and a processor, the memory is used for storing computer instructions executable on the processor, and the processor is used for executing the computer instructions to implement the method according to the first aspect.

[0052] According to a fifth aspect of the embodiments of the present application, a computer non-transient readable storage medium is provided, which stores a computer program, and the program is executed by a processor to implement the method according to the first aspect.

[0053] According to the above embodiments, by obtaining a data flow of a board card and controlling an activated bandwidth of a dynamic random memory according to the data flow, the activated bandwidth of the dynamic random memory can be in a non-constant state, i.e., the bandwidth of the dynamic random memory is not activated all the time but in a changeable state. Therefore, when the bandwidth is not activated all the time, certain energy consumption is saved. Since the specific activated bandwidth is controlled according to the data flow of the board card, the bandwidth can meet the demand of the data flow, and certain energy consumption is saved when the bandwidth is not activated all the time.

[0054] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application, as claimed. BRIEF DESCRIPTION OF DRAWINGS

[0055] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and serve to explain the principles of the application, in which, like reference numerals designate corresponding elements throughout the several views.

[0056] Figure 1 is a structural schematic diagram of a board card shown in an embodiment of the application;

[0057] Figure 2 is an internal schematic diagram of a processor shown in an embodiment of the application;

[0058] Figure 3 is a flow schematic diagram of a power consumption control method shown in an embodiment of the application;

[0059] Figure 4 is a structural schematic diagram of a power consumption control device shown in an embodiment of the application;

[0060] Figure 5 is a structural schematic diagram of an electronic device shown in an embodiment of the application. DETAILED DESCRIPTION

[0061] The detailed description set forth below in connection with the appended drawings is intended as a description of exemplary embodiments and is not intended to represent the only embodiments consistent with the present application. Rather, the detailed description is intended to represent just one example embodiment consistent with the present application and is not intended to limit the scope of the application in any way as is apparent from the following description and the attached claims.

[0062] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0063] It should be understood that although the terms first, second, third, etc. can be used herein to describe various information, the information should not be limited by these terms. These terms are only used to distinguish one piece of information from another. For example, a first information can be termed a second information without departing from the scope of the present application, similarly, a second information can be termed a first information. The word "if" as used herein means "when" or "upon" or "in response to the determination" depending on the context.

[0064] To address the energy waste problem of circuit boards in related technologies, at least one embodiment of this disclosure provides a power consumption control method applied to circuit boards. Before introducing the power consumption control method, let's first refer to the appendix... Figure 1 and attached Figure 2 The structure and function of the board are explained in detail.

[0065] The board includes a processor 101 (CPU), a data input interface 102, a data output interface 103, a dynamic random access memory (DRAM) 104, a flash memory 105, a power supply 106, and a power supply controller 107 for the DRAM, all connected to the processor 101 (CPU). The processor 101 includes a write controller 1011, a read controller 1012, a read / write bus arbitrator 1013, and a cache controller 1014. The cache controller 1014 is connected to the DRAM 104. The DRAM 104 includes multiple DRAM sub-memories 1041, and the power supply controller 107 controls the power supply to each DRAM sub-memory 1041.

[0066] Among them, the data input interface 102 can be a video input interface such as HDMI interface, DP interface and DVI interface; the data output interface 103 can be a video output interface such as a display screen interface; the dynamic random access memory 104 can be DDR2 SDRAM or DDR3 SDRAM; the flash memory 105 can be Flash memory, and the number can be one or multiple; the power supply 106 can be equipped with a power management module, and can supply power to the processor 101.

[0067] The write controller 1011 can be connected with the data input interface 102, and is configured to convert data input by the data input interface 102 into a storage format of the cache controller 1014 and store the data into the cache controller 1014. The write controller 1011 can be provided in multiple sets, and each set of the write controller 1011 is connected with one data input interface 102. The read controller 1012 can be connected with the data output interface 103, and is configured to read data stored in the cache controller 1014 and convert the data into a format required by the data output interface 103, and transmit the data to the data output interface 103. The read controller 1012 can be provided in multiple sets, and each set of the read controller 1012 is connected with one data output interface 103. Only one of the multiple sets of the write controller 1011 can perform data transmission with the cache controller 1014, and only one of the multiple sets of the read controller 1012 can perform data transmission with the cache controller 1014. Therefore, the read-write bus arbiter 1013 is configured to select the write controller 1011 and / or the read controller 1012 that performs data transmission with the cache controller 1014. For example, when one video (video 1) is input, the data of the video 1 is written into the first write controller 1011 (FIFO). If the cache controller 1014 is idle, the data in the first write controller 1011 is written into the cache controller 1014, and the data of another video (video 2) is written into the second write controller 1011. After the data of the video 1 is written into the cache controller 1014, the first write controller 1011 releases the occupation of the cache controller 1014, and the second write controller 1011 occupies the cache controller 1014 to write the data of the video 2 into the cache controller 1014. The above operation is repeated to complete the cyclic operation of the two videos. For another example, the data of the video is read from the cache controller 1014. Because the time sequence of external display is relatively slow, and the time sequence of reading from the cache controller 1014 is relatively fast, the read controller 1012 is used to buffer the data read from the cache controller 1014 to match the different time sequences of the data. The cache controller 1014 is configured to write and read data into and from the dynamic random access memory 104.

[0068] Next, based on the structure and functions of the above board card, a power consumption control method provided by at least one embodiment of the present disclosure is introduced. Figure 3 which shows the flow of the method, including steps S301 and S302.

[0069] The method can be applied to a board card, such as a SOC (System on Chip) board card, and can be applied to the processor 101 of the board card.

[0070] In step S301, a data stream of the board card is acquired.

[0071] The data stream is used to control the bandwidth of the dynamic random memory 104 in step S302, so the bandwidth of the data stream can be acquired to match the bandwidth of the board card data stream with the bandwidth of the dynamic random memory 104.

[0072] The data stream can include a write data stream and / or a read data stream, so the write data stream and the read data stream can be acquired respectively and then the data stream is obtained by summarizing. That is, the data stream is acquired in the following way: first, the write data stream is acquired from the transmission channel between the write controller 1011 and the cache controller 1014; next, the read data stream is acquired from the transmission channel between the read controller 1012 and the cache controller 1014; finally, the data stream is determined according to the write data stream and the read data stream.

[0073] Since there can be multiple write controls, when the write data stream is acquired from the transmission channel between the write controller 1011 and the cache controller 1014, a target write controller can be determined from the multiple write controllers 1011 according to the arbitration result of the read-write bus arbiter 1013, and then the write data stream is acquired from the transmission channel between the target write controller and the cache controller 1014. That is, the data stream is acquired from the write controller 1011 that is currently transmitting data with the cache controller 1014, so the pertinence, accuracy and efficiency are improved.

[0074] Since there can be multiple read controls, when the read data stream is acquired from the transmission channel between the read controller 1012 and the cache controller 1014, a target read controller can be determined from the multiple read controllers 1012 according to the arbitration result of the read-write bus arbiter 1013, and then the read data stream is acquired from the transmission channel between the target read controller and the cache controller 1014. That is, the data stream is acquired from the read controller that is currently transmitting data with the cache controller 1014, so the pertinence, accuracy and efficiency are improved.

[0075] When the read data stream and the write data stream are summarized, their bandwidths can be summed as the summary result, or the maximum one can be taken as the summary result.

[0076] In step S302, the active bandwidth of the dynamic random memory is controlled according to the data stream.

[0077] The number of activated dynamic random sub-memories 1041 is determined according to the bandwidth of the data stream and the bandwidth of each dynamic random sub-memory 1041; the number of activated dynamic random sub-memories 1041 is controlled according to the relationship between the number of activated dynamic random sub-memories 1041 and the number of activated dynamic random sub-memories 1041, that is, at least one activated dynamic random sub-memory 1041 is determined as a sub-memory to be idle, the configuration file in each of the sub-memories to be idle is transferred to the flash memory 105, the power supply of each of the sub-memories to be idle is cut off, and at least one unactivated dynamic random sub-memory 1041 is determined as a sub-memory to be activated, the configuration file of each of the sub-memories to be activated is read from the flash memory 105, the configuration file is transferred to the corresponding sub-memory to be activated, and the power supply of each of the sub-memories to be activated is restored.

[0078] The sub-memory whose configuration file is transferred to the flash memory 105 and whose power supply is cut off is idle, that is, suspended, so that the sub-memory does not exist in power consumption, thereby saving the power consumption of the idle sub-memory.

[0079] The number of sub-memories to be idle can be obtained by subtracting the number of activated dynamic random sub-memories 1041 from the number of activated dynamic random sub-memories 1041, and the number of sub-memories to be activated can be obtained by subtracting the number of activated dynamic random sub-memories 1041 from the number of activated dynamic random sub-memories 1041. That is, after the sub-memory to be idle is idle, the number of activated dynamic random sub-memories 1041 is equal to the number of activated dynamic random sub-memories 1041, and after the sub-memory to be activated is activated, the number of activated dynamic random sub-memories 1041 is equal to the number of activated dynamic random sub-memories 1041.

[0080] In a display system, the bandwidth usage of the dynamic random memory 104 is basically constant after a certain mode is selected, and only when the mode is switched (such as input channel selection, input source change, etc.) the bandwidth will change greatly. For example, when the input changes from a 1920x1080 resolution video format to a 3840x2160 input format, the bandwidth usage becomes 4 times the original. The control method provided by the embodiment of the disclosure can accurately adjust the bandwidth when the display system mode is switched.

[0081] For example, the dynamic random memory 104 includes 4 dynamic random sub-memories 1041, the total bandwidth analyzer can be used to analyze the bandwidth required by the resolution of the input video, if 32 bits are required, the data of the last two dynamic random sub-memories 1041 is configured to be stored in the flash memory 105, the processor 101 stops the data read and write of the last two dynamic random sub-memories 1041, and at the same time, a control signal is given to control the power supply of the two dynamic random sub-memories 1041 to be turned off, and the data is read in the first two dynamic random sub-memories 1041; when a high-resolution video is transmitted, for example, the total data is 64 bits, the configuration information in the flash memory 105 is restored to the corresponding dynamic random sub-memory 1041, and at the same time, the power supply of the two dynamic random sub-memories 1041 is restored.

[0082] According to the above embodiment, by acquiring the data flow of the board card and controlling the active bandwidth of the dynamic random memory according to the data flow, the active bandwidth of the dynamic random memory can be in a non-constant state, that is, the bandwidth of the dynamic random memory is not all activated, but is in a changing state. Therefore, when the bandwidth is not all activated, a certain energy consumption is saved; since the specific active bandwidth is controlled according to the data flow of the board card, the bandwidth can meet the demand of the data flow, and a certain energy consumption is saved when the bandwidth is not all activated.

[0083] On the other hand, at least one embodiment of the present disclosure provides a power consumption control device applied to a board card, please refer to the accompanying Figure 4 which shows the structure diagram of the device, including:

[0084] The acquisition module 401 is configured to acquire a data flow of the board card.

[0085] The control module 402 is configured to control an active bandwidth of the dynamic random memory according to the data flow.

[0086] In some embodiments of the present disclosure, the board card further has a write controller, a read controller and a cache controller.

[0087] The acquisition module includes:

[0088] The write data flow acquisition unit is configured to acquire a write data flow from a transmission channel between the write controller and the cache controller.

[0089] The read data flow acquisition unit is configured to acquire a read data flow from a transmission channel between the read controller and the cache controller.

[0090] The data flow summarizing unit is configured to determine a data flow according to the write data flow and the read data flow.

[0091] In some embodiments of the present disclosure, the board card further has a read-write bus arbitrator;

[0092] The write data stream acquisition unit is specifically configured to:

[0093] determine a target write controller from the plurality of write controllers according to an arbitration result of the read-write bus arbitrator;

[0094] acquire a write data stream from a transmission channel between the target write controller and the cache controller;

[0095] The read data stream acquisition unit is specifically configured to:

[0096] determine a target read controller from the plurality of read controllers according to an arbitration result of the read-write bus arbitrator;

[0097] acquire a read data stream from a transmission channel between the target read controller and the cache controller.

[0098] In some embodiments of the present disclosure, when the acquisition module is used to acquire a data stream of the board card, it is specifically configured to:

[0099] acquire a bandwidth of the data stream.

[0100] In some embodiments of the present disclosure, the board card further has a power supply controller of a flash memory and a dynamic random memory, and the dynamic random memory includes a plurality of dynamic random sub-memories;

[0101] The control module is specifically configured to:

[0102] determine an activation number of the dynamic random sub-memories according to the bandwidth of the data stream and a bandwidth of each of the dynamic random sub-memories;

[0103] in response to the activation number being greater than a number of the dynamic random sub-memories that are activated, determine at least one of the dynamic random sub-memories that are activated as a to-be-idle sub-memory, transfer a configuration file in each of the to-be-idle sub-memories to the flash memory, and cut off power supply of each of the to-be-idle sub-memories through the power supply controller;

[0104] in response to the activation number being less than the number of the dynamic random sub-memories that are activated, determine at least one of the dynamic random sub-memories that are not activated as a to-be-activated sub-memory, read a configuration file of each of the to-be-activated sub-memories from the flash memory, transfer the configuration file to the corresponding to-be-activated sub-memory, and restore power supply of each of the to-be-activated sub-memories through the power supply controller.

[0105] As to the apparatus in the above-mentioned embodiments, the specific manner in which each module performs operations has been described in detail in the embodiments related to the method, and thus will not be described in detail here.

[0106] In yet another aspect, at least one embodiment of the present application provides an electronic device, please refer to the accompanying Figure 5 which shows the structure of the device, the device includes a memory, a processor, the memory is used to store computer instructions that can be run on the processor, the processor is used to implement the power consumption control method when executing the computer instructions.

[0107] In yet another aspect, at least one embodiment of the present application provides a computer non-transient readable storage medium, which stores a computer program, the program is executed by the processor to implement the power consumption control method.

[0108] In the present application, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance. The term "a plurality of" refers to two or more, unless otherwise explicitly limited.

[0109] Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. The present application is intended to cover any variations, uses or adaptive changes of this application following the general principles thereof and including the general knowledge or custom of this art. The specification and examples are to be regarded as illustrative only, and the true scope and spirit of the present application are indicated by the following claims.

[0110] It should be understood that the present application is not limited to the precise structures described above and shown in the drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A power consumption control method, characterized in that, Applied to a board, the board having dynamic random access memory, a write controller, a read controller, a cache controller, and a read / write bus arbiter, including: Obtain the data stream of the board; The activation bandwidth of the dynamic random access memory is controlled according to the data flow; The process of acquiring the data stream of the board includes: The write data stream is obtained from the transmission channel between the write controller and the cache controller; The read data stream is obtained from the transmission channel between the read controller and the cache controller; The data stream is determined based on the write data stream and the read data stream; The step of obtaining the write data stream from the transmission channel between the write controller and the cache controller includes: Based on the arbitration result of the read / write bus arbitrator, a target write controller is determined from among the multiple write controllers; The write data stream is obtained from the transmission channel between the target write controller and the cache controller; The step of obtaining the read data stream from the transmission channel between the read controller and the cache controller includes: Based on the arbitration result of the read / write bus arbitrator, a target read controller is determined from among the multiple read controllers; The read data stream is obtained from the transmission channel between the target read controller and the cache controller.

2. The power consumption control method according to claim 1, characterized in that, The process of acquiring the data stream of the board includes: Obtain the bandwidth of the data stream.

3. The power consumption control method according to claim 2, characterized in that, The board also has a power supply controller for flash memory and dynamic random access memory, the dynamic random access memory including multiple dynamic random access sub-memories; The step of controlling the activation bandwidth of the dynamic random access memory according to the data flow includes: The number of activated dynamic random sub-memories is determined based on the bandwidth of the data stream and the bandwidth of each dynamic random sub-memory. In response to the activation number being greater than the number of activated dynamic random sub-memories, at least one activated dynamic random sub-memory is identified as a sub-memory to be idled, the configuration file in each sub-memory to be idled is transferred to the flash memory, and the power supply to each sub-memory to be idled is cut off by the power supply controller. In response to the fact that the number of activated sub-memories is less than the number of activated dynamic random sub-memories, at least one inactive dynamic random sub-memory is identified as a sub-memory to be activated. The configuration file of each sub-memory to be activated is read from the flash memory and transferred to the corresponding sub-memory to be activated. The power supply to each sub-memory to be activated is restored through the power supply controller.

4. A power consumption control device, characterized in that, Applied to a board, the board having dynamic random access memory, a write controller, a read controller, a cache controller, and a read / write bus arbiter, including: The acquisition module is used to acquire the data stream of the board; A control module is used to control the activation bandwidth of the dynamic random access memory according to the data stream; The acquisition module includes: A write data stream acquisition unit is used to acquire a write data stream from the transmission channel between the write controller and the cache controller; A read data stream acquisition unit is used to acquire a read data stream from the transmission channel between the read controller and the cache controller; A data stream aggregation unit is used to determine a data stream based on the write data stream and the read data stream; The write data stream acquisition unit is specifically used for: Based on the arbitration result of the read / write bus arbitrator, a target write controller is determined from among the multiple write controllers; The write data stream is obtained from the transmission channel between the target write controller and the cache controller; The read data stream acquisition unit is specifically used for: Based on the arbitration result of the read / write bus arbitrator, a target read controller is determined from among the multiple read controllers; The read data stream is obtained from the transmission channel between the target read controller and the cache controller.

5. The power consumption control device according to claim 4, characterized in that, When the acquisition module is used to acquire the data stream of the board, it is specifically used for: Obtain the bandwidth of the data stream.

6. The power consumption control device according to claim 5, characterized in that, The board also has a power supply controller for flash memory and dynamic random access memory, the dynamic random access memory including multiple dynamic random access sub-memories; The control module is specifically used for: The number of activated dynamic random sub-memories is determined based on the bandwidth of the data stream and the bandwidth of each dynamic random sub-memory. In response to the activation number being greater than the number of activated dynamic random sub-memories, at least one activated dynamic random sub-memory is identified as a sub-memory to be idled, the configuration file in each sub-memory to be idled is transferred to the flash memory, and the power supply to each sub-memory to be idled is cut off by the power supply controller. In response to the fact that the number of activated sub-memories is less than the number of activated dynamic random sub-memories, at least one inactive dynamic random sub-memory is identified as a sub-memory to be activated. The configuration file of each sub-memory to be activated is read from the flash memory and transferred to the corresponding sub-memory to be activated. The power supply to each sub-memory to be activated is restored through the power supply controller.

7. A circuit board, characterized in that, It includes a processor, a data input interface and a data output interface respectively connected to the processor, a dynamic random access memory, a flash memory, a power supply and a power supply controller for the dynamic random access memory; The processor includes a write controller, a read controller, a read-write bus arbitrator, and a cache controller, the cache controller being connected to the dynamic random access memory; the processor is used to execute the method as described in any one of claims 1 to 3. The dynamic random access memory includes multiple dynamic random sub-memories, and the power supply controller is used to control the power supply to each of the dynamic random sub-memories.

8. An electronic device, characterized in that, The device includes a memory and a processor, the memory being used to store computer instructions executable on the processor, and the processor being used to execute the computer instructions based on the method of any one of claims 1 to 3.

9. A computer non-transient readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method according to any one of claims 1 to 3.

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