Full level programming of memory devices in memory subsystems

Abstract

This application relates to full level programming of memory devices in a memory sub-system. Control logic in a memory device identifies a set of a plurality of memory cells of a multi-level cell (MLC) memory configured to be programmed during a program operation and applies a ramping word line voltage to a set of word lines associated with a memory array during a first period of the program operation. The control logic causes a set of pillars associated with the set of memory cells to be disconnected from a power supply voltage and a ground voltage during the first period, where each pillar corresponds to a program level of a set of program levels. The control logic further causes a set of program pulses to be applied to the set of memory cells during a second period of the program operation, where each program pulse of the set of program pulses programs each program level of the set of program levels associated with the identified set of memory cells.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to full-level programming of memory devices within memory subsystems. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, the host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] One aspect of this disclosure provides a memory device comprising: a memory array including a plurality of memory cells configured as multilevel cell (MLC) memory; and control logic operatively coupled to the memory array to perform operations including: identifying a group of the plurality of memory cells programmed during a programming operation; during a first time period of the programming operation, causing a swashplate word line voltage to be applied to a group of word lines associated with the memory array; during the first time period, causing a group of posts associated with the group of memory cells to be disconnected from a power supply voltage and a ground voltage, wherein each post corresponds to a corresponding programming level in a set of programming levels; and during a second time period of the programming operation, causing a programming pulse to be applied to the group of memory cells, wherein the programming pulse programs each of the set of programming levels associated with the identified group of memory cells.

[0004] Another aspect of this disclosure provides a method comprising: identifying a group of a plurality of memory cells programmed during a programming operation; during a first time period of the programming operation, causing a ramp word line voltage to be applied to a group of word lines associated with a memory array; during the first time period, causing a group of posts associated with the group of memory cells to be disconnected from a power supply voltage and a ground voltage, wherein each post corresponds to a programming level in a set of programming levels; and during a second time period of the programming operation, causing a set of programming pulses to be applied to the group of memory cells, wherein each programming pulse in the set of programming pulses programs each programming level in the set of programming levels associated with the identified group of memory cells.

[0005] Another aspect of this disclosure provides a memory device comprising: a memory array including a plurality of memory cells; and control logic operatively coupled to the memory array to perform operations including: during a first time period of programming operation, applying a swashplate word line voltage to a set of word lines associated with the memory array; during a first set of different times during the first time period, causing a corresponding column in a set of columns associated with the plurality of memory cells to float, wherein the voltage of each column increases with each increase of the swashplate word line voltage during the floating; and during a second time period, causing a first programming pulse to be applied to a set of memory cells, wherein the first programming pulse programs each of a set of programming levels associated with the identified set of memory cells. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof.

[0007] Figure 1A This describes an instance computing system including a memory subsystem according to some embodiments.

[0008] Figure 1B This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to an embodiment.

[0009] Figures 2A to 2C This is a reference based on the embodiments. Figure 1B A schematic diagram of a portion of the memory cell array in the described type of memory.

[0010] Figure 3 This is a reference based on the embodiments. Figure 1B A schematic block diagram of a portion of the memory cell array in the described type of memory.

[0011] Figure 4 This describes an example memory array comprising word lines and bit lines corresponding to a plurality of programming levels programmed according to one or more embodiments of the present disclosure.

[0012] Figure 5 This describes an example programming pulse waveform corresponding to full-level programming of a memory device in a memory subsystem according to one or more embodiments of the present disclosure.

[0013] Figure 6 This describes an example programming operation comprising a plurality of pulses for full-level programming of a memory device in a memory subsystem, according to one or more embodiments of the present disclosure.

[0014] Figure 7This is a flowchart of an example method for full-level programming of a memory device in a memory subsystem according to one or more embodiments of the present disclosure.

[0015] Figure 8 This is a block diagram of an example computer system operable in accordance with embodiments of this disclosure. Detailed Implementation

[0016] This disclosure relates to full-level programming of memory devices in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. The following is combined with… Figure 1A Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components such as memory devices for storing data. The host system can provide data stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0017] The memory subsystem may include high-density non-volatile memory devices, where it is desirable to retain data when no power is supplied to the memory devices. One example of a non-volatile memory device is a NAND flash memory device. Other examples of non-volatile memory devices are described below. Figure 1A Description. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logical states associated with the numbers of the stored bits. Logical states may be represented by binary values ​​such as “0” and “1” or combinations of such values.

[0018] Memory cells are formed on a silicon wafer as an array of columns (hereinafter also referred to as "bit lines") and rows (hereinafter also referred to as "word lines"). A word line can refer to one or more rows of memory cells in a memory device, which, together with one or more bit lines, is used to generate the address of each memory cell. The intersection of a bit line and a word line constitutes the address of the memory cell.

[0019] A block, hereinafter, refers to a cell in a memory device used for storing data and may comprise a group of memory cells, a group of word lines, a word line, or an individual memory cell. Each block may contain several sub-blocks, each defined by an associated pillar (e.g., a vertical conductive trace) extending from a shared bit line. A memory page (also referred to herein as a “page”) stores one or more bits of binary data corresponding to data received from a host system. To achieve high density, a string of memory cells in a non-volatile memory device may be configured to comprise several memory cells that at least partially surround pillars of polysilicon channel material (i.e., channel regions). Memory cells may be coupled to access lines (i.e., word lines) typically fabricated together with the memory cells to form a string array (e.g., a memory array) in the memory block. The compactness of some non-volatile memory devices (e.g., 3D flash NAND memory) means that word lines are shared for many memory cells within a memory block. Some memory devices use certain types of memory cells (such as three-level cell (TLC) memory cells), which store three data bits in each memory cell, and can enable more applications to be moved from older hard drives to newer memory subsystems (such as NAND solid-state drives (SSDs)).

[0020] Memory access operations (such as programming and erasing operations) can be performed relative to memory cells by applying word line bias voltages to word lines connected to memory cells of the selected page. For example, during a programming operation, one or more selected memory cells can be programmed by applying a programming voltage to the selected word line. In one approach, an incremental step pulse programming (ISPP) process or scheme can be employed to maintain a tight cell threshold voltage distribution for higher data reliability. In ISPP, a series of high-amplitude pulses with increasing voltage levels (e.g., according to a predefined pulse step height) are applied to word lines connected to one or more memory cells to gradually increase the voltage level of the memory cells to a level higher than the word line voltage level corresponding to the memory access operation (e.g., the target programming level). The word line driver of the memory device applies uniformly increasing pulses to enable the selected word line to be scaled or increased to the word line voltage level (V) corresponding to the memory access operation. wl Similarly, a series of voltage pulses with uniformly increasing voltage levels can be applied to the word lines to swash the word lines to the corresponding word line voltage levels during an erase operation.

[0021] A series of incremental voltage programming pulses are applied to selected word lines to increase the charge level of each memory cell connected to the word line, thereby increasing the threshold voltage. After each programming pulse or after several programming pulses, a programming verification operation is performed to determine whether the threshold voltage of one or more memory cells has increased to the desired programming level. For example, the pulse value can be incremented (e.g., by a step voltage value, such as 0.33V) to increase the charge stored in the charge storage structure corresponding to each pulse. The memory device can achieve a target programming level voltage for a specific programming level by incrementally storing or increasing the amount of charge corresponding to the programming step voltage.

[0022] According to this method, a series of programming pulses and programming verification operations are applied to sequentially program each programming level (e.g., programming levels L1 to L7 of a TLC memory cell). For example, this method sequentially programs the levels (e.g., L1 to L7) of the memory cell by applying a first set of pulses to program level L1 to a first target voltage level, then applying a second set of pulses to program level L2 to a second target voltage level, and so on, until all levels are programmed.

[0023] In this method, each level requires multiple programming pulses and programming verification operations to reach the target programming voltage associated with the corresponding programming level. Therefore, this results in a long programming time associated with one or more memory cells (e.g., the time from the initial programming pulse until the programming verification threshold voltage is reached, also known as Tprog). For example, programming each level of a TLC memory cell one at a time (e.g., programming levels L1 to L7) requires a large number of total programming pulses (e.g., approximately 24 pulses) and a large number of associated programming verification operations (e.g., approximately 42 programming verification operations). In this example, if the time associated with each pulse is 37.5 μs, then the total time for a set of pulses (i.e., 24 pulses) is 900 μs. Additionally, the time associated with performing the program verification operations can add an extra 900 μs, resulting in a total programming time of, for example, 1800 μs.

[0024] Additionally, sequential programming of each level results in higher bit power and higher peak current levels, which can lead to performance degradation. Specifically, this method requires faster word line slack, which results in high peak current levels or spikes.

[0025] This disclosure addresses the aforementioned and other drawbacks by implementing full-level programming of memory devices in a memory subsystem. In one embodiment, instead of programming multiple levels (e.g., levels L1 to L7 of a TLC memory cell) sequentially, each programming pulse programs all levels simultaneously. In this embodiment, a full-level programming operation is performed so that each programming pulse can program all levels of the selected word line. In this embodiment, the full-level programming operation includes a first phase in which an increased or ramped word line voltage (e.g., a voltage applied to one or more word lines that is periodically ramped or increased by a step voltage amount) is applied to a set of word lines of the memory array (e.g., selected word lines and one or more unselected word lines). In this embodiment, during the first phase, corresponding pillars (e.g., vertical conductive traces) corresponding to the programming levels (e.g., L1 to L6 of a TLC memory device) are floated (e.g., disconnected from both the power supply voltage and ground). In this embodiment, a set of pillars corresponding to different programming levels floats sequentially during the first phase (e.g., the first pillar corresponding to L1 floats at a first time, the second pillar corresponding to L2 floats at a second time, and so on).

[0026] In one embodiment, the pillar can be floated by turning off both the Select Gate Drain (SGD) and the Select Gate Source (SGS) (e.g., switching the selected SGD from a high voltage level (Vsgd_high) to approximately 0V to prevent the corresponding bit line from discharging to the corresponding pillar). In another embodiment, the bit line corresponding to the first pillar associated with programming level L1 is switched from approximately 0V to a high voltage level (Vbl_high) to ensure that the pillar remains floated during the remainder of the first phase (e.g., when a scalar word line voltage is applied).

[0027] In this embodiment, once a column floats, the voltage of each column can be increased or increased according to the step or increase of the swashplate voltage. At the end of the first phase, the column voltage level (Vpillar) is increased to different voltage levels (e.g., Vpillar for programming level L1 is increased to the highest value, Vpillar for programming level L2 is increased to the second highest value, until Vpillar for programming level L0 remains at 0V during the first phase).

[0028] In one embodiment, the full-level programming operation includes a second stage in which a programming pulse is applied to the target word line. In another embodiment, the programming pulse is applied to program all programming levels (e.g., L1 to L7 of a TLC memory device). In yet another embodiment, the first and second stages can be performed iteratively until the programming of all programming levels is verified. In yet another embodiment, each iteration of the second stage of the programming operation includes applying a programming pulse, wherein each programming pulse simultaneously programs all programming levels.

[0029] For each pulse in a set of pulses, a programming verification operation can be performed on each programming level to verify that the target voltage corresponding to each respective programming level has been reached. This results in a significant reduction in the number of programming pulses required to program all levels of the target word line. The advantages of this method include (but are not limited to) improved performance of the memory subsystem. The reduced number of programming pulses required to program all levels results in reduced programming time, less power per bit, and reduced peak word line current. Furthermore, in this embodiment, a program verification operation is performed on each programming pulse and each programming level, thus eliminating the need to skip programming verification, thereby simplifying the control of the memory subsystem and achieving the verified target programming level. Therefore, the overall quality of service provided by the memory subsystem is improved.

[0030] Furthermore, after each programming pulse, various programming distributions of memory cells corresponding to different memory cells are established. Each distribution may contain cells programmed at a rate different from other cells corresponding to the same programming level. For example, within a given programming cycle, a fast cell may have a higher threshold voltage than a slow cell. Therefore, a faster memory cell may be programmed before a slower cell because the faster cell requires fewer programming pulses. This can result in the threshold voltage (Vt) or programming distribution of the faster cell differing from the threshold voltage distribution of the slower cell. Additionally, within a given programming cycle, a slower memory cell may have a relatively lower threshold voltage than other memory cells corresponding to the same programming level.

[0031] According to aspects of this disclosure, after a programming pulse is applied as part of a full-level programming operation, one or more regions of memory cells within a programming distribution corresponding to a target programming level (e.g., target level Ln) can be identified. One or more regions of memory cells associated with fast cells (e.g., memory cell regions located in the upper tail of the corresponding programming distribution) can be identified based on a comparison of a corresponding threshold voltage following the pulse with one or more programming verification voltage levels. In embodiments, one or more memory cells identified in one or more regions can undergo a level shift operation, wherein the identified memory cells are logically shifted to a lower programming level (e.g., Ln-1, Ln-2, ​​etc.) and programmed using a lower programming intensity during subsequent iterations of the first and second phases of the full-level programming operation.

[0032] This disclosure further relates to identifying one or more regions of slow memory cells (e.g., memory cell regions located in the lower tail of a corresponding programming distribution) based on a comparison of a corresponding threshold voltage following a pulse with one or more programming verification voltage levels. In embodiments, the one or more memory cells identified in these regions may undergo a level shift operation, wherein the identified memory cells are logically shifted from a first programming level (e.g., Ln+1) to a higher programming level (e.g., Ln+2, Ln+3, etc.) and programmed using a higher programming intensity during the first phase and subsequent iterations of the second phase of a full-level programming operation.

[0033] Figure 1A This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., one or more memory devices 130), or a combination thereof.

[0034] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital storage (SD) devices, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0035] The computing system 100 may be a computing device including, for example, a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, drone, train, car or other means of transport), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment or networked commercial device), or such a computing device including memory and processing.

[0036] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1A This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0037] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110 (for example) to write data to and read data from memory subsystem 110.

[0038] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include (but are not limited to) Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Double Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM socket interfaces supporting Double Data Rate (DDR)), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1A The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0039] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (such as memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0040] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-situ write memory, such as a three-dimensional crosspoint (“3D crosspoint”) memory device, which is a crosspoint array of non-volatile memory cells. The crosspoint array of non-volatile memory can perform bit storage based on volume resistance variations combined with a stackable crossgate format data access array. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-situ write operations, where non-volatile memory cells can be programmed without prior erasing of the non-volatile memory cells. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0041] Each of the memory devices 130 may include one or more arrays of memory cells. For example, one type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include SLC portions and MLC portions, TLC portions, QLC portions, or PLC portions of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks. In one embodiment, the term "MLC memory" may be used to refer to any type of memory cell that stores more than one bit per cell (e.g., 2 bits, 3 bits, 4 bits, or 5 bits per cell).

[0042] Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND flash memories (e.g., 2D NAND, 3D NAND) have been described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0043] The memory subsystem controller 115 (or controller 115, for simplicity) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0044] The memory subsystem controller 115 may be a processing means configured to execute instructions stored in local memory 119, and may include one or more processors (e.g., processor 117). In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0045] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although already Figure 1A The instance memory subsystem 110 is described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0046] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, discard item collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions for accessing the memory device 130, and also translate responses associated with the memory device 130 into information for the host system 120.

[0047] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0048] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0049] In one embodiment, memory subsystem 110 includes memory interface component 113. Memory interface component 113 is responsible for handling interactions between memory subsystem controller 115 and memory devices of memory subsystem 110, such as memory device 130. For example, memory interface component 113 may send memory access commands corresponding to requests received from host system 120 to memory device 130, such as programming commands, read commands, or other commands. Additionally, memory interface component 113 may receive data from memory device 130, such as data retrieved in response to a read command or confirmation of successful execution of a programming command. For example, memory subsystem controller 115 may include processor 117 (processing means) configured to execute instructions stored in local memory 119 to perform the operations described herein.

[0050] In one embodiment, memory device 130 includes a program manager 134 configured to perform a corresponding memory access operation in response to receiving a memory access command from memory interface 113. In some embodiments, local media controller 135 includes at least a portion of program manager 134 and is configured to perform the functionality described herein. In some embodiments, program manager 134 is implemented on memory device 130 using firmware, hardware components, or a combination thereof. In one embodiment, program manager 134 receives a request from, for example, a requester of memory interface 113 to program data into a memory array of one or more memory devices 130. The memory array may comprise an array of memory cells formed at the intersections of word lines and bit lines. In one embodiment, memory cells are grouped into blocks, and blocks may be further divided into sub-blocks, wherein, for example, a given word line is shared across several sub-blocks. In one embodiment, each sub-block corresponds to a separate plane in the memory array. The group of memory cells associated with a word line within a sub-block is called a physical page. In one embodiment, a memory array may exist in multiple portions, such as a first portion where sub-blocks are configured as SLC memory and a second portion where sub-blocks are configured as multilevel cell (MLC) memory (i.e., memory cells containing two or more bits of information per cell). For example, the second portion of the memory array may be configured as TLC memory. The voltage levels of the memory cells in the TLC memory form a set of eight programming distributions, representing eight different combinations of the three bits stored in each memory cell. Depending on their configuration, each physical page in one of the sub-blocks may contain multiple page types. For example, a physical page formed by a single-level cell (SLC) has a single page type called a lower logic page (LP). The multilevel cell (MLC) physical page type may contain LP and an upper logic page (UP), the TLC physical page type is LP, UP, and an additional logic page (XP), and the QLC physical page type is LP, UP, XP, and a top logic page (TP). For example, a physical page formed by memory cells of the QLC memory type may have a total of four logical pages, where each logical page may store data that is different from the data stored in other logical pages associated with the physical page.

[0051] In one embodiment, program manager 134 may receive data programmed into memory device 130 (e.g., a TLC memory device). Therefore, program manager 134 may perform a full-level programming operation to program each memory cell to one of eight possible programming levels (i.e., voltages representing eight different values ​​for the three bits). In one embodiment, program manager 134 may program memory cells in the TLC portion of the memory array to all of the multiple corresponding programming levels (e.g., programming levels L0, L1, L2…L7), where each programming pulse programs all programming levels from L1 to L7. For example, after identifying a set of memory cells to be programmed (e.g., memory cells associated with one or more word lines of the memory array), program manager 134 may perform a first stage of the full-level programming operation, where a ramp word line voltage is applied and each pillar corresponding to the respective programming level floats. In an embodiment, the voltage (Vpillar) of each pillar may be boosted using the ramp word line voltage while floating.

[0052] In one embodiment, program manager 134 may perform a second phase of a full-level programming operation such that a single programming pulse (e.g., a set of programming pulses) is applied to an identified group of memory cells to program the memory cells to each of a plurality of corresponding programming levels (i.e., L1, L2, ... L7). In another embodiment, program manager 134 may perform a programming verification operation corresponding to each programming pulse and programming level to verify whether the memory cells in the group are programmed to all corresponding programming levels. Program manager 134 may perform a first phase and a second phase (where each iteration of the second phase includes applying a programming pulse) until all programming levels reach the corresponding target programming voltage level. Program manager 134 may identify one or more regions of memory cells in a target programming distribution (e.g., Ln) that satisfy conditions associated with one or more programming verification voltage levels associated with the target programming level and logically shift the memory cells in the region to a lower programming level (e.g., Ln-1, Ln-2, ​​etc.) (also referred to as a "level downshift operation" or "level downshift operation"). In this embodiment, memory cells in one or more identified regions are programmed using a lower programming strength during the first and subsequent iterations of the second phase of the full-level programming operation. Additionally, the program manager 134 can identify one or more regions of memory cells with a programming distribution of threshold voltages (e.g., Ln+1) that satisfies conditions corresponding to one or more programming verification voltage levels associated with another programming level (e.g., Ln) and logically shift the memory cells in said regions to a higher programming level (e.g., Ln+2, Ln+3, etc.) (also referred to as a "level up operation" or "level up operation"). In this embodiment, memory cells in these regions are programmed using a higher programming strength during the first and subsequent iterations of the second phase of the full-level programming operation. Further details regarding the operation of the program manager 134 are described below.

[0053] Figure 1B It is a present memory subsystem according to an embodiment (e.g.) Figure 1A This is a simplified block diagram of a first device in the form of a memory device 130 communicating with a second device in the form of a memory subsystem 110 and a memory subsystem controller 115. Examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, game consoles, home appliances, vehicles, wireless devices, mobile phones, and the like. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0054] Memory device 130 includes an array 150 of memory cells logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access line (e.g., a word line), while memory cells in logical columns are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with memory cells in more than one logical row, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 150 ( Figure 1B (Not shown in the text) It can be programmed to one of at least two target data states.

[0055] Row decoding circuitry 108 and column decoding circuitry 110 are provided to decode address signals. Address signals are received and decoded to access memory cell array 150. Memory device 130 also includes input / output (I / O) control circuitry 112 for managing commands, addresses, and data input to and from memory device 130 and outputting data and status information from memory device 130. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 110 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 112 and local media controller 135 to latch incoming commands.

[0056] A controller (e.g., a local media controller 135 within memory device 130) controls access to memory cell array 150 in response to commands and generates status information for external memory subsystem controller 115. Specifically, the local media controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on memory cell array 150. The local media controller 135 communicates with row decoding circuitry 108 and column decoding circuitry 110 to control them in response to addresses. In one embodiment, the local media controller 135 includes a program manager 134 capable of implementing full-level programming of memory device 130, as described herein.

[0057] The local media controller 135 also communicates with cache register 118. Cache register 118 latches incoming or outgoing data according to instructions from the local media controller 135 to temporarily store data while memory cell array 150 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 118 to data register 120 to memory cell array 150; subsequently, new data can be latched from I / O control circuitry 112 into cache register 118. During read operations, data can be transferred from cache register 118 to I / O control circuitry 112 to memory subsystem controller 115; subsequently, new data can be transferred from data register 120 to cache register 118. Cache register 118 and / or data register 120 may form a page buffer for memory device 130 (e.g., may form part of a page buffer for memory device 100). The page buffer may further include sensing means for sensing the data state of the memory cells, for example, by sensing the state of the data lines connected to the memory cells in the memory cell array 150. Figure 1B (Not shown in the image). Status register 122 can communicate with I / O control circuitry 112 and local memory controller 135 to latch status information for output to memory subsystem controller 115.

[0058] Memory device 130 receives control signals from local media controller 135 via control link 132 at memory subsystem controller 115. For example, control signals may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protection signal WP#. Additional or alternative control signals (not shown) may be further received via control link 132 depending on the nature of memory device 130. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 134 and outputs data to memory subsystem controller 115 via I / O bus 134.

[0059] For example, commands can be received at I / O control circuitry 112 via I / O bus 134 input / output (I / O) pins [7:0] and then written to command register 124. Addresses can be received at I / O control circuitry 112 via I / O bus 134 input / output (I / O) pins [7:0] and then written to address register 114. Data can be received at I / O control circuitry 112 via 8-bit device input / output (I / O) pins [7:0] or 16-bit device input / output (I / O) pins [15:0] and then written to cache register 118. Data can then be written to data register 120 to program memory cell array 150.

[0060] In this embodiment, cache register 118 may be omitted, and data may be written directly to data register 120. Data may also be output via input / output (I / O) pins [7:0] of an 8-bit device or input / output (I / O) pins [15:0] of a 16-bit device. Although references may be made to I / O pins, they may include any conductive nodes, such as conductive pads or conductive bumps, that provide electrical connections to memory device 130 via external devices, such as memory subsystem controller 115.

[0061] In this embodiment, cache register 118 may be omitted, and data may be written directly to data register 120. Data may also be output via input / output (I / O) pins [7:0] of an 8-bit device or input / output (I / O) pins [15:0] of a 16-bit device. Although references may be made to I / O pins, they may include any conductive nodes, such as conductive pads or conductive bumps, that provide electrical connections to memory device 130 via external devices, such as memory subsystem controller 115.

[0062] Those skilled in the art should understand that additional circuitry and signals can be provided, and that simplification has been achieved. Figure 1B The memory device 130. It should be understood that, reference Figure 1B The functionality of the various block components described is not necessarily separated into different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 1B The functionality of one or more block components. Alternatively, one or more components or component portions of an integrated circuit device may be combined to perform... Figure 1B The functionality of a single block component. Additionally, while specific I / O pins are described according to general conventions for receiving and outputting various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0063] Figures 2A to 2CThis is a reference that can be used according to the embodiments. Figure 1B A schematic diagram of a portion (e.g., as part of memory cell array 104) of a memory cell array 200A (e.g., a NAND memory array) of the described type of memory. Memory array 200A includes access lines (e.g., word lines 2020 to 202). N ) and data lines (e.g., bit lines 2040 to 204) M Word line 202 can be connected in a many-to-one relationship. Figure 2A Global access lines (e.g., global word lines) not shown in the diagram. In some embodiments, the memory array 200A may be formed on a semiconductor, for example, the semiconductor may be conductively doped to have a conductivity type, such as p-type conductivity for forming a p-well or n-type conductivity for forming an n-well.

[0064] The memory array 200A can be arranged in rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can contain a series of serially connected memory cells (e.g., non-volatile memory cells), such as NAND strings 2060 to 206. M One of them. Each NAND string 206 may be connected (e.g., selectively connected) to the common source (SRC) 216 and may contain memory cells 2080 to 208. N Memory cell 208 may represent a non-volatile memory cell used for data storage. The memory cell 208 of each NAND string 206 may be connected in series with select gate 210 (e.g., field-effect transistor) (e.g., select gates 2100 to 210). M One of them (for example, it could be a source-select transistor, often referred to as the selector source) and selector 212 (for example, a field-effect transistor) (for example, selectors 2120 to 212) M Between one of them (for example, it could be a drain-select transistor, often referred to as the select gate drain). Select gates 2100 to 210 M They can be connected together to select line 214 (e.g., source select line (SGS)), and select gates 2120 to 212. M They can be connected together to select line 215 (e.g., drain select line (SGD)). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent a plurality of select gates connected in series, wherein each select gate connected in series is configured to receive the same or independent control signal.

[0065] The source of each select gate 210 can be connected to the common source 216. The drain of each select gate 210 can be connected to the memory cell 2080 of the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to the memory cell 2080 of the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to the select line 214.

[0066] The drain of each select gate 212 can be connected to the bit line 204 of the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to the bit line 2040 of the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of select gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding bit line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0067] Figure 2A The memory array 200A can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, NAND string 206, and bit line 204 extend in a substantially parallel plane. Alternatively, Figure 2A The memory array 200A in the memory array can be a three-dimensional memory array, for example, in which the NAND string 206 can extend substantially perpendicular to the plane containing the common source 216 and substantially parallel to the plane containing the bit line 204.

[0068] A typical configuration of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trap, or the like) that determines the data state of the memory cell (e.g., through changes in a threshold voltage) and a control gate 236, such as... Figure 2A The data storage structure 234 may include both conductive and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 may further have defined source / drain (e.g., source) 230 and defined source / drain (e.g., drain) 232. The memory cell 208 connects its control gate 236 to (and in some cases forms) a word line 202.

[0069] A row of memory cells 208 may be a NAND string 206 or several NAND strings 206 selectively connected to a given positioning line 204. A row of memory cells 208 may be memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 may (but not necessarily) contain all memory cells 208 commonly connected to a given word line 202. Multiple rows of memory cells 208 may typically be divided into one or more physical page groups of memory cells 208, and the physical pages of memory cells 208 typically contain every other memory cell 208 commonly connected to a given word line 202. For example, commonly connected to word line 202... N Furthermore, memory cells 208 selectively connected to even-numbered bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be a physical page of memory cell 208 (e.g., an even-numbered memory cell), while those commonly connected to word line 202 N Furthermore, the memory cell 208 selectively connected to the odd bit line 204 (e.g., bit line 2041, 2043, 2045, etc.) can be another physical page of the memory cell 208 (e.g., an odd memory cell).

[0070] although Figure 2A Bit lines 2043 to 2045 are not explicitly depicted in the figure, but as can be seen from the figure, bit lines 204 of the memory cell array 200A can be numbered consecutively from bit line 2040 to bit line 204. M Other groups of memory cells 208 commonly connected to a given word line 202 may also define physical pages of memory cells 208. For a given memory device, all memory cells commonly connected to a given word line may be considered physical pages of the memory cells. A portion of the physical page of a memory cell read during a single read operation or programmed during a single programmable operation (in some embodiments, this may still be an entire line) (e.g., the upper or lower page of the memory cell) may be considered a logical page of the memory cell. A block of memory cells may contain memory cells configured to be erased together, such as those connected to word lines 2020 to 202. N All memory cells (e.g., all NAND strings 206 sharing a common word line 202). Unless explicitly distinguished, reference to a memory cell page herein refers to the memory cell's logical page. Although Figure 2A The examples are combined with the discussion of NAND flash, but the embodiments and concepts described in this article are not limited to a specific array architecture or structure, but may include other structures (such as SONOS, phase change, ferroelectric, etc.) and other architectures (such as AND arrays, NOR arrays, etc.).

[0071] Figure 2B It can be used for reference. Figure 1BAnother schematic diagram of a portion of a memory cell array 200B in a memory of the described type (e.g., as part of memory cell array 104). Figure 2B The same numbered elements in the middle correspond to about Figure 2A The description provided. Figure 2B Additional details are provided for an example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B may be incorporated into a vertical structure that may contain semiconductor pillars, a portion of which may serve as channel regions for the memory cells of NAND strings 206. Each of the NAND strings 206 may be selectively connected to bit lines 2040 to 2046 via a select transistor 212 (e.g., which may be a drain select transistor, commonly referred to as a select gate drain). M Furthermore, a selection transistor 210 (e.g., which may be a source selection transistor, commonly referred to as a select gate source) is selectively connected to the common source 216. Multiple NAND strings 206 can be selectively connected to the same bit line 204. A subset of the NAND strings 206 can be connected by applying bias voltage to select lines 2150 to 215. K Selective selection transistors 212, each located between NAND string 206 and bit line 204, are connected to their respective bit lines 204 by selective activation. Selection transistors 210 can be activated by applying a bias to selection line 214. Each word line 202 can be connected to multiple rows of memory cells in memory array 200B. Several rows of memory cells interconnected via specific word lines 202 can be collectively referred to as a layer.

[0072] Figure 2C It can be used for reference. Figure 1B Another schematic diagram of a portion of a memory cell array 200C in a memory of the described type (e.g., as part of memory cell array 104). Figure 2C The same numbered elements in the middle correspond to about Figure 2A The provided description indicates that the memory cell array 200C may include a series of serially connected memory cells (e.g., NAND strings) 206, access (e.g., word) lines 202, data (e.g., bit) lines 204, select lines 214 (e.g., source select lines), select lines 215 (e.g., drain select lines), and sources 216, as shown below. Figure 2A As depicted in the diagram. For example, a portion of memory cell array 200A may be a portion of memory cell array 200C.

[0073] Figure 2C The diagram depicts the NAND string 206 being grouped into memory cell blocks 250, such as memory cell blocks 2500 to 250. LMemory cell block 250 may be a grouping of memory cells 208 that can be erased together in a single erase operation, sometimes referred to as an erase block. Each memory cell block 250 may represent a NAND string 206 commonly associated with a single select line 215 (e.g., select line 2150). The source 216 of memory cell block 2500 may be the same as that of memory cell block 250. L The source of 216. For example, each memory cell block 2500 to 250. L They can be selectively connected to source 216. Access lines 202 and select lines 214 and 215 of a memory cell block 250 do not need to be directly connected to memory cell blocks 2500 to 2500 respectively. L Access lines 202 and select lines 214 and 215 for any other memory cell blocks.

[0074] Bit line 2040 to 204 M It can be connected (e.g., selectively connected) to buffer portion 240, which may be part of page buffer 152 of memory device 130. Buffer portion 240 may correspond to memory planes (e.g., memory cell blocks 2500 to 250). L (Group of data). Buffer section 240 may include sensing circuitry (which may include a sensing amplifier) ​​for sensing the data value indicated on the corresponding bit line 204.

[0075] Figure 3 It can be used for reference. Figure 1B This is a schematic block diagram of a portion of a memory cell array 300 in a memory of the described type. The memory cell array 300 is depicted having four memory planes 350 (e.g., memory planes 3500 to 3503), each communicating with a corresponding buffer portion 240, which together form a page buffer 352. Although four memory planes 350 are depicted, a number of other memory planes 350 may communicate with the page buffer 352. Each memory plane 350 is depicted to contain L+1 memory cell blocks 250 (e.g., memory cell blocks 2500 to 2503). L ).

[0076] Figure 4 This describes the instance group pillars in instance memory array 450. For example... Figure 4As shown, according to one or more embodiments of the present disclosure, an example memory array 450 of a TLC memory device includes word lines (e.g., target word line (WLn), a first set of unselected word lines (e.g., WLn-1 and WLn+1 to WLn+x), and a second set of unselected word lines (e.g., WLn-2 to WLn-y)) and a set of bit lines (e.g., BL0 to BL7), said set of bit lines corresponding to an erase level (L0) and a plurality of programming levels (L1, ... L7) programmed according to a full-level programming operation. Figure 4 As shown, memory array 450 can be arranged in rows (each corresponding to a word line) and columns (each corresponding to a bit line), where the intersection of word lines and bit lines constitutes the address of a memory cell. Each column can contain a series of memory cells connected (e.g., selectively connected) to a common-source (SRC). The common-source can be coupled to a reference voltage (e.g., ground voltage or simply "Gnd") or a voltage source (e.g., a charge pump circuit or power supply, which can be selectively configured (e.g., to a specific voltage suitable for optimizing programming operations)). A series of memory cells can be connected in series between a first selection transistor (e.g., a source-side selection transistor) called a source-select gate (SGS) and a second selection transistor (e.g., a drain-side selection transistor) called a drain-select gate (SGD). The source-select transistors can be connected together to a first select line (e.g., a source select line), and the drain-select transistors can be connected together to a second select line (e.g., a drain select line).

[0077] like Figure 4 As shown, memory array 450 includes a set of pillars (e.g., pillar 0, pillar 1... pillar 7) corresponding to a substantially vertical string of series-coupled memory cells of memory array 450. In an embodiment, a pillar refers to the channel region of the access transistor of the vertical string of memory cells (e.g., composed of polysilicon). According to an embodiment, each pillar floats and the corresponding voltage is boosted at different voltage levels (Vpillar) at different times by turning off the source-side select transistor (SGS) and drain-side select transistor (SGD). In an embodiment, the channel region is first discharged to ground before floating and boosting to a specific voltage. In an embodiment, once the corresponding pillar floats, the voltage (Vpillar) of each pillar can be boosted or increased according to a step or increase in the swashplate word line voltage, as per the relevant information. Figure 5 More detailed description.

[0078] Figure 5This describes example voltage waveforms of various portions of a memory array during a full-level programming process. In an embodiment, according to an embodiment of this disclosure, a portion of the memory array includes a set of memory cells associated with a target word line 501 (WLn) and a corresponding voltage waveform resulting from a full-level programming operation (e.g., the operation of method 700, described in more detail below). In an embodiment, processing logic identifies a set of memory cells programmed via a full-level programming operation (e.g., target word line 501 (WLn)). In an embodiment, the full-level programming operation includes a first phase (starting from time T0) in which a ramp word line voltage is applied to a set of word lines (e.g., target word line 501 and a set of one or more unselected word lines 502). For example, as... Figure 5 The diagram illustrates applying a ramp word line voltage to word line 501, where the voltage ramps from 0V to 3V between T0 and T5. As the ramp word line voltage is applied, a set of pillars corresponding to different programming levels floats sequentially (e.g., by decoupling the set of pillars in operation 330). In this embodiment, a second set of unselected word lines (e.g., WLn-2 and below) is set to 0V (e.g., the source select gate voltage (VSGS) is 0V, and unsel_SGD = 0V).

[0079] refer to Figure 4 At the end of the first phase, the pillar voltage level (Vpillar) is increased to different voltage levels (e.g., Vpillar for programming level L1 is increased to the highest value, Vpillar for programming level L2 is increased to the second highest value, until Vpillar for programming level L0 remains at approximately 0V during the first phase).

[0080] In the embodiments, in Figure 5 Before the first stage shown (e.g., before applying the swash word line voltage), the pillar floating associated with the erase level (L0), corresponding to bit lines 503A (according to the first variant) and 503B (according to the second variant) of L0, is set to V. BL_highThe selected SGD (Sel_SGD 504A, Sel_SGD 504B) is set to Vsgd_high. In an embodiment, the selected SGD can switch between Vsgd_high and ground (e.g., about 0V), as shown in the first waveform corresponding to Sel_SGD 504A. According to another embodiment, the selected SGD can remain at Vsgd_high during the first phase, as shown in the second waveform corresponding to Sel_SGD 504B. In an embodiment, using Sel_SGD 504A (e.g., a switching variant) is a first variant that can be implemented by processing logic. In another embodiment, using Sel_SGD 504B (e.g., a variant where Sel_SGD 504B remains at Vsgd_high) is a second variant that can be implemented by processing logic.

[0081] like Figure 5 The diagram illustrates that, between times T0 and T1, a first ramp of the slope word line voltage (e.g., from approximately 0V to a value of 1, depending on the step voltage) is applied. During the time period between T1 and T2, a ramp word line voltage is applied to the first pillar corresponding to the programming level L1 (e.g., ...). Figure 4 (Pillar 1). In an embodiment, during this period, the voltage (Vpillar1) of pillar 1 is discharged through bit lines 503A and 503B corresponding to L1, which is set to ground (e.g., about 0V).

[0082] In this embodiment, the voltage levels of the selected SGD 504A and bit lines 503A and 503B can be used to sequentially float the pillars and boost the corresponding pillar voltage (e.g., Vpillar) when each pillar is in a floating state. Figure 5 The diagram shows the voltage level (V) applied to the selected SGD 504A during the first time period (e.g., T0 to T2). SGD ) is the high source voltage level (Vsgd_high). In the embodiment, as Figure 5 As shown in the diagram, at time T2, the selected SGD 504A can be switched from Vsgd_high to ground (e.g., approximately 0V) so that the first pillar corresponding to the programming level L1 (e.g., ...) can be switched to ground. Figure 4 Column 1) Floating. For example... Figure 5 As shown, at time t2, the selected SGD504A switches from Vsgd_high to ground (e.g., approximately 0V), causing pillar 1 to disconnect and the voltage (Vpillar1) of pillar 1 corresponding to the programming level L1 to float. In the embodiment, in response to V... SGD Switching (e.g., switching the selected SGD 504A) or in the V SGD After the switch, the L1 bit line is switched from ground (e.g., 0V) to high voltage (V). BL_highAs illustrated by arrow 506A in the first variant and arrow 506B in the second variant. In an embodiment, the L1 bit line is switched to V. BL_high Ensure that pillar 1 floats and Vpillar1 can be boosted according to the word line slack level during floating. In the embodiment, the voltage of pillar 1 on the bit line (V BL ) greater than or equal to V SGD Time fluctuates.

[0083] exist Figure 5 In the example shown, Vpillar1 is raised and exposed to the longest relative duration of applying a swashplate word line voltage to the target word line while pillar 1 is floating (e.g., in a floating state), where the swashplate word line voltage increases periodically or the step word line step voltage level is reached. In this example, Vpillar1 remains floating from T2 until the end of the first phase (e.g., given that the corresponding bit line is set to V). BL_high Furthermore, the ramp word line voltage is repeatedly increased whenever the ramp word line voltage ramps or increases. At the end of stage 1, Vpillar1 increases the word line step voltage (or the preset boost ratio of the word line step voltage). For example, after completing the first stage, Vpillar1 increases to a value of 7 (e.g., about 7V) (e.g., Vpillar1 = [total ramp word line voltage (e.g., about 8V)] - [word line voltage level when Vpillar1 is floating (e.g., 1V)]).

[0084] In an embodiment, such as Figure 5 As shown in the diagram, when switching the selected SGD 504A (at time T2) and increasing the L1 bit line voltage level from approximately 0V to V, BL_high (As illustrated by arrow 506A in the first variant and arrow 506B in the second variant) subsequently, the bit line voltage level (e.g., V) BL ) greater than V SGD This causes column 1 to remain in a floating state and be subjected to the boosted skew voltage until the first stage ends.

[0085] like Figure 5 As shown, the floating of the corresponding column in each of the set of columns (e.g., columns corresponding to L1 to L6) continues so that each Vpillar can be boosted according to the swashplate word line voltage. For example, at time T3, the selected SGD 504A switches from approximately 0V to Vsgd_high to be able to set the swashplate word line voltage according to the next step or increase. It should be noted that the SGD 504A is shared among various strings and columns, such that the switching of the SGD 504A from low to high (e.g., at time T3) does not affect Vpillar1 (e.g., the Vpillars of columns that floated before the SGD 504A switched from low to high are unaffected). Figure 5 As shown in the image, when the selected SGD504A is Vsgd_high and VBL2 During the time period between T3 and T4, approximately 0V, a sloped bit line voltage of value 2 is applied. At time T4, post 2 is floated by switching the selected SGD 504A from Vsgd_high to ground (e.g., approximately 0V). In this embodiment, after the selected SGD 504A switches to Vsgd_high, the L2 bit line switches from ground (e.g., approximately 0V) to Vsgd_high. BL_high As illustrated by arrow 507A in the first variant and arrow 507B in the second variant. In this embodiment, switching the L2 bit line to an inhibit voltage level causes post 2 to remain floating for the remainder of the first phase.

[0086] In an embodiment, as the slant word line voltage is applied, a set of pillars (e.g.) Figure 4 Each column (from column 1 to column 6) floats sequentially. (See reference) Figure 4 In this embodiment, the voltage of the column (column 0) corresponding to the erase state floats before the slash word line voltage is applied. For example, column 1 floats for a first time during the application of the slash word line voltage, column 2 floats for a second time during the application of the slash word line voltage, and so on.

[0087] In an embodiment, when the corresponding column is in a floating state, the voltage corresponding to said column is boosted to increase the word line voltage. For example, column 1 floats in the first instant and increases to the column voltage level corresponding to each increase in the word line voltage (e.g., whenever the word line voltage steps). In this example, since column 1 floats in the first instant, the corresponding column voltage (e.g., Vpillar1) increases multiple times according to each increase in the word line voltage until the word line scalping phase of the full-level programming operation (e.g., the first phase) ends, as per the relevant information. Figure 6 More detailed display and description.

[0088] In an embodiment, such as Figure 4 As shown in the diagram, because the columns float sequentially (e.g., column 1 floats before column 2, column 2 floats before column 3, etc.), the corresponding column voltages are... Figure 4 The voltage level shifts from high to low as it moves from left to right. In this respect, Vpillar1 is higher than Vpillar2, Vpillar2 is higher than Vpillar3, and so on, varying over time as each pillar floats. In an embodiment, whenever the skew word line voltage increases, the Vpillar of the floating pillar increases to a higher voltage level. Therefore, earlier floating pillars increase the number of word line skew increases.

[0089] although Figure 5The waveform shown relates to the floating of pillars 1 and 2. It should be understood that, according to the first variant, the described operation can be repeated as part of a full-level programming procedure with floating pillars to move or adjust the corresponding Vpillar level for each remaining programming level (e.g., L3 to L7 of a TLC memory device). As shown, according to the first variant, the L6 bit line switches from ground (e.g., approximately 0V) to V... BL_high (As illustrated by arrow 508A) and the L7 bit line switches from ground (e.g., approximately 0V) to V. BL_high (As illustrated by arrow 509A).

[0090] In another embodiment, according to the second variant, since the corresponding Vpillar is approximately 0V, pillar 7 corresponding to programming level L7 does not float, such as Figure 4 As shown in section B. For example, at the end of the first stage, Vpillar1 rises to a first value (e.g., 6V), where Vpillar1 = [total glitched word line voltage (e.g., Vpass)] - [word line voltage level when pillar 1 is floating (e.g., value 1)], Vpillar2 rises to a second value (e.g., 5V), where Vpillar2 = [total glitched word line voltage (e.g., Vpass)] - [word line voltage level when Vpillar2 is floating (e.g., value 2)], Vpillar3 rises to a third value (e.g., 4V), where Vpillar3 = [total glitched word line voltage (e.g., Vpass)] - [word line voltage level when Vpillar3 is floating (e.g., value 3)], and so on. Figure 5 As shown in the second variant, the L6 bit line switches from ground (e.g., approximately 0V) to V. BL_high As illustrated by arrow 508B. Therefore, a lifting Vpillar is established for each corresponding column.

[0091] According to an embodiment, L0 to L7 are approximately 8V (or higher), 6V, 5V, 4V, 3V, 2V, 1V, and 0V, respectively. In an embodiment, the Vpillar of L0 is equal to Vpass (e.g., between 8V and 10V). In an embodiment, there is a gap (e.g., a gap of 2V or higher) between the Vpillar of L0 and the Vpillar of L1. In an embodiment, since the Vpillar of L7 is approximately 0V, 1V can be added for each level, making the Vpillars of L1 to L7 from 6V to approximately 0V.

[0092] In an embodiment, at the end of the first phase (e.g., at Tpulse), word lines 501 and 502 are ramped to the pass voltage level (Vpass). In an embodiment, unselected word lines are ramped to Vpass with seven ramp levels to fine-tune Vpillar (e.g., pillar potential). At time Tn, different programming stress levels have been applied to the corresponding programming level (Ln), as represented by the following expression:

[0093] V stresslevel(Ln) =Vpgm_WL - Vpillar, where Vpillar = (Vpass - Vwl_time_of_float) × boost_ratio;

[0094] Where Vwl_time_of_float is the voltage level of the slope word line voltage when the column (Pillar_n) floats corresponding to the programming level (Ln); and boost_ratio is a preset value (e.g., 1, 0.8, 0.6, etc.) corresponding to the boost amount of Vpillar that varies according to the slope word line voltage.

[0095] In an embodiment, according to the second variant described above, the selected SGD 504B can be maintained at Vsgd_high. According to this variant, such as... Figure 5 As shown, during the first phase of the programming operation, the selected SGD 504B remains at Vsgd_high (e.g., the selected SGD 504B does not switch). According to this variant, while the selected SGD 504B remains at Vsgd_high, the floating of each pin is initiated by switching the voltage (Vbl) of the bit line 503 corresponding to the respective pin from approximately 0V to Vbl_high. For example, the L1 bit line can switch from ground (e.g., 0V) to a high voltage (V...). BL_high (As illustrated by arrow 506) so that column 1 floats. In an embodiment, the L1 bit line is switched to V. BL_high Ensure that column 1 floats and Vpillar1 can be boosted according to the word line slant level when floating, and repeatedly boosted whenever the word line slant level increases.

[0096] Figure 6 This describes an example programming operation according to an embodiment of the present disclosure, comprising a set of multiple pulses 605 (e.g., pulse 1, pulse 2... pulse N) applied to program all programming levels (e.g., L1, L2, ... L7) of an identification group memory cell of a memory array. Figure 6As shown, each corresponding pulse (e.g., pulse 1, pulse 2, ..., pulse N) is used to program each programming level (e.g., L1 to L7) of a memory device in a memory subsystem according to one or more embodiments of the present disclosure. In an embodiment, each pulse simultaneously programs the entire set of programming levels 610 (e.g., all levels) of the memory cells. In an embodiment, a set of pulses 605 is applied to a target word line (e.g., WL) associated with the set of memory cells to be programmed. n (See reference) Figures 4 to 6 Display and description.

[0097] like Figure 5 and 6 The text demonstrates that during the second phase of the programming operation, in... Figure 5 The time Tpulse applies the first programmed pulse (e.g. Figure 6 The first programming pulse (Pulse 1) programs each programming level (e.g., L1 to L7). In an embodiment, the programming voltage (Vpgm) of each pulse is applied to the selected word line 501 to program each level (L1 to L7 of the TLC memory device). In an embodiment, the same Vpgm_WL is applied to the second-stage Vpgm for memory cells in the selected page. However, different Vpillars are set during the first stage depending on the corresponding target data level. In an embodiment, different Vpillars are applied to the memory cells L1 to L7. stresslevels In an embodiment, a series of programming pulses (e.g., such as...) Figure 6 The example demonstrates that pulses applied to a target word line 501 are used to complete programming a set of programming levels. In an embodiment, for each pulse in the applied set, a programming verification operation can be performed on each programming level to verify that the target voltage corresponding to each respective programming level has been reached.

[0098] exist Figures 4 to 6 In the example shown, a set of programming pulses is applied to the selected word line (WLn). In the embodiment, as... Figure 4 The diagram illustrates that the first set of unselected word lines, including WLn-1 and WLn+1 to WLn+x, are ramped to the pass voltage (Vpass) of programming levels L1 to L7 (e.g., WLn+1 and above are ramped to Vpass in seven levels to fine-tune the corresponding column potential). In an embodiment, the column potential can be maintained at approximately 0V or disabled at any of the seven voltages (e.g., between 0V and Vpass) by conducting the corresponding bit line programmed using L7, depending on the user data level. In an embodiment, the second set of unselected word lines, including WLn-2 to WLn-y, is set to 0V (e.g., approximately 0V for SGS, approximately 0V for SGD).

[0099] Figure 7This is a flowchart of an example method 700 for full-level programming of a memory device in a memory subsystem according to some embodiments of the present disclosure. Reference Figures 4 to 6 Method 700 is described. Method 700 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, special-purpose logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 700 is performed by… Figure 1A and 1B The program manager 134 executes the process. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0100] In operation 710, a set of memory cells is identified. For example, processing logic (e.g., program manager 134) may receive a request from a requester, such as memory interface 113 of memory subsystem controller 115, to perform a memory access operation on a memory array (e.g., memory array 250) of a memory device (e.g., memory device 130). In one embodiment, the memory access operation includes a programming operation that programs the set of memory cells to a set of programming levels (e.g., L1 to L7; where L0 is an erase state). In one embodiment, the programming operation relates to one or more specific memory cell addresses. In one embodiment, the processing logic may identify a set of memory cells (e.g., a subgroup of memory cells of memory array 250 or 450 (described in more detail below), such as memory cells associated with one or more word lines of memory array 250). In one embodiment, the set of memory cells is configured as an MLC memory (e.g., any type of memory cell storing more than one bit per cell, including 2 bits, 3 bits, 4 bits, or more per cell). In one embodiment, the identified group of memory cells will be programmed to multiple programming levels (e.g., L1, L2…L7 of a TLC memory device). In another embodiment, the request includes a set of physical or logical addresses corresponding to the group of memory cells to be programmed. In yet another embodiment, the processing logic identifies the group of memory cells based on the set of addresses provided as part of the request.

[0101] In operation 720, a voltage is applied. For example, the processing logic may cause a ramp word line voltage to be applied to one or more word lines of the memory array (e.g., a ramp word line voltage applied to target word line 501, as referenced). Figure 5(Detailed description). In an embodiment, the full-level programming operation includes a first stage in which an increased or ramped word line voltage (e.g., a voltage applied to one or more word lines via a periodic ramp or ramped word line step voltage) is applied to a set of word lines of the memory array (e.g., selected word lines corresponding to a set of identified memory cells to be programmed and one or more unselected word lines). For example, after identifying a set of memory cells to be programmed (e.g., memory cells associated with one or more word lines of the memory array identified in operation 710), the control logic of the memory device may initiate the first stage of the full-level programming operation, during which a ramped word line voltage is applied to a set of word lines containing the target word lines associated with the set of memory cells to be programmed.

[0102] In operation 730, a set of voltage levels is established. In an embodiment, as a ramp word line voltage is applied to a set of word lines (in operation 720), a set of pillars float sequentially. In an embodiment, a pillar refers to the channel region (e.g., composed of polysilicon) of the access transistors in a vertical string of memory cells. In an embodiment, by floating each pillar associated with a corresponding programming level at different times in operation 730, each pillar is exposed to a different length of word line voltage ramping process while in a floating state. In an embodiment, therefore, each pillar rises to a different voltage depending on the different exposure times associated with the ramp word line voltage. For example, the first pillar that floats sequentially is exposed to the longest relative time length of word line voltage and thus rises to the highest voltage level, the second pillar that floats sequentially is exposed to the second longest relative time length of word line voltage and thus rises to the second highest voltage level, and so on.

[0103] For example, in operation 730, the processing logic may cause a set of pillars associated with a set of memory cells to be disconnected from both the power supply voltage and the ground voltage (i.e., ground), where each pillar corresponds to a programming level in a set of programming levels (e.g., L1 to L7 of a TLC memory device). In an embodiment, during a first phase of a full-level programming operation, the corresponding pillars (e.g., vertical conductive traces of the memory array) corresponding to the programming levels (e.g., L1 to L6 of a TLC memory device) float (e.g., disconnected from both the power supply voltage and ground). In an embodiment, a set of pillars corresponding to different programming levels floats sequentially during the first phase (e.g., the first pillar corresponding to L1 floats at a first time, the second pillar corresponding to L2 floats at a second time, and so on).

[0104] In one embodiment, the pillar is floated by turning off the corresponding source-side select transistor (SGS) and the corresponding drain-side select transistor (SGD). In another embodiment, the pillar can be floated by turning off both the select gate source (SGS) and the select gate drain (SGD) (e.g., the selected SGD switches from a high voltage level (e.g., Vsgd_high) to approximately 0V to prevent the corresponding bit line from discharging to the corresponding pillar). In another embodiment, the bit line corresponding to the first pillar associated with programming level L1 switches from approximately 0V to a high voltage level (e.g., Vsgd_high). BL_high This ensures that the column remains floating during the remainder of the first phase (e.g., when the slant voltage is applied to the word line).

[0105] In this embodiment, once floating, the voltage (Vpillar) of each pillar can be periodically increased or increased according to each step or increase of the swashplate word line voltage (e.g., each step of the swashplate word line voltage increases or increases the pillar voltage of the floating pillar). At the end of the first phase, the pillar voltage level (Vpillar) is increased to different voltage levels (e.g., Vpillar for programming level L1 is increased to the highest value, Vpillar for programming level L2 is increased to the second highest value, until Vpillar for programming level L0 remains at approximately 0V during the first phase).

[0106] In operation 740, a programming pulse is applied. For example, the processing logic may cause the programming pulse to be applied to a set of memory cells (e.g., ...). Figure 1B 150 or Figure 4 The memory array 450 contains a set of memory cells, wherein programming pulses program all programming levels associated with the identified set of memory cells. In an embodiment, programming pulses may be applied to one or more target word lines associated with a set of memory cells to be programmed (e.g., a set of memory cells identified in operation 710), wherein the programming pulses program each programming level simultaneously (e.g., programming levels L1 to L7 are programmed using programming pulses). In an embodiment, boosting the pillar voltage during the first stage enables simultaneous programming of all programming levels using each programming pulse, allowing memory cells with corresponding programming levels to rise to their corresponding target voltage levels more quickly and efficiently.

[0107] In this embodiment, operations 720 to 740 may be performed iteratively (e.g., iteratively executed). Figure 5 As shown in stages 1 and 2), each execution of operation 740 involves applying a single programming pulse until each programming level reaches a corresponding target voltage level. For example, operations 720 to 740 can be executed iteratively to enable the following operations: Figure 6Pulses 1, 2, ..., N are applied until all programming levels (e.g., L1 to L7) are programmed. For each pulse in a set of pulses, a programming verification operation can be performed on each programming level to verify that the target voltage corresponding to each respective programming level has been reached. In an embodiment, the processing logic completes the execution of method 700 in response to verifying (using programming verification operations) that all programming levels have been programmed (e.g., after applying a set of pulses according to the iterative execution of operations 720 to 740 of method 700). In an example, a full-level programming operation may consist of a set of pulses (e.g., six pulses) to program seven programming levels, resulting in the application of forty-two programming verification operations.

[0108] In an embodiment, such as Figure 7 As shown, after each programming pulse and associated programming verification operation, operations 720 to 740 can be repeated until programming of each programming level is complete.

[0109] Advantageously, full-level programming operation results in reduced programming time. Specifically, compared to other programming algorithms such as ISPP, programming time is reduced by executing fewer programming pulses. In an embodiment, the total programming time associated with full-level programming operation includes the time corresponding to the execution of word line ramps (e.g., executing six word line ramps), a set of programming pulses (e.g., six pulses) simultaneously programming each programming level, and a set of programming verification operations (e.g., forty-two programming verification operations), wherein programming verification operations are performed for each level (e.g., seven levels) of each pulse (e.g., six pulses). This results in a significant reduction in Tprog, a reduction in bit power, and a reduction in word line peak current. Furthermore, in the embodiment, programming verification operations are performed for each programming pulse and each programming level, thus eliminating the need to skip programming verifications. This simplifies the control of the memory subsystem and achieves the verified target programming level. Therefore, the overall quality of service provided by the memory subsystem is improved.

[0110] Figure 8 This describes an example machine of a computer system 800 in which a set of instructions for causing a machine to perform any or more of the methodologies discussed herein can be executed. In some embodiments, the computer system 800 may correspond to a host system (e.g., Figure 1A The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., a memory subsystem). Figure 1A The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1A(Operation of the program manager 134). In alternative embodiments, the machine may connect (e.g., network) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0111] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, while individual machines have been described, the term "machine" should also be considered as any collection of machines that individually or jointly execute a set (or more) of instructions to perform any or more of the methodologies discussed herein.

[0112] The example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.) and a data storage system 818, which communicate with each other via a bus 830.

[0113] Processing device 802 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or multiple processors implementing combinations of instruction sets. Processing device 802 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 802 is configured to execute instructions 826 for performing the operations and steps discussed herein. Computer system 800 may further include a network interface device 808 communicating via network 820.

[0114] The data storage system 818 may include a machine-readable storage medium 824 (also referred to as a computer-readable medium, such as a non-transitory computer-readable medium) on which one or more sets of instructions 826 or software embodying any or more of the methodologies or functions described herein are stored. The instructions 826 may also reside wholly or at least partially in main memory 804 and / or processing device 802 during execution by computer system 800, which also constitute machine-readable storage media. The machine-readable storage medium 824, data storage system 818, and / or main memory 804 may correspond to... Figure 1A The memory subsystem 110.

[0115] In one embodiment, instruction 826 includes instructions for implementing the corresponding Figure 1A The program manager 134 provides functional instructions. Although the machine-readable storage medium 824 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered as a single medium or multiple media containing one or more sets of instructions. The term "machine-readable storage medium" should also be considered as any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any or more of the methodologies of this disclosure. The term "machine-readable storage medium" should accordingly be considered as including (but not limited to) solid-state memory, optical media, and magnetic media.

[0116] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are, in this document and generally, considered to be self-consistent sequences of operations that lead to desired results. An operation is an operation that requires the physical manipulation of physical quantities. Usually, but not always, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient to sometimes refer to these signals as bits, values, elements, symbols, characters, items, numbers, or the like, primarily for reasons of habitual use.

[0117] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure may relate to the operation and processes of a computer system or similar electronic computing device, which manipulate or transform data representing physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented in the memory or registers of the computer system or other such information storage systems.

[0118] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specially constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0119] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the teachings and procedures herein, or it may be proven convenient to construct more specialized devices to implement the methods. The structures for various such systems will appear as described below. Furthermore, this disclosure does not refer to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of this disclosure described herein.

[0120] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any means for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0121] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It should be understood that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure set forth in the appended claims. Therefore, the specification and drawings should be regarded as illustrative rather than limiting.

Claims

1. A memory device comprising: A memory array comprising multiple memory cells configured as multilevel cell (MLC) memory; and Control logic, operably coupled to the memory array, to perform operations including: Identify a group of the plurality of memory cells that are programmed during the programming operation; During the first time period of the programming operation, a swashplate word line voltage is applied to a set of word lines associated with the memory array; During the first time period, a set of pillars associated with the set of memory cells is disconnected from the power supply voltage and the ground voltage, wherein each pillar corresponds to a corresponding programming level in a set of programming levels; and During the second period of the programming operation, a programming pulse is applied to the set of memory cells, wherein the programming pulse programs each of the set of programming levels associated with the identified set of memory cells.

2. The memory device of claim 1, wherein causing the set of pillars to disconnect comprises switching the drain of a first select gate corresponding to a first pillar in the set of pillars from a first voltage level to ground.

3. The memory device of claim 1, wherein the control logic performs a further operation including causing a switching of the first line voltage level corresponding to the first post.

4. The memory device of claim 1, wherein causing the set of pillars to disconnect includes causing a first pillar of the set of pillars to float at a first time during the first time period.

5. The memory device of claim 4, wherein whenever the swashplate voltage is increased, the first column voltage of the first column is increased incrementally.

6. The memory device of claim 1, wherein causing the set of pillars to disconnect comprises causing each pillar in the set of pillars to float sequentially during the first time period.

7. The memory device of claim 1, wherein the control logic execution includes the following further operations: In response to the application of the programming pulse, one or more programming verification operations are performed to verify whether the group of the plurality of memory cells is programmed to each programming level in the group of programming levels.

8. The memory device of claim 1, wherein the control logic execution includes the following further operations: During the third time period of the programming operation, the swashplate word line voltage is applied to the set of word lines associated with the memory array; During the third time period, the set of pillars associated with the set of memory cells is disconnected from the power supply voltage and the ground voltage; and During the fourth period of the programming operation, a subsequent programming pulse is applied to the set of memory cells, wherein the subsequent programming pulse programs each of the set of programming levels associated with the identified set of memory cells.

9. The memory device of claim 1, wherein causing the set of pillars to disconnect comprises sequentially floating corresponding pillars in the set of pillars at intervals of the first time period, and wherein when floating, the pillar voltage corresponding to the corresponding pillar increases according to the increase of the swashplate voltage.

10. A method for performing memory operations, comprising: Identify a group of multiple memory cells that are programmed during the programming operation; During the first period of the programming operation, a ramp word line voltage is applied to a set of word lines associated with the memory array; During the first time period, a set of pillars associated with the set of memory cells is disconnected from the power supply voltage and the ground voltage, wherein each pillar corresponds to a programming level in a set of programming levels; and During the second period of the programming operation, a set of programming pulses is applied to the set of memory cells, wherein each programming pulse in the set programs each of the set of programming levels associated with the identified group of memory cells.

11. The method of claim 10, wherein causing the set of pillars to disconnect comprises causing the drain of a first select gate corresponding to a first pillar in the set of pillars to switch from a first voltage level to ground.

12. The method of claim 10, further comprising causing a switching of the first line voltage level corresponding to the first post.

13. The method of claim 10, wherein causing the set of columns to disconnect further includes causing a first column in the set of columns to float at a first time during the first time period.

14. The method of claim 13, wherein whenever the slant voltage is increased, the voltage of the first column of the first column is increased incrementally.

15. The method of claim 10, wherein causing the set of columns to disconnect further comprises causing each column in the set of columns to float sequentially during the first time period.

16. The method of claim 10, further comprising, in response to applying each programming pulse, performing one or more programming verification operations to verify whether the group of the plurality of memory cells is programmed to each programming level of the group of programming levels.

17. The method of claim 10, wherein the unselected word line subgroup of the set of word lines is sloping to the pass voltage level during the first time period.

18. The method of claim 10, wherein causing the set of columns to disconnect further comprises sequentially floating each column in the set of columns at intervals of the first time period, and wherein, while floating, the voltage of each column is increased according to the increase of the slant word line voltage.

19. A memory device comprising: A memory array, which includes multiple memory cells; and Control logic, operably coupled to the memory array, to perform operations including: During the first phase of the programming operation, a swashplate word line voltage is applied to a set of word lines associated with the memory array; During the first time period, at a first set of different times, a corresponding column in a set of columns associated with the plurality of memory cells is floated, wherein the voltage of each column increases with each increase of the swashplate word line voltage during the float; and During the second time period, a first programming pulse is applied to a set of memory cells, wherein the first programming pulse programs each of a set of programming levels associated with the plurality of memory cells.

20. The memory device of claim 19, wherein the control logic execution includes the following further operations: During the third time period of the programming operation, the swashplate word line voltage is applied to the set of word lines associated with the memory array; During the second set of different times in the third time period, the corresponding column in the set of columns associated with the plurality of memory cells is floated, wherein the voltage of each column is increased according to each increase of the swashplate word line voltage as it floats; and During the fourth time period, a second programming pulse is applied to the set of memory cells, wherein the second programming pulse programs each of the set of programming levels associated with the plurality of memory cells.

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