NOR flash memory chip and its erase operation control system and control method

Abstract

The present invention discloses a NOR flash memory chip and an erase operation control system and control method thereof, the system comprising a first state marking module, a marking information storage device and a repair processing module; the first state marking module is used to set the first state marking information stored in the non-volatile marking information storage device as a state characterizing an abnormal interruption of the erase operation before the NOR flash memory chip is powered off or restarted due to power interference or abnormal power failure that causes the erase interruption during the erase operation; the repair processing module is used to obtain the first state marking information after power-on startup to control the use of a preset erase repair strategy for erase repair. The entire power-on and repair process of the present invention is automatically completed by the internal circuit of the chip, avoiding external complex control processes, improving the erase recovery processing efficiency and accuracy of the erase interruption situation in the chip, and avoiding the occurrence of data errors after the chip restarts due to power interruption during the erase operation.

Description

Technical Field

[0001] The present invention relates to the field of flash memory technology, and in particular to a NOR (a type of flash memory chip) type flash memory chip and an erase operation control system and a control method thereof. Background Art

[0002] Semiconductor memory is an indispensable component of modern information processing systems. According to the physical characteristics of storage, it is mainly divided into two categories: VM (Volatile Memory) and NVM (Nonvolatile Memory). Flash memory is the most common non-volatile memory. According to the different memory cell array structures and read and write methods, the current flash memory is mainly divided into two types: NOR flash memory and NAND flash memory. The basic operations of flash memory include writing (Program), erasing (Erase) and reading (Read); among them, writing and erasing correspond to the charging and discharging processes of the FG (floating gate layer) or ONO (silicon oxide-silicon nitride-silicon oxide) layer of the flash memory.

[0003] Taking NOR flash memory as an example, its erase operation corresponds to the discharge process of FG or ONO, which is generally achieved through FN tunneling. According to the arrangement of the flash memory array, the erase can be operated as a whole sector or block. In order to ensure the uniformity of the threshold voltage (VT) distribution of the flash memory storage cell (Cell), the conventional NOR flash memory erase operation process includes several steps such as "Preprogram Step", "Erase Step", "Recovery Step", and "Refresh Step".

[0004] The time for the erase operation in NOR flash memory is longer than that for other operations such as read and write, which is in the order of tens or hundreds of milliseconds. If there is an interruption or interference in the power supply during the erase operation, causing the chip to restart and the erase operation to be interrupted unexpectedly, the data stored in the chip will have a high risk of reading errors. The reason is that after the chip restarts, the chip working status register is reset and will not automatically continue the previously unfinished operation. The data status of the area that was being erased before the restart is uncertain after the erase operation is interrupted. Figure 1The possible impact of interruptions on data at different steps in a typical erase operation of NOR flash memory is listed. In addition, in addition to the risk of data reading errors in the target area, data in adjacent areas may also be affected. The reason is that on the one hand, if the power interruption restart occurs in the Erase Step or Recovery Step, the VT reduction caused by the negative voltage interference of the erase and write operation in the adjacent area cannot be recovered, which may affect data reliability; on the other hand, if the threshold voltage VT of the cell in the target erase operation area is too low, the adjacent area of ​​the shared bit line (Bit line) will have a bit line leakage current during the read operation, causing a read error, such as Figure 2 shown.

[0005] At present, the following two protection measures are mainly used to prevent data errors caused by power failure during the erasing operation of flash memory chips (especially NOR flash memory chips):

[0006] (1) The user is required to keep the power supply of the flash memory chip stable and check the status register status before any software or hardware restart to ensure that the erase operation is complete. However, this method cannot prevent the flash memory from being passively restarted due to unstable system power supply.

[0007] (2) Adding specific over-erase recovery operation commands; however, this method has problems such as requiring external supervision and control and complex external processes. Summary of the invention

[0008] The technical problem to be solved by the present invention is to overcome the defects in the prior art of NOR flash memory chips that when there is an interruption or interference in the power supply during the erase operation, an erase interruption occurs, which easily causes data errors. The execution scheme either needs to increase the chip startup time or requires external supervision and control, and the external process is complicated. The purpose is to provide a NOR flash memory chip and its erase operation control system and control method.

[0009] The present invention solves the above technical problems through the following technical solutions:

[0010] The present invention provides an erasing operation control system for a NOR flash memory chip, the erasing operation control system comprising a first state marking module, a marking information storage device and a repair processing module which are electrically connected in sequence;

[0011] The first status marking module is used to set the first status marking information stored in the non-volatile marking information memory to a state indicating that the erasing operation is abnormally interrupted before the NOR flash memory chip is powered off or restarted due to power interference or abnormal power failure that causes the erasing interruption during the erasing operation;

[0012] The repair processing module is used to obtain the first state mark information stored in the mark information storage device after power-on startup, and control the use of a preset erase repair strategy to perform erase repair according to the first state mark information.

[0013] In this solution, once the NOR flash memory chip is powered off or restarted during the erasing operation due to power interference or abnormal power failure that causes erasing interruption, and then powered on again, the first state mark information representing the abnormal interruption of the erasing operation stored in the mark information memory can be automatically read, and then the corresponding erasing repair scheme can be determined based on the analysis of the first state mark information, so as to automatically perform the erasing repair operation using the erasing repair scheme. The entire power-on and repair process of this solution is automatically completed by the internal circuit of the chip, without the need for external system supervision and control, avoiding external complex control processes; at the same time, it can save chip startup time, and effectively improve the efficiency of erasing recovery processing for erasing interruptions in NOR flash memory chips without relying on external system supervision and control, ensuring the accuracy and reliability of the erasing recovery operation, and avoiding the occurrence of data errors after the chip restarts due to power interruption during the erasing operation.

[0014] Preferably, the erasing operation control system further comprises an erasing state monitoring module electrically connected to the first state marking module;

[0015] The erase state monitoring module is used to monitor the power state of the NOR flash memory chip during the erase operation, and when power interference or abnormal power failure that causes the erase interruption is detected, a trigger signal is generated and transmitted to the first state marking module;

[0016] The first status marking module is used to set the first status marking information stored in the non-volatile marking information memory to a state indicating that an abnormal interruption of an erase operation occurs based on the trigger signal.

[0017] In the present solution, the erasure interruption interference factors that cause the interruption of the erasure operation can be monitored in real time, and the first state mark information representing the abnormal interruption of the erasure operation can be set in time and stored in the non-volatile mark information storage device, so as to ensure that once the NOR flash memory chip is powered off or restarted due to power interference or abnormal power failure that causes the erasure interruption during the erasure operation and then powered on again, the first state mark information in the mark information storage device can be automatically read, so as to effectively improve the timeliness, reliability and accuracy of the erasure recovery processing of the erasure interruption situation in the NOR flash memory chip.

[0018] Preferably, the repair processing module comprises a state reading unit and an erase repair control unit which are electrically connected to the mark information storage in sequence;

[0019] The state reading unit is used to read the first state mark information in the mark information storage device and send it to the erase repair control unit after the NOR flash memory chip is powered on;

[0020] The erase repair control unit is used to obtain the corresponding preset erase repair strategy to perform erase repair when the first status mark information is a state indicating that an erase operation is abnormally interrupted.

[0021] In this solution, the repair processing module is provided with two functional units, which independently complete the reading function of the first state mark information and the control function of the erase repair operation based on the first state mark information. Based on the independence and correlation between the two, the execution efficiency of the repair processing operation is guaranteed; the entire power-on and repair process is automatically completed by the internal circuit of the chip, without the need for external system supervision and control, and it also belongs to the improved design requirements adapted to the NOR flash memory chip, ensuring the rationality and effectiveness of the erase operation control scheme implemented in the NOR flash memory chip.

[0022] Preferably, the erasing operation control system further comprises a block erasing state marking module;

[0023] The block erase status mark module includes a plurality of erase operation completion mark storage units corresponding to each physical block of the NOR flash memory chip one by one;

[0024] The erasing operation control system is used to control the erasing operation completion mark storage unit to perform an erasing operation together with the corresponding physical block;

[0025] The erasing operation control system is further used to perform a write operation on the erasing operation completion mark storage unit after the physical block corresponding to the erasing operation completion mark storage unit completes the erasing operation;

[0026] The repair processing module is used to confirm the block address of the physical block where the erasure interruption occurs according to whether the write operation is performed on the storage unit marked by the completion of the erasure operation when the first status mark information is a state representing that the erasure operation has been abnormally interrupted, and perform erase repair on the physical block at the block address.

[0027] In this solution, each physical block of the NOR flash memory chip is provided with a corresponding erase operation completion mark storage unit, and the erase operation completion mark storage unit performs the same erase operation during the corresponding physical block erase process. The difference between the two operations is that after the physical block corresponding to the erase operation completion mark storage unit completes the erase operation, the erase operation completion mark storage unit also performs a write operation to indicate that the corresponding physical block has completed the complete erase operation. Therefore, by judging whether the erase operation completion mark storage unit is written to, the physical block where the erase interruption occurs can be quickly and accurately located, and the physical block can be automatically erased and repaired based on the block address of the physical block, thereby ensuring the accuracy and efficiency of the erase recovery processing of the erase interruption in the NOR flash memory chip.

[0028] Preferably, the erase operation control system further includes a bit line current detection module;

[0029] The repair processing module is used to call the bit line current detection module when the first state mark information is a state indicating that an abnormal interruption of an erase operation occurs;

[0030] The bit line current detection module is used to obtain the bit line current information of the entire flash memory array in the NOR flash memory chip, and when the bit line current information indicates the existence of bit line leakage current, obtain the address information corresponding to the physical block or physical sector where the bit line leakage current occurs, and erase and repair the physical block or physical sector corresponding to the address information.

[0031] In this solution, when an abnormal interruption occurs in the erase operation of a NOR flash memory chip, after powering on again, the bit line current information of the entire flash memory array is promptly detected to see if there is a bit line leakage current. Once there is, the address of the physical block where the bit line leakage current occurs is automatically obtained, or the address of the corresponding physical sector, both of which are acceptable, to perform erase repair on the corresponding physical block or physical sector, thereby effectively ensuring the efficiency, feasibility and flexibility of the erase recovery process for the erase interruption in the NOR flash memory chip. The entire power-on and repair process is automatically completed by the internal circuit of the chip, without the need for external system supervision and control.

[0032] Preferably, the erase status monitoring module is also used to monitor the power status of the NOR flash memory chip during the erase repair operation, and when power interference or abnormal power failure causing erase interruption is detected, the trigger signal is generated again and transmitted to the first status marking module.

[0033] In this solution, during the erase and repair process, it is still monitored in real time whether the factors causing the interruption of the erase and repair occur. Once it occurs, the first state marking module is triggered in time to mark the first state marking information of the erase interruption situation, so that after the NOR flash memory chip is powered on again, the corresponding erase and repair solution is determined in time according to the latest recorded first state marking information until the erase operation of the NOR flash memory chip is completed, thereby achieving any erase operation, as long as the erase interruption caused by power interruption interference occurs, the erase repair can be performed in time, even if the erase interruption occurs in the erase repair for multiple consecutive times, the erase repair can be performed in time and efficiently, which effectively improves the effectiveness, reliability and efficiency of the recovery processing of the erase interruption situation in the flash memory chip.

[0034] Preferably, the first status marking module includes an erase status determination unit and a status memory erase unit;

[0035] The erase state determination unit is electrically connected to the erase operation state machine in the NOR flash memory chip and the state memory erase unit respectively;

[0036] The erase state determination unit is used to receive a state signal generated and output by the erase operation state machine when performing an erase operation;

[0037] Wherein, the status signal includes a start signal and an end signal of the erase operation;

[0038] The state memory erasing unit is used to set the first state flag information stored in the non-volatile flag information memory to a state indicating that an abnormal interruption of an erasing operation occurs according to the state signal and the trigger signal.

[0039] In this solution, based on the erase state determination unit receiving the status signal corresponding to the erase operation sent by the erase operation state machine, the state of the erase operation can be known. Once the erase state monitoring module detects that an abnormal power interruption occurs during the erase process, the state memory erase unit is automatically triggered to execute the writing of the first status mark information representing the state of the abnormal interruption of the erase operation. The two functional modules are independent of each other and cooperate with each other, which ensures the execution efficiency and reliability of the erase interruption mark, thereby improving the control efficiency and accuracy of the entire erase operation.

[0040] Preferably, the state memory erase unit comprises a power pump and an auxiliary power supply electrically connected to the power pump;

[0041] The power pump is used to provide the state memory erase unit with a first operating voltage when performing erase operations and write operations;

[0042] The auxiliary power supply is used to provide the state memory erasing unit with a second operating voltage of a first set duration in the event of an abnormal power outage.

[0043] In this solution, under normal conditions, the first operating voltage when performing erase and write operations is obtained based on the power pump; once an erase interruption occurs, the power support provided by the power pump cannot be obtained. At this time, it is necessary to rely on an auxiliary power supply that pre-stores a certain amount of electricity (usually a storage capacitor) to provide power support for a certain period of time to the state memory erase and write unit to ensure that the generation and writing of the first state mark information can be completed. This is the key to ensuring that subsequent erase and repair operations can be achieved.

[0044] Preferably, the erase state determination unit comprises a D flip-flop;

[0045] Wherein, the clock terminal of the D flip-flop is connected to the start signal of the erase operation, and the reset signal terminal of the D flip-flop is controlled by the power-on signal and the end signal of the erase operation;

[0046] The D end of the D flip-flop is in a pull-up state, and the output end of the D flip-flop outputs the first state mark information indicating whether a power interruption occurs during an erase operation.

[0047] In this solution, by selecting a D flip-flop as the erase state determination unit, it is possible to independently obtain the mark information of different dimensions contained in the first state mark information, thereby ensuring the accuracy of the first state mark information, thereby improving the control efficiency and accuracy of the entire erase operation; at the same time, the corresponding circuit also has the advantages of simple structure, small space occupation, and low hardware investment cost.

[0048] Preferably, the state memory erasing unit comprises a NAND gate circuit and a data erasing circuit, and the data erasing circuit is electrically connected to the NAND gate circuit and the tag information memory respectively;

[0049] The two input ends of the NAND gate circuit are electrically connected to the output end of the erase state monitoring module and the output end of the D flip-flop respectively;

[0050] The NAND gate circuit is used to trigger the data erasing circuit to write the first state mark information into the mark information memory when the output end of the erasing state monitoring module and the output end of the D flip-flop both output a high level; or trigger the data erasing circuit to first erase the historical mark information in the mark information memory and then write the first state mark information into the mark information memory;

[0051] The write operation is completed before the NOR flash memory chip is powered off or restarted.

[0052] In this scheme, when an erase interrupt occurs, the NAND gate circuit outputs a high level based on the level signals of the two input terminals, and dynamically triggers the data erase circuit to write the first state mark information in a timely manner, that is, based on the cooperation between the logic control circuit and the data erase circuit, the processing efficiency of writing the first state mark information to the mark information storage device is guaranteed, and then it is guaranteed that the stored first state mark information can be obtained in time after the NOR flash memory chip is powered on, and the control efficiency of the entire erase operation is effectively guaranteed.

[0053] Preferably, the auxiliary power supply includes a storage capacitor, one end of the storage capacitor is electrically connected to the power pump and the data erasing circuit respectively, and the other end of the storage capacitor is grounded.

[0054] Preferably, the erase status monitoring module is used to monitor the voltage information of the power supply of the NOR flash memory chip, and when the voltage information is less than a set voltage threshold, or less than the set voltage threshold and lasts for a second set time, determine that the power supply is interrupted and generate the trigger signal;

[0055] In this solution, by monitoring the voltage of the power supply in real time, when the voltage is less than the set value or is continuously less than the set value, it is directly determined that a power interruption has occurred, and the generation of the first state mark information is triggered in a timely manner and written into the non-volatile mark information memory, thereby ensuring the timeliness of the generation and writing of the first state mark information, and then ensuring the processing accuracy and timeliness of subsequent erase and recovery operations.

[0056] and / or,

[0057] The erase repair control unit is used for controlling the clearing of the first state mark information in the mark information storage after performing the erase repair operation.

[0058] In this solution, after executing the erase and repair operation, all the first state mark information recorded and stored is automatically cleared without the need for subsequent clearing operations, thereby simplifying the entire processing flow; at the same time, it ensures that only the latest first state mark information is stored in the mark information storage device, thereby improving the reading efficiency of the first state mark information by the state reading unit and avoiding the occurrence of information reading errors, thereby effectively improving the subsequent erase and repair control efficiency and accuracy.

[0059] Preferably, the tag information storage is implemented by a setting flash memory array, and the setting flash memory array is arranged at a setting position away from a reference array in the NOR type flash memory chip;

[0060] and / or,

[0061] The setting flash memory array and the reference array share the same read-write circuit;

[0062] and / or,

[0063] The flash memory array and the reference array are set not to share bit lines;

[0064] and / or,

[0065] The flash memory array and the reference array are set to be in different P potential wells;

[0066] and / or,

[0067] The setting flash memory array independently configures the corresponding data selector;

[0068] and / or,

[0069] The data selector comprises a multiplexer;

[0070] and / or,

[0071] The state reading unit is a reading circuit of a setting register in the NOR flash memory chip.

[0072] The present invention also provides an erase operation control method for a NOR flash memory chip, the erase operation control method is implemented by using the above-mentioned erase operation control system, and the erase operation control method comprises:

[0073] Before the NOR flash memory chip is powered off or restarted due to power interference or abnormal power failure that causes erasure interruption during an erasure operation, the first state flag information stored in the non-volatile flag information memory is set to a state indicating that an abnormal interruption of the erasure operation occurs;

[0074] After power-on startup, the stored first state mark information is obtained, and according to the first state mark information, a preset erase repair strategy is used to perform erase repair.

[0075] Preferably, the erase operation control method further includes:

[0076] Monitoring the power state of the NOR flash memory chip during the erasing operation, and generating a trigger signal when power interference or abnormal power failure causing the erasing interruption is detected;

[0077] The first state flag information stored in the non-volatile flag information memory is set to a state indicating that an abnormal interruption of an erase operation occurs based on the trigger signal.

[0078] Preferably, the erasing operation control system further comprises a block erasing state marking module;

[0079] The block erase status mark module includes a plurality of erase operation completion mark storage units corresponding to each physical block of the NOR flash memory chip one by one;

[0080] The erasing operation control system is used to control the erasing operation completion mark storage unit to perform an erasing operation together with the corresponding physical block;

[0081] The erase operation control method further includes:

[0082] After the physical block corresponding to the erase operation completion mark storage unit completes the erase operation, performing a write operation on the erase operation completion mark storage unit;

[0083] When the first status mark information is a state indicating that an erase operation is abnormally interrupted, the block address of the physical block where the erase interruption occurs is confirmed based on whether the erase operation completion mark storage unit is written, and erase repair is performed on the physical block at the block address.

[0084] Preferably, the step of controlling the use of a preset erasure repair strategy to perform erasure repair according to the first status mark information includes:

[0085] When the first state mark information is a state indicating that an erase operation is abnormally interrupted, obtaining bit line current information of the entire flash memory array in the NOR flash memory chip;

[0086] When the bit line current information indicates the presence of a bit line leakage current, address information corresponding to a physical block or a physical sector where the bit line leakage current occurs is obtained, and the physical block or the physical sector corresponding to the address information is erased and repaired.

[0087] Preferably, the erase operation control method further includes:

[0088] The power state of the NOR flash memory chip during the erase and repair operation is monitored, and when a power disturbance or abnormal power failure causing the interruption of the erase is detected, the trigger signal is generated again.

[0089] The present invention also provides a NOR flash memory chip, and the NOR flash memory chip includes the above-mentioned erase operation control system.

[0090] On the basis of being in accordance with the common sense in the art, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present invention.

[0091] The positive and progressive effects of the present invention are:

[0092] The present invention can realize that once the NOR flash memory chip is powered off or restarted due to power interference or abnormal power failure that causes erasure interruption during the erasure operation, and then powered on again, the first state mark information in the mark information storage device can be automatically read, and then the corresponding erase repair scheme is determined according to the analysis of the first state mark information, so as to automatically perform the erase repair operation using the erase repair scheme. The entire power-on and repair process of the scheme is automatically completed by the internal circuit of the chip, without the need for external system supervision and control, thus avoiding external complex control processes; at the same time, it can save chip startup time, and effectively improve the efficiency of erase recovery processing for erase interruption situations in NOR flash memory chips without relying on external system supervision and control, thereby ensuring the accuracy and reliability of erase recovery operations, and avoiding the occurrence of data errors after chip restart due to power interruption during the erase operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0093] Figure 1 Schematic diagram of the impact of interruptions on data at different steps in a typical erase operation of an existing NOR flash memory.

[0094] Figure 2 A schematic diagram of bit line leakage current in adjacent areas sharing a bit line in a NOR flash memory during a read operation.

[0095] Figure 3 This is a structural schematic diagram of an erase operation control system of a NOR flash memory chip according to Embodiment 1 of the present invention.

[0096] Figure 4 This is a first structural schematic diagram of an erase operation control system of a NOR flash memory chip according to Embodiment 2 of the present invention.

[0097] Figure 5 This is a second structural schematic diagram of the erase operation control system of the NOR flash memory chip according to the second embodiment of the present invention.

[0098] Figure 6 This is a schematic diagram of the first implementation principle of the erase operation control system of the NOR flash memory chip according to the second embodiment of the present invention.

[0099] Figure 7 It is a schematic diagram of setting ECMB (Erase Completion Mark Bit) in the erase operation control system of the NOR flash memory chip according to the second embodiment of the present invention.

[0100] Figure 8 This is a schematic diagram of a second implementation principle of the erase operation control system of the NOR flash memory chip according to the second embodiment of the present invention.

[0101] Fig. 9This is a flow chart of an erase operation control method for a NOR flash memory chip according to Embodiment 3 of the present invention.

[0102] Fig.10 This is a flow chart of an erase operation control method for a NOR flash memory chip according to a fourth embodiment of the present invention. DETAILED DESCRIPTION

[0103] The present invention is further described below by way of examples, but the present invention is not limited to the scope of the examples.

[0104] Example 1

[0105] like Figure 3 As shown, the erase operation control system of the NOR flash memory chip of this embodiment includes a first state marking module 1, a marking information storage 2 and a repair processing module 3 which are electrically connected in sequence; wherein the marking information storage 2 can also be called PSI_SR (Power Supply Interruption Status Registers).

[0106] The first state marking module 1 is used to set the first state marking information stored in the non-volatile marking information memory 2 to the state representing the abnormal interruption of the erasing operation before the NOR flash memory chip is powered off or restarted due to power interference or abnormal power failure that causes the erasing interruption during the erasing operation;

[0107] The flag information storage 2, namely, PSI_SR, is a group of non-volatile registers, which is used to write the first state flag information representing the state of abnormal interruption of the erase operation when the NOR flash memory chip is in the erase state and encounters a power interruption.

[0108] The repair processing module 3 is used to obtain the first state mark information stored in the mark information storage device 2 after power-on startup, and control the use of a preset erase repair strategy to perform erase repair according to the first state mark information.

[0109] In this solution, the erase interruption condition can be automatically judged and identified in time, so that the multiple dimensional information associated with the erase interruption can be marked and recorded and stored in time, so that the first state mark information can be automatically read and called directly after the NOR flash memory chip is powered on again, so as to automatically and accurately determine and start the corresponding erase repair plan, so as to provide timely protection and remedy for the erase interruption situation.

[0110] It should be noted that: in this embodiment, when PSI_SR encounters a power interruption during the erase operation, the first state mark information is marked and written, and the post-power-on repair processing module is instructed to complete the erase repair during the next power-on startup, and then the PSI_SR is erased and cleared; therefore, the first state mark information is generated and stored only when a power interruption is encountered during the erase operation, and there is only one write operation and one erase operation at the next power-on, and the PSI_SR signal, i.e., the first state mark information, will not be erased and written multiple times, thereby ensuring the reliability and stability of the operation of the NOR flash memory chip.

[0111] In the present embodiment, once the NOR flash memory chip is powered off or restarted and then powered on again during the erasing operation due to power interference or abnormal power failure that causes erasing interruption, the first state mark information in the mark information storage device is automatically read, and then the corresponding erase repair scheme is determined according to the analysis of the first state mark information, so as to automatically perform the erase repair operation using the erase repair scheme, that is, it is possible to automatically and quickly detect whether there is an abnormal interruption in the erase operation, and automatically start the erase repair operation if there is an abnormal interruption, effectively improving the erase recovery processing efficiency of the erase interruption situation in the NOR flash memory chip, ensuring the accuracy and reliability of the erase recovery operation, and avoiding the occurrence of data errors after the chip is restarted due to abnormal power interruption during the erase operation; and the entire power-on and repair process is automatically completed by the internal circuit of the chip, without the need for external system supervision and control, thus avoiding complex external control processes; in addition, it can also save the startup time of the chip.

[0112] Example 2

[0113] like Figure 4 and Figure 5 As shown, the erasing operation control system of the NOR flash memory chip of this embodiment is a further improvement of the embodiment 1, specifically:

[0114] In an implementable solution, the tag information storage 2 is implemented by a set flash memory array, and the set flash memory array is set at a set position away from a reference array in a NOR type flash memory chip.

[0115] The flash memory array and the reference array are configured to share the same read / write circuit.

[0116] Specifically, the tag information storage device, namely, PSI_SR, uses one bit, and can further be implemented using one Flash Cell, thereby achieving the effects of effectively saving chip area and reducing write power consumption.

[0117] In order to simplify the peripheral circuit design, the PSI_SR array corresponding to the tag information storage device can be placed near the standard reference array (Reference Array) in the NOR flash memory chip so that the PSI_SR array can share the read and write circuits of the standard reference array. There is no need to design a special read and write circuit that is compatible with the PSI_SR array, which simplifies the circuit layout structure, reduces the layout space, and also reduces the hardware investment cost.

[0118] It should be noted that: according to the usage convention of registers and flash memory chips, the "0" and "1" states corresponding to the erase and write states in the PSI_SR array and the standard reference array Reference Array are opposite. In the PSI_SR array, the erase state corresponds to "0" and the write state corresponds to "1"; while in the standard reference array Reference Array, the erase state corresponds to "1" and the write state corresponds to "0".

[0119] The flash memory array and the reference array are set not to share bit lines, and the standard reference array Reference Array does not share bit lines with the tag information memory PSI_SR. In this way, when PSI_SR is erased, if there is a power outage, the risk of bit line leakage current caused by excessive erasure of the tag information memory PSI_SR is avoided, thereby ensuring the stability and safety of the overall operation of the NOR flash memory chip.

[0120] The flash memory array and the reference array are set to be in different P potential wells;

[0121] The flash memory array is set to independently configure a corresponding data selector; specifically, the data selector includes a multiplexer.

[0122] Specifically, the PSI_SR array and the standard reference array Reference Array can be in different P-potential wells (TPW, Triple P-Well) and have a separate word line Y-way selector (YMUX). This arrangement saves chip area as much as possible, simplifies circuit design, and avoids interfering with the standard reference array Reference Array when operating PSI_SR.

[0123] In an implementable solution, the erasing operation control system further includes an erasing state monitoring module 4 electrically connected to the first state marking module 1;

[0124] The erase state monitoring module 4 is used to monitor the power state of the NOR flash memory chip during the erase operation, and when power interference or abnormal power failure that causes the erase interruption is detected, a trigger signal is generated and transmitted to the first state marking module 1;

[0125] The first state marking module 1 is used to set the first state marking information stored in the non-volatile marking information memory 2 to a state indicating that an abnormal interruption of an erase operation occurs based on a trigger signal.

[0126] like Figure 6 As shown, the erase operation control system corresponds to the erase status monitoring, automatic writing of PSI_SR and other erase operation control logics.

[0127] In the present solution, the erasure interruption condition can be automatically monitored and identified in time, the erasure interruption interference factors that cause the erasure operation to be interrupted can be monitored in real time, and the first state mark information representing the abnormal interruption of the erasure operation can be triggered in time to be set and stored in the non-volatile mark information storage device 2, so as to ensure that once the NOR flash memory chip is powered off or restarted due to power interference or abnormal power failure that causes the erasure interruption during the erasure operation and then powered on again, the first state mark information in the mark information storage device 2 can be automatically read, so as to effectively improve the timeliness, reliability and accuracy of the erasure recovery processing of the erasure interruption condition in the NOR flash memory chip.

[0128] In an practicable solution, the repair processing module 3 includes a state reading unit 5 and an erase repair control unit 6 which are electrically connected to the tag information storage 2 in sequence;

[0129] The state reading unit 5 is used to read the first state mark information in the mark information storage 2 and send it to the erase repair control unit 6 after the NOR flash memory chip is powered on;

[0130] The erasure repair control unit 6 is used to obtain a corresponding preset erasure repair strategy to perform erasure repair when the first state mark information is a state indicating that an abnormal interruption of the erasure operation occurs.

[0131] In this solution, the repair processing module 3 is provided to include two functional units, which independently complete the reading function of the first state mark information and the control function of the erase repair operation based on the first state mark information. Based on the independence and correlation between the two, the execution efficiency of the repair processing operation is guaranteed; the entire power-on and repair process is automatically completed by the internal circuit of the chip, without the need for external system supervision and control, and it also belongs to the improved design requirements adapted to the NOR flash memory chip, ensuring the rationality and effectiveness of the erase operation control scheme implemented in the NOR flash memory chip.

[0132] In addition, the status reading unit 5 can be a reading circuit for setting registers of a NOR flash memory chip, that is, the existing reading circuit can be shared to effectively simplify the circuit design and save chip area.

[0133] In an implementable solution, the erase operation control system further includes a block erase state marking module 7 .

[0134] The block erase state marking module 7 includes a plurality of erase operation completion marking storage units 8 corresponding to each physical block of the NOR flash memory chip one by one;

[0135] The erase operation control system is used to control the erase operation completion mark storage unit 8 to perform an erase operation together with the corresponding physical block;

[0136] The erasing operation control system is also used to perform a write operation on the erasing operation completion mark storage unit 8 to indicate that the complete erasing operation has been completed after the physical block corresponding to the erasing operation completion mark storage unit 8 completes the erasing operation;

[0137] The repair processing module 3 is used to confirm the block address of the physical block where the erasure interruption occurs according to whether the write operation is performed on the erase operation completion mark storage unit 8 when the first state mark information is a state representing that the erase operation has been abnormally interrupted, and perform erase repair on the physical block at the block address.

[0138] Specifically, ECMB is set in each physical block and combined with a single-bit PSI_SR, the unfinished erase operation address is automatically and quickly detected when the chip is powered on and an automatic and quick repair operation is performed.

[0139] Specifically, Figure 7 As shown, it is a schematic diagram of ECMB settings. The erase operation of the storage array is based on PB (Physical Block, which can be understood as sector). In this embodiment, an ECMB bit is set in each physical block PB (PB0, PB1, ..., PBn) to mark the completion status of the erase operation. In the erase operation, ECMB and other storage units in the physical block PB are Preprogrammed, Erase, and Recovery together; in the last step of the erase operation (after the conventional Refresh step is completed), an ECMB write operation (ECMB Program) is added; in this way, when ECMB = 0, it means that a physical block has undergone a complete erase operation; if ECMB = 1, it means that an erase operation has not been completed normally in the physical block, and then the block address of the physical block can be obtained, and the physical block at the block address can be erased and repaired in time.

[0140] Among them, the erasing operation control system also includes a reading module for the completion status of the erasing operation, which is used to read whether the erasing operation completion mark storage unit 8 has been written and sent to the repair processing module; the reading module can directly use the reading circuit of the flash memory array to simplify the chip hardware design, reduce the chip area and reduce the investment cost.

[0141] Specifically, in this solution, each physical block of the NOR flash memory chip is provided with a corresponding erase operation completion mark storage unit, and the erase operation completion mark storage unit performs the same erase operation during the corresponding physical block erase process. The difference between the two operations is that after the physical block corresponding to the erase operation completion mark storage unit completes the erase operation, a write operation is also performed on the erase operation completion mark storage unit to indicate that the complete erase operation has been completed. Therefore, by judging whether the erase operation completion mark storage unit 8 is written to, the physical block where the erase interruption occurs can be quickly and accurately located, and the physical block can be automatically erased and repaired based on the block address of the physical block, thereby ensuring the accuracy and efficiency of the erase recovery processing of the erase interruption in the NOR flash memory chip.

[0142] In an implementable solution, the erase operation control system further includes a bit line current detection module 9;

[0143] The repair processing module 3 is used to call the bit line current detection module 9 when the first state mark information is a state indicating that the erase operation is abnormally interrupted;

[0144] The bit line current detection module 9 is used to obtain the bit line current information (or column leakage current information) of the entire flash memory array in the NOR flash memory chip, and when the bit line current information indicates the existence of bit line leakage current (or column leakage current), obtain the address information corresponding to the physical block or physical sector where the bit line leakage current occurs, and call the repair processing module to erase and repair the physical block or physical sector corresponding to the address information.

[0145] Specifically, Figure 8 As shown, the erase operation control logic executed by the corresponding erase operation control system when based on the bit line current detection module.

[0146] In this solution, when an abnormal interruption occurs in the erase operation of a NOR flash memory chip, the bit line current information of the entire flash memory array is promptly detected to see whether it indicates the presence of a bit line leakage current. If so, the address of the physical block where the bit line leakage current occurs is automatically obtained, or the address of the corresponding physical sector, both of which are acceptable, to perform erase repair on the corresponding physical block or physical sector, thereby effectively ensuring the efficiency, feasibility and flexibility of the erase recovery process for the erase interruption in the NOR flash memory chip. The entire power-on and repair process is automatically completed by the internal circuit of the chip, without the need for external system supervision and control.

[0147] In an implementable solution, the erase status monitoring module 4 is also used to monitor the power status of the NOR flash memory chip during the erase repair operation, and when power interference or abnormal power failure that causes erase interruption is detected, a trigger signal is generated again and transmitted to the first status marking module 1.

[0148] In this solution, during the erase and repair process, it is still monitored in real time whether the factors causing the interruption of the erase and repair occur. Once it occurs, the first state marking module 1 is triggered in time to mark the first state marking information of the erase interruption situation, so that after the NOR flash memory chip is powered on again, the corresponding erase and repair solution is determined in time according to the latest recorded first state marking information until the erase operation of the NOR flash memory chip is completed, thereby achieving any erase operation, as long as the erase interruption caused by power interruption interference occurs, the erase repair can be performed in time, even if the erase interruption occurs in the erase repair for multiple consecutive times, the erase repair can be performed in time and efficiently, which effectively improves the effectiveness, reliability and efficiency of the recovery processing of the erase interruption situation in the flash memory chip.

[0149] In an implementable solution, the first state marking module 1 includes an erase state determination unit 10 and a state memory erase unit 11;

[0150] The erase state determination unit 10 is electrically connected to the erase operation state machine and the state memory erase unit 11 in the NOR flash memory chip respectively;

[0151] The erase state determination unit 10 is used to receive a state signal generated and output by the erase operation state machine when performing an erase operation;

[0152] The status signal includes a start signal Erase_op_start and an end signal Erase_op_done of the erase operation;

[0153] The state memory erasing unit 11 is used to set the first state flag information stored in the non-volatile flag information memory 2 to a state indicating that an abnormal interruption of the erasing operation occurs according to the state signal and the trigger signal.

[0154] In this solution, based on the erasing state determination unit 10 receiving the state signal corresponding to the erasing operation sent by the erasing operation state machine, the state of the erasing operation can be known. Once the erasing state monitoring module 4 detects that an abnormal power interruption occurs during the erasing process, the state memory erasing unit 11 is automatically triggered to execute the writing of the first state mark information representing the state of abnormal interruption of the erasing operation. The two functional modules are independent of each other and cooperate with each other, which ensures the execution efficiency and reliability of the erase interruption mark, thereby improving the control efficiency and accuracy of the entire erasing operation.

[0155] In an practicable solution, the state memory erase unit 11 includes a power pump and an auxiliary power supply electrically connected to the power pump;

[0156] The power pump is used to provide the state memory erase unit 11 with a first operating voltage when performing erase operations and write operations;

[0157] The auxiliary power supply is used to provide the state memory erasing unit 11 with a second operating voltage for a first set duration in the event of an abnormal power outage.

[0158] In this solution, under normal conditions, the first operating voltage for performing erase and write operations is obtained based on the power pump; once an abnormal power interruption occurs during the erase process, the power support provided by the power pump cannot be obtained. At this time, it is necessary to rely on an auxiliary power supply that pre-stores a certain amount of electricity (usually a storage capacitor) to provide power support for a certain period of time to the state memory erase unit 11 to ensure that the generation and writing of the first state mark information can be completed, which is the key to ensuring that subsequent erase and repair operations can be achieved.

[0159] In one practicable solution, the erase state determination unit 10 includes a D flip-flop;

[0160] The clock terminal of the D flip-flop is connected to the start signal of the erase operation, and the reset signal terminal of the D flip-flop is controlled by the power-on signal and the end signal of the erase operation;

[0161] The D end of the D flip-flop is in a pull-up state, and the output end of the D flip-flop outputs first state mark information indicating whether a power interruption occurs during the erase operation.

[0162] Specifically, Figure 5 As shown, the input signal (D) of the D flip-flop with reset is at a high level, and the erase start signal (erase_op_start) output from the erase operation state machine (Erase Operation State Machine) controls the trigger clock (CK), and the output signal (Q) of the trigger is the erase progress signal; the erase completion signal (erase_op_done) output from the erase state machine and the power-on restart signal (POR) are logically taken or to control the reset of the flip-flop.

[0163] In this solution, by selecting a D flip-flop as the erase state determination unit 10, it is possible to independently obtain the mark information of different dimensions contained in the first state mark information, thereby ensuring the accuracy of the first state mark information, thereby improving the control efficiency and accuracy of the entire erase operation; at the same time, the corresponding circuit also has the advantages of simple structure, small space occupation, and low hardware investment cost.

[0164] In an practicable solution, the state memory erase unit 11 includes a NAND gate circuit 12 and a data erase circuit 13, and the data erase circuit 13 is electrically connected to the NAND gate circuit 12 and the tag information memory 2 respectively;

[0165] The two input terminals of the NAND gate circuit 12 are electrically connected to the output terminal of the erase state monitoring module 4 and the output terminal of the D flip-flop respectively;

[0166] The NAND gate circuit 12 is used to trigger the data erasing circuit 13 to write the first state mark information into the mark information memory 2 when the output end of the erasing state monitoring module 4 and the output end of the D flip-flop both output a high level; or, trigger the data erasing circuit 13 to first erase the historical mark information in the mark information memory 2 and then write the first state mark information into the mark information memory 2;

[0167] The write operation is completed before the NOR flash memory chip is powered off or restarted.

[0168] Specifically, combined Figure 5 , the erase_in_operation (erase in progress) is output from the erase state determination unit 10 and input to the data erase circuit 13 (or PSI_SR erase circuit), the tag information memory PSI_SR controls the write circuit in the data erase circuit 13 through a NAND gate, and when the NAND gate output is 0, it means that the power is interrupted and the erase operation is not completed, and the chip automatically writes the tag information memory PSI_SR; the power pump in the data erase circuit 13 provides the tag information memory PSI_SR with voltages VPPX, VPPY, and VPPD for performing erase and write operations; in order to support the write function of the tag information memory PSI_SR after power failure, the power pump in the circuit is connected to a storage capacitor (C Drain), and the size of the storage capacitor is related to the number of bits of the tag information memory PSI_SR, which is sufficient to ensure that it can support the writing of the tag information memory PSI_SR after the chip is powered off (duration is in microseconds). Among them, in order to save the capacitor area and the area occupied by PSI_SR itself, PSI_SR is preferably implemented using a one-bit non-volatile Cell.

[0169] The status reading unit 5 and the erase repair control unit 6 that automatically run after the chip is powered on automatically read the PSI_SR signal after power-on, perform logic control based on one bit of PSI_SR, recover the erase operation that was not completed due to power interruption, and then erase and clear the PSI_SR signal from the tag information memory PSI_SR.

[0170] In this solution, when an erase interrupt occurs, the NAND gate circuit 12 outputs a high level based on the level signals of the two input terminals, and dynamically triggers the data erase circuit 13 to write the first state mark information in a timely manner. That is, based on the cooperation between the logic control circuit and the data erase circuit 13, the processing efficiency of writing the first state mark information to the mark information storage device is guaranteed, thereby ensuring that the stored first state mark information can be obtained in time after the NOR flash memory chip is powered on, and effectively ensuring the control efficiency of the entire erase operation.

[0171] In an implementable solution, the auxiliary power supply includes a storage capacitor, one end of the storage capacitor is electrically connected to the power pump and the data erasing circuit 13 respectively, and the other end of the storage capacitor is grounded.

[0172] Among them, the auxiliary power supply can select a storage capacitor of set specifications; it can also be composed of one or more storage capacitors; when the auxiliary power supply is composed of multiple storage capacitors, these storage capacitors can be connected in series, in parallel, partially in series and the rest in parallel, etc.; the specific design of the auxiliary power supply can be designed or adjusted according to actual needs.

[0173] In an implementable solution, the erase status monitoring module 4 is used to monitor the voltage information of the power supply of the NOR flash memory chip, and when the voltage information is less than a set voltage threshold, or less than the set voltage threshold and lasts for a second set time, it is determined that the power supply is interrupted and a trigger signal is generated.

[0174] In this solution, by monitoring the voltage of the power supply in real time, when the voltage is less than the set value (for example: 1.5V) or is continuously less than the set value, it is directly determined that the power supply is interrupted and the generation of the first state mark information is triggered in time and written into the non-volatile mark information memory, thereby ensuring the timeliness of the generation and writing of the first state mark information, and then ensuring the processing accuracy and timeliness of subsequent erase and recovery operations.

[0175] In an implementable solution, the erase repair control unit 6 is used to control the clearing of the first state mark information in the mark information storage 2 after performing the erase repair operation.

[0176] In this solution, after executing the erase and repair operation, all the first state mark information recorded and stored is automatically cleared without the need for subsequent clearing operations, thereby simplifying the entire processing flow; at the same time, it ensures that only the latest first state mark information is stored in the mark information storage device, thereby improving the reading efficiency of the first state mark information by the state reading unit 5, avoiding the occurrence of information reading errors, and thereby effectively improving the subsequent erase and repair control efficiency and accuracy.

[0177] The implementation principle of the erasing operation control system of the NOR flash memory chip of this embodiment is specifically described below based on an example:

[0178] In the process of the NOR flash memory chip receiving the erase instruction and the erase operation state machine executing the erase operation, the erase interrupt status monitoring module is used to monitor the changes in the power supply voltage in real time. When the power supply voltage is too low, for example, lower than the preset value of 1.5V, if the first status marking module determines that the erase operation is not completed, the PSI_SR erase module (data erase circuit) automatically executes the PSI_SR signal (first status marking information), that is, automatically executes the PSI_SR write operation to ensure that the PSI_SR write is completed before the chip is powered off or restarted.

[0179] If there is no power interruption during the erase operation and the erase operation is completed normally, the first state marking module will not be accessed, and the entire control process is automatically completed by the internal circuit of the chip without the need for external system supervision and control, ensuring that the erase operation control process of the NOR flash memory chip is timely and efficient.

[0180] After the chip is powered on, the first state flag information in the flag information memory PSI_SR is automatically read.

[0181] For PSI_SR, 1 represents the write state and 0 represents the erase state. If PSI_SR=0 is read, it means that there was no uncompleted erase operation caused by power interruption interference before, and the chip enters the standby state waiting for further instructions. If PSI_SR=1 is read, it means that there was an uncompleted erase operation before, and the erase operation repair process is started. The entire process is automatically completed by the internal circuit of the chip, without the need for external system supervision and control.

[0182] There are several options for the erase operation repair process:

[0183] Solution 1: Use the bit line current detection module to detect the bit line current of the entire flash array. If bit line leakage current is found, perform a complete erase operation on the physical sector or physical block where it is located; after the erase operation repair process is completed, perform an erase and clear operation on PSI_SR, and the chip completes the power-on process and waits for further instructions; the entire power-on and repair process is automatically completed by the chip's internal circuit, without the need for external system supervision and control. The entire power-on and repair process is automatically completed by the chip's internal circuit, without the need for external system supervision and control.

[0184] Solution 2: After the chip is powered on, PSI_SR is automatically read; if PSI_SR=0 is read, it means that there is no previous power interruption interference that caused the erase operation to be incomplete, and the chip enters the standby state and waits for further instructions; if PSI_SR=1 is read, it means that there is an unfinished erase operation before, and the erase operation repair process is started; the erase operation repair process reads the ECMB of all physical blocks PB, and if a physical block with ECMB=1 is found, the physical block is completely erased, and after the erase operation repair process is completed, PSI_SR is erased and cleared, the chip completes the power-on process and waits for further instructions; the entire power-on and repair process is automatically completed by the internal circuit of the chip, without the need for external system supervision and control. That is, after the NOR flash memory chip is powered on, ECMB is read only when the previous erase operation is detected to be abnormally interrupted (PSI_SR=1), thereby greatly shortening the chip power-on time, and at the same time effectively ensuring the judgment accuracy of power interference or abnormal power failure that causes erase interruption, as well as the efficiency and reliability of erase repair operation control.

[0185] In the present embodiment, the entire power-on and repair process is automatically completed by the internal circuit of the chip, without the need for external system supervision and control, thus avoiding complex external control processes; at the same time, it can save chip startup time, and effectively improve the efficiency of erase recovery processing for erase interruptions in NOR flash memory chips without relying on external system supervision and control, thereby ensuring the accuracy and reliability of erase recovery operations and avoiding data errors after chip restart due to power interruption during the erase operation.

[0186] Example 3

[0187] The erase operation control method of the NOR flash memory chip of this embodiment is implemented by using the erase operation control system of the NOR flash memory chip of embodiment 1 or 2.

[0188] like Fig. 9 As shown, the erase operation control method of the NOR flash memory chip of this embodiment includes:

[0189] S101, before the NOR flash memory chip is powered off or restarted due to power interference or abnormal power failure that causes erasure interruption during an erasure operation, setting first state flag information stored in a non-volatile flag information memory to a state indicating that an abnormal interruption of the erasure operation occurs;

[0190] S102: After power-on, obtain the stored first state mark information, and control the use of a preset erase and repair strategy to perform erase and repair according to the first state mark information.

[0191] In this solution, the erase interruption condition can be automatically judged and identified in time, so that the multiple dimensional information associated with the erase interruption can be marked and recorded and stored in time, so that the first state mark information can be automatically read and called directly after the NOR flash memory chip is powered on again, so as to automatically and accurately determine and start the corresponding erase repair plan, so as to provide timely protection and remedy for the erase interruption situation.

[0192] It should be noted that in this embodiment, the first state mark information is generated and stored, and there is only one write operation when an abnormal power interruption occurs during the erase operation and an erase operation at the next power-on. The PSI_SR signal, that is, the first state mark information, will not be erased and written multiple times, thereby ensuring the reliability and stability of the operation of the NOR flash memory chip.

[0193] In the present embodiment, once the NOR flash memory chip is powered off or restarted and then powered on again during the erasing operation due to power interference or abnormal power failure that causes erasing interruption, the first state mark information in the mark information storage device is automatically read, and then the corresponding erase repair scheme is determined according to the analysis of the first state mark information, so as to automatically perform the erase repair operation using the erase repair scheme, that is, it is possible to automatically and quickly detect whether there is an abnormal interruption in the erase operation, and automatically start the erase repair operation if there is an abnormal interruption, effectively improving the erase recovery processing efficiency of the erase interruption situation in the NOR flash memory chip, ensuring the accuracy and reliability of the erase recovery operation, and avoiding the occurrence of data errors after the chip is restarted due to abnormal power interruption during the erase operation; and the entire power-on and repair process is automatically completed by the internal circuit of the chip, without the need for external system supervision and control, thus avoiding complex external control processes; in addition, it can also save the startup time of the chip.

[0194] Example 4

[0195] The erase operation control method of the NOR flash memory chip of this embodiment is a further improvement of the embodiment 3, specifically:

[0196] In one feasible solution, Fig.10 As shown, step S101 includes:

[0197] S1011, monitoring the power state of the NOR flash memory chip during the erasing operation, and generating a trigger signal when power interference or abnormal power failure that causes the erasing interruption is detected;

[0198] S1012: Based on the trigger signal, set the first state flag information stored in the non-volatile flag information memory to a state indicating that an abnormal interruption of the erase operation occurs.

[0199] In the present solution, the erasure interruption condition can be automatically monitored and identified in time, the erasure interruption interference factors causing the erasure operation to be interrupted can be monitored in real time, and the first state mark information representing the abnormal interruption of the erasure operation can be triggered in time to be set and stored in a non-volatile mark information memory, so as to ensure that once the NOR flash memory chip is powered off or restarted due to power interference or abnormal power failure causing the erasure interruption during the erasure operation and then powered on again, the first state mark information in the mark information memory can be automatically read, so as to effectively improve the timeliness, reliability and accuracy of the erasure recovery processing of the erasure interruption condition in the NOR flash memory chip.

[0200] In an implementable solution, the erase operation control system further includes a block erase status marking module;

[0201] The block erase status mark module includes a plurality of erase operation completion mark storage units corresponding to each physical block of the NOR flash memory chip one by one;

[0202] The erasing operation control system is used to control the erasing operation completion mark storage unit to perform an erasing operation together with the corresponding physical block;

[0203] The erase operation control method further includes:

[0204] After the physical block corresponding to the erase operation completion mark storage unit completes the erase operation, performing a write operation on the erase operation completion mark storage unit to indicate that a complete erase operation has been completed;

[0205] When the first status mark information is a state indicating that an erase operation is abnormally interrupted, the block address of the physical block where the erase interruption occurs is confirmed based on whether the erase operation completion mark storage unit is written, and erase repair is performed on the physical block at the block address.

[0206] In one feasible solution, step S102 includes:

[0207] When the first state mark information is a state indicating that an abnormal interruption of an erase operation occurs, obtaining bit line current information of the entire flash memory array in the NOR flash memory chip;

[0208] When the bit line current information indicates the presence of bit line leakage current, the address information corresponding to the physical block or physical sector where the bit line leakage current occurs is obtained, and the repair processing module is called to erase and repair the physical block or physical sector corresponding to the address information.

[0209] In an implementable solution, the erase operation control method further includes:

[0210] The power state of the NOR flash memory chip during the erase repair operation is monitored, and a trigger signal is generated again when a power disturbance or abnormal power failure causing the interruption of the erase is detected.

[0211] It should be noted that the implementation principle of the erase operation control method of this embodiment is the same as the implementation principle of Embodiment 1 or 2, and will not be repeated here.

[0212] In the present embodiment, the entire power-on and repair process is automatically completed by the internal circuit of the chip, without the need for external system supervision and control, thus avoiding complex external control processes; at the same time, it can save chip startup time, and effectively improve the efficiency of erase recovery processing for erase interruptions in NOR flash memory chips without relying on external system supervision and control, thereby ensuring the accuracy and reliability of erase recovery operations and avoiding data errors after chip restart due to power interruption during the erase operation.

[0213] Example 5

[0214] The NOR flash memory chip of this embodiment includes the erase operation control system of the first or second embodiment.

[0215] The NOR flash memory chip in this embodiment, due to the integration of the above-mentioned erase operation control system, can automatically read the first state mark information corresponding to the last erase interruption once the flash memory chip is powered on again, and generate an erase repair scheme corresponding thereto to automatically perform the erase repair operation, thereby effectively improving the recovery processing efficiency of the erase interruption situation in the NOR flash memory chip, avoiding the occurrence of data errors after the chip is restarted due to power interruption during the erase operation, and thus effectively improving the overall product performance of the existing NOR flash memory chip.

[0216] Although the specific embodiments of the present invention are described above, it should be understood by those skilled in the art that this is only for illustration and the protection scope of the present invention is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but these changes and modifications all fall within the protection scope of the present invention.

Claims

1. A NOR flash memory chip erase operation control system, characterized in that: The erasing operation control system comprises a first state marking module, a marking information storage device and a repair processing module which are electrically connected in sequence; The first status marking module is used to set the first status marking information stored in the non-volatile marking information memory to a state indicating that the erasing operation is abnormally interrupted before the NOR flash memory chip is powered off or restarted due to power interference or abnormal power failure that causes the erasing interruption during the erasing operation; The repair processing module is used to obtain the first state mark information stored in the mark information storage device after power-on startup, and control the use of a preset erase repair strategy to perform erase repair according to the first state mark information; The erasing operation control system further includes an erasing state monitoring module electrically connected to the first state marking module; The erase state monitoring module is used to monitor the power state of the NOR flash memory chip during the erase operation, and when power interference or abnormal power failure that causes the erase interruption is detected, a trigger signal is generated and transmitted to the first state marking module; The first status marking module is used to set the first status marking information stored in the non-volatile marking information storage to a state indicating that an abnormal interruption of an erase operation occurs based on the trigger signal; The erase status monitoring module is also used to monitor the power status of the NOR flash memory chip during the erase repair operation, and when power interference or abnormal power failure that causes erase interruption is detected, the trigger signal is generated again and transmitted to the first status marking module.

2. The erase operation control system of the NOR flash memory chip as claimed in claim 1, characterized in that: The repair processing module includes a state reading unit and an erasure repair control unit which are electrically connected to the mark information storage in sequence; The state reading unit is used to read the first state mark information in the mark information storage device and send it to the erase repair control unit after the NOR flash memory chip is powered on; The erase repair control unit is used to obtain the corresponding preset erase repair strategy to perform erase repair when the first status mark information is a state indicating that an erase operation is abnormally interrupted.

3. The erasing operation control system of a NOR flash memory chip according to claim 1 or 2, characterized in that: The erase operation control system also includes a block erase state marking module; The block erase status mark module includes a plurality of erase operation completion mark storage units corresponding to each physical block of the NOR flash memory chip one by one; The erasing operation control system is used to control the erasing operation completion mark storage unit to perform an erasing operation together with the corresponding physical block; The erasing operation control system is further used to perform a write operation on the erasing operation completion mark storage unit after the physical block corresponding to the erasing operation completion mark storage unit completes the erasing operation; The repair processing module is used to confirm the block address of the physical block where the erasure interruption occurs according to whether the write operation is performed on the storage unit marked by the completion of the erasure operation when the first status mark information is a state representing that the erasure operation has been abnormally interrupted, and perform erase repair on the physical block at the block address.

4. The erasing operation control system of a NOR flash memory chip according to claim 1 or 2, characterized in that: The erase operation control system further includes a bit line current detection module; The repair processing module is used to call the bit line current detection module when the first state mark information is a state indicating that an abnormal interruption of an erase operation occurs; The bit line current detection module is used to obtain the bit line current information of the entire flash memory array in the NOR flash memory chip, and when the bit line current information indicates the existence of bit line leakage current, obtain the address information corresponding to the physical block or physical sector where the bit line leakage current occurs, and erase and repair the physical block or physical sector corresponding to the address information.

5. The erasing operation control system of a NOR flash memory chip according to claim 1 or 2, characterized in that: The first status marking module includes an erase status determination unit and a status memory erase unit; The erase state determination unit is electrically connected to the erase operation state machine in the NOR flash memory chip and the state memory erase unit respectively; The erase state determination unit is used to receive a state signal generated and output by the erase operation state machine when performing an erase operation; Wherein, the status signal includes a start signal and an end signal of the erase operation; The state memory erasing unit is used to set the first state flag information stored in the non-volatile flag information memory to a state indicating that an abnormal interruption of an erasing operation occurs according to the state signal and the trigger signal.

6. The erasing operation control system of a NOR flash memory chip as claimed in claim 5, characterized in that: The state memory erase unit includes a power pump and an auxiliary power supply electrically connected to the power pump; The power pump is used to provide the state memory erase unit with a first operating voltage when performing erase operations and write operations; The auxiliary power supply is used to provide the state memory erasing unit with a second operating voltage of a first set duration in the event of an abnormal power outage.

7. The erasing operation control system of a NOR flash memory chip as claimed in claim 6, characterized in that: The erase state determination unit includes a D flip-flop; Wherein, the clock terminal of the D flip-flop is connected to the start signal of the erase operation, and the reset signal terminal of the D flip-flop is controlled by the power-on signal and the end signal of the erase operation; The D end of the D flip-flop is in a pull-up state, and the output end of the D flip-flop outputs the first state mark information indicating whether a power interruption occurs during an erase operation.

8. The erasing operation control system of a NOR flash memory chip as claimed in claim 7, characterized in that: The state memory erasing unit comprises a NAND gate circuit and a data erasing circuit, and the data erasing circuit is electrically connected to the NAND gate circuit and the tag information memory respectively; The two input ends of the NAND gate circuit are electrically connected to the output end of the erase state monitoring module and the output end of the D flip-flop respectively; The NAND gate circuit is used to trigger the data erasing circuit to write the first state mark information into the mark information memory when the output end of the erasing state monitoring module and the output end of the D flip-flop both output a high level; Or, triggering the data erasing circuit to first erase the historical marking information in the marking information memory, and then writing the first state marking information into the marking information memory; The write operation is completed before the NOR flash memory chip is powered off or restarted.

9. The erasing operation control system of a NOR flash memory chip as claimed in claim 8, characterized in that: The auxiliary power supply comprises a storage capacitor, one end of which is electrically connected to the power pump and the data erasing circuit respectively, and the other end of which is grounded.

10. The erasing operation control system according to claim 2, characterized in that: The erase status monitoring module is used to monitor the voltage information of the power supply of the NOR flash memory chip, and when the voltage information is less than a set voltage threshold, or is less than the set voltage threshold and lasts for a second set time, determine that the power supply is interrupted and generate the trigger signal; and / or, The erase repair control unit is used for controlling the clearing of the first state mark information in the mark information storage after performing the erase repair operation.

11. The erasing operation control system according to claim 2, characterized in that: The tag information storage is implemented by a setting flash memory array, and the setting flash memory array is arranged at a setting position away from a reference array in the NOR type flash memory chip; and / or, The setting flash memory array and the reference array share the same read-write circuit; and / or, The flash memory array and the reference array are set not to share bit lines; and / or, The flash memory array and the reference array are set to be in different P potential wells; and / or, The setting flash memory array independently configures the corresponding data selector; and / or, The data selector comprises a multiplexer; and / or, The state reading unit is a reading circuit of a setting register in the NOR flash memory chip.

12. A method for controlling the erase operation of a NOR flash memory chip, characterized in that: The erasing operation control method is implemented by using the erasing operation control system according to any one of claims 1 to 11, and the erasing operation control method comprises: Before the NOR flash memory chip is powered off or restarted due to power interference or abnormal power failure that causes erasure interruption during an erasure operation, the first state flag information stored in the non-volatile flag information memory is set to a state indicating that the erasure operation is abnormally interrupted; After power-on startup, acquiring the stored first state mark information, and controlling the use of a preset erase and repair strategy to perform erase and repair according to the first state mark information; The erase operation control method further includes: Monitoring the power state of the NOR flash memory chip during the erasing operation, and generating a trigger signal when power interference or abnormal power failure causing the erasing interruption is detected; The first state flag information stored in the non-volatile flag information memory is set to a state indicating that an abnormal interruption of an erase operation occurs based on the trigger signal; The erase operation control method further includes: The power state of the NOR flash memory chip during the erase and repair operation is monitored, and when a power disturbance or abnormal power failure causing the interruption of the erase is detected, the trigger signal is generated again.

13. The method for controlling the erasing operation of a NOR flash memory chip according to claim 12, wherein: The erase operation control system also includes a block erase state marking module; The block erase status mark module includes a plurality of erase operation completion mark storage units corresponding to each physical block of the NOR flash memory chip one by one; The erasing operation control system is used to control the erasing operation completion mark storage unit to perform an erasing operation together with the corresponding physical block; The erase operation control method further includes: After the physical block corresponding to the erase operation completion mark storage unit completes the erase operation, performing a write operation on the erase operation completion mark storage unit; When the first status mark information is a state indicating that an erase operation is abnormally interrupted, the block address of the physical block where the erase interruption occurs is confirmed based on whether the erase operation completion mark storage unit is written, and erase repair is performed on the physical block at the block address.

14. The method for controlling the erasing operation of a NOR flash memory chip according to claim 12, wherein: The step of controlling the use of a preset erasure repair strategy to perform erasure repair according to the first status mark information comprises: When the first state mark information is a state indicating that an erase operation is abnormally interrupted, obtaining bit line current information of the entire flash memory array in the NOR flash memory chip; When the bit line current information indicates the presence of a bit line leakage current, address information corresponding to a physical block or a physical sector where the bit line leakage current occurs is obtained, and the physical block or the physical sector corresponding to the address information is erased and repaired.

15. A NOR flash memory chip, characterized in that: The NOR flash memory chip includes the erase operation control system according to any one of claims 1-11.

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