Integrated packaging method and integrated packaging structure

Abstract

An integrated packaging method and an integrated packaging structure of the present disclosure relate to the field of semiconductors. The integrated packaging method includes forming a first integrated component and a second integrated component, providing a substrate, mounting a front-mounted chip on the substrate, and mounting a first flip-chip on a side of the front-mounted chip away from the substrate; a first conductive adhesive film is provided on a side of the first flip-chip away from the flip-chip pad; mounting a heat sink on the substrate; a second conductive adhesive film is provided on a side of the heat sink away from the substrate; flipping the second integrated component and mounting it to the first integrated component, so that the flip-chip pad in the first integrated component is electrically connected to the second conductive adhesive film in the second integrated component, and the flip-chip pad in the second integrated component is electrically connected to the second conductive adhesive film in the first integrated component, which can achieve the interconnection between adjacent chips, has a simple process, reliable electrical connection, and is beneficial to improving the packaging integration degree.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular, to an integrated packaging method and an integrated packaging structure. Background Art

[0002] In existing packaging structures, if it is necessary to achieve the interconnection of multiple chips or the interconnection of multiple packaging components, wire bonding or vertical interconnection through through-silicon via technology, or connection through the fabrication of RDL (redistribution layer) is usually adopted. The above processes are complex, and the wire bonding method is also likely to cause an increase in the module height, and the through-silicon via technology is likely to cause problems such as unstable electrical connection and poor conductivity. Summary of the Invention

[0003] The objectives of the present invention include, for example, providing an integrated packaging method and an integrated packaging structure, which can simplify the process steps and improve the packaging efficiency; at the same time, it can facilitate the electrical connection between chips or modules, the structure is more compact, the electrical connection is stable and reliable, which is conducive to realizing high-density packaging and improving the packaging quality.

[0004] The embodiments of the present invention can be implemented as follows:

[0005] In a first aspect, the present invention provides an integrated packaging method, including:

[0006] Providing a substrate;

[0007] Mounting a front-mounted chip on the substrate;

[0008] Mounting a first flip-chip on the side of the front-mounted chip away from the substrate; wherein, the first flip-chip includes a first surface and a second surface arranged opposite to each other, the first surface is provided with a flip-chip pad, the second surface is provided with a first conductive adhesive film, the first conductive adhesive film is electrically connected to at least two of the front-mounted chips, and the flip-chip pad is located on the side of the first flip-chip away from the front-mounted chip;

[0009] Mounting a heat sink on the substrate; wherein, the heat sink is spaced from the front-mounted chip, and a second conductive adhesive film is provided on the side of the heat sink away from the substrate to form at least two integrated components, and the two integrated components include a first integrated component and a second integrated component;

[0010] Flipping the second integrated component and mounting it on the first integrated component, so that the flip-chip pad in the first integrated component is electrically connected to the second conductive adhesive film in the second integrated component, and the flip-chip pad in the second integrated component is electrically connected to the second conductive adhesive film in the first integrated component.

[0011] In an alternative embodiment, a first solder joint is provided on the substrate, and a front-side pad is provided on the front-side chip. The step of mounting the front-side chip on the substrate includes:

[0012] Electrically connecting the first solder joint to the front-side pad.

[0013] In an alternative embodiment, the step of electrically connecting the first solder joint to the front-side pad includes:

[0014] Bonding a wire between the first solder joint and the front-side pad.

[0015] In an alternative embodiment, after the step of mounting the front-side chip on the substrate, the integrated packaging method further includes:

[0016] Mounting a second flip-chip on the substrate; wherein, the substrate is provided with a second solder joint, and the second flip-chip is attached to the second solder joint and electrically connected to the second solder joint.

[0017] In an alternative embodiment, the step of mounting the second flip-chip on the substrate includes:

[0018] The second flip-chip is spaced apart from the front-side chip, a gap is formed between the second flip-chip and the front-side chip, or a gap is formed between the second flip-chip and the heat sink, and the gap is filled with a protective adhesive.

[0019] In an alternative embodiment, the step of mounting a first flip-chip on the side of the front-side chip away from the substrate includes:

[0020] The first flip-chip is attached to two adjacent front-side chips, and the flip-chip pad is located on the side away from the front-side chip.

[0021] In an alternative embodiment, the integrated packaging method further includes:

[0022] Mounting a separation block on the substrate, and a conductive colloid is provided between the separation block and the substrate;

[0023] The step of flipping the second integrated component and attaching it to the first integrated component further includes:

[0024] Heating the substrate in the first integrated component and the substrate in the second integrated component to separate the conductive colloid from the separation block, removing the separation block, and melting the conductive colloid in the first integrated component and the conductive colloid in the second integrated component together to electrically connect the first integrated component and the second integrated component.

[0025] In an alternative embodiment, the step of mounting the separation block on the substrate includes:

[0026] The separation block is mounted on the wire bonding structure between the direct chip and the substrate.

[0027] In a second aspect, the present invention provides an integrated package structure, comprising:

[0028] At least two integrated components;

[0029] Each of the integrated components includes a substrate, on which a heat dissipation block and a plurality of direct chips are provided. On a side of the direct chip away from the substrate, a first flip chip is provided. On a first surface of the first flip chip, a flip chip pad is provided. On a second surface of the first flip chip away from the flip chip pad, a first conductive adhesive film is provided; the first conductive adhesive film is used for electrically connecting the plurality of direct chips; on a side of the heat dissipation block away from the substrate, a second conductive adhesive film is provided;

[0030] The two integrated components include a first integrated component and a second integrated component; the second integrated component is connected to the first integrated component so that the flip chip pad in the first integrated component is electrically connected to the second conductive adhesive film in the second integrated component, and the flip chip pad in the second integrated component is electrically connected to the second conductive adhesive film in the first integrated component.

[0031] In an alternative embodiment, a first solder joint is provided on the substrate; a direct chip pad is provided on the direct chip, and the first solder joint is electrically connected to the direct chip pad.

[0032] In an alternative embodiment, the first solder joint and the direct chip pad are connected by wire bonding.

[0033] In an alternative embodiment, a second flip chip is further included; a second solder joint is provided on the substrate, and the second flip chip is disposed on the second solder joint and is electrically connected to the second solder joint.

[0034] In an alternative embodiment, the second flip chip and the direct chip are spaced apart, a gap is formed between the second flip chip and the direct chip, or a gap is formed between the second flip chip and the heat dissipation block, and the gap is filled with a protective adhesive.

[0035] In an alternative embodiment, the width of the gap is at least greater than twice the particle size of the colloid of the protective adhesive.

[0036] In an alternative embodiment, the heat dissipation block is disposed between the two second flip chips.

[0037] In an alternative embodiment, the first flip chip is disposed on two adjacent front-mounted chips, and the flip chip pads are located on a side away from the front-mounted chips.

[0038] In an alternative embodiment, it further includes a conductive colloid disposed on the substrate; the conductive colloid in the first integrated component is connected to the conductive colloid in the second integrated component.

[0039] In an alternative embodiment, the conductive colloid covers the wire bonding structure between the front-mounted chip and the substrate.

[0040] The beneficial effects of the embodiments of the present invention include, for example:

[0041] The integrated packaging method and integrated packaging structure provided by the embodiments of the present invention use the same process to fabricate the first integrated component and the second integrated component. The first conductive adhesive film on the back of the first flip chip can achieve electrical interconnection of multiple front-mounted chips; then the first integrated component is mounted on the second integrated component, so that the flip chip pads in the first integrated component are embedded in the second conductive adhesive film in the second integrated component, realizing electrical interconnection of multiple first flip chips in the first integrated component. Similarly, the flip chip pads in the second integrated component are embedded in the second conductive adhesive film in the first integrated component, realizing electrical interconnection of multiple first flip chips in the second integrated component. The electrical connection between chips is more stable and reliable, the structure is more compact, the process is simpler, which is conducive to realizing high-density integration and improving the packaging efficiency and quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0043] Figure 1 It is a schematic structural diagram of the substrate provided by the integrated packaging method of the embodiments of the present invention;

[0044] Figure 2 It is a schematic structural diagram of mounting a front-mounted chip on the substrate in the integrated packaging method of the embodiments of the present invention;

[0045] Figure 3 It is a schematic structural diagram of mounting a heat sink on the substrate in the integrated packaging method of the embodiments of the present invention;

[0046] Figure 4 It is a schematic structural diagram of mounting a second flip chip on the substrate in the integrated packaging method of the embodiments of the present invention;

[0047] Figure 5 For Figure 4 Partial enlarged schematic diagram at position A in

[0048] Figure 6 Schematic diagram of mounting the first flip chip on the substrate in the integrated packaging method provided by the embodiment of the present invention;

[0049] Figure 7 Schematic diagram of mounting two integrated components in the integrated packaging method provided by the embodiment of the present invention;

[0050] Figure 8 Schematic diagram of ball planting after mounting two integrated components in the integrated packaging method provided by the embodiment of the present invention;

[0051] Figure 9 Schematic diagram of ball planting and cutting into single products in the integrated packaging method provided by the embodiment of the present invention;

[0052] Figure 10 Schematic diagram of mounting the separation block in the integrated packaging method provided by the embodiment of the present invention;

[0053] Figure 11 Schematic diagram of mounting two integrated components after mounting the separation block in the integrated packaging method provided by the embodiment of the present invention;

[0054] Figure 12 Schematic diagram of mounting two integrated components and removing the separation block in the integrated packaging method provided by the embodiment of the present invention;

[0055] Figure 13 Another schematic diagram of the integrated packaging structure provided by the embodiment of the present invention;

[0056] Figure 14 Schematic diagram of the split structure in which the first conductive adhesive film and the second conductive adhesive film are respectively connected to the chip in the integrated packaging structure provided by the embodiment of the present invention.

[0057] Icon: 100 - integrated packaging structure; 200 - first integrated component; 210 - substrate; 211 - third surface; 213 - fourth surface; 215 - first solder joint; 217 - second solder joint; 219 - third solder joint; 220 - front-mounted chip; 221 - front-mounted pad; 223 - structural adhesive; 225 - metal wire; 230 - first flip chip; 231 - flip-chip pad; 233 - first conductive adhesive film; 240 - heat sink; 241 - second conductive adhesive film; 250 - second flip chip; 251 - protective adhesive; 260 - metal ball; 270 - separation block; 271 - conductive colloid; 235 - pad one; 236 - pad two; 237 - pad three; 238 - pad four; 300 - second integrated component. Detailed implementation manners

[0058] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Components of the embodiments of the present invention usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0059] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0060] It should be noted that like reference numerals and letters denote like items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0061] In the description of the present invention, it should be noted that if terms such as "upper", "lower", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the present invention is usually placed during use, it is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation of the present invention.

[0062] In addition, terms such as "first", "second", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0063] It should be noted that, without conflict, the features in the embodiments of the present invention can be combined with each other.

[0064] With the rapid development of the semiconductor industry, the chiplet technology is a new design method that packages small chips with different functions together to form a heterogeneous integrated chip packaging structure. As the input and output density of chips is getting higher and higher and the number integrated in a single package has increased significantly, various 2.5D and 3D packaging technologies adopt a multi-chip packaging scheme to improve the packaging integration by connecting the adjacent chip pad lines within a single package.

[0065] Currently, a vertical interconnect structure is usually fabricated on a silicon interposer using the through-silicon via (TSV) technology. A flip-chip is mounted on the surface of the interconnect structure or adjacent chips are interconnected directly using the TSV technology. This method has complex processes and structures. Moreover, the silicon via technology is prone to causing silicon plate fragmentation or poor electrical conductivity, and the overall size of this structure is relatively large.

[0066] To overcome at least one defect in the prior art, the present application provides an integrated packaging method and an integrated packaging structure 100, which are applicable to high-density integrated packaging, improve the integration degree of chips, and are conducive to simplifying the process, reducing the size, and facilitating the electrical connection of adjacent chips.

[0067] First Embodiment

[0068] This embodiment provides an integrated packaging method, including:

[0069] Step S10: Fabricate a first integrated component 200;

[0070] Step S20: Fabricate a second integrated component 300;

[0071] Step S30: Flip the second integrated component 300 and mount the second integrated component 300 on the first integrated component 200.

[0072] Among them, the processes of step S10 and step S20 are exactly the same. The specific method of step S10 can be combined with Figures 1 to 9 , including step S100 and step S200.

[0073] Step S100: Provide a substrate 210. As Figure 1 , the substrate 210 includes a third surface 211 and a fourth surface 213 arranged oppositely. The third surface 211 is provided with a first solder joint 215 and a second solder joint 217, the fourth surface 213 is provided with a third solder joint 219, and an intermediate circuit is arranged in the substrate 210. The intermediate circuit includes but is not limited to a redistribution layer (RDL) or other circuits, and the intermediate circuit is used to realize the electrical connection between the first solder joint 215 and the third solder joint 219, and can also realize the electrical connection between the second solder joint 217 and the third solder joint 219. The first solder joint 215 and the second solder joint 217 can be electrically connected or not according to actual situations, and the substrate 210 can be fabricated in a board factory. The substrate 210 includes but is not limited to a substrate, silicon, ceramics, etc., and no specific limitation is made here.

[0074] Combined with Figures 2 to 5 , step S200: Mount a front-mounted chip 220, a first flip-chip 230, and a heat sink 240 on the substrate 210; among which, it includes:

[0075] Mount the front-mounted chip 220 on the substrate 210;

[0076] Mount a first flip chip 230 on the side of the surface mount chip 220 away from the substrate 210; the first flip chip 230 includes a first surface and a second surface disposed opposite to each other, the first surface is provided with a flip chip pad 231, the second surface is provided with a first conductive adhesive film 233, the first conductive adhesive film 233 is electrically connected to at least two surface mount chips 220, and the flip chip pad 231 is located on the side of the first flip chip 230 away from the surface mount chip 220;

[0077] Mount a heat sink 240 on the substrate 210; wherein, the heat sink 240 is disposed at an interval from the surface mount chip 220, and a second conductive adhesive film 241 is provided on the side of the heat sink 240 away from the substrate 210 to form at least two integrated components. For the convenience of description, the two integrated components include a first integrated component 200 and a second integrated component 300; the manufacturing methods and structures of the first integrated component 200 and the second integrated component 300 are similar.

[0078] Optionally, after the step of mounting the surface mount chip 220 on the substrate 210, or after the step of mounting the heat sink 240 on the substrate 210, the integrated packaging method further includes mounting a second flip chip 250 on the substrate 210; making the structure more compact and stable, which is beneficial to integrating more chips or devices or electronic modules. Specifically, the implementation process of step S200 is as follows:

[0079] Step S200 includes step S210, step S220, step S230 and step S240.

[0080] Such as Figure 2 , step S210: Mount the surface mount chip 220 on the substrate 210. The surface mount chip 220 is provided with a surface mount pad 221, and the surface mount pad 221 is mounted upward, that is, the surface mount pad 221 is located on the side of the surface mount chip 220 away from the substrate 210. Optionally, the surface mount chip 220 is bonded and fixed to the substrate 210, that is, a structural adhesive 223 is provided between the side of the surface mount chip 220 away from the surface mount pad 221 and the substrate 210, and the bonding and fixing is realized by baking and curing the structural adhesive 223. The structural adhesive 223 can be conductive or non-conductive, which is not specifically limited here. A plurality of surface mount chips 220 are spaced on the substrate 210. Optionally, the first solder joint 215 is used to be electrically connected to the outermost surface mount chip 220 by wire bonding, and a metal wire 225 is provided between the surface mount chip 220 and the substrate 210.

[0081] Such as Figure 3, Step S220: Attach a heat sink 240 to the third surface 211 of the substrate 210. The attachment method of the heat sink 240 is the same as that of the flip-chip 220, and it can also be fixed with a structural adhesive 223, which is not specifically limited here. It is easy to understand that the heat sink 240 and the flip-chip 220 are arranged at intervals, and the attachment of the flip-chip 220 and the heat sink 240 avoids the first solder joints 215 and the second solder joints 217. Among them, the second solder joints 217 are arranged inside the multiple first solder joints 215 that enclose the attachment area, and the first solder joints 215 are used for wire bonding electrical connection with the outermost flip-chip 220.

[0082] Optionally, a second conductive adhesive film 241 is attached to the side of the heat sink 240 away from the substrate 210. Corresponding conductive traces are provided in the second conductive adhesive film 241, and the conductive traces are formed by laser cutting the conductive adhesive film and are designed according to the interconnection circuit requirements of the chip components. The conductive adhesive film can be set on the heat sink 240 first, and then the heat sink 240 is attached to the substrate 210. The heat sink 240 can be made of high thermal conductivity heat dissipation materials such as ceramics or metals, which not only play a heat dissipation role but also a supporting and buffering role. The second conductive adhesive film 241 on the heat sink 240 plays a role in electrically connecting adjacent chips. The heat sink 240 is symmetrically arranged in the whole structure, which is beneficial to offsetting stress and preventing warping.

[0083] Such as Figure 4 and Figure 5, Step S230: Attach the second flip chip 250 to the third surface 211 of the substrate 210. The second flip chip 250 is disposed between two adjacent front-mounted chips 220, or between an adjacent front-mounted chip 220 and the heat sink 240. The second flip chip 250 is disposed on the second solder joint 217 and is electrically connected to the second solder joint 217. The design of the second flip chip 250 greatly improves the chip integration. Optionally, the height of the second flip chip 250, the height of the front-mounted chip 220, and the height of the heat sink 240 are equal. A gap is formed between the second flip chip 250 and the front-mounted chip 220, and a gap is formed between the second flip chip 250 and the heat sink 240. The gap is filled with a protective adhesive 251. The protective adhesive 251 fills the gap and the bottom of the second flip chip 250 to protect the pads at the bottom of the second flip chip 250 and ensure stable and reliable electrical connection between the second flip chip 250 and the substrate 210. The protective adhesive 251 is an insulating adhesive. After the protective adhesive 251 is filled and cured, the height of the protective adhesive 251 is the same as the height of the second flip chip 250, that is, the surface of the protective adhesive 251 is flush with the surface of the second flip chip 250. The width of the gap needs to be at least greater than twice the particle size of the colloid of the protective adhesive 251. For example, if the particle size of the colloid of the protective adhesive 251 is 30 microns, the gap width needs to be greater than 60 microns to ensure that the protective adhesive 251 can better fill the gap and prevent other impurities from falling into the gap, especially to avoid the inflow of other conductive media into the gap. It should be noted that Step S230 is an optional step, which can be set according to actual needs to improve the integration of chip packaging.

[0084] Such as Figure 6 , Step S240: Attach the first flip chip 230 to the side of the front-mounted chip 220 away from the substrate 210. The first flip chip 230 is attached in a front-mounted manner. The first flip chip 230 is provided with a flip chip pad 231, and the flip chip pad 231 is arranged upward, that is, the flip chip pad 231 is located on the side of the first flip chip 230 away from the substrate 210. A first conductive adhesive film 233 is provided on the side of the first flip chip 230 away from the flip chip pad 231. The first flip chip 230 is attached to two adjacent front-mounted chips 220. It can be understood that conductive bumps are provided on the flip chip pad 231. In this way, after the first flip chip 230 is attached, the first conductive adhesive film 233 is located between the front-mounted chip 220 and the first flip chip 230, and the first conductive adhesive film 233 can realize the electrical connection of the front-mounted pads 221 on two adjacent front-mounted chips 220, that is, realize the electrical connection of two front-mounted chips 220. The conductive bumps can be embedded in the second conductive adhesive film 241 of another integrated component, and the second conductive adhesive film 241 plays a role in protecting the flip chip pad 231 and the conductive bumps. Similarly, the first conductive adhesive film 233 can also protect the front-mounted pads 221 on the front-mounted chip 220 and the conductive bumps on the front-mounted pads 221.

[0085] It is easy to understand that the first conductive adhesive film 233 can be pre - disposed on the first flip - chip 230, and then the first flip - chip 230 is mounted on the front - mounted chip 220. The combination method of the first conductive adhesive film 233 and the first flip - chip 230 can be: first grind the first flip - chip 230 to a preset thickness, attach a conductive adhesive film to the back of the first flip - chip 230, and use a laser cutting method to form corresponding conductive traces on the conductive adhesive film. The conductive traces are designed according to the interconnection requirements of the front - mounted chip 220. Similarly, the setting method of the second conductive adhesive film 241 on the heat sink 240 is similar to that of the first conductive adhesive film 233, and will not be elaborated here. The second conductive adhesive film 241 can be first disposed on the heat sink 240, and then the heat sink 240 and the second conductive adhesive film 241 are integrally mounted on the substrate 210, or the heat sink 240 can be first mounted on the substrate 210, and then the second conductive adhesive film 241 is disposed on the heat sink 240.

[0086] It should be noted that the sequence of steps S210, S220, and S230 can be flexibly adjusted, or they can be carried out simultaneously, and no specific limitation is made here. The manufacturing methods and material properties of the first conductive adhesive film 233 and the second conductive adhesive film 241 are similar. They can be formed by mixing polyester (PET), high - molecular epoxy resin, conductive particles, and adhesives, etc., which can achieve a conductive effect and have thermoplastic characteristics. After heating, the first conductive adhesive film 233 and the second conductive adhesive film 241 are softened, which can play a buffering role and better protect the pads and conductive bumps on the chip. Among them, the conductive particles include but are not limited to nano - silver or nano - copper.

[0087] In this way, the first integrated component 200 is completed. By using the above - mentioned method to form at least two integrated components, after manufacturing the first integrated component 200, steps S100 and S200 can be repeated to form the second integrated component 300. The manufacturing method of the second integrated component 300 is the same as that of the first integrated component 200. In actual processes, multiple integrated components are manufactured at one time and then mounted in pairs. In this embodiment, for the convenience of description, the integrated components are divided into the first and the second, and the structures of the first integrated component 200 and the second integrated component 300 are exactly the same.

[0088] Combined with Figure 7, in step S30, when mounting, one of the components needs to be flipped 180 degrees before mounting. During the mounting process, the first integrated component 200 and the second integrated component 300 are heated respectively to soften the first conductive adhesive film 233 and the second conductive adhesive film 241, so as to better cover the chip pads (including the front-mounted pads 221 and the flip-chip pads 231), achieving the purpose of electrical connection between the pads of the chips. Optionally, the two integrated components are heated simultaneously. One integrated component can be heated through the mounting platform, and the other can be heated through the mounting head. There is no specific limitation here. The first conductive adhesive film 233 and the second conductive adhesive film 241 in the two integrated components are softened by heat simultaneously and cover the chip pads, achieving electrical connection between the chips. The chip pads are embedded in the conductive adhesive film layer. The first conductive adhesive film 233 plays a protective and buffering role for the front-mounted pads 221, and the second conductive adhesive film 241 plays a protective and buffering role for the flip-chip pads 231.

[0089] It can be understood that in the prior art, the chip pads are electrically connected by welding, and the generated stress is relatively large. Especially after the flip-chip is welded, due to excessive stress, it is extremely easy to appear phenomena such as fracture, resulting in unstable electrical connection. In this embodiment, the chip pads are embedded in the first conductive adhesive film 233 or the second conductive adhesive film 241. After the conductive adhesive film is softened, it can better protect the chip pads, prevent the pads from being invisibly cracked or fractured, and the electrical connection is more stable and reliable. At the same time, it can also make the electrical connection line short, shorten the signal transmission path, reduce the wiring lines on the substrate 210, reduce the signal transmission delay and loss, reduce the power consumption and the package volume, and realize the multi-functional, high-performance, and high-density chip system-level packaging.

[0090] Combined with Figure 8 and Figure 9 , after the first integrated component 200 and the second integrated component 300 are mounted, plastic encapsulation protection is still required. After plastic encapsulation, ball implantation is performed on the third pads on at least one of the two substrates 210 to form the metal balls 260, and then the product is cut into single packaged bodies. It can be understood that if the third solder joints 219 of one of the substrates 210 are used for ball implantation of the metal balls 260, the third solder joints 219 on the other substrate 210 can be used for stacking other chips or components or other electronic modules. There is no specific limitation here.

[0091] Since the structures of the two components are exactly the same, the symmetry of the structure is beneficial to eliminating the stress during the encapsulation process, alleviating the stress warping problem, and improving the encapsulation quality. It is easy to understand that in the integrated packaging structure 100 after mounting, the structures of the front-mounted chip 220, the flip-chip, and the heat sink 240 are respectively centrosymmetrically distributed, playing a role in stress balance and preventing warping.

[0092] Second Embodiment

[0093] Combined withFigures 10 to 13 , based on the first embodiment, by mounting the separation block 270, a conductive colloid 271 is provided on the separation block 270, so that electrical connection of two integrated components is achieved after mounting. For example, electrical interconnection of two substrates 210 can be realized according to actual needs, or interconnection between chips in two integrated components. Specifically, the integrated packaging method further includes step S300, which can be after S240 or flexibly adjusted according to actual situations.

[0094] Step S300: Mount the separation block 270 on the substrate 210, and a conductive colloid 271 is provided between the separation block 270 and the substrate 210; it can be understood that the conductive colloid 271 can be pre-mounted on the separation block 270 and then bonded to the substrate 210 through the conductive colloid 271; alternatively, the conductive colloid 271 can also be provided on the substrate 210 and then the separation block 270 is arranged on the substrate 210. In this embodiment, first, the conductive colloid 271 is provided on the separation block 270, and then the separation block 270 and the conductive colloid 271 are integrally mounted on the substrate 210. Among them, the method of providing the conductive colloid 271 on the separation block 270 is similar to the method of providing the second conductive film 241 on the heat dissipation block 240. The separation block 270 can be a metal block, an insulating block or the heat dissipation block 240, etc., and the materials include but are not limited to wood, ceramics, fibers, glass, silicon or other materials. It is easy to understand that conductive traces are also provided on the conductive colloid 271, which is similar to the preparation methods of the first conductive film 233 and the second conductive film 241, and the circuit traces of the conductive traces are set according to actual electrical connection needs.

[0095] Optionally, in step S30, removing the separation block 270 is further included. During the mounting process, the first integrated component 200 and the second integrated component 300 are heated respectively, and both the separation block 270 and the conductive colloid 271 in the two substrates 210 are heated. After the conductive colloid 271 is heated, since the conductive colloid 271 has thermoplasticity, the conductive colloid 271 is separated from the separation block 270, and the separation block 270 can be taken out from the substrate 210; after the separation blocks 270 on the two substrates 210 are removed, the conductive colloids 271 on the two substrates 210 are melted together to realize electrical interconnection of the two substrates 210, that is, the conductive colloid 271 can realize electrical connection between the first integrated component 200 and the second integrated component 300.

[0096] Furthermore, the separation block 270 is mounted on the wire bonding structure of the flip-chip 220 and the substrate 210. The melted conductive colloid 271 together can wrap the wire bonding structure. On the one hand, it can protect the wire bonding structure, and on the other hand, due to the conductivity of the conductive colloid 271, electrical connection with the metal wire 225 can be realized, that is, the conductive colloid 271 is electrically connected to the first solder joints 215 on the two substrates 210 respectively to realize electrical interconnection of the two substrates 210, and the electrical connection is more stable and reliable.

[0097] It should be noted that the separation block 270 and the conductive colloid 271 can be selected and set according to actual needs. If not set, that is, the two substrates 210 are not electrically connected. In this way, metal balls 260 are implanted on the third solder joints 219 of one of the substrates 210 and welded to the circuit board through the metal balls 260, which can play a role in improving the performance of the circuit board; electronic devices or components can be continuously mounted on the third solder joints 219 of the other substrate 210 to improve the performance of the electronic devices. Encapsulating the first integrated component 200 and the second integrated component 300 with the same structural performance in the same structure can reduce the encapsulation volume and achieve the purpose of functional partitioning on both sides. If the conductive colloid 271 is set, the electrical connection between the two substrates 210 can be realized, which can improve the integration degree of the electronic devices and is beneficial to the packaging of high-performance and multi-functional chips.

[0098] Optionally, in some embodiments, the separation block 270 and the conductive colloid 271 can also be set only in the first integrated component 200 or the second integrated component 300, that is, it can be set in any one of the two, and similar electrical connection effects can also be achieved, saving materials, reducing costs, and reducing process steps.

[0099] Optionally, in other embodiments, if the separation block 270 and the conductive colloid 271 are set, the electrical connection between the two substrates 210 can be realized by covering the first solder joints 215 on the two substrates 210 with the conductive colloid 271 respectively. If the conductive colloid 271 covers the first solder joints 215 on the two substrates 210 and the direct bonding pads 221 connected to the two first solder joints 215, the wire bonding structure between the first solder joints 215 and the direct bonding pads 221 can be omitted. In this way, the electrical connection between the two substrates 210 can be realized, and the electrical connection between the direct bonding chip 220 and the substrate 210 can also be realized. The process is simple, the operation is convenient, the packaging efficiency is high, the structure is reliable, and the packaging quality is good.

[0100] Other parts not mentioned in this embodiment are the same as those described in the first embodiment and will not be elaborated here.

[0101] It should be noted that the number and stacking layers of the chips (not limited to the direct bonding chips 220 and the flip chips) and the heat dissipation blocks 240 mounted on the substrate 210 can be flexibly set according to the actual situation and are not limited to the illustrated situation.

[0102] Third Embodiment

[0103] Combined with Figure 9, an integrated packaging structure 100 provided by an embodiment of the present invention is obtained by using the foregoing integrated packaging method, and includes at least two integrated components. The two integrated components include a first integrated component 200 and a second integrated component 300, and the structures of the first integrated component 200 and the second integrated component 300 are the same. Each integrated component includes a substrate 210, on which a heat dissipation block 240 and a plurality of front-mounted chips 220 are provided. On the side of the front-mounted chip 220 away from the substrate 210, a first flip-chip 230 is provided. On the first surface of the first flip-chip 230, a flip-chip pad 231 is provided, and on the second surface of the first flip-chip 230 away from the flip-chip pad 231, a first conductive adhesive film 233 is provided; the first conductive adhesive film 233 is used for electrically connecting the plurality of front-mounted chips 220; on the side of the heat dissipation block 240 away from the substrate 210, a second conductive adhesive film 241 is provided;

[0104] The two integrated components include a first integrated component 200 and a second integrated component 300; the second integrated component 300 is connected to the first integrated component 200 so that the flip-chip pad 231 in the first integrated component 200 is electrically connected to the second conductive adhesive film 241 in the second integrated component 300, and the flip-chip pad 231 in the second integrated component 300 is electrically connected to the second conductive adhesive film 241 in the first integrated component 200. In this structure, two adjacent front-mounted chips 220 in the first integrated component 200 can be electrically interconnected through the second conductive adhesive film 241 in the second integrated component 300, and two adjacent front-mounted chips 220 in the second integrated component 300 can be electrically interconnected through the second conductive adhesive film 241 in the first integrated component 200. The structure is compact, the process is simple, the number of wiring layers on the substrate 210 and the number of wiring layers in the packaging structure are reduced, which is beneficial to shortening the length of the interconnecting wire, reducing the transmission path, making the electrical connection more reliable, reducing signal transmission delay and loss, reducing power consumption and packaging volume, realizing a multi-functional and high-performance chip system-level packaging, and improving the packaging quality and efficiency. In addition, after the two integrated components are mounted, the flip-chip pad 231 can be embedded in the second conductive adhesive film 241, and the second conductive adhesive film 241 plays a protective role on the flip-chip pad 231, solving the problem of the fracture of the bump on the pad caused by the stress generated during the soldering of the pad in the prior art, and the electrical connection performance is more stable.

[0105] It can be understood that after the two integrated components are mounted, the flip-chip pads 231 of two adjacent first flip-chips 230 are simultaneously embedded in a second conductive adhesive film 241. In this way, the second conductive adhesive film 241 can realize the electrical interconnection of the two first flip-chips 230. Combined with Figure 14, for example, a first flip chip 230 is provided with two flip pads 231. Two adjacent first flip chips 230 are provided with a total of four flip pads 231, and the four flip pads 231 are arranged in sequence from left to right, namely pad one 235, pad two 236, pad three 237, and pad four 238. Among them, pad one 235 and pad two 236 are provided on the same first flip chip 230, and pad three 237 and pad four 238 are provided on another first flip chip 230. Pad one 235 is electrically connected to the direct mount pad 221 of a direct mount chip 220, pad two 236 is embedded in the second conductive adhesive film 241, pad three 237 is embedded in the second conductive adhesive film 241, and pad four 238 is electrically connected to the direct mount pad 221 on another direct mount chip 220. In this way, the second conductive adhesive film 241 realizes the interconnection of the two first flip chips 230. At the same time, the first flip chip 230 on one substrate 210 and the direct mount chip 220 on another substrate 210 are electrically connected.

[0106] The substrate 210 is provided with a first solder joint 215; the direct mount chip 220 is provided with a direct mount pad 221, and the first solder joint 215 is electrically connected to the direct mount pad 221. In this embodiment, the first solder joint 215 and the direct mount pad 221 are connected by wire bonding 225.

[0107] Optionally, a second flip chip 250 is further provided between two adjacent direct mount chips 220, or between the direct mount chip 220 and the heat sink 240. A gap is formed between the second flip chip 250 and the direct mount chip 220, or a gap is formed between the second flip chip 250 and the heat sink 240. The gap is filled with a protective adhesive 251; the width of the gap is at least greater than twice the particle size of the colloid of the protective adhesive 251 to ensure that the gap is filled perfectly and prevent other particles or foreign objects from entering the gap, especially to avoid conductive substances from entering the gap, because once the conductive substances enter, they are likely to be electrically connected to the bottom pads of the second flip chip 250, thus causing phenomena such as short circuits.

[0108] In this embodiment, the heat sink 240 is provided between two second flip chips 250, which plays a role in heat dissipation. At the same time, it plays a role in structural support and improves the structural strength. In the entire integrated package structure 100, the heat sink 240 is centrally symmetrically arranged, which is beneficial to balancing stress and alleviating warping.

[0109] The first flip chip 230 is attached to two adjacent front-mounted chips 220, and the flip chip pad 231 is located on the side away from the front-mounted chips 220. The first flip chip 230 adopts a forward mounting method, that is, the flip chip pad 231 is mounted upward. In this way, the first conductive adhesive film 233 on the back of the first flip chip 230 can be electrically connected to the two front-mounted chips 220 in the lower layer, and the flip chip pads 231 arranged upward can be electrically connected to the second conductive adhesive film 241 and the front-mounted chip pads 221 in the upper layer structure (another integrated component) respectively.

[0110] Combined Figure 13 , optionally, the integrated package structure 100 further includes a conductive colloid 271, which is disposed between the two substrates 210 and covers the first solder joints 215. In this way, electrical connection between the two substrates 210 can be achieved, improving the packaging integration. Further, the conductive colloid 271 covers the wire bonding structures of the first solder joints 215 and the front-mounted chip pads 221, playing a protective role for the wire bonding structures.

[0111] For other parts not mentioned in this embodiment, they are similar to those described in the first embodiment and the second embodiment, and will not be elaborated here.

[0112] In summary, the embodiments of the present invention provide an integrated packaging method and an integrated package structure 100, having the following beneficial effects:

[0113] The embodiments of the present invention provide an integrated packaging method and an integrated package structure 100, which can facilitate the electrical connection between adjacent chips, reduce the transmission path and the wiring on the substrate 210, effectively shorten the length of the interconnection line, reduce signal transmission delay and loss, reduce power consumption and packaging volume, and achieve a multi-functional and high-performance chip system-level packaging. The packaging process is simple, the wire bonding interconnection structure is reduced, the packaging structure is compact, which is beneficial to reducing the packaging volume and improving the integration of the chip packaging. By setting the heat dissipation block 240, the heat dissipation performance is improved and the structural strength is enhanced. By setting the separation block 270 and the conductive colloid 271, the packaging method is simple and feasible, with high efficiency, and is convenient for realizing the interconnection of the two substrates 210.

[0114] The integrated package structure 100 adopts two completely identical integrated components, and by flipping and mounting one of the integrated components, the overall structure is centrosymmetric, which is beneficial to balancing the stress generated during the packaging process, alleviating structural warping or deformation, and improving the packaging accuracy and quality.

[0115] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. An integrated packaging method, characterized in that, Including: Providing a substrate; Mounting a flip-chip on the substrate; Mounting a first flip-chip on a side of the flip-chip away from the substrate; wherein, the first flip-chip includes a first surface and a second surface arranged opposite to each other, the first surface is provided with a flip-chip pad, the second surface is provided with a first conductive adhesive film, the first conductive adhesive film electrically connects at least two of the flip-chips, the flip-chip pad is located on a side of the first flip-chip away from the flip-chip; the flip-chip is provided with a flip-chip pad; conductive bumps are respectively arranged on the flip-chip pad and the flip-chip pad; the conductive bump on the flip-chip pad is embedded in the first conductive adhesive film; Mounting a heat sink on the substrate; wherein, the heat sink is arranged at an interval from the flip-chip, and a second conductive adhesive film is provided on a side of the heat sink away from the substrate to form an integrated component; obtaining at least two of the integrated components, and the two integrated components include a first integrated component and a second integrated component; Flipping the second integrated component and mounting it on the first integrated component, so that the flip-chip pad in the first integrated component is electrically connected to the second conductive adhesive film in the second integrated component, and the flip-chip pad in the second integrated component is electrically connected to the second conductive adhesive film in the first integrated component; the conductive bump on the flip-chip pad is embedded in the second conductive adhesive film.

2. The integrated packaging method according to claim 1, wherein A first solder joint is provided on the substrate, and a flip-chip pad is provided on the flip-chip. The step of mounting the flip-chip on the substrate includes: Electrically connecting the first solder joint to the flip-chip pad.

3. The integrated packaging method according to claim 2, wherein The step of electrically connecting the first solder joint to the flip-chip pad includes: Bonding a wire between the first solder joint and the flip-chip pad.

4. The integrated packaging method according to claim 1, wherein After the step of mounting the flip-chip on the substrate, the integrated packaging method further includes: Mounting a second flip-chip on the substrate; wherein, a second solder joint is provided on the substrate, and the second flip-chip is attached to the second solder joint and electrically connected to the second solder joint.

5. The integrated packaging method according to claim 4, wherein The step of mounting the second flip-chip on the substrate includes: The second flip-chip is arranged at an interval from the flip-chip, a gap is formed between the second flip-chip and the flip-chip, or a gap is formed between the second flip-chip and the heat sink, and the gap is filled with a protective glue.

6. The integrated packaging method according to claim 1, characterized in that, The step of mounting the first flip-chip on a side of the flip-chip away from the substrate includes: The first flip-chip is attached to two adjacent flip-chips, and the flip-chip pad is located on a side away from the flip-chip.

7. The integrated packaging method according to any one of claims 1 to 6, characterized in that The integrated packaging method further includes: Mounting a separation block on the substrate, and a conductive colloid is provided between the separation block and the substrate; In the step of flipping the second integrated component and mounting it on the first integrated component, it further includes: Heating the substrate in the first integrated component and the substrate in the second integrated component to separate the conductive colloid from the separation block, removing the separation block, and melting the conductive colloid in the first integrated component and the conductive colloid in the second integrated component together to electrically connect the first integrated component and the second integrated component.

8. The integrated packaging method according to claim 7, characterized in that The step of mounting the separation block on the substrate includes: The separation block is mounted on the wire bonding structure of the front-mounted chip and the substrate.

9. An integrated package structure, characterized in that, It includes: At least two integrated components; Each of the integrated components includes a substrate, on which a heat dissipation block and a plurality of front-mounted chips are provided. On the side of the front-mounted chip away from the substrate, a first flip-chip is provided. On the first surface of the first flip-chip, a flip-chip pad is provided. On the second surface of the first flip-chip away from the flip-chip pad, a first conductive adhesive film is provided; the first conductive adhesive film is used for electrically connecting the plurality of front-mounted chips; on the side of the heat dissipation block away from the substrate, a second conductive adhesive film is provided; on the front-mounted chip, a front-mounted pad is provided; conductive bumps are respectively provided on the front-mounted pad and the flip-chip pad; the conductive bump on the front-mounted pad is embedded in the first conductive adhesive film; The two integrated components include a first integrated component and a second integrated component; the second integrated component is connected to the first integrated component so that the flip-chip pad in the first integrated component is electrically connected to the second conductive adhesive film in the second integrated component, and the flip-chip pad in the second integrated component is electrically connected to the second conductive adhesive film in the first integrated component; the conductive bump on the flip-chip pad is embedded in the second conductive adhesive film.

10. The integrated packaging structure according to claim 9, wherein, A first solder joint is provided on the substrate; a front-mounted pad is provided on the front-mounted chip, and the first solder joint is electrically connected to the front-mounted pad.

11. The integrated package structure according to claim 10, wherein The first solder joint and the front-mounted pad are connected by wire bonding.

12. The integrated package structure according to claim 9, characterized in that, It further includes a second flip-chip; the substrate is provided with a second solder joint, and the second flip-chip is disposed on the second solder joint and is electrically connected to the second solder joint.

13. The integrated packaging structure according to claim 12, characterized in that, The second flip-chip and the front-mounted chip are spaced apart, a gap is formed between the second flip-chip and the front-mounted chip, or a gap is formed between the second flip-chip and the heat dissipation block, and the gap is filled with a protective adhesive.

14. The integrated packaging structure according to claim 13, wherein The width of the gap is at least greater than twice the particle size of the colloid of the protective adhesive.

15. The integrated package structure according to claim 12, wherein The heat dissipation block is disposed between the two second flip-chips.

16. The integrated package structure according to claim 9, wherein The first flip-chip is attached to two adjacent front-mounted chips, and the flip-chip pad is located on the side away from the front-mounted chip.

17. The integrated packaging structure according to any one of claims 9 to 16, characterized in that, It further includes a conductive colloid disposed on the substrate; the conductive colloid in the first integrated component and the conductive colloid in the second integrated component are connected.

18. The integrated packaging structure according to claim 17, wherein The conductive colloid covers the wire bonding structure of the front-mounted chip and the substrate.

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