A semiconductor test device and a method for preparing the same

Abstract

The present invention provides a semiconductor test device and a preparation method thereof, comprising: a substrate; a first metal wiring layer, located on the substrate, comprising an insulated interconnection metal line and a test metal line, wherein the test metal line is arranged around the interconnection metal line; a dielectric layer, covering the first metal wiring layer and the substrate, and having an air gap in the dielectric layer between the interconnection metal line and the test metal line; a second metal wiring layer, located on the dielectric layer, and electrically connected to the interconnection metal line through a plug penetrating the dielectric layer. When the plug has a sidewall fracture or protrusion, the dielectric layer between the air gap and the plug will produce cracks due to the stress between the film layers, and the cracks connect the plug and the air gap, causing the plug to be disconnected. The operator can determine whether the plug has a defect by measuring the resistance of the plug.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor testing device and a preparation method thereof. Background Art

[0002] As integrated circuits develop towards ultra-large-scale integrated circuits, the circuit density inside integrated circuits is increasing, and the number of components contained is also increasing. This development trend has led to the use of two or more metal interconnect layers inside integrated circuits. The metal interconnect layers are electrically connected through plugs, but during the production process, it was found that some plugs would have sidewall protrusions or fractures due to factors such as stress between film layers. The defects of the plugs will result in the inability to make effective electrical connections between the metal interconnect layers, thereby affecting the yield of semiconductor test devices.

[0003] The existing technology uses WAT (Wafer acceptance test) to measure the electrical properties of the wafer after the process flow to check whether the various performance of the wafer meets the standards, but WAT technology cannot detect defects in the plug, so a semiconductor test device that can directly measure the plug performance is needed. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor test device and a method for preparing the same, which can determine whether a plug has defects.

[0005] In order to achieve the above object, the present invention provides a semiconductor testing device, comprising:

[0006] substrate;

[0007] A first metal wiring layer, located on the substrate, comprising insulated interconnection metal lines and test metal lines, wherein the test metal lines are arranged around the interconnection metal lines;

[0008] a dielectric layer covering the first metal wiring layer and the substrate, wherein an air gap is provided in the dielectric layer between the interconnect metal line and the test metal line;

[0009] The second metal wiring layer is located on the dielectric layer and is electrically connected to the interconnection metal line via a plug penetrating the dielectric layer.

[0010] Optionally, the top of the air gap is higher than the top of the first metal wiring layer.

[0011] Optionally, the plug is located at one end of the interconnect metal line.

[0012] Optionally, the plugs are located at two ends of the interconnect metal line.

[0013] Optionally, the plug is located in a region between two ends of the interconnect metal line.

[0014] Optionally, the test metal line is U-shaped, and one end of the interconnection metal line corresponding to the plug is located in the U-shaped opening of the test metal line.

[0015] Optionally, the test metal lines form a closed pattern, and the interconnection metal lines are located inside the closed pattern.

[0016] Optionally, the test metal line is arranged in parallel with the interconnection metal line.

[0017] Optionally, the distance between the test metal line and the interconnection metal line is 0.15 μm to 0.7 μm, and / or the height of the interconnection metal line and the test metal line is 0.25 μm to 0.7 μm. Based on the same inventive concept, the present invention also provides a method for preparing a semiconductor test device, comprising:

[0018] providing a substrate;

[0019] forming a first metal wiring layer on the substrate, comprising an insulated interconnection metal line and a test metal line, wherein the test metal line is arranged around the interconnection metal line;

[0020] forming a dielectric layer on the first metal wiring layer, wherein the dielectric layer covers the first metal wiring layer and the substrate, and an air gap is provided in the dielectric layer between the interconnection metal line and the test metal line;

[0021] A second metal wiring layer is formed on the dielectric layer, and the second metal wiring layer is electrically connected to the interconnection metal line through a plug penetrating the dielectric layer.

[0022] Optionally, the interconnection metal line and the test metal line are formed synchronously.

[0023] Optionally, the distance between the test metal line and the interconnection metal line is 0.15μm to 0.7μm, the height of the interconnection metal line and the test metal line is 0.25μm to 0.7μm, and the dielectric layer is formed by chemical vapor deposition process so that there is an air gap in the dielectric layer between the interconnection metal line and the test metal line.

[0024] Optionally, after forming the second metal wiring layer, the method further includes:

[0025] The resistance of the plug is tested, and whether the plug is defective is determined according to the resistance of the plug.

[0026] Optionally, the defects of the plug include breakage of the plug and protrusion of a side wall of the plug.

[0027] The present invention provides a semiconductor test device and a preparation method thereof, comprising: a substrate; a first metal wiring layer, located on the substrate, the first metal wiring layer comprising an interconnection metal line and a test metal line, the test metal line is arranged around the interconnection metal line, and the test metal line and the interconnection metal line are insulated; a dielectric layer, located on and covering the first metal wiring layer, and an air gap is provided in the dielectric layer between the interconnection metal line and the test metal line; a second metal wiring layer, located on the dielectric layer, and electrically connected to the interconnection metal line through a plug. When the plug has defects such as sidewall protrusion or fracture, cracks will be generated in the dielectric layer between the air gap and the plug due to the stress between the film layers, and the cracks connect the plug and the air gap, causing the plug to be disconnected. The operator can determine whether the plug has a defect by measuring the resistance of the plug. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 5 A top view of a semiconductor testing device provided by an embodiment of the present invention;

[0029] Figure 6 A flowchart of a method for preparing a semiconductor test device provided by an embodiment of the present invention;

[0030] Figures 7 to 12 A schematic structural diagram corresponding to corresponding steps of a method for preparing a semiconductor test device provided by an embodiment of the present invention;

[0031] The accompanying drawings are as follows:

[0032] 100 - substrate; 102 - insulating layer; 103 - first conductive material layer; 104 - interconnecting metal line; 106 - testing metal line; 108 - dielectric layer; 109 - air gap; 110 - through hole; 112 - plug; 114 - second metal wiring layer. DETAILED DESCRIPTION

[0033] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0034] Hereinafter, the terms "first", "second", etc. are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if the method described herein includes a series of steps, the steps presented herein are not necessarily the only order in which the steps can be performed, and some of the steps described may be omitted and / or other steps not described in the text may be added to the method.

[0035] Fig.12 A schematic diagram of the structure of the semiconductor test device provided in this embodiment, such as Fig.12 As shown, this embodiment provides a semiconductor testing device, including: a substrate 100 , a first metal wiring layer, a dielectric layer 108 and a second metal wiring layer 114 .

[0036] Specifically, the substrate 100 further includes an insulating layer 102 , and the insulating layer 102 has a gate structure therein. The first metal wiring layer is located on the insulating layer 102 and is electrically connected to the gate structure through an electrical connector.

[0037] The first metal wiring layer includes an interconnect metal line 104 and a test metal line 106, the interconnect metal line 104 is electrically connected to the gate structure, the test metal line 106 is insulated from the gate structure and the interconnect metal line 104, and the distance between the test metal line 106 and the interconnect metal line 104 is 0.15μm~0.7μm, the height of the interconnect metal line 104 and the test metal line 106 is 0.25μm~0.7μm, and the groove between the interconnect metal line 104 and the test metal line 106 has a large aspect ratio.

[0038] Furthermore, the dielectric layer 108 covers the first metal wiring layer, and an air gap 109 is provided in the dielectric layer 108 between the interconnection metal line 104 and the test metal line 106 , and a top surface of the air gap 109 is higher than a top surface of the first metal wiring layer.

[0039] The second metal wiring layer 114 is located on the dielectric layer 108 and is electrically connected to the interconnection metal line via a plug 112 penetrating the dielectric layer.

[0040] Figures 1 to 3 A top view of a semiconductor test device provided in this embodiment, wherein: Fig.10 for Figures 1 to 3 The cross-sectional view of the semiconductor test device along the line A to A'. Figure 1As shown, the plug 112 is located at one end of the interconnect metal line 104 , the test metal line 106 is arranged around the interconnect metal line 104 , and the test metal line 106 is U-shaped, and one end of the interconnect metal line 104 corresponding to the plug 112 is located in the U-shaped opening of the test metal line 106 .

[0041] like Figure 2 As shown, when the plug 112 is located in the area between the two ends of the interconnection metal line 104, the test metal line 106 is arranged in parallel with the interconnection metal line 104; Figure 3 As shown, when the plug 112 is located at both ends of the interconnect metal line 104 , the test metal line 106 surrounds the interconnect metal line 104 to form a closed pattern, and the interconnect metal line 104 is located inside the closed pattern to ensure that the air gap 109 is present outside the plug 112 . Figures 1 to 3 Only a preferred embodiment of the present invention is illustrated. The arrangement of the test metal line 106 in the present invention is not affected by the position of the plug 112 . It is only necessary to ensure that there is an air gap 109 in the dielectric layer between the plug 112 and the test metal line 106 .

[0042] Figure 4 and Figure 5 A top view of the semiconductor test device provided in this embodiment, such as Figure 4 and Figure 5 As shown, when the distance between the interconnecting metal lines 104 is relatively close, the test metal line 106 may be formed as follows: Figure 4 and Figure 5 The parallel array shown reduces process costs and improves monitoring efficiency. It should be understood that the U-shaped test metal lines 106 and the closed-shaped test metal lines 106 can be arranged alternately, and the present invention does not limit this.

[0043] It should be noted that the first metal wiring layer, the plug 112 and the air gap 109 are not actually visible when viewed from above. Figures 1 to 3 The positions and connection relationships among the first metal wiring layer, the plug 112 , the air gap 109 and the second metal wiring layer 114 are only shown from a top view.

[0044] During the manufacturing process, the plug 112 may have defects such as side wall protrusion or breakage due to process and stress problems between film layers. The defects of the plug 112 will cause poor connection between the first metal wiring layer and the second metal wiring layer 114, and the defects of the plug 112 are difficult to detect by conventional detection means.

[0045] In this embodiment, the test metal line 106 is arranged around the outer periphery of the interconnect metal line 104, the distance between the test metal line 106 and the interconnect metal line 104 is small, and the trench between the interconnect metal line 104 and the test metal line 106 has a large aspect ratio. When a process with a weaker filling capability is selected to form the dielectric layer 108, the air gap 109 will be formed between the interconnect metal line 104 and the test metal line 106 due to the surface tension of the material during the formation of the dielectric layer 108. In the longitudinal direction, the top surface of the air gap 109 is higher than the top surface of the first metal wiring layer, so that the air gap 109 and the plug 112 have a partial area overlap; in the transverse direction, the distance between the air gap 109 and the plug 112 is small. If the plug 112 has defects such as sidewall protrusion or fracture during the formation process, the dielectric layer 108 between the air gap 109 and the plug 112 will be broken, resulting in a crack connected to the plug 112. When the air gap 109 is connected to the plug 112 through the crack, the plug 112 is disconnected, and the operator can test whether the plug 112 is defective by measuring resistance.

[0046] Figure 6 A flowchart of a method for preparing a semiconductor test device provided in this embodiment is shown in FIG. Figure 6 As shown, the present invention provides a method for preparing a semiconductor test device, comprising:

[0047] Step S1: providing a substrate;

[0048] Step S2: forming a first metal wiring layer on the substrate, including insulated interconnection metal lines and test metal lines, wherein the test metal lines are arranged around the interconnection metal lines;

[0049] Step S3: forming a dielectric layer on the first metal wiring layer, wherein the dielectric layer covers the first metal wiring layer and the substrate, and an air gap is provided in the dielectric layer between the interconnect metal line and the test metal line;

[0050] Step S4: forming a second metal wiring layer on the dielectric layer, wherein the second metal wiring layer is electrically connected to the interconnection metal line via a plug penetrating the dielectric layer.

[0051] Figures 7 to 12 The following is a schematic diagram of the structure corresponding to the corresponding steps of the method for preparing a semiconductor test device provided in this embodiment, and is combined with the attached Figures 5 to 10 A method for preparing a semiconductor test device provided in this embodiment is described in more detail, wherein a preferred embodiment of the present invention is illustrated.

[0052] like Figure 7 As shown, a substrate 100 is provided, and an insulating layer 102 is formed on the substrate 100 . The insulating layer 102 has a gate structure (not shown) therein.

[0053] like Figure 8 and Fig. 9 As shown, a first conductive material layer 103 is formed on the insulating layer 102, and the first conductive material layer 103 is etched to form a first metal wiring layer, wherein the first metal wiring layer includes an interconnection metal line 104 and a test metal line 106, wherein the test metal line 106 is formed synchronously with the interconnection metal line 104, and the test metal line 106 is insulated from the interconnection metal line 104.

[0054] like Fig.10 As shown, a dielectric layer 108 is formed on the first metal wiring layer by a chemical vapor deposition process, and the dielectric layer 108 covers the first metal wiring layer and the substrate 100. When forming the dielectric layer 108, since the filling ability of the chemical vapor deposition process is relatively weak and the trench between the interconnection metal line 104 and the test metal line 106 has a relatively large aspect ratio, an air gap 109 is formed when the dielectric layer 108 fills the gap between the interconnection metal line 104 and the test metal line 106, and the top surface of the air gap 109 is higher than the top surface of the first metal wiring layer. It should be understood that since the dielectric constant of air is very small, the air gap 109 can reduce the parasitic capacitance between the interconnection metal line 104 and the test metal line 106.

[0055] like Fig.11 and Fig.12 As shown, the dielectric layer 108 is etched, and a through hole 110 penetrating the dielectric layer 108 is formed in the dielectric layer 108, and the through hole 110 exposes the interconnection metal line 104. Then, a second conductive material layer is formed on the dielectric layer 108, and the second conductive material layer also fills the through hole 110. The portion of the second conductive material layer located in the through hole 110 constitutes a plug 112, and the portion of the second conductive material layer located on the dielectric layer 108 constitutes a second metal wiring layer 114; the interconnection metal line 104 is electrically connected to the second metal wiring layer 114 through the plug 112, and the second metal wiring layer 114 is insulated from the test metal line 106.

[0056] Furthermore, after forming the second metal wiring layer 114 , the method further includes: measuring the resistance of the plug 112 , and determining whether the plug has a defect according to the resistance of the plug.

[0057] Since the second conductive material is generally a stack of metal titanium, titanium nitride and metal tungsten, and the stress of metal titanium and titanium nitride is relatively high, when forming the plug 112 and the second metal wiring layer 114, the plug 112 may have defects such as sidewall protrusion or fracture due to the stress between the film layers. The dielectric layer 108 between the plug 112 and the air gap 109 is relatively thin. When the plug 112 has defects such as sidewall protrusion or fracture, the dielectric layer 108 between the air gap 109 and the plug 112 will break, resulting in a crack connected to the plug 112. The crack and the air gap 109 can cause the plug 112 to be disconnected, and the operator can test whether the plug 112 has defects by measuring resistance.

[0058] In summary, the present invention provides a semiconductor test device and a preparation method thereof, comprising: a substrate 100; a first metal wiring layer, located on the substrate 100, the first metal wiring layer comprising an interconnection metal line 104 and a test metal line 106, the test metal line 106 is arranged around the interconnection metal line 104, and the test metal line 106 is insulated from the interconnection metal line 104; a dielectric layer 108, located on and covering the first metal wiring layer, and an air gap 109 is provided in the dielectric layer 108 between the interconnection metal line 104 and the test metal line 106; a second metal wiring layer 114, located on the dielectric layer 108, and electrically connected to the interconnection metal line 104 through a plug 112. When the plug 112 has defects such as protrusion or fracture of the side wall, cracks will be generated in the dielectric layer 108 between the air gap 109 and the plug 112 due to the stress between the film layers. The cracks connect the plug 112 and the air gap 109, causing the plug 112 to be disconnected. The operator can determine whether the plug 112 has defects by measuring the resistance of the plug 112. In addition, the layout between the test metal line 106 and the interconnect metal line 104 is changed according to the position of the plug 112 to ensure that there is an air gap 109 outside the plug 112, so as to more accurately determine whether the plug 112 has defects.

[0059] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A semiconductor testing device, characterized in that: include: substrate; A first metal wiring layer, located on the substrate, comprising insulated interconnection metal lines and test metal lines, wherein the test metal lines are arranged around the interconnection metal lines; a dielectric layer, covering the first metal wiring layer and the substrate, wherein an air gap is provided in the dielectric layer between the interconnection metal line and the test metal line, and a top of the air gap is higher than a top of the first metal wiring layer; The second metal wiring layer is located on the dielectric layer and is electrically connected to the interconnection metal line via a plug penetrating the dielectric layer.

2. A semiconductor testing device as claimed in claim 1, characterized in that: The plug is located at one end of the interconnect metal line.

3. A semiconductor testing device as claimed in claim 1, characterized in that: The plugs are located at both ends of the interconnection metal line.

4. A semiconductor testing device as claimed in claim 1, characterized in that: The plug is located in a region between both ends of the interconnection metal line.

5. A semiconductor testing device according to any one of claims 2 to 4, characterized in that: The test metal line is U-shaped, and one end of the interconnection metal line corresponding to the plug is located in the U-shaped opening of the test metal line.

6. A semiconductor testing device according to any one of claims 2 to 4, characterized in that: The test metal lines form a closed pattern, and the interconnection metal lines are located inside the closed pattern.

7. A semiconductor testing device as claimed in claim 4, characterized in that: The test metal line is arranged in parallel with the interconnection metal line.

8. A semiconductor testing device as claimed in claim 1, characterized in that: The distance between the test metal line and the interconnection metal line is 0.15 μm to 0.7 μm, and / or the height of the interconnection metal line and the test metal line is 0.25 μm to 0.7 μm.

9. A method for preparing a semiconductor test device, characterized in that: include: providing a substrate; forming a first metal wiring layer on the substrate, comprising an insulated interconnection metal line and a test metal line, wherein the test metal line is arranged around the interconnection metal line; forming a dielectric layer on the first metal wiring layer, the dielectric layer covering the first metal wiring layer and the substrate, and an air gap is provided in the dielectric layer between the interconnection metal line and the test metal line, and the top of the air gap is higher than the top of the first metal wiring layer; A second metal wiring layer is formed on the dielectric layer, and the second metal wiring layer is electrically connected to the interconnection metal line through a plug penetrating the dielectric layer.

10. The method for preparing a semiconductor test device according to claim 9, characterized in that: The interconnection metal line is formed simultaneously with the test metal line.

11. The method for preparing a semiconductor test device according to claim 9, characterized in that: The distance between the test metal line and the interconnection metal line is 0.15μm to 0.7μm, the height of the interconnection metal line and the test metal line is 0.25μm to 0.7μm, and the dielectric layer is formed by chemical vapor deposition process so that there is an air gap in the dielectric layer between the interconnection metal line and the test metal line.

12. The method for preparing a semiconductor test device according to claim 9, characterized in that: After forming the second metal wiring layer, the method further includes: The resistance of the plug is tested, and whether the plug is defective is determined according to the resistance of the plug.

13. The method for preparing a semiconductor test device according to claim 12, characterized in that: Defects of the plug include breakage of the plug and bulging of the sidewall of the plug.

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