Signal transmission circuit packaging structure

Abstract

The present invention provides a signal transmission circuit packaging structure, comprising a main body, a main circuit unit, a plurality of power pins, a plurality of input pins, a plurality of output pins, a plurality of control pins, and a plurality of ground pins. The main circuit unit is disposed in the center of the main body. The plurality of power pins are disposed in the center of the main body and supply power signals to the main circuit unit. The plurality of input pins and the plurality of output pins are disposed on a first side and a second side of the main body and electrically connected to the main circuit unit. The plurality of control pins are disposed on a second side of the main body and electrically connected to the main circuit unit. The plurality of ground pins are disposed in the corners of the main body to separate the plurality of input pins, the plurality of output pins, and the plurality of control pins.

Description

Technical Field

[0001] The present invention relates to a signal transmission circuit packaging structure, in particular to a signal transmission circuit packaging structure capable of separating transmission paths of different speeds to avoid interference. Background Art

[0002] With technological advancements, data transmission speeds are increasing. Communications equipment and data servers alike demand high-speed data transmission. Current PCIe Gen5 transmission speeds reach 32Gb / s, while PCIe Gen6 can reach 64Gb / s. However, in such high-speed transmission environments, predicting path loss is crucial. Therefore, the design of integrated circuit packaging structures has become a key factor in high-speed data transmission.

[0003] Therefore, it is necessary to invent a new signal transmission circuit packaging structure to solve the deficiencies of the prior art. Summary of the Invention

[0004] The main purpose of the present invention is to provide a signal transmission circuit packaging structure that can separate transmission paths of different speeds to avoid interference.

[0005] To achieve the above-mentioned objectives, the signal transmission circuit packaging structure of the present invention includes a main body, a main circuit unit, a plurality of power pins, a plurality of input pins, a plurality of output pins and a plurality of control pins. The main body includes a first side and a second side, and the first side is adjacent to the second side. The main circuit unit is arranged in the center of the main body. The plurality of power pins are arranged in the center of the main body and supply power signals to the main circuit unit. The plurality of input pins are arranged on the first side and the second side of the main body and are electrically connected to the main circuit unit. The plurality of output pins are arranged on the first side and the second side of the main body and are electrically connected to the main circuit unit. The plurality of control pins are arranged on the second side of the main body and are electrically connected to the main circuit unit. The plurality of ground pins are arranged at the corners of the main body and between each of the plurality of input pins, the plurality of output pins and the plurality of control pins to separate the plurality of input pins, the plurality of output pins and the plurality of control pins. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A is a schematic diagram of the pin layout of the signal transmission circuit packaging structure of the present invention;

[0007] Figure 1B It is a schematic diagram of the architecture of the main circuit unit of the routing integrated circuit element of the present invention;

[0008] Figure 2 is a schematic diagram of a transmission channel of a signal transmission circuit packaging structure of the present invention;

[0009] Figure 3 It is a schematic diagram of the overlapped pin layout and transmission channel of the signal transmission circuit packaging structure of the present invention.

[0010]

Explanation of symbols

[0011] Signal transmission circuit packaging structure 1

[0012] Body 10

[0013] First side 11

[0014] Second side 12

[0015] Main circuit unit 20

[0016] Demultiplexer circuits 21a, 21b

[0017] Multiplexer circuits 22a, 22b

[0018] First high-speed input channel 31

[0019] Second high-speed input channel 32

[0020] The third high-speed input channel 33

[0021] Fourth high-speed input channel 34

[0022] Fifth high-speed input channel 35

[0023] Sixth high-speed input channel 36

[0024] First high-speed output channel 41

[0025] Second high-speed output channel 42

[0026] The third high-speed output channel 43

[0027] Fourth high-speed output channel 44

[0028] Fifth high-speed output channel 45

[0029] Sixth high-speed output channel 46

[0030] Low-speed transmission channel 51

[0031] Input ports A1, A3, B1, B3, C0, C2

[0032] Output ports A0, A2, B0, B2, C1, C3

[0033] Input pins A1_iP, A1_iN, A3_iP, A3_iN, B1_iP, B1_iN, B3_iP, B3_iN, C0_iP, C0_iN, C2_iP, C2_iN

[0034] Output pins A0_oP, A0_oN, A2_oP, A2_oN, B0_oP, B0_oN, B2_oP, B2_oN, C1_oP, C1_oN, C3_oP, C3_oN

[0035] Control pins ctrl0, ctrl1, ctrl2, ctrl3

[0036] Power pin Vcc

[0037] Ground pin Vss DETAILED DESCRIPTION

[0038] In order to better understand the technical content of the present invention, preferred specific embodiments are described below.

[0039] Please refer to the following Figure 1A It is a schematic diagram of the pin layout of the signal transmission circuit packaging structure of the present invention.

[0040] In an embodiment of the present invention, the signal transmission circuit packaging structure 1 is electrically connected to at least one other electronic module to transmit electronic signals. The transmission mode of the electronic signal can be in the form of a single-ended signal or a differential signal, but the present invention is not limited thereto. In the embodiment of the present invention, it is described in the form of a differential signal. It should be noted that although the description of the present invention uses the terms "first", "second", etc. to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another. For example, without departing from the scope of the various described embodiments, the first input pin can be referred to as the second input pin, and similarly, the second input pin can be referred to as the first input pin. The first input pin and the second input pin are both input pins, but they are not the same input pin.

[0041] The signal transmission circuit packaging structure 1 includes a body 10, a main circuit unit 20 (such as Figure 1B), multiple power pins Vcc, multiple input pins A1_iP, A1_iN, A3_iP, A3_iN, B1_iP, B1_iN, B3_iP, B3_iN, C0_iP, C0_iN, C2_iP, C2_iN, multiple output pins A0_oP, A0_oN, A2_oP, A2_oN, B0_oP, B0_oN, B2_oP, B2_oN, C1_oP, C1_oN, C3_oP, C3_oN, multiple control pins ctrl0, ctrl1, ctrl2, ctrl3, and multiple ground pins Vss. The body 10 can be a single-layer or multi-layer circuit board and includes a first side 11 and a second side 12. The first side 11 is adjacent to the second side 12. The main circuit unit 20 is located in the center of the main body 10 and may be located on a different layer of the circuit board than other pins. The main circuit unit 20 includes demultiplexer circuits 21a and 21b and multiplexer circuits 22a and 22b, but the present invention is not limited thereto. A plurality of power pins Vcc are located in the center of the main body 10 and supply a power signal to the main circuit unit 20. A plurality of input pins A1_iP, A1_iN, A3_iP, A3_iN, B1_iP, B1_iN, B3_iP, B3_iN, C0_iP, C0_iN, C2_iP, and C2_iN are located on the first side 11 and the second side 12 of the main body 10 and electrically connect to the main circuit unit 20. Multiple output pins A0_oP, A0_oN, A2_oP, A2_oN, B0_oP, B0_oN, B2_oP, B2_oN, C1_oP, C1_oN, C3_oP, and C3_oN are located on the first and second sides 11 and 12 of the main body 10 and are electrically connected to the main circuit unit 20. Therefore, signals are input from the multiple input pins into the main circuit unit 20 and then transmitted to the multiple output pins. Input pins C0_iP and C0_iN are located on the same side of the main body 10 as output pins A0_oP and A0_oN, and on adjacent sides of the main body 10 as output pins B0_oP and B0_oN. Input pins A1_iP and A1_iN are located on opposite sides of the main body 10 from input pins B1_iP and B1_iN, and on the same side of the main body 10 as output pins C1_oP and C1_oN. Input pins C2_iP and C2_iN are located on the same side of the main body 10 as output pins A2_oP and A2_oN, and on opposite sides of the main body 10 from output pins B2_oP and B2_oN. Input pins A3_iP and A3_iN are located on adjacent sides of the main body 10 from input pins B3_iP and B3_iN, and on the same side of the main body 10 as output pins C3_oP and C3_oN.The input pins A1_iP, A1_iN, A3_iP, A3_iN, B1_iP, B1_iN, B3_iP, B3_iN, C0_iP, C0_iN, C2_iP, C2_iN and the output pins A0_oP, A0_oN, A2_oP, A2_oN, B0_oP, B0_oN, B2_oP, B2_oN, C1_oP, C1_oN, C3_oP, C3_oN directly connect the main circuit unit 20 to an external electronic module and shorten the transmission path.

[0042] Please also refer to Figure 1B It is a schematic diagram of the architecture of the main circuit unit of the routing integrated circuit element of the present invention.

[0043] In this embodiment of the present invention, the main circuit unit 20 includes two demultiplexer circuits 21a and 21b and two multiplexer circuits 22a and 22b, thereby being suitable for use with three electronic modules. The input ports C0 and C2 of the demultiplexer circuits 21a and 21b are connected to input pins C0_iP, C0_iN, C2_iP, and C2_iN. The output ports A0 and A2 are connected to output pins A0_oP, A0_oN, A2_oP, and A2_oN. The output ports B0 and B2 are connected to output pins B0_oP, B0_oN, B2_oP, and B2_oN. Input ports A1 and A3 of multiplexer circuits 22a and 22b are connected to input pins A1_iP, A1_iN, A3_iP, and A3_iN, input ports B1 and B3 are connected to input pins B1_iP, B1_iN, B3_iP, and B3_iN, and output ports C1 and C3 are connected to output pins C1_oP, C1_oN, C3_oP, and C3_oN. A plurality of input pins A1_iP, A1_iN, A3_iP, A3_iN, B1_iP, B1_iN, B3_iP, B3_iN, C0_iP, C0_iN, C2_iP, C2_iN and output pins A0_oP, A0_oN, A2_oP, A2_oN, B0_oP, B0_oN, B2_oP, B2_oN, C1_oP, C1_oN, C3_oP, C3_oN are pins capable of high-speed transmission and are arranged at the edge of the main body 10 to coordinate with the layout of the demultiplexer circuits 21a, 21b and the multiplexer circuits 22a, 22b to shorten the signal transmission path.

[0044] Figure 1AThe multiple power pins Vcc are located in the center of the main body 10 to more conveniently receive incoming power signals. The multiple control pins ctrl0, ctrl1, ctrl2, and ctrl3 are low-speed transmission pins located at the edge of the main body 10, transmitting control signals to the demultiplexer circuits 21a and 21b and the multiplexer circuits 22a and 22b. The multiple ground pins Vss are located at the edge of the main body 10, separating the pins of each input / output pin and the control pins ctrl0, ctrl1, ctrl2, and ctrl3 to prevent signal interference between the individual pins.

[0045] Please refer to Figure 2 It is a schematic diagram of the transmission channel of the signal transmission circuit packaging structure of the present invention.

[0046] The input pins A1_iP, A1_iN, A3_iP, A3_iN, B1_iP, B1_iN, B3_iP, B3_iN, C0_iP, C0_iN, C2_iP, and C2_iN are electrically connected to the main circuit unit via the first high-speed input channel 31, the second high-speed input channel 32, the third high-speed input channel 33, the fourth high-speed input channel 34, the fifth high-speed input channel 35, and the sixth high-speed input channel 36. Element 20 is then electrically connected to output pins A0_oP, A0_oN, A2_oP, A2_oN, B0_oP, B0_oN, B2_oP, B2_oN, C1_oP, C1_oN, C3_oP, C3_oN via a first high-speed output channel 41, a second high-speed output channel 42, a third high-speed output channel 43, a fourth high-speed output channel 44, a fifth high-speed output channel 45, and a sixth high-speed output channel 46. All high-speed input channels 31 to 36 are arranged to coordinate with the relative positions of input ports A1, A3, B1, B3, C0, and C2 to connect to input pins A1_iP, A1_iN, A3_iP, A3_iN, B1_iP, B1_iN, B3_iP, B3_iN, C0_iP, C0_iN, C2_iP, and C2_iN. Similarly, all high-speed output channels 41 through 46 are configured to coordinate the relative positions of output ports A0, A2, B0, B2, C1, and C3 with their connections to output pins A0_oP, A0_oN, A2_oP, A2_oN, B0_oP, B0_oN, B2_oP, B2_oN, C1_oP, C1_oN, C3_oP, and C3_oN. This shortens transmission distances and reduces signal energy loss.

[0047] Finally, please refer to Figure 3 It is a schematic diagram of the overlapped pin layout and transmission channel of the signal transmission circuit packaging structure of the present invention.

[0048] Finally, as Figure 3 As shown, the input pins C0_iP and C0_iN of the demultiplexer circuit 21a are connected to the first high-speed input channel 31, the output pins A0_oP and A0_oN are connected to the first high-speed output channel 41, and the output pins B0_oP and B0_oN are connected to the second high-speed output channel 42. The input pins A1_iP and A1_iN of the multiplexer circuit 22a are connected to the second high-speed input channel 32, the input pins B1_iP and B1_iN are connected to the third high-speed input channel 33, and the output pins C1_oP and C1_oN are connected to the third high-speed output channel 43. Input pins C2_iP and C2_iN of demultiplexer circuit 21b are connected to fourth high-speed input channel 34, output pins A2_oP and A2_oN are connected to fourth high-speed output channel 44, and output pins B2_oP and B2_oN are connected to fifth high-speed output channel 45. Input pins A3_iP and A3_iN of multiplexer circuit 22a are connected to fifth high-speed input channel 35, input pins B3_iP and B3_iN are connected to sixth high-speed input channel 36, and output pins C3_oP and C3_oN are connected to sixth high-speed output channel 46. The plurality of input pins A1_iP, A1_iN, A3_iP, A3_iN, B1_iP, B1_iN, B3_iP, B3_iN, C0_iP, C0_iN, C2_iP, C2_iN, the plurality of output pins A0_oP, A0_oN, A2_oP, A2_oN, B0_oP, B0_oN, B2_oP, B2_oN, C1_oP, C1_oN, C3_oP, C3_oN, and the plurality of control pins ctrl0, ctrl1, ctrl2, and ctrl3 are separated by a ground pin Vss. Furthermore, the high-speed input channels 31-36 and the high-speed output channels 41-46 are not located near the plurality of low-speed transmission channels 51 and are spaced a predetermined distance apart from each other. Therefore, the electronic signal transmitted at high speed will not be interfered by the control signal transmitted at low speed, and the electronic signal transmitted at high speed will have the best high-speed signal quality.

[0049] As can be seen from the above description, the signal transmission circuit packaging structure 1 of the present invention can reduce factors such as the signal transmission distance, the total signal attenuation, the number of circuit board vias, and the complexity of the circuit layout, thereby avoiding the problems of crosstalk interference and signal quality degradation, and is significantly superior to the design of the prior art.

[0050] It should be noted that the above is only an example and is not intended to limit the present invention. For example, any changes that do not depart from the basic structure of the present invention should be within the scope of the rights claimed by this patent and should be subject to the claims.

Claims

1. A signal transmission circuit packaging structure, characterized in that: The signal transmission circuit packaging structure includes: A body comprising a first side and a second side, wherein the first side is adjacent to the second side; A main circuit unit is disposed in the center of the body; A plurality of power pins are arranged at the center of the body and supply a power signal to the main circuit unit; A plurality of input pins are disposed on the first side and the second side of the body and are electrically connected to the main circuit unit; A plurality of output pins are disposed on the first side and the second side of the body and are electrically connected to the main circuit unit; A plurality of control pins are disposed on the second side of the body and electrically connected to the main circuit unit; and A plurality of ground pins are disposed at corners of the body and between each of the plurality of input pins, the plurality of output pins, and the plurality of control pins to separate the plurality of input pins, the plurality of output pins, and the plurality of control pins. The plurality of input pins are electrically connected to the main circuit unit via a plurality of high-speed input channels and are further electrically connected to the plurality of output pins via a plurality of high-speed output channels. The plurality of control pins are electrically connected to the main circuit unit via a plurality of low-speed transmission channels. The plurality of low-speed transmission channels are each spaced a specific distance from the plurality of high-speed input channels and the plurality of high-speed output channels to prevent signal interference.

2. The signal transmission circuit packaging structure according to claim 1, wherein: The main circuit unit has a multiplexer circuit and a demultiplexer circuit.

3. The signal transmission circuit packaging structure according to claim 2, wherein: The plurality of input pins and the plurality of output pins are arranged on the same side and adjacent sides of the body.

4. The signal transmission circuit packaging structure according to claim 2, wherein: The plurality of input pins and the plurality of output pins are arranged on the same side and the opposite side of the body.

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