Manufacturing Method of Air Gap Isolation Structure

Abstract

The present invention discloses a manufacturing method for an air gap isolation structure, comprising: Step 1, forming a first graphic structure. Step 2, performing pretreatment by using a first plasma formed with a non-film-forming gas and applying a bias voltage to form an electron aggregation region at the top of each first graphic structure and a positive ion aggregation region at the bottom of each first trench. Step 3, depositing a first dielectric film by using a CVD process, and making the positively charged reactants in the CVD process enrich at the top corners of the first graphic structure by virtue of the attraction of the electron aggregation region and the repulsion of the positive ion aggregation region, so that the first dielectric film is pinched off at the top opening of the first trench and an air gap isolation structure is formed at the bottom of the pinched-off position. Step 4, planarizing the surface of the first dielectric film. The present invention can quickly pinch off the trench during the filling of the dielectric film without increasing the difficulty of dry etching the trench, thereby increasing the volume of the air gap isolation structure.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and particularly to a method for manufacturing an air-gap isolation structure. Background Art

[0002] In order to achieve the durability and data retention of NAND flash memories at technology nodes below 20 nm, using an air gap for isolation between floating gates is a very effective method. This method involves encapsulating an air bubble between floating gates to replace the original solid dielectric material. Since the dielectric constant of air is 1, which is the best for blocking electrons among all dielectric materials, the problem of mutual interference between floating gates is effectively solved after adopting the air-gap process, breaking through the physical limit of miniaturization of NAND flash memory technology and further increasing the storage density.

[0003] In existing methods, the air-gap process usually uses a chemical vapor deposition (CVD) process with poor step coverage and a fast lateral growth rate to quickly seal the gaps between gate structures, so that air is retained therein. The most critical technical index is the morphology of the air gap, requiring the air gap between adjacent floating gates to be as large as possible, with the best case being that the space between floating gates is completely filled with air. In particular, the closing position at the top of the air gap must be higher than the gate top metal silicide to prevent leakage between metal silicides with better conductivity by bypassing the air layer. Since the step coverage of the general CVD process highly depends on the trench morphology, the above indexes pose extremely high requirements on the dry etching process, that is, a series of densely arranged trenches with an aspect ratio of more than 10 need to be etched, and the sidewalls of the trenches need to be kept smooth and perpendicular to the substrate. However, the actual situation is that the sidewalls of trenches with such a high aspect ratio often have a certain inclination angle after the etching process, so that the CVD process cannot quickly pinch off and seal the trenches, resulting in partial filling of the trench bottom with dielectric material, a corresponding reduction in the cross-sectional area of the air gap, and a corresponding reduction in the isolation effect; while the pinching-off position at the upper part of the trench is lower than the gate top metal silicide, posing a potential risk of crosstalk between gates. Therefore, for the air-gap process, how to find a method that can not further increase the difficulty of dry etching trenches and at the same time meet the requirement of quickly pinching off the gaps between gate structures by CVD has become the key point of the air-gap manufacturing process.

[0004] As Figures 1A to 1B shown, it is a schematic diagram of the device structure in each step of the existing method for manufacturing an air-gap isolation structure; the existing method for manufacturing an air-gap isolation structure includes the following steps:

[0005] Step 1: As Figure 1A shown, a first pattern structure 102 is formed on the front surface of a semiconductor substrate 101, and a first trench 103 is provided between each of the first pattern structures 102.

[0006] When the air gap isolation structure 106 serves as the isolation structure between gate structures, the first graphic structure 102 is a gate structure.

[0007] Generally, the first graphic structure 102 is the gate structure of a NAND flash memory. As the process technology node shrinks, the aspect ratio of the first trench 103 between the gate structures will increase to more than 10, which poses extremely high requirements for the etching process of the first trench 103, and the first trench 103 often has a certain inclination angle. That is, Figure 1A In the figure, the dashed line 103b represents the position when the side surface 103a of the first trench 103 is completely vertical. In fact, the side surface 103a of the first trench 103 will deviate from the position corresponding to the dashed line 103b, making the first trench 103 have a structure with a top opening width larger than the bottom opening width.

[0008] Step two: As Figure 1B shown, deposit a first dielectric film 105 using a CVD process. After the top of the first dielectric film 105 is pinched off, an air gap isolation structure 106 is formed inside the first trench 103.

[0009] Return to Figure 1A shown, in the CVD process, due to the structure of the side surface 103a of the first trench 103 with a top opening width larger than the bottom opening width being inclined, the reactants easily reach the bottom of the first trench 103 along the path corresponding to the arrow line 104. As Figure 1B shown, finally, the first dielectric film 105 will also be deposited at the bottom of the first trench 103, and the thickness of the first dielectric film 105 at the bottom of the first trench 103 is d101.

[0010] The thickness d101 of the first dielectric film 105 at the bottom of the first trench 103 will cause the cross-sectional area of the air gap isolation structure 106 to shrink, the volume to decrease, and the isolation effect to decrease. As Figure 1B shown, the arrow line 107 is used to represent the electron interference between adjacent gate structures. Summary of the Invention

[0011] The technical problem to be solved by the present invention is to provide a manufacturing method for an air gap isolation structure, which can quickly pinch off a trench during the filling of a dielectric film without increasing the difficulty of dry etching the trench, thereby increasing the volume of the air gap isolation structure, increasing the isolation between the graphic structures on both sides of the air gap isolation structure, reducing interference, and improving the performance of the device.

[0012] To solve the above technical problem, the manufacturing method for the air gap isolation structure provided by the present invention includes the following steps:

[0013] Step 1: Form a first pattern structure on the front surface of a semiconductor substrate, with a first trench between each of the first pattern structures.

[0014] Step 2: Perform a pretreatment using a first plasma formed from a non-film-forming gas and applying a bias voltage perpendicular to the front surface of the semiconductor substrate to the first plasma. The pretreatment forms an electron accumulation region at the top of each of the first pattern structures and a positive ion accumulation region at the bottom of each of the first trenches. The electron accumulation region covers the top surface and the top corners of the first pattern structures.

[0015] Step 3: Deposit a first dielectric film using a CVD process. Utilize the attracting effect of the electron accumulation region and the repulsive effect of the positive ion accumulation region to enrich the positively charged reactants in the CVD process at the top corners of the first pattern structures, such that the growth rate of the first dielectric film at the top corners of the first trenches increases and the growth rate at the bottom of the first trenches decreases, causing the first dielectric film to be pinched off at the top opening of the first trenches and forming an air gap isolation structure at the bottom of the pinched-off position.

[0016] Step 4: Planarize the surface of the first dielectric film using a chemical mechanical polishing process.

[0017] A further improvement is that the side surface of the first trench is inclined and the width of the top opening is greater than the width of the bottom opening.

[0018] A further improvement is that the semiconductor substrate includes a silicon substrate.

[0019] A further improvement is that the first pattern structure is a gate structure.

[0020] A further improvement is that the first pattern structure is a gate structure of a NAND flash memory.

[0021] A further improvement is that the gate structure includes a stacked structure of a floating gate dielectric layer, a polysilicon floating gate, an inter-gate dielectric layer, and a polysilicon control gate.

[0022] A further improvement is that a metal silicide is also formed on the top surface of the polysilicon control gate.

[0023] A further improvement is that in Step 2, the non-film-forming gas is nitrogen, hydrogen, or argon.

[0024] A further improvement is that in Step 3, the surface coverage of the first dielectric film is reduced by increasing the lateral growth rate of the first dielectric film. The worse the surface coverage, the higher the pinched-off position.

[0025] A further improvement is that the material of the first dielectric film includes silicon dioxide or silicon nitride.

[0026] A further improvement is that the thickness of the first dielectric film above the pinch-off position is 10 μm to 20 μm.

[0027] A further improvement is that in step one, silicon oxide sidewalls are also formed on the sides of the polysilicon floating gate and the polysilicon control gate.

[0028] A further improvement is that the silicon oxide sidewalls are formed by thermally oxidizing the polysilicon floating gate and the polysilicon control gate.

[0029] A further improvement is that both step two and step three are carried out in a CVD process chamber, and the bias voltage is a negative voltage applied to the bottom of the semiconductor substrate.

[0030] A further improvement is that the CVD process uses a PECVD process.

[0031] After the formation of the first trench between the first graphic structures of the present invention, a pretreatment is carried out by applying a bias voltage to a first plasma formed with a non-film-forming gas. By utilizing the electron shielding effect of the first trench on the first plasma under the action of the bias voltage, electrons are accumulated at the top of the first graphic structure to form an electron accumulation region, and positive ions are accumulated at the bottom of the first trench to form a positive ion accumulation region. Among them, the electron shielding effect is as follows: the positive ions in the first plasma are easily vertically moved to the bottom region of the first trench and accumulated in the bottom region of the first trench under the action of the bias voltage, while the movement trajectory of the electrons in the first plasma is not vertical movement but tends to be isotropic movement and is easily affected by the antenna effect and accumulated at the top of the first graphic structure. Therefore, the electrons are shielded outside the first trench. When a CVD growth process is carried out after the pretreatment, the electron accumulation region can attract positively charged reactants, so the reactants are more easily enriched at the top corners of the first graphic structure. The top corners of the first graphic structure are also the top corners of the first trench. Therefore, the growth rate at the top corners of the first trench is faster, which can not only ensure that the first dielectric film is pinched off at the top opening of the first trench, but also quickly make the first dielectric film pinched off at the top opening of the first trench, thereby increasing the volume of the air gap isolation structure. After the volume of the air gap isolation structure is increased, the isolation of the graphic structures on both sides of the air gap isolation structure can be increased and interference can be reduced, improving the performance of the device, such as improving the durability of the device.

[0032] Since the control of the air gap isolation structure in the present invention is achieved through the pretreatment of the first plasma with a bias voltage, and it has low dependence on the topography requirements of the first trench, the present invention can directly adopt the first trench with a side inclination and a top opening width larger than the bottom opening width. This can greatly reduce the formation process requirements of the first trench, so that the present invention can not only not increase the requirements for dry etching the trench, but also ensure the integrity and stability of the air gap isolation structure.

[0033] The present invention is particularly suitable for forming the air gap isolation structure between the gate structures of NAND flash memories; as the process technology node shrinks, such as when the process technology node shrinks to below 20 nm, the spacing between the gate structures further shrinks, and the aspect ratio of the first trench between the gate structures is larger, so that the first trench has a stronger electron shielding effect, which is more conducive to the fabrication of the air gap isolation structure and can further increase the volume of the air gap isolation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The present invention will be further described in detail below with reference to the drawings and specific embodiments:

[0035] Figures 1A - 1B is a schematic diagram of the device structure in each step of the manufacturing method of the existing air gap isolation structure;

[0036] Figure 2 is a flowchart of the manufacturing method of the air gap isolation structure according to an embodiment of the present invention;

[0037] Figures 3A - 3C is a schematic diagram of the device structure in each step of the manufacturing method of the air gap isolation structure according to an embodiment of the present invention;

[0038] Figures 4A - 4C is a schematic diagram of the device structure in each step of the manufacturing method of the air gap isolation structure according to a preferred embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0039] As Figure 2 shown, it is a flowchart of the manufacturing method of the air gap isolation structure according to an embodiment of the present invention; as Figures 3A to 3C shown, it is a schematic diagram of the device structure in each step of the manufacturing method of the air gap isolation structure according to an embodiment of the present invention; the manufacturing method of the air gap isolation structure according to an embodiment of the present invention includes the following steps:

[0040] Step 1, as Figure 3A shown, a first pattern structure 202 is formed on the front surface of the semiconductor substrate 201, and a first trench 203 is provided between each of the first pattern structures 202.

[0041] In an embodiment of the present invention, the side surface 203a of the first trench 203 is inclined and the width of the top opening is greater than the width of the bottom opening, which can reduce the requirements for dry etching of the first trench 203.

[0042] The semiconductor substrate 201 includes a silicon substrate.

[0043] The first pattern structure 202 is a gate structure.

[0044] Step 2: As Figure 3C shown, a first plasma formed of a non-film-forming gas is used and a bias voltage perpendicular to the front surface of the semiconductor substrate 201 is applied to the first plasma for pretreatment. An electron accumulation region 303 is formed at the top of each of the first pattern structures 202 and a positive ion accumulation region 304 is formed at the bottom of each of the first trenches 203. The electron accumulation region 303 covers the top surface and the top corners of the first pattern structure 202.

[0045] As Figure 3B shown, the electron shielding effect is utilized in Step 2 of the embodiment of the present invention, including: Positive ions in the first plasma are likely to vertically move to the bottom region of the first trench 203 as shown by the mark 301 under the action of the bias voltage and accumulate in the bottom region of the first trench 203 to form the positive ion focusing region 304. However, the movement trajectory of electrons in the first plasma is not a vertical movement but tends to be an isotropic movement as shown by the mark 302 and is likely to accumulate at the top of the first pattern structure due to the antenna effect. Therefore, electrons will be shielded outside the first trench 203 to form the electron focusing region 303.

[0046] In an embodiment of the present invention, the non-film-forming gas is nitrogen, hydrogen or argon.

[0047] Step 3: As Figure 3C shown, a first dielectric film 204 is deposited by a CVD process. By utilizing the attracting effect of the electron accumulation region 303 and the repulsive effect of the positive ion accumulation region 304, the positively charged reactants in the CVD process are enriched at the top corners of the first pattern structure 202, so that the growth rate of the first dielectric film 204 at the top corners of the first trench 203 increases and the growth rate at the bottom of the first trench 203 decreases, causing the first dielectric film 204 to be pinched off at the top opening of the first trench 203 and an air gap isolation structure 205 to be formed at the bottom of the pinched-off position.

[0048] In an embodiment of the present invention, the surface coverage of the first dielectric film 204 is reduced by increasing the lateral growth rate of the first dielectric film 204. The worse the surface coverage, the higher the pinched-off position.

[0049] The material of the first dielectric film 204 includes silicon dioxide or silicon nitride.

[0050] The thickness of the first dielectric film 204 above the pinch-off position is 10 μm to 20 μm.

[0051] Both Step 2 and Step 3 are carried out in a CVD process chamber, and the bias voltage is a negative voltage applied to the bottom of the semiconductor substrate 201. More preferably, the CVD process uses a PECVD process.

[0052] Step 4: As Figure 3C shown, a chemical mechanical polishing process is used to planarize the surface of the first dielectric film 204.

[0053] After the first trench 203 is formed between the first graphic structures 202 in the embodiment of the present invention, a first plasma formed by a non-film-forming gas is used to apply a bias voltage for pretreatment. Utilizing the fact that the first trench 203 has an electron shielding effect on the first plasma under the action of the bias voltage, electrons accumulate at the top of the first graphic structure 202 to form an electron accumulation region 303 and positive ions accumulate at the bottom of the first trench 203 to form a positive ion accumulation region 304; wherein, the electron shielding effect is: the positive ions in the first plasma are easily vertically moved to the bottom region of the first trench 203 and accumulate in the bottom region of the first trench 203 under the action of the bias voltage, while the movement trajectory of the electrons in the first plasma is not vertical movement but tends to be isotropic movement and is easily affected by the antenna effect and accumulates at the top of the first graphic structure 202. Therefore, the electrons are shielded outside the first trench 203; when a CVD growth process is carried out after the pretreatment, the electron accumulation region 303 can attract positively charged reactants, so the reactants are more easily enriched at the top corners of the first graphic structure 202. The top corners of the first graphic structure 202 are also the top corners of the first trench 203. Therefore, the growth rate at the top corners of the first trench 203 is faster, which can not only ensure that the first dielectric film 204 is pinched off at the top opening of the first trench 203, but also quickly make the first dielectric film 204 be pinched off at the top opening of the first trench 203, thereby increasing the volume of the air gap isolation structure 205; after the volume of the air gap isolation structure 205 increases, the isolation of the graphic structures on both sides of the air gap isolation structure 205 can be increased and interference can be reduced, improving the performance of the device such as improving the durability of the device.

[0054] Since the control of the air gap isolation structure 205 in the embodiments of the present invention is achieved through the pretreatment of the first plasma with a bias voltage applied, the dependence on the topography requirements of the first trench 203 is not high. The present invention can directly adopt the first trench 203 with a side inclination and a top opening width greater than the bottom opening width, which can greatly reduce the formation process requirements of the first trench 203. Therefore, the embodiments of the present invention can not only not increase the requirements for dry etching the trench but also ensure the integrity and stability of the air gap isolation structure 205.

[0055] The embodiments of the present invention are particularly suitable for forming the air gap isolation structure 205 between the gate structures of NAND flash memories; as the process technology node is reduced, such as when the process technology node is reduced to below 20 nm, the spacing between the gate structures is further reduced, and the aspect ratio of the first trench 203 between the gate structures is larger, so that the first trench 203 has a stronger electron shielding effect, which is more conducive to the fabrication of the air gap isolation structure 205 and can further increase the volume of the air gap isolation structure 205.

[0056] As Figures 4A to 4C shown, it is a schematic diagram of the device structure in each step of the manufacturing method of the air gap isolation structure 205 according to the preferred embodiment of the present invention; the manufacturing method of the air gap isolation structure 205 according to the preferred embodiment of the present invention includes the following steps:

[0057] Step 1, as Figure 4A shown, a first pattern structure 202 is formed on the front surface of the semiconductor substrate 201, and a first trench 203 is provided between each of the first pattern structures 202.

[0058] In the preferred embodiment of the present invention, the side surface 203a of the first trench 203 is inclined and the top opening width is greater than the bottom opening width, which can reduce the dry etching requirements for the first trench 203.

[0059] The semiconductor substrate 201 includes a silicon substrate.

[0060] The first pattern structure 202 is a gate structure. The first pattern structure 202 is a gate structure of a NAND flash memory.

[0061] The gate structure includes a stacked structure 202a of a floating gate dielectric layer, a polysilicon floating gate, an inter-gate dielectric layer, and a polysilicon control gate.

[0062] A metal silicide 202c is further formed on the top surface of the polysilicon control gate.

[0063] Silicon oxide sidewalls 202b are further formed on the side surfaces of the polysilicon floating gate and the polysilicon control gate.

[0064] The silicon oxide sidewall 202b is formed by thermally oxidizing the polysilicon floating gate and the polysilicon control gate.

[0065] Step 2: As Figure 4B shown, a first plasma formed of a non-film-forming gas is used and a bias voltage perpendicular to the front surface of the semiconductor substrate 201 is applied to the first plasma for pretreatment. Figure 4B In, the pretreatment is represented by the arrow line corresponding to the label 401. The pretreatment forms an electron accumulation region at the top of each of the first graphic structures 202 and a positive ion accumulation region at the bottom of each of the first trenches 203. The electron accumulation region covers the top surface and the top corners of the first graphic structures 202.

[0066] In a preferred embodiment of the present invention, the non-film-forming gas is nitrogen, hydrogen or argon.

[0067] Step 3: As Figure 4C shown, a first dielectric film 204 is deposited by a CVD process. By using the attracting effect of the electron accumulation region and the repulsive effect of the positive ion accumulation region, the positively charged reactants in the CVD process are enriched at the top corners of the first graphic structures 202, so that the growth rate of the first dielectric film 204 at the top corners of the first trenches 203 increases and the growth rate at the bottom of the first trenches 203 decreases, causing the first dielectric film 204 to be pinched off at the top opening of the first trenches 203 and an air gap isolation structure 205 to be formed at the bottom of the pinched-off position.

[0068] In a preferred embodiment of the present invention, the surface coverage of the first dielectric film 204 is reduced by increasing the lateral growth rate of the first dielectric film 204. The worse the surface coverage, the higher the pinched-off position.

[0069] The material of the first dielectric film 204 includes silicon dioxide or silicon nitride.

[0070] The thickness of the first dielectric film 204 above the pinched-off position is 10 μm to 20 μm.

[0071] Both Step 2 and Step 3 are carried out in a CVD process chamber. The bias voltage is a negative voltage and is applied to the bottom of the semiconductor substrate 201. More preferably, the CVD process uses a PECVD process.

[0072] Step 4: As Figure 4C shown, a chemical mechanical polishing process is used to planarize the surface of the first dielectric film 204.

[0073] The present invention has been described in detail through specific embodiments, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present invention.

Claims

1. A manufacturing method of an air gap isolation structure, characterized in that, it includes the following steps: Step 1, form a first pattern structure on the front surface of a semiconductor substrate, and there is a first trench between each of the first pattern structures; Step 2, use a first plasma formed by a non-film-forming gas and apply a bias voltage perpendicular to the front surface of the semiconductor substrate to perform pretreatment. The pretreatment forms an electron aggregation region on the top of each of the first pattern structures and a positive ion aggregation region at the bottom of each of the first trenches. The electron aggregation region covers the top surface and the top corners of the first pattern structures; Step 3, deposit a first dielectric film by CVD process. Utilize the attraction of the electron aggregation region and the repulsion of the positive ion aggregation region to make the positively charged reactants in the CVD process enrich at the top corners of the first pattern structures, so that the growth rate of the first dielectric film at the top corners of the first trenches increases and the growth rate at the bottom of the first trenches decreases, causing the first dielectric film to be pinched off at the top opening of the first trench and forming an air gap isolation structure at the bottom of the pinch-off position; Step 4, perform planarization on the surface of the first dielectric film by chemical mechanical polishing process.

2. The manufacturing method of the air gap isolation structure as claimed in claim 1, characterized in that: The side surface of the first trench is inclined and the top opening width is greater than the bottom opening width.

3. The manufacturing method of the air gap isolation structure as claimed in claim 1, characterized in that: The semiconductor substrate includes a silicon substrate.

4. The manufacturing method of the air gap isolation structure as claimed in claim 3, characterized in that: The first pattern structure is a gate structure.

5. The manufacturing method of the air gap isolation structure as claimed in claim 4, characterized in that: The first pattern structure is a gate structure of a NAND flash memory.

6. The manufacturing method of the air gap isolation structure as claimed in claim 5, characterized in that: The gate structure includes a stacked structure of a floating gate dielectric layer, a polysilicon floating gate, an inter-gate dielectric layer, and a polysilicon control gate.

7. The manufacturing method of the air gap isolation structure as claimed in claim 6, characterized in that: A metal silicide is further formed on the top surface of the polysilicon control gate.

8. The manufacturing method of the air gap isolation structure as claimed in claim 1, characterized in that: In step 2, the non-film-forming gas is nitrogen, hydrogen or argon.

9. The manufacturing method of the air gap isolation structure as claimed in claim 1, characterized in that: In step 3, by increasing the lateral growth rate of the first dielectric film to reduce the surface coverage of the first dielectric film. The worse the surface coverage, the higher the pinch-off position.

10. The manufacturing method of the air gap isolation structure as claimed in claim 9, characterized in that: The material of the first dielectric film includes silicon dioxide or silicon nitride.

11. The manufacturing method of the air gap isolation structure as claimed in claim 1, characterized in that: The thickness of the first dielectric film above the pinch-off position is 10μm - 20μm.

12. The manufacturing method of the air gap isolation structure according to claim 6, characterized in that: In step one, silicon oxide sidewalls are further formed on the sides of the polysilicon floating gate and the polysilicon control gate.

13. The manufacturing method of the air gap isolation structure according to claim 12, characterized in that: The silicon oxide sidewalls are formed by thermally oxidizing the polysilicon floating gate and the polysilicon control gate.

14. The manufacturing method of the air gap isolation structure according to claim 1, characterized in that: Both step two and step three are carried out in a CVD process chamber, and the bias voltage is a negative voltage applied to the bottom of the semiconductor substrate.

15. The manufacturing method of the air gap isolation structure according to claim 1 or 14, characterized in that: The CVD process uses a PECVD process.

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