Semiconductor memory device and method of manufacturing the same

Abstract

Embodiments provide a semiconductor storage device with improved reliability and a manufacturing method thereof. According to the embodiments, there are provided: a first wiring layer (104_6); a first insulating layer (103_7) provided on the first wiring layer; a second wiring layer (104_7) provided on the first insulating layer; a second insulating layer (103_8) provided on the second wiring layer; a third wiring layer (104_8) provided on the second insulating layer; and a first pillar (LMP) that penetrates the first wiring layer, the first insulating layer, the second wiring layer, the second insulating layer, and the third wiring layer, and that includes a first semiconductor layer (114). A first step difference between a first face of the first wiring layer opposite the first pillar and a second face of the first insulating layer opposite the first pillar is greater than a second step difference between a third face of the second wiring layer opposite the first pillar and a fourth face of the second insulating layer opposite the first pillar, and a third step difference between the fourth face and a fifth face of the third wiring layer opposite the first pillar.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2021-49444 (filed on March 24, 2021). This application incorporates all the contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to semiconductor memory devices and methods for manufacturing the same. Background Technology

[0004] NAND flash memory is known as a semiconductor storage device. Summary of the Invention

[0005] One embodiment of the present invention provides a semiconductor memory device with improved reliability and a method for manufacturing the same.

[0006] The semiconductor memory device according to the embodiment includes: a first wiring layer; a first insulating layer disposed on the first wiring layer; a second wiring layer disposed on the first insulating layer; a second insulating layer disposed on the second wiring layer; a third wiring layer disposed on the second insulating layer; and a first pillar extending along a first direction, passing through the first wiring layer, the first insulating layer, the second wiring layer, the second insulating layer, and the third wiring layer, and containing a first semiconductor layer. A first order difference is greater than a second order difference and a third order difference. The first order difference is the order difference between the first surface of the first wiring layer opposite to the first pillar and the second surface of the first insulating layer opposite to the first pillar. The second order difference is the order difference between the third surface of the second wiring layer opposite to the first pillar and the fourth surface of the second insulating layer opposite to the first pillar. The third order difference is the order difference between the fourth surface and the fifth surface of the third wiring layer opposite to the first pillar. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating the semiconductor memory device according to the first embodiment.

[0008] Figure 2 This is a circuit diagram of the memory cell array according to the first embodiment.

[0009] Figure 3 This is a cross-sectional view of the memory cell array according to the first embodiment.

[0010] Figure 4 yes Figure 3 A magnified view of region RA.

[0011] Figure 5 It means along Figure 4A diagram of the plane of lines A1-A2, B1-B2, C1-C2, and D1-D2.

[0012] Figure 6 , Figure 7 This is a flowchart illustrating the manufacturing process of the memory cell array according to the first embodiment.

[0013] Figures 8 to 24 This is a cross-sectional view showing the manufacturing process of the memory cell array according to the first embodiment.

[0014] Figure 25 This is a cross-sectional view of the memory cell array according to the second embodiment.

[0015] Figure 26 yes Figure 25 A magnified view of region RB.

[0016] Figure 27 It means along Figure 26 A diagram of the plane of lines A1-A2, B1-B2, C1-C2, and D1-D2.

[0017] Figure 28 This is a flowchart illustrating the manufacturing process of the memory cell array according to the second embodiment.

[0018] Figure 29 This is a cross-sectional view showing the manufacturing process of the memory cell array according to the second embodiment.

[0019] Figure 30 This is a cross-sectional view of the memory cell array according to the third embodiment.

[0020] Figure 31 yes Figure 30 A magnified view of the RC region.

[0021] Figure 32 This is a flowchart illustrating the manufacturing process of the memory cell array involved in the third embodiment.

[0022] Figures 33-42 This is a cross-sectional view showing the manufacturing process of the memory cell array according to the third embodiment.

[0023] Figure 43 This is a cross-sectional view of the memory cell array involved in the variant example. Detailed Implementation

[0024] Hereinafter, embodiments will be described with reference to the accompanying drawings. Furthermore, in the following description, constituent elements having substantially the same function and structure will be labeled with the same reference numerals. Descriptions may be omitted where repetition is unnecessary. Additionally, the embodiments shown below exemplify apparatus and methods for embodying the technical concept of this embodiment. The technical concept of the embodiments does not specify the materials, shapes, structures, and arrangements of the constituent parts as described below. Various modifications can be made to the technical concept of the embodiments without departing from the spirit of the invention. These embodiments and their variations are included within the scope of the invention as described in the claims and its equivalents.

[0025] 1. First Implementation Method

[0026] The semiconductor memory device according to the first embodiment is described.

[0027] 1.1 Composition

[0028] 1.1.1 Overall Structure of Semiconductor Memory Devices

[0029] First, refer to Figure 1 An example of the overall structure of a semiconductor memory device will be given. Figure 1 This is an example of a block diagram representing the basic overall structure of a semiconductor memory device.

[0030] like Figure 1 As shown, the semiconductor memory device 1 is, for example, a three-dimensional stacked NAND flash memory. In a three-dimensional stacked NAND flash memory, non-volatile memory cell transistors are arranged three-dimensionally on a semiconductor substrate. The semiconductor memory device 1 includes a memory chip 10 and a control unit 20. The memory chip 10 is the central unit for operation in the semiconductor memory device 1. Data writing, reading, and erasing operations are performed in the memory chip 10. The control unit 20 is a circuit unit disposed around the memory chip 10. The control unit 20 performs data input / output to and from the memory chip 10 and controls the operations within the memory chip 10.

[0031] The internal structure of the memory chip 10 will now be described. The memory chip 10 includes a memory cell array 11, a row decoder 12, and a sense amplifier 13.

[0032] The memory cell array 11 is a region in three dimensions in which non-volatile memory cell transistors are arranged.

[0033] Storage cell array 11 has multiple block BLKs. Figure 1In the example, memory cell array 11 contains BLK0, BLK1, BLK2, and BLK3. A block BLK is, for example, a collection of multiple memory cell transistors whose data is erased together. A block BLK contains multiple memory cell transistors corresponding to rows and columns. Each block BLK contains multiple string cells SU. Figure 1 In the example, block BLK contains four serial cells SU0, SU1, SU2, and SU3. Serial cell SU, for example, contains a set of multiple NAND strings NS selected together in a write or read operation. Serial cell SU contains multiple NAND strings NS. NAND strings NS contain a set of multiple memory cell transistors connected in series. Furthermore, the number of blocks BLK within memory cell array 11 and the number of serial cells SU within a block BLK are arbitrary. Details of memory cell array 11 will be described later.

[0034] The row decoder 12 is a circuit that decodes the row address. The row decoder 12 receives row address-related information from an external controller. Based on the decoding result of the row address-related information, the row decoder 12 selects one of the blocks BLK. Then, the row decoder 12 supplies voltage to the row-direction wiring (word lines and select gate lines) of the selected block BLK.

[0035] The sensing amplifier 13 is a circuit that performs data writing and reading. When reading data, the sensing amplifier 13 reads data from the memory cell transistors of one of the blocks BLK. In addition, when writing data, the sensing amplifier 13 applies a voltage corresponding to the data being written to the memory cell array 11.

[0036] The internal structure of the control unit 20 will now be described. The control unit 20 includes a sequencer 21 and a voltage generation circuit 22.

[0037] The sequencer 21 is a circuit that controls the semiconductor memory device 1. The sequencer 21 controls the overall operation of the semiconductor memory device 1. More specifically, the sequencer 21 controls the voltage generation circuit 22, the line decoder 12, and the sense amplifier 13 during write, read, and erase operations.

[0038] The voltage generation circuit 22 generates voltages for write, read, and erase operations. The voltage generation circuit 22 supplies voltages to, for example, the line decoder 12 and the sense amplifier 13.

[0039] 1.1.2 Circuit configuration of memory cell array

[0040] Below, refer to Figure 2 This illustrates an example of the circuit configuration of the memory cell array 11. Furthermore, Figure 2 The example shows the circuit configuration of a BLK block.

[0041] like Figure 2 As shown, block BLK contains, for example, four string units SU0, SU1, SU2, and SU3. Each string unit SU contains multiple NAND strings NS. For example, n+1 NAND strings NS (n is an integer greater than or equal to 1) within string unit SU are connected to n+1 bit lines BL0 to BLn. Each NAND string NS contains multiple memory cell transistors MC, multiple dummy memory cell transistors MCD, and select transistors ST1 and ST2. Figure 2 In the example, the NAND string NS contains 12 memory cell transistors MC0 to MC11. Additionally, the NAND string NS contains two dummy memory cell transistors MCDL and MCDU. The number of memory cell transistors MC and dummy memory cell transistors MCD is arbitrary. There can also be zero dummy memory cell transistors MCD.

[0042] The memory cell transistor MC non-volatilely stores data. The dummy memory cell transistor MCD has the same structure as the memory cell transistor MC. The dummy memory cell transistor MCD is used for dummy operations and may not be used for data storage. Furthermore, data read from the dummy memory cell transistor MCD is not treated as valid data. Both the memory cell transistor MC and the dummy memory cell transistor MCD contain a control gate and a charge storage layer.

[0043] The memory cell transistor (MC) and the dummy memory cell transistor (MCD) can be either MONOS (Metal-Oxide-Nitride-Oxide-Silicon) or FG (Floating Gate) type. The MONOS type uses an insulating layer as the charge storage layer. The FG type uses a conductive layer as the charge storage layer. The following explanation focuses on the MONOS type case for both the memory cell transistor (MC) and the dummy memory cell transistor (MCD).

[0044] Selector transistors ST1 and ST2 are used to select the string unit SU during various operations. The number of selector transistors ST1 and ST2 is arbitrary. It is sufficient that there is at least one selector transistor ST1 and at least one ST2 in the NAND string NS.

[0045] The current paths of the memory cell transistors MC, dummy memory cell transistors MCD, and select transistors ST1 and ST2 within each NAND string NS are connected in series. More specifically, their current paths are connected in series in the following order: select transistor ST2, memory cell transistors MC0-MC5, dummy memory cell transistors MCDL, dummy memory cell transistors MCDU, memory cell transistors MC6-MC11, and select transistor ST1. The drain of select transistor ST1 is connected to a bit line BL. The source of select transistor ST2 is connected to the source line SL.

[0046] Within the same block BLK, the control gates of memory cell transistors MC0 to MC11 are commonly connected to word lines WL0 to WL11. Similarly, the control gates of dummy memory cell transistors MCDL and MCDU are commonly connected to dummy word lines WLDL and WLDU, respectively. More specifically, for example, block BLK contains four serial cells SU0 to SU3. Furthermore, each serial cell SU0 to SU3 contains multiple memory cell transistors MC0. The control gates of these multiple memory cell transistors MC0 within block BLK are commonly connected to one word line WL0. The same applies to memory cell transistors MC1 to MC11 and dummy memory cell transistors MCDL and MCDU.

[0047] The gates of multiple selection transistors ST1 within a series unit SU are connected to a common ground and a single selection gate line SGD. More specifically, series unit SU0 contains multiple selection transistors ST1. The gates of the multiple selection transistors ST1 within series unit SU0 are connected to a common ground and a selection gate line SGD0. Similarly, the gates of the multiple selection transistors ST1 within series unit SU1 are connected to a common ground and a selection gate line SGD1. The gates of the multiple selection transistors ST1 within series unit SU2 are connected to a common ground and a selection gate line SGD2. The gates of the multiple selection transistors ST1 within series unit SU3 are connected to a common ground and a selection gate line SGD3.

[0048] The gates of multiple select transistors ST2 within the same block BLK are connected to a common ground via a select gate line SGS. More specifically, for example, the block BLK contains four string cells SU0 to SU3. Each string cell SU0 to SU3 contains multiple select transistors ST2. The gates of these multiple select transistors ST2 within the block BLK are connected to a common ground via a select gate line SGS.

[0049] Word lines WL0 to WL11, dummy word lines WLDL and WLDU, select gate lines SGD0 to SGD3 and select gate line SGS are each connected to the line decoder 12.

[0050] Bit lines BL are commonly connected to one NAND string NS within each string cell SU of each block BLK. Multiple NAND strings NS connected to one bit line BL are assigned the same column address. Each bit line BL is connected to the sense amplifier 13.

[0051] Source lines (SLs) are shared, for example, across multiple block BLKs.

[0052] Within a single string unit SU, a collection of multiple memory cell transistors MC connected to a single word line WL is, for example, described as a "cell unit" (CU). For instance, if a memory cell transistor MC stores 1 bit of data, the storage capacity of a cell unit CU is defined as "1 page of data". Depending on the number of bits of data stored by the memory cell transistor MC, a cell unit CU can have a storage capacity of more than 2 pages of data.

[0053] 1.1.3 Cross-sectional structure of the memory cell array

[0054] Below, refer to Figure 3 This illustrates an example of the cross-sectional configuration of the storage cell array 11. Figure 3 The cross-sectional structure of one NAND string NS is shown. In the following description, the direction that is substantially parallel to the semiconductor substrate 100 is referred to as the X direction. The direction that is substantially parallel to the semiconductor substrate 100 and intersects the X direction is referred to as the Y direction. Furthermore, the direction that intersects both the X and Y directions and is substantially perpendicular to the semiconductor substrate 100 is referred to as the Z direction.

[0055] like Figure 3 As shown, an insulating layer 101 is formed on the semiconductor substrate 100. A wiring layer 102 is disposed on the insulating layer 101. The insulating layer 101 is, for example, silicon oxide (SiO) containing oxygen and silicon. In addition, circuitry such as a line decoder 12 or a sense amplifier 13 may be disposed in the region where the insulating layer 101 is formed, i.e., between the semiconductor substrate 100 and the wiring layer 102.

[0056] Wiring layer 102 extends in both the X and Y directions. Wiring layer 102 functions as the source line SL. Wiring layer 102 contains a conductive material. The conductive material may be a metal or an n-type semiconductor. An n-type semiconductor is a semiconductor formed by adding impurities such as phosphorus (P) or arsenic (As) to a semiconductor material such as silicon (Si).

[0057] Above the wiring layer 102, multiple insulation layers 103 and multiple wiring layers 104 are stacked alternately, one layer at a time. Figure 3In this example, the eight insulating layers 103_1 to 103_8 and the eight wiring layers 104_1 to 104_8 are stacked alternately, one layer at a time. More specifically, wiring layer 104_1 is disposed on top of insulating layer 103_1. Insulating layer 103_2 is disposed on top of wiring layer 104_1. Wiring layer 104_2 is disposed on top of insulating layer 103_2. Insulating layer 103_3 is disposed on top of wiring layer 104_2. Wiring layer 104_3 is disposed on top of insulating layer 103_3. Insulating layer 103_4 is disposed on top of insulating layer 103_4. Wiring layer 104_4 is disposed on top of wiring layer 104_4. Insulating layer 103_5 is disposed on top of insulating layer 103_5. Wiring layer 104_5 is disposed on top of insulating layer 103_5. An insulation layer 103-6 is provided above the wiring layer 104-6. An insulation layer 103-7 is provided above the wiring layer 104-6. An insulation layer 104-7 is provided above the insulation layer 103-7. An insulation layer 103-8 is provided above the wiring layer 104-8.

[0058] For example, wiring layer 104_1 functions as the select gate line (SGS). Wiring layers 104_2 to 104_7 function as word lines WL0 to WL5, respectively. Wiring layer 104_8 functions as the dummy word line (WLDL).

[0059] An insulation layer 105 is provided above the wiring layer 104-8.

[0060] Above the insulation layer 105, multiple wiring layers 106 and multiple insulation layers 107 are stacked alternately, one layer at a time. Figure 3In this example, the eight wiring layers 106_1 to 106_8 and the eight insulation layers 107_1 to 107_8 are stacked alternately, one layer at a time. More specifically, an insulation layer 107_1 is disposed on top of wiring layer 106_1. A wiring layer 106_2 is disposed on top of insulation layer 107_1. An insulation layer 107_2 is disposed on top of wiring layer 106_2. A wiring layer 106_3 is disposed on top of insulation layer 106_3. An insulation layer 107_3 is disposed on top of wiring layer 106_3. A wiring layer 106_4 is disposed on top of insulation layer 107_4. An insulation layer 107_4 is disposed on top of insulation layer 107_4. A wiring layer 106_5 is disposed on top of wiring layer 106_5. An insulation layer 107_5 is disposed on top of wiring layer 106_5. A wiring layer 106-6 is disposed above the insulation layer 107-5. An insulation layer 107-6 is disposed above the wiring layer 106-6. A wiring layer 106-7 is disposed above the insulation layer 107-6. An insulation layer 107-7 is disposed above the wiring layer 106-7. A wiring layer 106-8 is disposed above the insulation layer 107-7. An insulation layer 107-8 is disposed above the wiring layer 106-8.

[0061] For example, wiring layer 106_1 functions as the dummy word line WLDU. Wiring layers 106_2 to 106_7 function as word lines WL6 to WL11, respectively. Wiring layer 106_8 functions as the select gate line SGD.

[0062] An insulating layer 108 is provided above the insulating layer 107-8.

[0063] The insulating layers 103_1 to 103_8, 105, 107_1 to 107_8, and 108 are, for example, made of SiO. The wiring layers 104_1 to 104_8 and 106_1 to 106_8 contain a conductive material. Metallic materials, n-type semiconductors, or p-type semiconductors can also be used as the conductive material. A p-type semiconductor is a semiconductor formed by adding impurities such as boron (B) to a semiconductor material such as Si. Hereinafter, the case where a stacked structure of titanium nitride (TiN) and tungsten (W) is used as the conductive material for wiring layers 104_1 to 104_8 and 106_1 to 106_8 will be described. TiN is formed by covering W. TiN functions as a barrier layer, for example, to suppress the reaction between W and SiO when W is formed by CVD (chemical vapor deposition), or as an adhesive layer to improve the adhesion of W. Wiring layers 104_1 to 104_8 and 106_1 to 106_8 may contain a high-dielectric-constant material such as alumina (AlO) containing oxygen and aluminum. In this case, the high-dielectric-constant material is formed in a manner that covers the conductive material. For example, in each wiring layer 104 and 106, AlO is provided in a manner that is in contact with the sides of the insulating layer and the storage pillar MP provided above and below the wiring layer. Then, TiN is provided in a manner that is in contact with AlO. Then, W is provided in a manner that is in contact with TiN and fills the interior of the wiring layer.

[0064] Multiple memory columns (MPs) are arranged within the memory cell array 11. One memory column (MP) corresponds to one NAND string (NS). The memory column (MP) passes through wiring layers 104_1 to 104_8 and 106_1 to 106_8. The bottom surface of the memory column (MP) reaches wiring layer 102. The memory column (MP) contains three columns, such as a lower memory column (LMP), a connector (JC), and an upper memory column (UMP). Alternatively, the memory column (MP) may contain four or more columns.

[0065] The lower memory module (LMP) passes through (penetrates) insulating layers 103-1 to 103-8 and wiring layers 104-1 to 104-8. The bottom surface of the lower memory module (LMP) reaches the wiring layer 102. In this embodiment, the upper end of the lower memory module (LMP) is higher than the lower surface of the insulating layer 105. Furthermore, the upper end of the lower memory module (LMP) is lower than the upper surface of the insulating layer 105. The lower memory module (LMP) has a generally cylindrical shape extending along the Z-direction. Furthermore, the shape of the plane (XY plane) of the lower memory module (LMP) can be circular or rectangular. The cross-sectional shape of the lower memory module (LMP) depends on the manufacturing process (dry etching processing characteristics). For example, the length of the lower memory module (LMP) in the Y-direction is [value missing], compared to the end portion [value missing], the central portion [value missing]. Figure 3In the example, the area near the insulation layer 103_7 and the wiring layer 104_7 is longer. Additionally, the length of the lower storage column (LMP) in the Y direction is shorter at the bottom than at the top.

[0066] In this embodiment, the lower storage column (LMP) has multiple protrusions PR1 on its side at the same layer as wiring layers 104_1 to 104_6. These protrusions PR1 extend from the center of the lower storage column (the central axis extending along the Z direction) toward the wiring layers 104_1 to 104_6. On the other hand, the lower storage column (LMP) does not have protrusions PR1 on its side at the same layer as the uppermost layer 104_8 and the second wiring layer 104_7 (the layer above the uppermost layer). Furthermore, regarding the number of wiring layers 104 where protrusions PR1 are not provided at the same layer, it is sufficient that there are two or more layers counting from the uppermost wiring layer 104 (wiring layer 104_8 in this embodiment). Additionally, due to manufacturing deviations, the lower storage column (LMP) may have minor irregularities compared to the protrusions PR1 at the same layer as wiring layers 104_7 and the uppermost layer 104_8.

[0067] The connector JC is disposed on the lower storage column LMP at the same layer as the insulating layer 105. The planar shape of the connector JC can be circular or rectangular. The length of the connector JC in the Y direction is longer than the length of the upper end of the lower storage column LMP. The connector JC and the uppermost wiring layer 104 (104_8) corresponding to the lower storage column LMP are adjacent in the Z direction via the insulating layer 105.

[0068] The upper storage column UMP passes through (penetrates) wiring layers 106_1 to 106_8 and insulation layers 107_1 to 107_8. The bottom surface of the upper storage column UMP is in contact with the connecting portion JC. The upper storage column UMP has a generally cylindrical shape extending along the Z direction. Furthermore, the planar shape of the upper storage column UMP can be either circular or rectangular. The cross-sectional shape of the upper storage column UMP depends on the manufacturing process. For example, similar to the lower storage column LMP, the length in the Y direction of the upper storage column UMP is [value missing], compared to the end portion [value missing], the central portion [value missing]. Figure 3 In the example, the area near the insulating layer 107_6 and the wiring layer 106_7 is longer. Furthermore, the length of the upper storage column UMP in the Y direction is shorter at the lower end than at the upper end. In this embodiment, the upper storage column UMP has a protrusion PR1 on its side at the same layer as the wiring layers 106_1 to 106_8. Multiple protrusions PR1 of the upper storage column UMP protrude from the center of the upper storage column UMP toward the wiring layers 106_1 to 106_8.

[0069] The internal structure of the storage column MP is described below. The storage column MP contains a block insulating film 111, a charge storage layer 112, a tunnel insulating film 113, a semiconductor layer 114, a core layer 115, and a capping layer 116.

[0070] More specifically, on the sides of the storage pillars MP (lower storage pillar LMP, connector JC, and upper storage pillar UMP), a block insulating film 111, a charge storage layer 112, and a tunnel insulating film 113 are sequentially stacked from the outside. A semiconductor layer 114 is disposed in contact with the sides of the tunnel insulating film 113 and the wiring layer 102. The semiconductor layer 114 is the region where the channels for the storage cell transistor MC, the dummy storage cell transistor MCD, and the select transistors ST1 and ST2 are formed. The interior of the semiconductor layer 114 is filled with a core layer 115. Figure 3 In this example, a cavity VD is formed inside the core layer 115. The shape of the cavity VD depends on the shape of the memory pillar MP and the manufacturing process. Alternatively, the cavity VD may not be formed. Above the memory pillar MP (upper memory pillar UMP), a capping layer 116 is formed above the semiconductor layer 114 and the core layer 115. The bottom surface of the capping layer 116 is at a higher height than the upper surface of the uppermost wiring layer 106 (106_8). The side of the capping layer 116 is in contact with the tunnel insulating film 113.

[0071] By combining the storage pillar MP with wiring layers 104_2 to 104_7 and 106_2 to 106_7, memory cell transistors MC0 to MC11 are formed. Thus, memory cell transistors MC0 to MC4 and MC6 to MC11 contain a protrusion PR1. Similarly, by combining the storage pillar MP with wiring layers 104_8 and 106_1, dummy memory cell transistors MCDL and MCDU are formed. Thus, dummy memory cell transistor MCDU contains a protrusion PR1. By combining the storage pillar MP with wiring layer 104_1, a select transistor ST2 is formed. By combining the storage pillar MP with wiring layer 106_8, a select transistor ST1 is formed. Thus, select transistors ST1 and ST2 contain a protrusion PR1.

[0072] In the block insulating film 111, tunnel insulating film 113, and core layer 115, SiO is used as an insulating material, for example. Silicon nitride (SiN) is used, for example, in the charge storage layer 112. Polycrystalline silicon is used, for example, in the semiconductor layer 114. An n-type semiconductor is used, for example, in the capping layer 116.

[0073] A contact plug 117 is provided on the cover layer 116 at the same layer as the insulating layer 108. A wiring layer 109 is provided on the contact plug 117. The wiring layer 109 functions as a bit line BL. The wiring layer 109 extends along the Y direction. The contact plug 117 and the wiring layer 109 contain a conductive material. As a conductive material, for example, a laminated structure of titanium (Ti), TiN, and W, or copper wiring, etc., are used.

[0074] 1.1.4 Shape of the wiring layer and insulation layer connected to the storage column MP

[0075] Below, refer to Figure 4 and Figure 5 This describes the shape of the wiring layer and insulation layer that are connected to the storage column MP. Figure 4 yes Figure 3 A magnified view of region RA. Figure 5 Show along Figure 4 Plan view of lines A1-A2, B1-B2, C1-C2, and D1-D2. Furthermore, in Figure 4 and Figure 5 In the example, the storage column MP has been omitted for simplicity. The side views of each layer show the faces opposite to the storage column MP. Additionally, in Figure 4 In the example, for the sake of simplicity, the sides of each layer are shown as extending along the Z direction.

[0076] Hereinafter, the plane along line A1-A2 will be referred to as plane A. The plane along line B1-B2 will be referred to as plane B. The plane along line C1-C2 will be referred to as plane C. The plane along line D1-D2 will be referred to as plane D. Plane A shows the plane along insulating layer 103-8. Plane B shows the plane along wiring layer 104-7. Plane C shows the plane along insulating layer 103-7. Plane D shows the plane along wiring layer 104-6. Furthermore, in the following description, the phrase "approximately equal" may include shape deviations caused by etching processes, etc.

[0077] like Figure 4 and Figure 5 As shown, the widths of the opposite sides of insulating layers 103_6, 103_7, and 103_8 in the Y direction are respectively denoted as L103_6, L103_7, and L103_8. The widths of the opposite sides of wiring layers 104_6, 104_7, and 104_8 in the Y direction are respectively denoted as L104_6, L104_7, and L104_8. Widths L104_6, L104_7, and L104_8 respectively indicate the diameters of the memory pillar MP at portions of memory cell transistors MC4 and MC5 and the dummy memory cell transistor MCDL, when the cross-sectional shape of the memory pillar MP in the XY plane is circular. Furthermore, the widths of the opposite sides of wiring layers 106_1 and 106_2 in the Y direction are respectively denoted as L106_1 and L106_2. Widths L106_1 and L106_2 respectively indicate the diameters of the memory pillar MP at portions of the dummy memory cell transistor MCDU and memory cell transistor MC6, when the cross-sectional shape of the memory pillar MP in the XY plane is circular. The width of the opposite sides of the insulating layer 107_1 in the Y direction is described as L107_1.

[0078] In this embodiment, widths L103_6, L103_7, and L103_8 are approximately equal. Additionally, widths L104_7 and L104_8 are approximately equal. Furthermore, width L104_6 is longer than both widths L104_7 and L104_8.

[0079] At the same layer as wiring layers 104_1 to 104_6, a protrusion PR1 is provided on the side of the lower storage column LMP. Therefore, the width L104_6 is longer than the widths L103_6 and L103_7. As a result, the sides of insulating layers 103_6 and 103_7 protrude relative to the side of wiring layer 104_6. In other words, the side of wiring layer 104_6 is recessed relative to the sides of insulating layers 103_6 and 103_7. Hereinafter, the concave region formed by the wiring layer and the insulating layers disposed above and below it will be described as a "groove region". The groove region corresponds to the shape of the protrusion of the storage column MP. More specifically, the groove region is formed by the side of wiring layer 104_6, the step difference between the lower end of wiring layer 104_6 and the upper end of insulating layer 103_6, and the step difference between the upper end of wiring layer 104_6 and the lower end of insulating layer 103_7. Figure 5 As shown in plane D, when the cross-sectional shape of the storage column MP in the XY plane is circular, the groove region has, for example, an annular shape. For example, let the step difference (groove width of the groove region) between the wiring layer 104_6 and the insulating layer 103_7 (or 103_6) be W1. The step difference W1 can be expressed by the width L104_6 and the width L103_7 as W1 = [(L104_6) - (L103_7)] / 2.

[0080] At the same level as wiring layer 104_7, no protrusion PR1 is provided on the side of the lower storage column LMP. Therefore, there is almost no step difference between the upper end of insulating layer 103_7 and the lower end of wiring layer 104_7, and between the upper end of wiring layer 104_7 and the lower end of insulating layer 103_8. In other words, the sides of insulating layer 103_7, wiring layer 104_7, and insulating layer 103_8 are arranged approximately flat in the Z direction. Alternatively, the sides of insulating layer 103_7, wiring layer 104_7, and insulating layer 103_8 are positioned approximately the same in the Y direction. Therefore, the widths L103_7, L104_7, and L103_8 are approximately equal. For example, let the step difference between wiring layer 104_7 and insulating layer 103_8 (or 103_7) be W2. The step difference W2 is approximately 0. Therefore, the step difference W2 can be expressed using widths L104_7 and L103_8 (or L103_7) as W2 = [(L104_7) - (L103_8)] / 2 = [(L104_7) - (L103_7)] / 2 ≒ 0. Alternatively, in an ideal case, it can be expressed as W2 = [(L104_7) - (L103_8)] / 2 = [(L104_7) - (L103_7)] / 2 = 0.

[0081] Similarly, there is almost no step difference between the upper end of the insulation layer 103_8 and the lower end of the wiring layer 104_8. In other words, the sides of the wiring layer 104_8 and the insulation layer 103_8 are arranged approximately flat in the Z direction. Alternatively, the sides of the wiring layer 104_8 and the insulation layer 103_8 are positioned approximately the same in the Y direction. Thus, the widths L103_8 and L104_8 are approximately equal. For example, let the step difference between the insulation layer 103_8 and the wiring layer 104_8 be W3. The step difference W3 is approximately 0. Therefore, the step difference W3 can be expressed using the widths L103_8 and L104_8 as W3 = [(L104_8) - (L103_8)] / 2 ≒ 0. Alternatively, ideally, it can be expressed as W3 = [(L104_8) - (L103_8)] / 2 = 0. Therefore, the groove widths (step differences) W1, W2, and W3 have the relationships W1 > W2 and W1 > W3. Hereinafter, the area on the side of the insulating layer 103 and the wiring layer 104 where almost no step difference is provided between the insulating layer 103 and the wiring layer 104 will be described as a "flat area". Figure 4 In the example, the side of insulation layer 103_7, the side of wiring layer 104_7, the side of insulation layer 103_8, and the side of wiring layer 104_8 are contained within a flat area.

[0082] At the same level as wiring layers 106_1 to 106_8, a protrusion PR1 is provided on the side of the upper storage column UMP. Let the step difference between wiring layer 106_1 and insulating layer 107_1 be W4. The step difference W4 can be expressed using widths L106_1 and L107_1 as W4 = [(L106_1) - (L107_1)] / 2. Similarly, let the step difference between wiring layer 106_2 and insulating layer 107_1 be W5. The step difference W5 can be expressed using widths L106_2 and L107_1 as W5 = [(L106_2) - (L107_1)] / 2. Step differences W4 and W5 correspond to the protrusion PR1 of the upper storage column UMP, respectively. Therefore, step differences W4 and W5 are approximately equal. Furthermore, the manufacturing processes for the recessed region corresponding to the lower storage column (LMP) and the recessed region corresponding to the upper storage column (UMP) are different. Therefore, the step W1 can be the same length as the step W4 and the step W5, or it can be a different length. Moreover, the steps W2 and W3, and the steps W4 and W5, have the relationships W2 < W4, W3 < W4, W2 < W5, and W3 < W5.

[0083] 1.2 Manufacturing Method of Memory Cell Array

[0084] Next, use Figures 6 to 24 This is an example illustrating the manufacturing method of the storage cell array 11. Figure 6 and Figure 7 This is a flowchart illustrating the manufacturing process of the storage cell array 11. Figures 8 to 24 They represent respectively with Figure 6 and Figure 7 The flowchart shows a cross-sectional view of the memory cell array 11 corresponding to steps S1 to S17. Hereinafter, as a method for forming wiring layers 104 and 106, a replacement method will be described whereby a structure equivalent to wiring layers 104 and 106 is formed using a sacrificial layer, and then the sacrificial layer is removed to replace it with wiring layers 104 and 106. Furthermore, the description of the photolithography process is omitted in the following explanation.

[0085] like Figure 8 As shown, multiple insulating layers 103, multiple sacrificial layers 120, and an insulating layer 105 are first formed. Figure 6Step S1). More specifically, an insulating layer 101 is formed on the semiconductor substrate 100. Additionally, a wiring layer 102 is formed on the insulating layer 101. In this state, for example, eight insulating layers 103_1 to 103_8 and eight sacrificial layers 120_1 to 120_8 are alternately stacked on the wiring layer 102, one layer at a time. For example, an insulating layer 103_1 is formed on the wiring layer 102. A sacrificial layer 120_1 is formed on the insulating layer 103_1. An insulating layer 103_2 is formed on the sacrificial layer 120_1. A sacrificial layer 120_2 is formed on the insulating layer 103_2. An insulating layer 103_3 is formed on the sacrificial layer 120_2. A sacrificial layer 120_3 is formed on the insulating layer 103_3. An insulating layer 103_4 is formed on the sacrificial layer 120_3. A sacrificial layer 120_4 is formed on the insulating layer 103_4. An insulating layer 103-5 is formed on the sacrificial layer 120-4. A sacrificial layer 120-5 is formed on the insulating layer 103-5. An insulating layer 103-6 is formed on the sacrificial layer 120-5. A sacrificial layer 120-6 is formed on the insulating layer 103-6. An insulating layer 103-7 is formed on the sacrificial layer 120-7. An insulating layer 103-8 is formed on the sacrificial layer 120-7. A sacrificial layer 120-8 is formed on the insulating layer 103-8. Then, an insulating layer 105 is formed on top of the uppermost sacrificial layer 120-8.

[0086] Sacrificial layers 120_1 to 120_8 correspond to wiring layers 104_1 to 104_8, respectively. Sacrificial layers 120_1 to 120_8 are subsequently replaced by wiring layers 104_1 to 104_8, respectively. The sacrificial layers 120 (120_1 to 120_8) use a material that provides a sufficient wet etching selectivity relative to the insulating layers 103 (103_1 to 103_8). Hereinafter, the case where the sacrificial layer 120 uses SiN containing nitrogen and silicon will be described.

[0087] Figure 9 As shown, a hole is formed in LMH ( Figure 6 (Step S2). The via LMH corresponds to the lower storage column LMP. More specifically, the via LMH penetrates 8 insulating layers 103_1 to 103_8, 8 sacrificial layers 120_1 to 120_8, and insulating layer 105. The bottom surface of the via LMH reaches the wiring layer 102. Furthermore, the shape of the opening of the via LMH is not limited to a circle (perfect circle). The shape of the opening of the via LMH can also be elliptical or rectangular. In addition, the cross-sectional shape of the via LMH can be conical, straight along the Z-direction, or arcuate.

[0088] like Figure 10 As shown, the sacrificial layer 120 is etched into grooves. Figure 6Step S3). More specifically, wet etching is performed on the side surface of the sacrificial layer 120 exposed within the hole LMH. This forms a groove region extending from the hole LMH. When the cross-sectional shape of the hole LMH in the XY plane is circular, the groove region extends from the hole LMH in a concentric circle. At this time, the wet etching conditions are set such that the etching rate of the sacrificial layer 120 is higher than that of the insulating layer 103. For example, when the sacrificial layer 120 is SiN, wet etching using phosphoric acid (H3PO4) is performed. Hereinafter, the process of forming a groove region by wet etching the side surface of the hole will be described as "groove etching".

[0089] like Figure 11 As shown, sacrificial layer 121 is used to fill the holes LMH ( Figure 6 Step S4). The sacrificial layer 121 uses a material that can achieve a sufficient wet etching selectivity relative to the insulating layer 103 and the sacrificial layer 120. Hereinafter, the case where the sacrificial layer 121 is made of amorphous silicon will be described.

[0090] like Figure 12 As shown, the sacrificial layer 121 is processed until sacrificial layers 120_7 and 120_8 are exposed. Figure 6 Step S5). More specifically, for example, the sacrificial layer 121 is etched by isotropic etching such as wet etching or CDE (Chemical Dry Etching) until sacrificial layers 120_7 and 120_8 are exposed on the side of the via LMH. Sacrificial layers 120_7 and 120_8 correspond to wiring layers 104_7 and 104_8 in the flat region. At this time, the etching conditions are set to a higher etching rate for sacrificial layer 121 compared to insulating layer 103, insulating layer 105, and sacrificial layer 120. For example, if sacrificial layer 121 is amorphous silicon, wet etching using hydrofluoric acid (HF) is performed.

[0091] like Figure 13 As shown, sacrificial layer 122 is selectively grown on sacrificial layers 120_7 and 120_8. Figure 6Step S6). More specifically, for example, sacrificial layer 122 is formed on the sides of sacrificial layers 120_7 and 120_8 exposed on the sides of the via LMH by selective CVD. In this case, the film thickness of sacrificial layer 122 is preferably such that there is (almost) no step difference between the side of sacrificial layer 122 exposed in the via LMH and the side of insulating layer 103_8. In other words, the side of insulating layer 103_6, the side of sacrificial layer 122 on sacrificial layer 120_7, the side of sacrificial layer 122 on sacrificial layer 120_8, and the side of insulating layer 103_8 are arranged in a manner that becomes substantially flat in the Z direction. Alternatively, the Y-direction position of the side of sacrificial layer 122 is substantially the same as the Y-direction position of the sides of insulating layers 103_6, 103_7, and 103_8. The sacrificial layer 122 uses a material that allows for a sufficient wet etching selectivity relative to insulating layer 103. The sacrificial layer 122 is preferably made of the same material as the sacrificial layer 120. By making the sacrificial layers 120 and 122 the same material, both sacrificial layers 120 and 122 can be removed together by wet etching. Hereinafter, the case where the sacrificial layer 122 is made of SiN will be explained.

[0092] like Figure 14 As shown, the upper part of the hole LMH is filled using the sacrificial layer 123. Figure 6 Step S7). The sacrificial layer 123 is made of a material that provides a sufficient wet etching selectivity relative to the insulating layer 103 and the sacrificial layer 120. The sacrificial layer 123 is preferably made of the same material as the sacrificial layer 121. By making the sacrificial layers 121 and 123 the same material, the sacrificial layers 121 and 123 can be removed together by wet etching. Hereinafter, the case where the sacrificial layer 123 is made of amorphous silicon will be described.

[0093] like Figure 15 As shown, a portion of the sacrificial layer 123 within the insulating layer 105 is removed by, for example, wet etching or CDE. Figure 6 (Step S8). At this time, the etching amount of the sacrificial layer 123 is adjusted so that the height of the upper end of the sacrificial layer 123, which is in contact with the side of the hole LMH, is higher than the bottom surface of the insulating layer 105. That is, the sacrificial layer 123 in the insulating layer 105 is not completely removed. As a result, the side of the uppermost sacrificial layer 120_8 is not exposed on the side of the hole LMH. The etching condition is set to a condition where the etching rate of the sacrificial layer 123 is higher than that of the insulating layer 105.

[0094] like Figure 16 As shown, a region corresponding to the connecting portion JC (hereinafter referred to as the "JC region") is formed within the insulating layer 105. Figure 6Step S9). For example, isotropic etching of the insulating layer 105 is performed by wet etching. As a result, the film thickness of the insulating layer 105 is reduced. In addition, the width of the holes LMH within the insulating layer 105 is increased. Furthermore, when the cross-sectional shape of the holes LMH within the insulating layer 105 in the XY plane is circular, the width of the holes LMH within the insulating layer 105 is increased in a concentric circle shape. At this time, the etching conditions are set to a condition where the etching rate of the insulating layer 105 is higher than that of the sacrificial layer 123.

[0095] like Figure 17 As shown, the JC area is filled using sacrificial layer 124. Figure 6 Step S10). The sacrificial layer 124 is made of a material that provides a sufficient wet etching selectivity relative to the insulating layer 103 and the sacrificial layer 120. The sacrificial layer 124 is preferably made of the same material as the sacrificial layers 121 and 123. By making the sacrificial layers 121, 123 and 124 the same material, the sacrificial layers 121, 123 and 124 can be removed together by wet etching. Hereinafter, the case where the sacrificial layer 124 is made of amorphous silicon will be described. After the sacrificial layer 124 is formed, the sacrificial layer 124 on the insulating layer 105 is removed, for example, by CMP (Chemical Mechanical Polishing).

[0096] like Figure 18 As shown, multiple sacrificial layers 125 and multiple insulating layers 107 are alternately stacked on the insulating layer 105 and the sacrificial layer 124, one layer at a time. Figure 7 Step S11). More specifically, for example, eight sacrificial layers 125_1 to 125_8 and eight insulating layers 107_1 to 107_8 are alternately stacked one layer at a time. For example, sacrificial layer 125_1 is formed on insulating layer 105 and sacrificial layer 124. Insulating layer 107_1 is formed on sacrificial layer 125_1. Sacrificial layer 125_2 is formed on insulating layer 107_2. Insulating layer 107_2 is formed on insulating layer 107_2. Sacrificial layer 125_3 is formed on insulating layer 107_3. Insulating layer 107_3 is formed on sacrificial layer 107_3. Sacrificial layer 125_4 is formed on insulating layer 107_4. Insulating layer 107_4 is formed on sacrificial layer 107_4. Sacrificial layer 125_5 is formed on insulating layer 107_5. Insulating layer 107_5 is formed on sacrificial layer 125_5. A sacrificial layer 125-6 is formed on top of the insulating layer 107-5. An insulating layer 107-6 is formed on top of the sacrificial layer 125-6. A sacrificial layer 125-7 is formed on top of the insulating layer 107-6. An insulating layer 107-7 is formed on top of the sacrificial layer 125-7. A sacrificial layer 125-8 is formed on top of the insulating layer 107-7. An insulating layer 107-8 is formed on top of the sacrificial layer 125-8.

[0097] Sacrificial layers 125_1 to 125_8 correspond to wiring layers 106_1 to 106_8, respectively. Sacrificial layers 125_1 to 125_8 are subsequently replaced by wiring layers 106_1 to 106_8, respectively. Sacrificial layers 125 (125_1 to 125_8) are made of a material that provides a sufficient wet etching selectivity relative to insulating layers 107 (107_1 to 107_8). Sacrificial layer 125 is preferably made of the same material as sacrificial layer 120. By making sacrificial layers 120 and 125 the same material, sacrificial layers 120 and 125 can be removed together by wet etching. The following explanation addresses the case where sacrificial layer 125 uses SiN.

[0098] like Figure 19 As shown, a hole UMH is formed on the sacrificial layer 124. Figure 7 (Step S12). The UMH via corresponds to the upper storage column UMP. More specifically, the UMH penetrates 8 sacrificial layers 125_1 to 125_8 and 8 insulating layers 107_1 to 107_8. The bottom surface of the UMH reaches the sacrificial layer 124. Furthermore, the shape of the opening of the UMH is not limited to a circle (perfect circle). The shape of the opening of the UMH can also be elliptical or rectangular. In addition, the cross-sectional shape of the UMH can be conical, linear, or arc-shaped.

[0099] like Figure 20 As shown, the groove etching of the sacrificial layer 125 is performed. Figure 7 Step S13). More specifically, wet etching is performed on the side surface of the sacrificial layer 125 exposed within the UMH. This forms a groove region from the UMH. When the cross-sectional shape of the UMH in the XY plane is circular, the groove region extends from the UMH in a concentric circle. At this time, the etching condition is set such that the etching rate of the sacrificial layer 125 is higher than that of the insulating layer 107 and the sacrificial layer 124. Furthermore, the groove width of the groove region in the UMH can be the same as or different from the groove width of the groove region in the LMH.

[0100] like Figure 21 As shown, sacrificial layers 121, 123, and 124 were removed by wet etching. Figure 7 (Step S14). At this time, the etching conditions are set such that the etching rates of sacrificial layers 121, 123, and 124 are higher than those of wiring layers 102, insulating layers 103, 105, and 107, and sacrificial layers 120 and 125. Thus, via MH is formed. Via MH corresponds to memory pillar MP.

[0101] like Figure 22 As shown, the lower storage column LMP, the connecting part JC, and the upper storage column UMP are formed together. Figure 7 Step S15). More specifically, firstly, block insulating films 111, charge storage layers 112, and tunnel insulating films 113, each with a thickness not used to fill the via MH, are sequentially stacked. Then, the block insulating films 111, charge storage layers 112, and tunnel insulating films 113 on the insulating layers 107-8 and the bottom surface of the via MH are removed by anisotropic etching, such as RIE (Reactive Ion Etching). This exposes the wiring layer 102 on the bottom surface of the via MH. Then, a semiconductor layer 114 and a core layer 115 are sequentially formed. The semiconductor layer 114 is connected to the wiring layer 102. Thus, the via MH is filled. In the case where SiO is formed using CVD for the core layer 115, a void VD is formed within the core layer 115, corresponding to the shape of the via MH and the step coverage of the SiO. Then, the semiconductor layer 114 and the core layer 115 on the insulating layers 107-8 are removed. At this time, the semiconductor layer 114 and core layer 115 on top of the via MH are also removed. Then, the capping layer 116 is formed in a manner that fills the top of the via MH. After the capping layer 116 is formed, the capping layer 116 on the insulating layer 107-8 is removed by, for example, CMP. Thus, the memory pillar MP is formed. After the memory pillar MP is formed, the insulating layer 108 is formed on the insulating layer 107-8 and the memory pillar MP.

[0102] Then, in Figure 7 In steps S16 and S17, the substitution is performed.

[0103] like Figure 23 As shown, firstly, sacrificial layers 120, 122, and 125 are removed by wet etching. Figure 7 Step S16). More specifically, firstly, in an area not shown, slits are formed that expose sacrificial layers 120 and 125 on the sides. That is, the slits penetrate (pass through) sacrificial layers 120-1 to 120-8 and sacrificial layers 125-1 to 125-8. After the slits are formed, sacrificial layers 120, 122, and 125 are removed from the sides of the slits by wet etching. At this time, the etching conditions are set to conditions where the etching rate of sacrificial layers 120, 122, and 125 is higher than that of insulating layers 103, 105, and 107, and block insulating film 111. As a result, voids GP corresponding to wiring layers 104-1 to 104-8 and wiring layers 106-1 to 106-8 are formed.

[0104] like Figure 24 As shown, wiring layers 104 and 106 are formed. Figure 7Step S17). For example, when TiN and W are used in the laminated structure of wiring layers 104 and 106, TiN is filmed from the side of the slit within the void GP. At this time, the film thickness of TiN is the same as the film thickness without filling the void GP. Then, W is filmed to fill the void GP. Then, W and TiN on the side of the slit and on the insulating layer 108 are removed. Thus, wiring layers 104_1 to 104_8 and wiring layers 106_1 to 106_8 are formed together.

[0105] 1.3 Effects of this implementation method

[0106] According to the configuration described in this embodiment, a semiconductor memory device with improved reliability can be provided. This effect will be described in detail.

[0107] For example, the topmost wiring layer 104 (dummy word line WLDL) of the lower memory cell (LMP) is adjacent to the connection portion JC in the Z direction. Therefore, during the erase operation, when the same voltage is applied to each wiring layer 104, there is a tendency for the electric field strength of the topmost wiring layer 104 to be stronger than that of the other wiring layers 104. If the electric field strength of the topmost wiring layer 104 is strong, charge may be injected into the charge storage layer from the gate side of the topmost wiring layer 104. This phenomenon will be described as reverse tunneling. If reverse tunneling occurs, the threshold voltage of the dummy memory cell transistor MCDL corresponding to the topmost wiring layer 104 will rise even during the erase operation. Therefore, erroneous operation may occur. As a countermeasure to this phenomenon, there is a method to make the voltage applied to the topmost wiring layer 104 higher than that of the other wiring layers 104 during the erase operation. However, in this situation, a voltage difference will occur between the topmost wiring layer 104 and the wiring layer 104 below it. Therefore, for example, if a protrusion is provided on the storage column MP at the same layer as the wiring layer 104 below it, the electric field will concentrate at the corner of the protrusion. As a result, reverse tunneling is likely to occur in the wiring layer 104 below it.

[0108] In contrast, according to the configuration of this embodiment, the lower storage column LMP, when on the same layer as the uppermost wiring layer 104 (104_8) and the wiring layer 104 (104_7) below the uppermost layer, does not have a protrusion PR1 on its side. Furthermore, the lower storage column LMP, when on the same layer as the other wiring layers 104 (104_1 to 104_6), has a protrusion PR1 on its side. That is, the side of the uppermost wiring layer 104 (104_8), the side of the insulating layer 103 (103_8) below it, and the side of the wiring layer 104 (104_7) below the uppermost layer are flat. Moreover, each of the lower wiring layers 104 (104_1 to 104_6) forms a groove region with a step difference between it and the insulating layers 103 (103_1 to 103_7) disposed above and below it. This suppresses reverse tunneling. This can improve the reliability of semiconductor memory device 1.

[0109] 2. Second Implementation Method

[0110] The second embodiment will now be described. In the second embodiment, the shape of the storage column MP and the manufacturing method of the storage cell array 11, which differ from the first embodiment, will be described. Hereinafter, the description will focus on the differences from the first embodiment.

[0111] 2.1 Cross-sectional structure of the memory cell array

[0112] First, refer to Figure 25 This illustrates an example of the cross-sectional configuration of the storage cell array 11. Figure 25 The cross-sectional structure of a NAND string NS is shown.

[0113] like Figure 25 As shown, in this embodiment, the lower storage column LMP has a protrusion PR2 that protrudes from the side at the same level as the wiring layer 104-7, the insulating layer 103-8, and the wiring layer 104-8. Furthermore, the upper end of the lower storage column LMP is located near the boundary between the wiring layer 104-8 and the insulating layer 105. That is, the bottom surface of the connecting portion JC is in contact with the wiring layer 104-8. Other configurations are the same as in the first embodiment. Figure 3 The cross-sectional structure of the storage column MP described in the text is the same.

[0114] 2.2 Shape of the wiring layer and insulation layer connected to the storage column MP

[0115] Below, refer to Figure 26 and Figure 27 This describes the shape of the wiring layer and insulation layer that are connected to the storage column MP. Figure 26 yes Figure 25 A magnified view of region RB. Figure 27 Indicates along Figure 26Plan view of lines A1-A2, B1-B2, C1-C2, and D1-D2. Furthermore, in Figure 26 and Figure 27 In the example, the storage column MP is omitted for simplicity. Furthermore, in Figure 26 In the example, for the sake of simplicity, the sides of each layer are shown to extend in the Z direction.

[0116] like Figure 26 and Figure 27 As shown, in this embodiment, the width L103_8 is longer than both the widths L103_6 and L103_7. Furthermore, the widths L104_6, L104_7, and L104_8 are approximately equal.

[0117] A protrusion PR2 is provided on the side of the lower storage column LMP at the same layer as wiring layer 104_7, insulation layer 103_8, and wiring layer 104_8. As a result, there is almost no step difference between the upper end of wiring layer 104_7 and the lower end of insulation layer 103_8, and between the upper end of insulation layer 103_8 and the lower end of wiring layer 104_8. In other words, the sides of wiring layer 104_7, insulation layer 103_8, and wiring layer 104_8 are arranged approximately flat in the Z direction. Alternatively, the sides of wiring layer 104_7, insulation layer 103_8, and wiring layer 104_8 are positioned approximately the same in the Y direction. Therefore, the widths L104_7, L103_8, and L104_8 are approximately equal.

[0118] On the other hand, a step difference is provided between the upper end of the insulation layer 103_7 and the lower end of the wiring layer 104_7 through the protrusion PR2. Let the step difference between the insulation layer 103_7 and the wiring layer 104_7 be W6. The step difference W6 can be expressed by the width L103_7 and the width L104_7 as W6 = [(L104_7) - (L103_7)] / 2. The step difference W6 is approximately equal to the step difference W1.

[0119] At the upper end of the insulation layer 103-7, a recess is provided in the portion protruding from the wiring layer 104-7. For example... Figure 27 As shown in plane C, when the cross-sectional shape of the hole LMH in the XY plane is circular, the recess may have, for example, an annular shape. Alternatively, there may be no recess.

[0120] 2.3 Manufacturing Method of Memory Cell Array

[0121] Next, use Figure 28 and Figure 29 This is an example illustrating the manufacturing method of the storage cell array 11. Figure 28 This is a flowchart illustrating the manufacturing process of the storage cell array 11. Figure 29Show respectively with Figure 28 The flowchart shows a cross-sectional view of the memory cell array 11 corresponding to step S20.

[0122] like Figure 28 As shown, steps S1 to S5 are the same as in the first embodiment.

[0123] like Figure 29 As shown, after the sacrificial layer 121 is processed until the sacrificial layers 120_7 and 120_8 are exposed, the insulating layers 103_8 and 105 are processed, for example, by wet etching. Figure 28 Step S20). A recess is formed on the insulating layer 103-7 by wet etching. At this time, the etching amount of the insulating layer 103-8 is adjusted so that the step difference between the upper end of the sacrificial layer 120-7 and the lower end of the insulating layer 103-8, and the step difference between the upper end of the insulating layer 103-8 and the lower end of the sacrificial layer 120-8 are almost non-existent. The etching conditions are set such that the etching rate of the insulating layers 103-8 and 105 is higher than that of the sacrificial layers 120-7 and 120-8, and the sacrificial layer 121.

[0124] Steps S10 to S15 after step S20 are the same as in the first embodiment.

[0125] In step S15, after forming the lower storage pillar LMP, the connector JC, and the upper storage pillar UMP, the sacrificial layers 120 and 125 are removed by wet etching. Figure 28 Step S21). Thus, a gap GP corresponding to wiring layers 104_1 to 104_8 and wiring layers 106_1 to 106_8 is formed.

[0126] Then, similarly to step S17 of the first embodiment, wiring layers 104_1 to 104_8 and 106_1 to 106_8 are formed.

[0127] 2.4 Effects of this implementation method

[0128] According to the configuration involved in this embodiment, the same effect as that of the first embodiment can be obtained.

[0129] 3. Third Implementation Method

[0130] The third embodiment will now be described. In the third embodiment, the shape of the storage column MP and the manufacturing method of the storage cell array 11, which differ from the first and second embodiments, will be described. Hereinafter, the description will focus on the differences from the first and second embodiments.

[0131] 3.1 Cross-sectional structure of the memory cell array

[0132] First, refer to Figure 30This illustrates an example of the cross-sectional configuration of the storage cell array 11. Figure 30 The cross-sectional structure of a NAND string NS is shown.

[0133] like Figure 30 As shown, in this embodiment, the lower storage column LMP has a protrusion PR3 on its side at the same level as the three wiring layers 104_1, 104_2, and 104_3 from the bottom. The three protrusions PR3 protrude from the center of the lower storage column LMP toward the wiring layers 104_1 to 104_3 respectively. Furthermore, regarding the number of wiring layers 104 where the protrusions PR3 are provided at the same level, it is sufficient to have at least two layers, counting from the bottommost wiring layer 104. Additionally, the lower storage column LMP has a protrusion PR1 on its side at the same level as the other wiring layers 104_4 to 104_8. The protrusion amount of the protrusion PR3 is greater than that of the protrusion PR1. Similarly, the upper storage column UMP has a protrusion PR3 on its side at the same level as the three wiring layers 106_1, 106_2, and 106_3 from the bottom. Additionally, the upper storage column UMP, located on the same layer as the other wiring layers 106_4 to 106_8, has a side-protruding protrusion PR1. Other configurations are the same as in the first embodiment. Figure 3 The cross-sectional structure of the storage column MP described in the text is the same.

[0134] 3.2 Shape of the wiring layer and insulation layer connected to the storage column MP

[0135] Below, refer to Figure 31 This describes the shape of the wiring layer and insulation layer that are connected to the storage column MP. Figure 31 yes Figure 30 A magnified view of the RC region. Furthermore, in Figure 31 In the example, for simplicity, the upper storage cylinder UMP is omitted. The side views of each layer show the faces opposite to the storage cylinder MP. Additionally, Figure 31 The example shows the case where the lower storage column (LMP) is tapered.

[0136] like Figure 31As shown, the widths of the upper ends of insulating layers 103_1, 103_2, 103_3, 103_4, and 103_5 in the Y direction are respectively denoted as L103_1, L103_2, L103_3, L103_4, and L103_5. The widths of the lower ends of wiring layers 104_1, 104_2, 104_3, 104_4, and 104_5 in the Y direction are respectively denoted as L104_1, L104_2, L104_3, L104_4, and L104_5. Width L104_1 represents the diameter of the lower end of the select transistor ST2. When the cross-sectional shape of the storage column MP in the XY plane is circular, widths L104_2, L104_3, L104_4, and L104_5 represent the diameters of the lower ends of the storage cell transistors MC0 to MC3.

[0137] In this embodiment, the widths L103_1, L103_2, L103_3, L103_4, and L103_5 are related by the relationship L103_1 < L103_2 < L103_3 < L103_4 < L103_5. Similarly, the widths L104_1, L104_2, and L104_3 are related by the relationship L104_1 < L104_2 < L104_3. Furthermore, the widths L104_4 and L104_5 are related by the relationship L104_4 < L104_5.

[0138] At the same level as wiring layers 104_1, 104_2, and 104_3, a protrusion PR3 is provided on the side of the lower storage column LMP. Let W7 be the step difference between the upper end of the insulating layer 103_1 and the lower end of the wiring layer 104_1. The step difference W7 can be expressed using the widths L103_1 and L104_1 as W7 = [(L104_1) - (L103_1)] / 2. Let W8 be the step difference between the upper end of the insulating layer 103_2 and the lower end of the wiring layer 104_2. The step difference W8 can be expressed using the widths L103_2 and L104_2 as W8 = [(L104_2) - (L103_2)] / 2. Furthermore, let W9 be the step difference between the upper end of the insulating layer 103_3 and the lower end of the wiring layer 104_3. The step difference W9 can be expressed using widths L103_3 and L104_3 as W9 = [(L104_3) - (L103_3)] / 2. Step differences W7, W8, and W9 correspond to the protrusion PR3 of the lower storage column LMP. Therefore, steps W7, W8, and W9 are approximately equal.

[0139] At the same level as wiring layers 104_4 and 104_5, a protrusion PR1 is provided on the side of the lower storage column LMP. Let W10 be the step difference between the upper end of the insulating layer 103_4 and the lower end of the wiring layer 104_4. The step difference W10 can be expressed using the widths L103_4 and L104_4 as W10 = [(L104_4) - (L103_4)] / 2. Let W11 be the step difference between the upper end of the insulating layer 103_5 and the lower end of the wiring layer 104_5. The step difference W11 can be expressed using the widths L103_5 and L104_5 as W11 = [(L104_5) - (L103_5)] / 2. Step differences W10 and W11 correspond to the protrusion PR1 of the lower storage column LMP. Therefore, step differences W10 and W11 are approximately equal. The protrusion of protrusion PR3 is greater than that of protrusion PR1. Therefore, the steps W7 to W11 exhibit the following relationships: W7 > W10, W7 > W11, W8 > W10, W8 > W11, W9 > W10, W9 > W11. Therefore, in Figure 31 In the example, there is a relationship between width L104_3 and width L104_4, where L104_3 > L104_4. That is, when the cross-sectional shape of the storage column MP in the XY plane is circular, the diameter of storage cell transistor MC1 is larger than the diameter of storage cell transistor MC2. By adjusting the difference between the step differences W7~W9 and the step differences W10 and W11, the diameters of the corresponding storage cell transistor MC and selection transistor ST2 can be adjusted.

[0140] 3.3 Manufacturing Method of Memory Cell Array

[0141] Next, use Figures 32-42 An example illustrating the manufacturing method of the storage cell array 11. Figure 32 This is a flowchart illustrating the manufacturing process of the storage cell array 11. Figures 33-42 Show respectively with Figure 32 The flowchart shows the cross-sectional view of the memory cell array 11 corresponding to steps S30 to S39.

[0142] like Figure 33 As shown, firstly, multiple insulating layers 103, multiple sacrificial layers 120, multiple sacrificial layers 130, and insulating layer 105 are formed. Figure 32Step S30). More specifically, an insulating layer 101 is formed on the semiconductor substrate 100. Additionally, a wiring layer 102 is formed on the insulating layer 101. In this state, an insulating layer 103_1 is formed on the wiring layer 102. A sacrificial layer 130_1 is formed on the insulating layer 103_1. An insulating layer 103_2 is formed on the sacrificial layer 130_1. A sacrificial layer 130_2 is formed on the insulating layer 103_2. An insulating layer 103_3 is formed on the sacrificial layer 130_2. A sacrificial layer 130_3 is formed on the insulating layer 103_3. An insulating layer 103_4 is formed on the sacrificial layer 130_3. A sacrificial layer 120_4 is formed on the insulating layer 103_4. An insulating layer 103_5 is formed on the sacrificial layer 120_5. An insulating layer 103_6 is formed on the sacrificial layer 120_5. A sacrificial layer 120-6 is formed on the insulating layer 103-6. An insulating layer 103-7 is formed on the sacrificial layer 120-6. A sacrificial layer 120-7 is formed on the insulating layer 103-7. An insulating layer 103-8 is formed on the sacrificial layer 120-7. A sacrificial layer 120-8 is formed on the 103-8. Then, an insulating layer 105 is formed on the uppermost sacrificial layer 120-8.

[0143] Sacrificial layers 130_1 to 130_3 correspond to wiring layers 104_1 to 104_3, respectively. Sacrificial layers 130_1 to 130_3 are subsequently replaced by wiring layers 104_1 to 104_3, respectively. Sacrificial layers 130 (130_1 to 130_3) use a material that allows for a sufficient wet etching selectivity relative to the insulating layer 103. Furthermore, sacrificial layers 130 use a material with a faster wet etching rate compared to sacrificial layer 120. For example, if sacrificial layer 120 is SiN, sacrificial layer 130 can use SiN with a lower density than the SiN in sacrificial layer 120, or SiN containing impurities [e.g., oxygen (O)]. For example, in the case of SiN containing impurities, by adjusting the density of the SiN or the concentration of impurities contained in the SiN, the wet etching selectivity of the SiN in sacrificial layer 120 and the SiN in sacrificial layer 130 can be controlled.

[0144] like Figure 34 As shown, a hole is formed in LMH ( Figure 32 Step S31). More specifically, the via LMH penetrates 8 insulating layers 103_1 to 103_8, 3 sacrificial layers 130_1 to 130_3, 5 sacrificial layers 120_4 to 120_8, and insulating layer 105. The bottom surface of the via LMH reaches the wiring layer 102. Furthermore, the shape of the opening of the via LMH is not limited to a circle (perfect circle). The shape of the opening of the via LMH can also be elliptical or rectangular. In addition, the cross-sectional shape of the via LMH can be conical, straight along the Z-direction, or arcuate.

[0145] like Figure 35 As shown, groove etching is performed on sacrificial layers 120 and 130. Figure 32 Step S32). More specifically, wet etching is performed on the sides of the sacrificial layers 120 and 130 exposed within the hole LMH. This forms a groove region extending from the hole LMH. When the cross-sectional shape of the hole LMH in the XY plane is circular, the groove region extends from the hole LMH in a concentric circle. At this time, the wet etching conditions are set to a condition where the etching rate of the sacrificial layers 120 and 130 is higher than the etching rate of the insulating layer 103. Furthermore, the etching rate of the sacrificial layer 130 is higher than the etching rate of the sacrificial layer 120. The groove region in the same layer as the sacrificial layers 130-1 to 130-3 corresponds to the protrusion PR3. The groove region in the same layer as the sacrificial layers 120-4 to 120-8 corresponds to the protrusion PR1. Therefore, the groove width (step difference) of the groove region in the same layer as the sacrificial layers 130-1 to 130-3 is greater than the groove width (step difference) of the groove region in the same layer as the sacrificial layers 120-4 to 120-8.

[0146] like Figure 36 As shown, sacrificial layer 123 is used to fill the holes LMH ( Figure 6 Step S33). In this embodiment, the entire hole LMH is filled using the sacrificial layer 123.

[0147] Steps S8 to S10 are the same as in the first embodiment.

[0148] like Figure 37 As shown, a plurality of sacrificial layers 125, a plurality of sacrificial layers 131, and a plurality of insulating layers 107 are formed on the insulating layer 105 and the sacrificial layer 124. Figure 32 Step S34). More specifically, a sacrificial layer 131_1 is formed on the insulating layer 105 and the sacrificial layer 124. An insulating layer 107_1 is formed on the sacrificial layer 131_1. A sacrificial layer 131_2 is formed on the insulating layer 107_1. An insulating layer 107_2 is formed on the sacrificial layer 131_2. A sacrificial layer 131_3 is formed on the insulating layer 107_2. An insulating layer 107_3 is formed on the sacrificial layer 131_3. A sacrificial layer 125_4 is formed on the insulating layer 107_4. An insulating layer 125_5 is formed on the insulating layer 107_4. An insulating layer 107_5 is formed on the sacrificial layer 125_5. A sacrificial layer 125_6 is formed on the sacrificial layer 125_6. An insulating layer 107_6 is formed on the sacrificial layer 125_6. A sacrificial layer 125-7 is formed on top of the insulating layer 107-6. An insulating layer 107-7 is formed on top of the sacrificial layer 125-7. A sacrificial layer 125-8 is formed on top of the insulating layer 107-7. An insulating layer 107-8 is formed on top of the sacrificial layer 125-8.

[0149] Sacrificial layers 131_1 to 131_3 correspond to wiring layers 106_1 to 106_3, respectively. Sacrificial layers 131_1 to 131_3 are subsequently replaced by wiring layers 106_1 to 106_3, respectively. Sacrificial layers 131 (131_1 to 131_3) use a material that allows for a sufficient wet etching selectivity relative to the insulating layer 107. Furthermore, sacrificial layers 131 use a material with a faster wet etching rate compared to sacrificial layer 125. For example, if sacrificial layer 125 is SiN, sacrificial layer 131, like sacrificial layer 130, can use SiN with a lower density compared to the SiN in sacrificial layer 125, or SiN containing impurities [e.g., oxygen (O)].

[0150] like Figure 38 As shown, a hole UMH is formed on the sacrificial layer 124. Figure 32 Step S35). More specifically, the UMH (Ultra-Hole Hole) penetrates three sacrificial layers 131_1 to 131_3, five sacrificial layers 125_4 to 125_8, and eight insulating layers 107_1 to 107_8. The bottom surface of the UMH reaches the sacrificial layer 124. Furthermore, the shape of the opening of the UMH is not limited to a circle (perfect circle). The shape of the opening of the UMH can also be elliptical or rectangular. In addition, the cross-sectional shape of the UMH can be conical, linear, or arc-shaped.

[0151] like Figure 39 As shown, groove etching is performed on sacrificial layers 125 and 131. Figure 32 Step S36). More specifically, wet etching is performed on the sides of the sacrificial layers 125 and 131 exposed within the UMH. This forms a groove region extending from the UMH. When the cross-sectional shape of the UMH in the XY plane is circular, the groove region extends from the UMH in a concentric circle. At this time, the wet etching conditions are set such that the etching rates of the sacrificial layers 125 and 131 are higher than those of the insulating layer 107 and the sacrificial layer 124. Furthermore, the etching rate of the sacrificial layer 131 is higher than that of the sacrificial layer 125. The groove region in the same layer as the sacrificial layers 131-1 to 131-3 corresponds to the protrusion PR3. The groove region in the same layer as the sacrificial layers 125-4 to 125-8 corresponds to the protrusion PR1. Therefore, the groove width (step difference) of the groove region in the same layer as the sacrificial layers 131-1 to 131-3 is greater than the groove width (step difference) of the groove region in the same layer as the sacrificial layers 125-4 to 125-8.

[0152] like Figure 40 As shown, sacrificial layers 123 and 124 are removed by wet etching. Figure 32Step S37). At this time, the etching conditions are set such that the etching rate of sacrificial layers 123 and 124 is higher than that of wiring layers 102, insulating layers 103, 105 and 107, and sacrificial layers 120, 125, 130 and 131. This forms the via MH.

[0153] Then, similarly to the first embodiment, in step S15, the lower storage column LMP, the connecting part JC, and the upper storage column UMP are formed together.

[0154] Then, in Figure 32 The substitution is performed in steps S38 and S39.

[0155] like Figure 41 As shown, firstly, sacrificial layers 120, 125, 130, and 131 are removed by wet etching. Figure 7 Step S38). More specifically, firstly, in an area not shown, slits are formed that expose sacrificial layers 120, 125, 130, and 131 on the sides. That is, the slits penetrate (pass through) sacrificial layers 130_1 to 130_3, sacrificial layers 120_4 to 120_8, sacrificial layers 131_1 to 131_3, and sacrificial layers 125_4 to 125_8. After the slits are formed, sacrificial layers 130_1 to 130_3, sacrificial layers 120_4 to 120_8, sacrificial layers 131_1 to 131_3, and sacrificial layers 125_4 to 125_8 are removed from the sides of the slits by wet etching. At this time, the etching conditions are set to have a higher etching rate for sacrificial layers 120, 125, 130, and 131 compared to insulating layers 103, 105, and 107, and block insulating film 111. This creates gaps GP corresponding to wiring layers 104_1 to 104_8 and wiring layers 106_1 to 106_8.

[0156] like Figure 42 As shown, similarly to step S17 of the first embodiment, wiring layers 104 and 106 are formed. Figure 38 Step S39).

[0157] 3.4 Effects of this implementation method

[0158] For example, when the memory pillar MP has a tapered shape, the memory cell transistor MC at the lower end of the memory pillar MP becomes thinner. When the cross-sectional shape of the memory pillar MP in the XY plane is circular, the diameter of the memory cell transistor MC at the lower end of the memory pillar MP becomes smaller. That is, within the memory pillar MP, there are variations in the thickness or diameter of multiple memory cell transistors MC. If the memory cell transistor MC becomes thinner or its diameter becomes smaller, the channel region of the memory cell transistor MC will become narrower. Therefore, compared to a thicker or larger diameter memory cell transistor MC, the electric field strength between the gate and the channel is stronger in a thinner or smaller diameter memory cell transistor MC. Therefore, threshold fluctuations caused by read operations (hereinafter referred to as "read interference") are more likely to occur in the thinner or smaller diameter memory cell transistor MC.

[0159] In contrast, according to the configuration of this embodiment, protrusions with varying protrusion amounts can be formed on the side of the memory pillar MP at the same layer as the plurality of wiring layers 104. That is, in regions where the memory pillar MP is thinner or where the diameter of the memory pillar MP is smaller, by making the protrusion amount of the protrusion larger, the memory pillar MP can be made relatively thicker or the diameter of the memory pillar MP can be relatively larger. As a result, deviations in the thickness or diameter of each memory cell transistor MC in the memory pillar MP can be suppressed. As a result, deviations in the electric field strength between the gate and the channel in each memory cell transistor MC can be suppressed. That is, read interference can be suppressed. As a result, the reliability of the semiconductor memory device 1 can be improved.

[0160] Furthermore, the third embodiment can be combined with the first or second embodiment.

[0161] 4. Variations, etc.

[0162] According to the above embodiment, the semiconductor memory device includes: a first wiring layer (104-6); a first insulating layer (103-7) disposed on the first wiring layer; a second wiring layer (104-7) disposed on the first insulating layer; a second insulating layer (103-8) disposed on the second wiring layer; a third wiring layer (104-8) disposed on the second insulating layer; and a first pillar (LMP) extending along a first direction (Z direction), passing through the first wiring layer, the first insulating layer, the second wiring layer, the second insulating layer and the third wiring layer, and including a first semiconductor layer (114). The first order difference (W1) is greater than the second order difference (W2) and the third order difference (W3). The first order difference (W1) is the order difference between the first surface of the first wiring layer opposite to the first post and the second surface of the first insulation layer opposite to the first post. The second order difference (W2) is the order difference between the third surface of the second wiring layer opposite to the first post and the fourth surface of the second insulation layer opposite to the first post. The third order difference (W3) is the order difference between the fourth surface and the fifth surface of the third wiring layer opposite to the first post.

[0163] By applying the above-described embodiments, a semiconductor memory device with improved reliability can be provided.

[0164] Furthermore, the implementation method is not limited to the method described above, and various modifications can be made.

[0165] For example, in the second embodiment, such as Figure 43 As shown, the side of the insulating layer 103_8 can also be bent in a manner that protrudes from the wiring layers 104_7 and 104_8. Figure 43 This is the second embodiment. Figure 25 A magnified view of region RB. For example, in the second embodiment... Figure 28 In step S20 described herein, when the insulating layer 103_8 is processed by wet etching, the shape of the end of the insulating layer 103_8 can be bent.

[0166] Furthermore, the "connection" in the above embodiments also includes the state in which they are indirectly connected via other components such as transistors or resistors.

[0167] The embodiments described are merely illustrative and do not limit the scope of the invention.

[0168] Explanation of the label

[0169] 1…Semiconductor memory devices

[0170] 10… Memory chip

[0171] 11… Storage cell array

[0172] 12…line decoder

[0173] 13…Sensing Amplifier

[0174] 20…Control Department

[0175] 21… Sequencer

[0176] 22…Voltage Generation Circuit

[0177] 100… Semiconductor substrate

[0178] Insulation layers 101, 103, 103_1 to 103_8, 105, 107, 107_1 to 107_8, 108…

[0179] 102, 104, 104_1 to 104_8, 106, 106_1 to 106_8, 109… Wiring layers

[0180] 111… Block insulation film

[0181] 112…charge storage layer

[0182] 113…Tunnel insulation film

[0183] 114…Semiconductor layer

[0184] 115…core layer

[0185] 116…cap layer

[0186] 117…Contact Plug

[0187] 120, 120_1~120_8, 121, 122, 123, 124, 125, 125_1~125_8, 130, 130_1~130_3, 131, 131_1~131_3… Sacrificial Layer

[0188] BL0~BLn…bit lines

[0189] MC0~MC11…memory cell transistors

[0190] PR1, PR2, PR3... protruding parts

[0191] SGD0~SGD3… Select gate lines

[0192] ST1, ST2... Select transistors

[0193] SU0~SU3… serial units

[0194] WL0~WL11… word lines.

Claims

1. A semiconductor memory device comprising: First wiring layer; A first insulating layer disposed above the first wiring layer; A second wiring layer disposed on top of the first insulation layer; A second insulating layer disposed above the second wiring layer; A third wiring layer disposed on top of the second insulation layer; The first post extends along the first direction, passing through the first wiring layer, the first insulating layer, the second wiring layer, the second insulating layer and the third wiring layer, and contains a first semiconductor layer; A connecting portion is disposed on the first pillar and contains the first semiconductor layer; as well as The second pillar, disposed above the connecting portion and extending along the first direction, contains the first semiconductor layer. The first order difference is greater than the second and third order differences. The first order difference is the order difference between the first surface of the first wiring layer opposite to the first post and the second surface of the first insulation layer opposite to the first post. The second order difference is the order difference between the third surface of the second wiring layer opposite to the first post and the fourth surface of the second insulation layer opposite to the first post. The third order difference is the order difference between the fourth surface and the fifth surface of the third wiring layer opposite to the first post.

2. The semiconductor memory device according to claim 1, wherein, The second, third, fourth, and fifth surfaces are arranged in a manner that makes them flat in the first direction.

3. The semiconductor memory device according to claim 1, wherein, The third wiring layer is adjacent to the connection portion in the first direction via the third insulation layer.

4. The semiconductor memory device according to claim 1, wherein, The third, fourth, and fifth surfaces are arranged in a manner that makes them flat in the first direction. The fourth order difference between the second surface and the third surface is greater than the second order difference and the third order difference.

5. The semiconductor memory device according to claim 1, wherein, The third wiring layer is connected to the third insulation layer in the first direction.

6. A method for manufacturing a semiconductor memory device, wherein, Multiple first insulation layers and multiple first sacrificial layers are alternately stacked on top of the first wiring layer. A second insulating layer is formed on top of the uppermost of the plurality of first sacrificial layers. A hole is formed that extends along the first direction through the plurality of first insulating layers, the plurality of first sacrificial layers, and the second insulating layer, with its bottom surface reaching the first wiring layer. The sides of the plurality of first sacrificial layers exposed on the sides of the holes are etched. A second sacrificial layer is formed to fill the holes. The second sacrificial layer is etched until the uppermost first sacrificial layer is exposed on the side of the hole. The third sacrificial layer is selectively grown on the side of the uppermost first sacrificial layer. After removing the second sacrificial layer, a pillar containing at least a semiconductor layer is formed within the hole. Remove the first sacrificial layer and the third sacrificial layer. Multiple second wiring layers are formed in the regions where the first and third sacrificial layers have been removed.

7. The method for manufacturing a semiconductor memory device according to claim 6, wherein, The side surface of the third sacrificial layer opposite to the post, and the side surface of the uppermost first insulating layer of the plurality of first insulating layers opposite to the post, are arranged in a manner that makes them flat in the first direction.

8. A method for manufacturing a semiconductor memory device, wherein, Multiple first insulation layers and multiple first sacrificial layers are alternately stacked on top of the first wiring layer. A second insulating layer is formed on top of the uppermost of the plurality of first sacrificial layers. A hole is formed that extends along the first direction through the plurality of first insulating layers, the plurality of first sacrificial layers, and the second insulating layer, with its bottom surface reaching the first wiring layer. The plurality of first sacrificial layers exposed on the sides of the hole are etched. A second sacrificial layer is formed to fill the holes. The second sacrificial layer is etched until at least the uppermost of the plurality of first insulating layers is exposed on the side of the hole. The side surface of the uppermost first insulating layer exposed in the hole is etched. After removing the second sacrificial layer, a first pillar containing at least a semiconductor layer is formed within the hole. Remove the first sacrificial layer. Multiple second wiring layers are formed in the region where the first sacrificial layer has been removed.

9. The method for manufacturing a semiconductor memory device according to claim 8, wherein, When etching the side surface of the uppermost first insulating layer exposed in the hole, the etching is performed in such a way that the side surface of the uppermost first insulating layer and the side surface of the uppermost first sacrificial layer are flat in the first direction.

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